Re: linux-next: build failure after merge of the final tree (powerpc related)

2012-06-20 Thread Benjamin Herrenschmidt 
On Thu, 2012-06-21 at 15:36 +1000, Michael Ellerman wrote:
> 
> powerpc64-linux-ld: 
> /src/next/net/openvswitch/vport-netdev.c:189:(.text+0x89b990): 
> sibling call optimization to `_restgpr0_28' does not allow automatic 
> multiple TOCs;
> recompile with -mminimal-toc or -fno-optimize-sibling-calls, or make 
> `_restgpr0_28' extern
> 
> 
> And those are generated calls so I don't see how we can fix them.

Is this a module ? We should really be linking that stuff directly with the 
module

The interesting thing is that we do build everything except a handful of
files with -mminimal-toc unless something's wrong with our main Makefile

Can you show the full build command that triggers the above ?

Cheers,
Ben.


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Re: linux-next: build failure after merge of the final tree (powerpc related)

2012-06-20 Thread Michael Ellerman 
On Wed, 2012-06-20 at 17:50 +1000, Stephen Rothwell wrote:
> Hi all,
> 
> After merging the final tree, today's linux-next build (powerpc
> allyesconfig) failed like this:
> 
> powerpc64-linux-ld: arch/powerpc/net/built-in.o: In function 
> `bpf_slow_path_word':
> (.text+0x90): sibling call optimization to `skb_copy_bits' does not allow 
> automatic multiple TOCs; recompile with -mminimal-toc or 
> -fno-optimize-sibling-calls, or make `skb_copy_bits' extern


Those seem to be caused because we don't have a nop after the call,
meaning we can't patch the TOC pointer on the way back. Adding a nop
fixes those.

But, then I get 32,410 variants of this:

powerpc64-linux-ld: 
/src/next/net/openvswitch/vport-netdev.c:189:(.text+0x89b990): 
sibling call optimization to `_restgpr0_28' does not allow automatic 
multiple TOCs;
recompile with -mminimal-toc or -fno-optimize-sibling-calls, or make 
`_restgpr0_28' extern


And those are generated calls so I don't see how we can fix them.

> I started building with gcc 4.6.3/binutils 2.22 today.  gcc
> 4.6.0/binutils 2.21 do not produce this error, it produces this instead
> (which has been happening for a long time):
> 
> powerpc64-linux-ld: TOC section size exceeds 64k


So presumably there's some new error checking that we're hitting, I
imagine it was always broken, but now it's being more explicit.

I think we need some help from the toolchain experts, hi Alan :)

cheers

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Re: [PATCH] PPC: PCI: Fix pcibios_io_space_offset() so it works for 32-bit ptr/64-bit rsrcs

2012-06-20 Thread Benjamin Herrenschmidt 
(Bjorn, added you back because I ended up digging a shitload
of issues including some generic ... see below)

On Tue, 2012-06-05 at 23:50 -0400, Ben Collins wrote:
> The commit introducing pcibios_io_space_offset() was ignoring 32-bit to
> 64-bit sign extention, which is the case on ppc32 with 64-bit resource
> addresses. This only seems to have shown up while running under QEMU for
> e500mc target. It may or may be suboptimal that QEMU has an IO base
> address > 32-bits for the e500-pci implementation, but 1) it's still a
> regression and 2) it's more correct to handle things this way.

So I came to the conclusion that this isn't the right fix... what we
have is an "interesting" combinations of issues here and I'll have to
dig with Bjorn to sort them all out.

In the meantime, let me know if the "quick fix" below works for you
as a workaround:

@@ -734,7 +740,7 @@ void __devinit pci_process_bridge_OF_ranges(struct pci_contr
hose->io_base_virt = ioremap(cpu_addr, size);
 
/* Expect trouble if pci_addr is not 0 */
-   if (primary)
+   if (primary || !isa_io_base)
isa_io_base =
(unsigned long)hose->io_base_virt;

(Note: The root of the qemu issue seems to be that qemu doesn't accept
an IO BAR with a value of 0 as a valid IO BAR... which is arguably a
qemu bug. However, we shouldn't have assigned that if it wasn't for
a bunch of other nasties)

Now, we have a combination of problems here Bjorn. A bunch of them are
powerpc specific and I'll fix them, but I'm hitting a couple of nasties
in the generic resource allocation code:

 * I'm not too happy with our pcibios_io_space_offset() sign extension,
but that's no biggie, I will fix that

 * It triggers a bunch of other problems where quite a bit of code
in pci-common.c seems to be assuming 32-bit arithmetic when messing
around with the port remapping, so I have fixes for all of that

 * Additionally, we end up with a crazy offset for IO because our
isa_io_base is only set if we mark a host bridge as "primary" and it
looks like the FSL code doesn't mark any. So our isa_io_base is 0
instead of the virt base of the first bridge, and thus our resource
offsets are equal to the virt base of the IO space of the bridge :-)
This isn't wrong per-se, ie, it -should- still work, but it then
trigger interesting problems. The patch above "corrects" that by making
isa_io_base default to the first bridge IO base if there's no primary.

 * PCIBIOS_IO_MIN (and MEM_MIN) are bogus... On most architectures
they represent a bus address, but the generic code uses them as a
resource address. So they don't work and we end up handing out
an IO resource equal to 0 (bus) instead of 0x1000 (bus) because the
offset'ed resource address isn't smaller than the min. Now I do have a
patch to fix that in the generic code, but I suspect that will break
a couple of archs:

arch/mn10300/include/asm/pci.h:#define PCIBIOS_MIN_IO   0xBE04
arch/alpha/include/asm/pci.h:#define PCIBIOS_MIN_IO 
alpha_mv.min_io_address

and maybe some mips stuff, I'm not sure. Do those archs do any
offsetting ? If they do we might want to change those defines
along with my patch:

diff --git a/drivers/pci/setup-res.c b/drivers/pci/setup-res.c
index eea85da..ec429f3 100644
--- a/drivers/pci/setup-res.c
+++ b/drivers/pci/setup-res.c
@@ -131,10 +131,20 @@ static int __pci_assign_resource(struct pci_bus *bus, 
struct pci_dev *dev,
int resno, resource_size_t size, resource_size_t align)
 {
struct resource *res = dev->resource + resno;
+   struct resource min_res;
+   struct pci_bus_region min_reg;
resource_size_t min;
int ret;
 
-   min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;
+   /*
+* We convert PCIBIOS_MIN_IO/MEM from bus addresses to
+* resources before passing them to pci_bus_alloc_resource
+*/
+   min_res.flags = res->flags;
+   min_reg.start =  (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : 
PCIBIOS_MIN_MEM;
+   min_reg.end = min_reg.start;
+   pcibios_bus_to_resource(dev, &min_res, &min_reg);
+   min = min_res.start;
 
/* First, try exact prefetching match.. */
ret = pci_bus_alloc_resource(bus, res, size, align, min,

 * Additionally, there's another problem inside pci_bus_alloc_resource()
itself:

/* Ok, try it out.. */
ret = allocate_resource(r, res, size,
r->start ? : min,
max, align,
alignf, alignf_data);

See the r->start ? : min ?

It only applies the "min" if r->start is 0 now we have a hack in 
arch/powerpc
to clear out resources we think are unassigned. Unfortunately that hack got 
broken
when moving the offett'ing to generic code because

[PATCH 18/18] powerpc: enforce usage of RA 0-R31 where possible

2012-06-20 Thread Michael Neuling 
Some macros use RA where when RA=R0 the values is 0, so make this
the enforced mnemonic in the macro.

Idea suggested by Andreas Schwab.

Signed-off-by: Michael Neuling 
---

 arch/powerpc/include/asm/ppc-opcode.h |   14 +++---
 arch/powerpc/kernel/cpu_setup_a2.S|2 +-
 arch/powerpc/kernel/exceptions-64e.S  |8 
 arch/powerpc/mm/tlb_low_64e.S |   10 +-
 arch/powerpc/mm/tlb_nohash_low.S  |   16 
 5 files changed, 25 insertions(+), 25 deletions(-)

Index: powerpc-test/arch/powerpc/include/asm/ppc-opcode.h
===
--- powerpc-test.orig/arch/powerpc/include/asm/ppc-opcode.h
+++ powerpc-test/arch/powerpc/include/asm/ppc-opcode.h
@@ -198,7 +198,7 @@
 #define PPC_RFDI   stringify_in_c(.long PPC_INST_RFDI)
 #define PPC_RFMCI  stringify_in_c(.long PPC_INST_RFMCI)
 #define PPC_TLBILX(t, a, b)stringify_in_c(.long PPC_INST_TLBILX | \
-   __PPC_T_TLB(t) | __PPC_RA(a) | 
__PPC_RB(b))
+   __PPC_T_TLB(t) | __PPC_RA0(a) | 
__PPC_RB(b))
 #define PPC_TLBILX_ALL(a, b)   PPC_TLBILX(0, a, b)
 #define PPC_TLBILX_PID(a, b)   PPC_TLBILX(1, a, b)
 #define PPC_TLBILX_VA(a, b)PPC_TLBILX(3, a, b)
@@ -207,23 +207,23 @@
 #define PPC_TLBIE(lp,a)stringify_in_c(.long PPC_INST_TLBIE | \
   ___PPC_RB(a) | ___PPC_RS(lp))
 #define PPC_TLBSRX_DOT(a,b)stringify_in_c(.long PPC_INST_TLBSRX_DOT | \
-   __PPC_RA(a) | __PPC_RB(b))
+   __PPC_RA0(a) | __PPC_RB(b))
 #define PPC_TLBIVAX(a,b)   stringify_in_c(.long PPC_INST_TLBIVAX | \
-   __PPC_RA(a) | __PPC_RB(b))
+   __PPC_RA0(a) | __PPC_RB(b))
 
 #define PPC_ERATWE(s, a, w)stringify_in_c(.long PPC_INST_ERATWE | \
__PPC_RS(s) | __PPC_RA(a) | __PPC_WS(w))
 #define PPC_ERATRE(s, a, w)stringify_in_c(.long PPC_INST_ERATRE | \
__PPC_RS(s) | __PPC_RA(a) | __PPC_WS(w))
 #define PPC_ERATILX(t, a, b)   stringify_in_c(.long PPC_INST_ERATILX | \
-   __PPC_T_TLB(t) | __PPC_RA(a) | \
+   __PPC_T_TLB(t) | __PPC_RA0(a) | \
__PPC_RB(b))
 #define PPC_ERATIVAX(s, a, b)  stringify_in_c(.long PPC_INST_ERATIVAX | \
-   __PPC_RS(s) | __PPC_RA(a) | __PPC_RB(b))
+   __PPC_RS(s) | __PPC_RA0(a) | 
__PPC_RB(b))
 #define PPC_ERATSX(t, a, w)stringify_in_c(.long PPC_INST_ERATSX | \
-   __PPC_RS(t) | __PPC_RA(a) | __PPC_RB(b))
+   __PPC_RS(t) | __PPC_RA0(a) | 
__PPC_RB(b))
 #define PPC_ERATSX_DOT(t, a, w)stringify_in_c(.long 
PPC_INST_ERATSX_DOT | \
-   __PPC_RS(t) | __PPC_RA(a) | __PPC_RB(b))
+   __PPC_RS(t) | __PPC_RA0(a) | 
__PPC_RB(b))
 #define PPC_SLBFEE_DOT(t, b)   stringify_in_c(.long PPC_INST_SLBFEE | \
__PPC_RT(t) | __PPC_RB(b))
 /* PASemi instructions */
Index: powerpc-test/arch/powerpc/kernel/cpu_setup_a2.S
===
--- powerpc-test.orig/arch/powerpc/kernel/cpu_setup_a2.S
+++ powerpc-test/arch/powerpc/kernel/cpu_setup_a2.S
@@ -112,7 +112,7 @@ _icswx_skip_guest:
 * a bolted entry though it will be in LRU and so will go away 
eventually
 * but let's not bother for now
 */
-   PPC_ERATILX(0,R0,R0)
+   PPC_ERATILX(0,0,R0)
 1:
blr
 
Index: powerpc-test/arch/powerpc/kernel/exceptions-64e.S
===
--- powerpc-test.orig/arch/powerpc/kernel/exceptions-64e.S
+++ powerpc-test/arch/powerpc/kernel/exceptions-64e.S
@@ -903,7 +903,7 @@ skpinv: addir6,r6,1 /* 
Increment */
bne 1b  /* If not, repeat */
 
/* Invalidate all TLBs */
-   PPC_TLBILX_ALL(R0,R0)
+   PPC_TLBILX_ALL(0,R0)
sync
isync
 
@@ -961,7 +961,7 @@ skpinv: addir6,r6,1 /* 
Increment */
tlbwe
 
/* Invalidate TLB1 */
-   PPC_TLBILX_ALL(R0,R0)
+   PPC_TLBILX_ALL(0,R0)
sync
isync
 
@@ -1020,7 +1020,7 @@ skpinv:   addir6,r6,1 /* 
Increment */
tlbwe
 
/* Invalidate TLB1 */
-   PPC_TLBILX_ALL(R0,R0)
+   PPC_TLBILX_ALL(0,R0)
sync
isync
 
@@ -1138,7 +1138,7 @@ a2_tlbinit_after_iprot_flush:
tlbwe
 #endif /* CONFIG_PPC_EARLY_DEBUG_WSP */
 
-   PPC_TLBILX(0,R0,R0)
+   PPC_TLBILX(0,0,R0)

[PATCH 17/18] powerpc: Add defines for RA 0-R31

2012-06-20 Thread Michael Neuling 
R0 is special since it'll be 0.

Signed-off-by: Michael Neuling 
---

 arch/powerpc/include/asm/ppc-opcode.h |   34 ++
 1 file changed, 34 insertions(+)

Index: powerpc-test/arch/powerpc/include/asm/ppc-opcode.h
===
--- powerpc-test.orig/arch/powerpc/include/asm/ppc-opcode.h
+++ powerpc-test/arch/powerpc/include/asm/ppc-opcode.h
@@ -48,6 +48,39 @@
 #define__REG_R30   30
 #define__REG_R31   31
 
+#define__REGA0_0   0
+#define__REGA0_R1  1
+#define__REGA0_R2  2
+#define__REGA0_R3  3
+#define__REGA0_R4  4
+#define__REGA0_R5  5
+#define__REGA0_R6  6
+#define__REGA0_R7  7
+#define__REGA0_R8  8
+#define__REGA0_R9  9
+#define__REGA0_R10 10
+#define__REGA0_R11 11
+#define__REGA0_R12 12
+#define__REGA0_R13 13
+#define__REGA0_R14 14
+#define__REGA0_R15 15
+#define__REGA0_R16 16
+#define__REGA0_R17 17
+#define__REGA0_R18 18
+#define__REGA0_R19 19
+#define__REGA0_R20 20
+#define__REGA0_R21 21
+#define__REGA0_R22 22
+#define__REGA0_R23 23
+#define__REGA0_R24 24
+#define__REGA0_R25 25
+#define__REGA0_R26 26
+#define__REGA0_R27 27
+#define__REGA0_R28 28
+#define__REGA0_R29 29
+#define__REGA0_R30 30
+#define__REGA0_R31 31
+
 /* sorted alphabetically */
 #define PPC_INST_DCBA  0x7c0005ec
 #define PPC_INST_DCBA_MASK 0xfc0007fe
@@ -149,6 +182,7 @@
 #define ___PPC_RS(s)   (((s) & 0x1f) << 21)
 #define ___PPC_RT(t)   ___PPC_RS(t)
 #define __PPC_RA(a)___PPC_RA(__REG_##a)
+#define __PPC_RA0(a)   ___PPC_RA(__REGA0_##a)
 #define __PPC_RB(b)___PPC_RB(__REG_##b)
 #define __PPC_RS(s)___PPC_RS(__REG_##s)
 #define __PPC_RT(t)___PPC_RT(__REG_##t)
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[PATCH 16/18] powerpc: enforce usage of R0-R31 where possible

2012-06-20 Thread Michael Neuling 
Enforce the use of R0-R31 in macros where possible now we have all the
fixes in.

R0-R31 macros are removed here so that can't be used anymore.  They
should not be defined anywhere.

Signed-off-by: Michael Neuling 
---

 arch/powerpc/include/asm/ppc-opcode.h |   41 +++---
 arch/powerpc/include/asm/ppc_asm.h|   17 --
 arch/powerpc/kernel/fpu.S |   12 +
 arch/powerpc/kvm/booke_interrupts.S   |3 +-
 4 files changed, 23 insertions(+), 50 deletions(-)

Index: powerpc-test/arch/powerpc/include/asm/ppc-opcode.h
===
--- powerpc-test.orig/arch/powerpc/include/asm/ppc-opcode.h
+++ powerpc-test/arch/powerpc/include/asm/ppc-opcode.h
@@ -15,39 +15,6 @@
 #include 
 #include 
 
-#defineR0  0
-#defineR1  1
-#defineR2  2
-#defineR3  3
-#defineR4  4
-#defineR5  5
-#defineR6  6
-#defineR7  7
-#defineR8  8
-#defineR9  9
-#defineR10 10
-#defineR11 11
-#defineR12 12
-#defineR13 13
-#defineR14 14
-#defineR15 15
-#defineR16 16
-#defineR17 17
-#defineR18 18
-#defineR19 19
-#defineR20 20
-#defineR21 21
-#defineR22 22
-#defineR23 23
-#defineR24 24
-#defineR25 25
-#defineR26 26
-#defineR27 27
-#defineR28 28
-#defineR29 29
-#defineR30 30
-#defineR31 31
-
 #define__REG_R00
 #define__REG_R11
 #define__REG_R22
@@ -181,10 +148,10 @@
 #define ___PPC_RB(b)   (((b) & 0x1f) << 11)
 #define ___PPC_RS(s)   (((s) & 0x1f) << 21)
 #define ___PPC_RT(t)   ___PPC_RS(t)
-#define __PPC_RA(a)(((a) & 0x1f) << 16)
-#define __PPC_RB(b)(((b) & 0x1f) << 11)
-#define __PPC_RS(s)(((s) & 0x1f) << 21)
-#define __PPC_RT(s)__PPC_RS(s)
+#define __PPC_RA(a)___PPC_RA(__REG_##a)
+#define __PPC_RB(b)___PPC_RB(__REG_##b)
+#define __PPC_RS(s)___PPC_RS(__REG_##s)
+#define __PPC_RT(t)___PPC_RT(__REG_##t)
 #define __PPC_XA(a)a) & 0x1f) << 16) | (((a) & 0x20) >> 3))
 #define __PPC_XB(b)b) & 0x1f) << 11) | (((b) & 0x20) >> 4))
 #define __PPC_XS(s)s) & 0x1f) << 21) | (((s) & 0x20) >> 5))
Index: powerpc-test/arch/powerpc/include/asm/ppc_asm.h
===
--- powerpc-test.orig/arch/powerpc/include/asm/ppc_asm.h
+++ powerpc-test/arch/powerpc/include/asm/ppc_asm.h
@@ -126,26 +126,26 @@ END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLP
 #define REST_32VRS(n,b,base)   REST_16VRS(n,b,base); REST_16VRS(n+16,b,base)
 
 /* Save the lower 32 VSRs in the thread VSR region */
-#define SAVE_VSR(n,b,base) li b,THREAD_VSR0+(16*(n));  STXVD2X(n,base,b)
+#define SAVE_VSR(n,b,base) li b,THREAD_VSR0+(16*(n));  
STXVD2X(n,R##base,R##b)
 #define SAVE_2VSRS(n,b,base)   SAVE_VSR(n,b,base); SAVE_VSR(n+1,b,base)
 #define SAVE_4VSRS(n,b,base)   SAVE_2VSRS(n,b,base); SAVE_2VSRS(n+2,b,base)
 #define SAVE_8VSRS(n,b,base)   SAVE_4VSRS(n,b,base); SAVE_4VSRS(n+4,b,base)
 #define SAVE_16VSRS(n,b,base)  SAVE_8VSRS(n,b,base); SAVE_8VSRS(n+8,b,base)
 #define SAVE_32VSRS(n,b,base)  SAVE_16VSRS(n,b,base); SAVE_16VSRS(n+16,b,base)
-#define REST_VSR(n,b,base) li b,THREAD_VSR0+(16*(n)); LXVD2X(n,base,b)
+#define REST_VSR(n,b,base) li b,THREAD_VSR0+(16*(n)); 
LXVD2X(n,R##base,R##b)
 #define REST_2VSRS(n,b,base)   REST_VSR(n,b,base); REST_VSR(n+1,b,base)
 #define REST_4VSRS(n,b,base)   REST_2VSRS(n,b,base); REST_2VSRS(n+2,b,base)
 #define REST_8VSRS(n,b,base)   REST_4VSRS(n,b,base); REST_4VSRS(n+4,b,base)
 #define REST_16VSRS(n,b,base)  REST_8VSRS(n,b,base); REST_8VSRS(n+8,b,base)
 #define REST_32VSRS(n,b,base)  REST_16VSRS(n,b,base); REST_16VSRS(n+16,b,base)
 /* Save the upper 32 VSRs (32-63) in the thread VSX region (0-31) */
-#define SAVE_VSRU(n,b,base)li b,THREAD_VR0+(16*(n));  STXVD2X(n+32,base,b)
+#define SAVE_VSRU(n,b,base)li b,THREAD_VR0+(16*(n));  
STXVD2X(n+32,R##base,R##b)
 #define SAVE_2VSRSU(n,b,base)  SAVE_VSRU(n,b,base); SAVE_VSRU(n+1,b,base)
 #define SAVE_4VSRSU(n,b,base)  SAVE_2VSRSU(n,b,base); SAVE_2VSRSU(n+2,b,base)
 #define SAVE_8VSRSU(n,b,base)  SAVE_4VSRSU(n,b,base); SAVE_4VSRSU(n+4,b,base)
 #define SAVE_16VSRSU(n,b,base) SAVE_8VSRSU(n,b,base); SAVE_8VSRSU(n+8,b,base)
 #define SAVE_32VSRSU(n,b,base) SAVE_16VSRSU(n,b,base); 
SAVE_16VSRSU(n+16,b,base)
-#define REST_VSRU(n,b,base)li b,THREAD_VR0+(16*(n)); LXVD2X(n+32,base,b)
+#define REST_VSRU(n,b,base)li b,THREAD_VR0+(16*(n)); 
LXVD2X(n+32,R##base,R##b)
 #define REST_2VSRSU(n,b,base)  REST_VSRU(n,b,base); REST_VSRU(n+1,b,base)
 #define REST_4VSRSU(n,b,base)  REST_2VSRSU(n,b,base); REST_2VSRSU(n+2,b,base)
 #define REST_8VSRSU(n,b,base)  REST_4VSRSU(n,b,base); REST_4

[PATCH 15/18] powerpc: Introduce new __REG_R macros

2012-06-20 Thread Michael Neuling 
Signed-off-by: Michael Neuling 
---

 arch/powerpc/include/asm/ppc-opcode.h |   33 +
 1 file changed, 33 insertions(+)

Index: powerpc-test/arch/powerpc/include/asm/ppc-opcode.h
===
--- powerpc-test.orig/arch/powerpc/include/asm/ppc-opcode.h
+++ powerpc-test/arch/powerpc/include/asm/ppc-opcode.h
@@ -48,6 +48,39 @@
 #defineR30 30
 #defineR31 31
 
+#define__REG_R00
+#define__REG_R11
+#define__REG_R22
+#define__REG_R33
+#define__REG_R44
+#define__REG_R55
+#define__REG_R66
+#define__REG_R77
+#define__REG_R88
+#define__REG_R99
+#define__REG_R10   10
+#define__REG_R11   11
+#define__REG_R12   12
+#define__REG_R13   13
+#define__REG_R14   14
+#define__REG_R15   15
+#define__REG_R16   16
+#define__REG_R17   17
+#define__REG_R18   18
+#define__REG_R19   19
+#define__REG_R20   20
+#define__REG_R21   21
+#define__REG_R22   22
+#define__REG_R23   23
+#define__REG_R24   24
+#define__REG_R25   25
+#define__REG_R26   26
+#define__REG_R27   27
+#define__REG_R28   28
+#define__REG_R29   29
+#define__REG_R30   30
+#define__REG_R31   31
+
 /* sorted alphabetically */
 #define PPC_INST_DCBA  0x7c0005ec
 #define PPC_INST_DCBA_MASK 0xfc0007fe
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[PATCH 14/18] powerpc: start using ___PPC_RA/B/S/T where necessary

2012-06-20 Thread Michael Neuling 
Now have ___PPC_RA/B/S/T we can use it in some places.  These are
places where we can't use the existing defines which will soon enforce
R0-R31 usage.  

The macros being changed here are being used in inline asm, which
can't convert to enforce the R0-R31 usage.

Signed-off-by: Michael Neuling 
---

 arch/powerpc/include/asm/ppc-opcode.h |   12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

Index: powerpc-test/arch/powerpc/include/asm/ppc-opcode.h
===
--- powerpc-test.orig/arch/powerpc/include/asm/ppc-opcode.h
+++ powerpc-test/arch/powerpc/include/asm/ppc-opcode.h
@@ -180,13 +180,13 @@
 #definePPC_DCBZL(a, b) stringify_in_c(.long PPC_INST_DCBZL | \
__PPC_RA(a) | __PPC_RB(b))
 #define PPC_LDARX(t, a, b, eh) stringify_in_c(.long PPC_INST_LDARX | \
-   __PPC_RT(t) | __PPC_RA(a) | \
-   __PPC_RB(b) | __PPC_EH(eh))
+   ___PPC_RT(t) | ___PPC_RA(a) | \
+   ___PPC_RB(b) | __PPC_EH(eh))
 #define PPC_LWARX(t, a, b, eh) stringify_in_c(.long PPC_INST_LWARX | \
-   __PPC_RT(t) | __PPC_RA(a) | \
-   __PPC_RB(b) | __PPC_EH(eh))
+   ___PPC_RT(t) | ___PPC_RA(a) | \
+   ___PPC_RB(b) | __PPC_EH(eh))
 #define PPC_MSGSND(b)  stringify_in_c(.long PPC_INST_MSGSND | \
-   __PPC_RB(b))
+   ___PPC_RB(b))
 #define PPC_POPCNTB(a, s)  stringify_in_c(.long PPC_INST_POPCNTB | \
__PPC_RA(a) | __PPC_RS(s))
 #define PPC_POPCNTD(a, s)  stringify_in_c(.long PPC_INST_POPCNTD | \
@@ -204,7 +204,7 @@
 #define PPC_WAIT(w)stringify_in_c(.long PPC_INST_WAIT | \
__PPC_WC(w))
 #define PPC_TLBIE(lp,a)stringify_in_c(.long PPC_INST_TLBIE | \
-  __PPC_RB(a) | __PPC_RS(lp))
+  ___PPC_RB(a) | ___PPC_RS(lp))
 #define PPC_TLBSRX_DOT(a,b)stringify_in_c(.long PPC_INST_TLBSRX_DOT | \
__PPC_RA(a) | __PPC_RB(b))
 #define PPC_TLBIVAX(a,b)   stringify_in_c(.long PPC_INST_TLBIVAX | \
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[PATCH 13/18] powerpc: introduce new ___PPC_RA/B/S/T macros

2012-06-20 Thread Michael Neuling 
These are currently the same as __PPC_RA/B/S/T but we'll wrap them
soon.

Signed-off-by: Michael Neuling 
---

 arch/powerpc/include/asm/ppc-opcode.h |4 
 1 file changed, 4 insertions(+)

Index: powerpc-test/arch/powerpc/include/asm/ppc-opcode.h
===
--- powerpc-test.orig/arch/powerpc/include/asm/ppc-opcode.h
+++ powerpc-test/arch/powerpc/include/asm/ppc-opcode.h
@@ -144,6 +144,10 @@
 #define PPC_INST_STBCIX0x7c0007aa
 
 /* macros to insert fields into opcodes */
+#define ___PPC_RA(a)   (((a) & 0x1f) << 16)
+#define ___PPC_RB(b)   (((b) & 0x1f) << 11)
+#define ___PPC_RS(s)   (((s) & 0x1f) << 21)
+#define ___PPC_RT(t)   ___PPC_RS(t)
 #define __PPC_RA(a)(((a) & 0x1f) << 16)
 #define __PPC_RB(b)(((b) & 0x1f) << 11)
 #define __PPC_RS(s)(((s) & 0x1f) << 21)
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[PATCH 12/18] powerpc: fix VSX macros so register names aren't wrapped

2012-06-20 Thread Michael Neuling 
We need to do this so we can enforce the name of a and b in called
macros PPC_RA/B later.

Signed-off-by: Michael Neuling 
---

 arch/powerpc/include/asm/ppc-opcode.h |6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

Index: powerpc-test/arch/powerpc/include/asm/ppc-opcode.h
===
--- powerpc-test.orig/arch/powerpc/include/asm/ppc-opcode.h
+++ powerpc-test/arch/powerpc/include/asm/ppc-opcode.h
@@ -234,11 +234,11 @@
 #define VSX_XX1(s, a, b)   (__PPC_XS(s) | __PPC_RA(a) | __PPC_RB(b))
 #define VSX_XX3(t, a, b)   (__PPC_XT(t) | __PPC_XA(a) | __PPC_XB(b))
 #define STXVD2X(s, a, b)   stringify_in_c(.long PPC_INST_STXVD2X | \
-  VSX_XX1((s), (a), (b)))
+  VSX_XX1((s), a, b))
 #define LXVD2X(s, a, b)stringify_in_c(.long PPC_INST_LXVD2X | \
-  VSX_XX1((s), (a), (b)))
+  VSX_XX1((s), a, b))
 #define XXLOR(t, a, b) stringify_in_c(.long PPC_INST_XXLOR | \
-  VSX_XX3((t), (a), (b)))
+  VSX_XX3((t), a, b))
 
 #define PPC_NAPstringify_in_c(.long PPC_INST_NAP)
 #define PPC_SLEEP  stringify_in_c(.long PPC_INST_SLEEP)
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[PATCH 11/18] powerpc: fixes for instructions not using correct register naming

2012-06-20 Thread Michael Neuling 
These macros are using integers where they could be using logical
names since they take registers.

We are going to enforce this soon, so fix these up now.

Signed-off-by: Michael Neuling 
---

 arch/powerpc/kernel/exceptions-64e.S |8 
 arch/powerpc/kernel/misc_64.S|4 ++--
 arch/powerpc/lib/ldstfp.S|4 ++--
 arch/powerpc/mm/tlb_nohash_low.S |   10 +-
 4 files changed, 13 insertions(+), 13 deletions(-)

Index: powerpc-test/arch/powerpc/kernel/exceptions-64e.S
===
--- powerpc-test.orig/arch/powerpc/kernel/exceptions-64e.S
+++ powerpc-test/arch/powerpc/kernel/exceptions-64e.S
@@ -903,7 +903,7 @@ skpinv: addir6,r6,1 /* 
Increment */
bne 1b  /* If not, repeat */
 
/* Invalidate all TLBs */
-   PPC_TLBILX_ALL(0,0)
+   PPC_TLBILX_ALL(R0,R0)
sync
isync
 
@@ -961,7 +961,7 @@ skpinv: addir6,r6,1 /* 
Increment */
tlbwe
 
/* Invalidate TLB1 */
-   PPC_TLBILX_ALL(0,0)
+   PPC_TLBILX_ALL(R0,R0)
sync
isync
 
@@ -1020,7 +1020,7 @@ skpinv:   addir6,r6,1 /* 
Increment */
tlbwe
 
/* Invalidate TLB1 */
-   PPC_TLBILX_ALL(0,0)
+   PPC_TLBILX_ALL(R0,R0)
sync
isync
 
@@ -1138,7 +1138,7 @@ a2_tlbinit_after_iprot_flush:
tlbwe
 #endif /* CONFIG_PPC_EARLY_DEBUG_WSP */
 
-   PPC_TLBILX(0,0,0)
+   PPC_TLBILX(0,R0,R0)
sync
isync
 
Index: powerpc-test/arch/powerpc/kernel/misc_64.S
===
--- powerpc-test.orig/arch/powerpc/kernel/misc_64.S
+++ powerpc-test/arch/powerpc/kernel/misc_64.S
@@ -309,7 +309,7 @@ _GLOBAL(real_205_readb)
mtmsrd  r0
sync
isync
-   LBZCIX(R3,0,R3)
+   LBZCIX(R3,R0,R3)
isync
mtmsrd  r7
sync
@@ -324,7 +324,7 @@ _GLOBAL(real_205_writeb)
mtmsrd  r0
sync
isync
-   STBCIX(R3,0,R4)
+   STBCIX(R3,R0,R4)
isync
mtmsrd  r7
sync
Index: powerpc-test/arch/powerpc/lib/ldstfp.S
===
--- powerpc-test.orig/arch/powerpc/lib/ldstfp.S
+++ powerpc-test/arch/powerpc/lib/ldstfp.S
@@ -332,7 +332,7 @@ _GLOBAL(do_lxvd2x)
beq cr7,1f
STXVD2X(0,R1,R8)
 1: li  r9,-EFAULT
-2: LXVD2X(0,0,R4)
+2: LXVD2X(0,R0,R4)
li  r9,0
 3: beq cr7,4f
bl  put_vsr
@@ -361,7 +361,7 @@ _GLOBAL(do_stxvd2x)
STXVD2X(0,R1,R8)
bl  get_vsr
 1: li  r9,-EFAULT
-2: STXVD2X(0,0,R4)
+2: STXVD2X(0,R0,R4)
li  r9,0
 3: beq cr7,4f
LXVD2X(0,R1,R8)
Index: powerpc-test/arch/powerpc/mm/tlb_nohash_low.S
===
--- powerpc-test.orig/arch/powerpc/mm/tlb_nohash_low.S
+++ powerpc-test/arch/powerpc/mm/tlb_nohash_low.S
@@ -266,7 +266,7 @@ BEGIN_MMU_FTR_SECTION
andi.   r3,r3,MMUCSR0_TLBFI@l
bne 1b
 MMU_FTR_SECTION_ELSE
-   PPC_TLBILX_ALL(0,0)
+   PPC_TLBILX_ALL(R0,R0)
 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_TLBILX)
msync
isync
@@ -279,7 +279,7 @@ BEGIN_MMU_FTR_SECTION
wrteei  0
mfspr   r4,SPRN_MAS6/* save MAS6 */
mtspr   SPRN_MAS6,r3
-   PPC_TLBILX_PID(0,0)
+   PPC_TLBILX_PID(R0,R0)
mtspr   SPRN_MAS6,r4/* restore MAS6 */
wrtee   r10
 MMU_FTR_SECTION_ELSE
@@ -331,7 +331,7 @@ _GLOBAL(_tlbil_pid)
mfmsr   r10
wrteei  0
mtspr   SPRN_MAS6,r4
-   PPC_TLBILX_PID(0,0)
+   PPC_TLBILX_PID(R0,R0)
wrtee   r10
msync
isync
@@ -343,14 +343,14 @@ _GLOBAL(_tlbil_pid_noind)
ori r4,r4,MAS6_SIND
wrteei  0
mtspr   SPRN_MAS6,r4
-   PPC_TLBILX_PID(0,0)
+   PPC_TLBILX_PID(R0,R0)
wrtee   r10
msync
isync
blr
 
 _GLOBAL(_tlbil_all)
-   PPC_TLBILX_ALL(0,0)
+   PPC_TLBILX_ALL(R0,R0)
msync
isync
blr
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[PATCH 10/18] powerpc: change LOAD_REG_ADDR to use real register names

2012-06-20 Thread Michael Neuling 
LOAD_REG_ADDR define is just a wrapper around real instructions so we
can just use real register names here (ie. lower case).

Signed-off-by: Michael Neuling 
---

 arch/powerpc/platforms/powernv/opal-wrappers.S |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Index: powerpc-test/arch/powerpc/platforms/powernv/opal-wrappers.S
===
--- powerpc-test.orig/arch/powerpc/platforms/powernv/opal-wrappers.S
+++ powerpc-test/arch/powerpc/platforms/powernv/opal-wrappers.S
@@ -32,7 +32,7 @@
std r12,PACASAVEDMSR(r13);  \
andcr12,r12,r0; \
mtmsrd  r12,1;  \
-   LOAD_REG_ADDR(R0,.opal_return); \
+   LOAD_REG_ADDR(r0,.opal_return); \
mtlrr0; \
li  r0,MSR_DR|MSR_IR;   \
andcr12,r12,r0; \
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[PATCH 9/18] powerpc: change mtcrf to use real register names

2012-06-20 Thread Michael Neuling 
mtocrf define is just a wrapper around the real instructions so we can
just use real register names here (ie. lower case).

Also remove braces in macro so this is possible.

Signed-off-by: Michael Neuling 
---

 arch/powerpc/include/asm/asm-compat.h |2 +-
 arch/powerpc/include/asm/ppc_asm.h|4 ++--
 arch/powerpc/lib/copyuser_64.S|6 +++---
 arch/powerpc/lib/mem_64.S |6 +++---
 arch/powerpc/lib/memcpy_64.S  |6 +++---
 5 files changed, 12 insertions(+), 12 deletions(-)

Index: powerpc-test/arch/powerpc/include/asm/asm-compat.h
===
--- powerpc-test.orig/arch/powerpc/include/asm/asm-compat.h
+++ powerpc-test/arch/powerpc/include/asm/asm-compat.h
@@ -29,7 +29,7 @@
 #define PPC_LLARX(t, a, b, eh) PPC_LDARX(t, a, b, eh)
 #define PPC_STLCX  stringify_in_c(stdcx.)
 #define PPC_CNTLZL stringify_in_c(cntlzd)
-#define PPC_MTOCRF(FXM, RS) MTOCRF((FXM), (RS))
+#define PPC_MTOCRF(FXM, RS) MTOCRF((FXM), RS)
 #define PPC_LR_STKOFF  16
 #define PPC_MIN_STKFRM 112
 #else /* 32-bit */
Index: powerpc-test/arch/powerpc/include/asm/ppc_asm.h
===
--- powerpc-test.orig/arch/powerpc/include/asm/ppc_asm.h
+++ powerpc-test/arch/powerpc/include/asm/ppc_asm.h
@@ -384,9 +384,9 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601)
 #ifdef CONFIG_PPC64
 #define MTOCRF(FXM, RS)\
BEGIN_FTR_SECTION_NESTED(848);  \
-   mtcrf   (FXM), (RS);\
+   mtcrf   (FXM), RS;  \
FTR_SECTION_ELSE_NESTED(848);   \
-   mtocrf (FXM), (RS); \
+   mtocrf (FXM), RS;   \
ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_NOEXECUTE, 848)
 #endif
 
Index: powerpc-test/arch/powerpc/lib/copyuser_64.S
===
--- powerpc-test.orig/arch/powerpc/lib/copyuser_64.S
+++ powerpc-test/arch/powerpc/lib/copyuser_64.S
@@ -30,7 +30,7 @@ _GLOBAL(__copy_tofrom_user_base)
dcbt0,r4
beq .Lcopy_page_4K
andi.   r6,r6,7
-   PPC_MTOCRF(0x01,R5)
+   PPC_MTOCRF(0x01,r5)
blt cr1,.Lshort_copy
 /* Below we want to nop out the bne if we're on a CPU that has the
  * CPU_FTR_UNALIGNED_LD_STD bit set and the CPU_FTR_CP_USE_DCBTZ bit
@@ -186,7 +186,7 @@ END_FTR_SECTION_IFCLR(CPU_FTR_UNALIGNED_
blr
 
 .Ldst_unaligned:
-   PPC_MTOCRF(0x01,R6) /* put #bytes to 8B bdry into cr7 */
+   PPC_MTOCRF(0x01,r6) /* put #bytes to 8B bdry into cr7 */
subfr5,r6,r5
li  r7,0
cmpldi  cr1,r5,16
@@ -201,7 +201,7 @@ END_FTR_SECTION_IFCLR(CPU_FTR_UNALIGNED_
 2: bf  cr7*4+1,3f
 37:lwzxr0,r7,r4
 83:stwxr0,r7,r3
-3: PPC_MTOCRF(0x01,R5)
+3: PPC_MTOCRF(0x01,r5)
add r4,r6,r4
add r3,r6,r3
b   .Ldst_aligned
Index: powerpc-test/arch/powerpc/lib/mem_64.S
===
--- powerpc-test.orig/arch/powerpc/lib/mem_64.S
+++ powerpc-test/arch/powerpc/lib/mem_64.S
@@ -19,7 +19,7 @@ _GLOBAL(memset)
rlwimi  r4,r4,16,0,15
cmplw   cr1,r5,r0   /* do we get that far? */
rldimi  r4,r4,32,0
-   PPC_MTOCRF(1,R0)
+   PPC_MTOCRF(1,r0)
mr  r6,r3
blt cr1,8f
beq+3f  /* if already 8-byte aligned */
@@ -49,7 +49,7 @@ _GLOBAL(memset)
bdnz4b
 5: srwi.   r0,r5,3
clrlwi  r5,r5,29
-   PPC_MTOCRF(1,R0)
+   PPC_MTOCRF(1,r0)
beq 8f
bf  29,6f
std r4,0(r6)
@@ -65,7 +65,7 @@ _GLOBAL(memset)
std r4,0(r6)
addir6,r6,8
 8: cmpwi   r5,0
-   PPC_MTOCRF(1,R5)
+   PPC_MTOCRF(1,r5)
beqlr+
bf  29,9f
stw r4,0(r6)
Index: powerpc-test/arch/powerpc/lib/memcpy_64.S
===
--- powerpc-test.orig/arch/powerpc/lib/memcpy_64.S
+++ powerpc-test/arch/powerpc/lib/memcpy_64.S
@@ -16,7 +16,7 @@ BEGIN_FTR_SECTION
 FTR_SECTION_ELSE
b   memcpy_power7
 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_VMX_COPY)
-   PPC_MTOCRF(0x01,R5)
+   PPC_MTOCRF(0x01,r5)
cmpldi  cr1,r5,16
neg r6,r3   # LS 3 bits = # bytes to 8-byte dest bdry
andi.   r6,r6,7
@@ -158,7 +158,7 @@ END_FTR_SECTION_IFCLR(CPU_FTR_UNALIGNED_
blr
 
 .Ldst_unaligned:
-   PPC_MTOCRF(0x01,R6) # put #bytes to 8B bdry into cr7
+   PPC_MTOCRF(0x01,r6) # put #bytes to 8B bdry into cr7
subfr5,r6,r5
li  r7,0
cmpldi  cr1,r5,16
@@ -173,7 +173,7 @@ END_FTR_SECTION_IFCLR(CPU_FTR_UNALIGNED_
 2: bf  cr7*4+1,3f
lwzxr0,r7,r4
stwxr0,r7,r3
-3: PPC_MTOCRF(0x01,R5)
+3: PPC_MTOCRF(0x01,r5)
add r4,r6,r4
add r3,r6,r3

[PATCH 8/18] powerpc: merge VCPU_GPR

2012-06-20 Thread Michael Neuling 
Merge the defines of VCPU_GPR from different places.

Signed-off-by: Michael Neuling 
---

 arch/powerpc/include/asm/ppc_asm.h  |7 +++
 arch/powerpc/kvm/book3s_hv_rmhandlers.S |3 ---
 arch/powerpc/kvm/book3s_interrupts.S|8 
 arch/powerpc/kvm/booke_interrupts.S |2 --
 arch/powerpc/kvm/bookehv_interrupts.S   |1 -
 5 files changed, 7 insertions(+), 14 deletions(-)

Index: powerpc-test/arch/powerpc/include/asm/ppc_asm.h
===
--- powerpc-test.orig/arch/powerpc/include/asm/ppc_asm.h
+++ powerpc-test/arch/powerpc/include/asm/ppc_asm.h
@@ -178,6 +178,13 @@ END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLP
 #define HMT_HIGH   or  3,3,3
 #define HMT_EXTRA_HIGH or  7,7,7   # power7 only
 
+#ifdef CONFIG_PPC64
+#define ULONG_SIZE 8
+#else
+#define ULONG_SIZE 4
+#endif
+#define VCPU_GPR(n)(VCPU_GPRS + (n * ULONG_SIZE))
+
 #ifdef __KERNEL__
 #ifdef CONFIG_PPC64
 
Index: powerpc-test/arch/powerpc/kvm/book3s_hv_rmhandlers.S
===
--- powerpc-test.orig/arch/powerpc/kvm/book3s_hv_rmhandlers.S
+++ powerpc-test/arch/powerpc/kvm/book3s_hv_rmhandlers.S
@@ -72,9 +72,6 @@ _GLOBAL(kvmppc_hv_entry_trampoline)
mtsrr1  r6
RFI
 
-#define ULONG_SIZE 8
-#define VCPU_GPR(n)(VCPU_GPRS + (n * ULONG_SIZE))
-
 /**
  **
  *   Entry code   *
Index: powerpc-test/arch/powerpc/kvm/book3s_interrupts.S
===
--- powerpc-test.orig/arch/powerpc/kvm/book3s_interrupts.S
+++ powerpc-test/arch/powerpc/kvm/book3s_interrupts.S
@@ -25,19 +25,11 @@
 #include 
 
 #if defined(CONFIG_PPC_BOOK3S_64)
-
-#define ULONG_SIZE 8
 #define FUNC(name) GLUE(.,name)
-
 #elif defined(CONFIG_PPC_BOOK3S_32)
-
-#define ULONG_SIZE  4
 #define FUNC(name) name
-
 #endif /* CONFIG_PPC_BOOK3S_XX */
 
-
-#define VCPU_GPR(n)(VCPU_GPRS + (n * ULONG_SIZE))
 #define VCPU_LOAD_NVGPRS(vcpu) \
PPC_LL  r14, VCPU_GPR(R14)(vcpu); \
PPC_LL  r15, VCPU_GPR(R15)(vcpu); \
Index: powerpc-test/arch/powerpc/kvm/booke_interrupts.S
===
--- powerpc-test.orig/arch/powerpc/kvm/booke_interrupts.S
+++ powerpc-test/arch/powerpc/kvm/booke_interrupts.S
@@ -25,8 +25,6 @@
 #include 
 #include 
 
-#define VCPU_GPR(n) (VCPU_GPRS + (n * 4))
-
 /* The host stack layout: */
 #define HOST_R1 0 /* Implied by stwu. */
 #define HOST_CALLEE_LR  4
Index: powerpc-test/arch/powerpc/kvm/bookehv_interrupts.S
===
--- powerpc-test.orig/arch/powerpc/kvm/bookehv_interrupts.S
+++ powerpc-test/arch/powerpc/kvm/bookehv_interrupts.S
@@ -37,7 +37,6 @@
 
 #define LONGBYTES  (BITS_PER_LONG / 8)
 
-#define VCPU_GPR(n)(VCPU_GPRS + (n * LONGBYTES))
 #define VCPU_GUEST_SPRG(n) (VCPU_GUEST_SPRGS + (n * LONGBYTES))
 
 /* The host stack layout: */
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[PATCH 7/18] powerpc: merge STK_REG/PARAM/FRAMESIZE

2012-06-20 Thread Michael Neuling 
Merge the defines of STACKFRAMESIZE, STK_REG, STK_PARAM from different
places.  

Signed-off-by: Michael Neuling 
---

 arch/powerpc/include/asm/ppc_asm.h |5 +
 arch/powerpc/lib/checksum_64.S |3 
 arch/powerpc/lib/copypage_power7.S |3 
 arch/powerpc/lib/copyuser_power7.S |3 
 arch/powerpc/lib/memcpy_power7.S   |3 
 arch/powerpc/mm/hash_low_64.S  |   88 +++--
 arch/powerpc/platforms/cell/beat_hvCall.S  |   28 +++
 arch/powerpc/platforms/powernv/opal-takeover.S |2 
 arch/powerpc/platforms/pseries/hvCall.S|   72 +---
 9 files changed, 93 insertions(+), 114 deletions(-)

Index: powerpc-test/arch/powerpc/include/asm/ppc_asm.h
===
--- powerpc-test.orig/arch/powerpc/include/asm/ppc_asm.h
+++ powerpc-test/arch/powerpc/include/asm/ppc_asm.h
@@ -181,6 +181,11 @@ END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLP
 #ifdef __KERNEL__
 #ifdef CONFIG_PPC64
 
+#define STACKFRAMESIZE 256
+#define STK_REG(i) (112 + ((i)-14)*8)
+
+#define STK_PARAM(i)   (48 + ((i)-3)*8)
+
 #define XGLUE(a,b) a##b
 #define GLUE(a,b) XGLUE(a,b)
 
Index: powerpc-test/arch/powerpc/lib/checksum_64.S
===
--- powerpc-test.orig/arch/powerpc/lib/checksum_64.S
+++ powerpc-test/arch/powerpc/lib/checksum_64.S
@@ -65,9 +65,6 @@ _GLOBAL(csum_tcpudp_magic)
srwir3,r3,16
blr
 
-#define STACKFRAMESIZE 256
-#define STK_REG(i) (112 + ((i)-14)*8)
-
 /*
  * Computes the checksum of a memory block at buff, length len,
  * and adds in "sum" (32-bit).
Index: powerpc-test/arch/powerpc/lib/copypage_power7.S
===
--- powerpc-test.orig/arch/powerpc/lib/copypage_power7.S
+++ powerpc-test/arch/powerpc/lib/copypage_power7.S
@@ -20,9 +20,6 @@
 #include 
 #include 
 
-#define STACKFRAMESIZE 256
-#define STK_REG(i) (112 + ((i)-14)*8)
-
 _GLOBAL(copypage_power7)
/*
 * We prefetch both the source and destination using enhanced touch
Index: powerpc-test/arch/powerpc/lib/copyuser_power7.S
===
--- powerpc-test.orig/arch/powerpc/lib/copyuser_power7.S
+++ powerpc-test/arch/powerpc/lib/copyuser_power7.S
@@ -19,9 +19,6 @@
  */
 #include 
 
-#define STACKFRAMESIZE 256
-#define STK_REG(i) (112 + ((i)-14)*8)
-
.macro err1
 100:
.section __ex_table,"a"
Index: powerpc-test/arch/powerpc/lib/memcpy_power7.S
===
--- powerpc-test.orig/arch/powerpc/lib/memcpy_power7.S
+++ powerpc-test/arch/powerpc/lib/memcpy_power7.S
@@ -19,9 +19,6 @@
  */
 #include 
 
-#define STACKFRAMESIZE 256
-#define STK_REG(i) (112 + ((i)-14)*8)
-
 _GLOBAL(memcpy_power7)
 #ifdef CONFIG_ALTIVEC
cmpldi  r5,16
Index: powerpc-test/arch/powerpc/mm/hash_low_64.S
===
--- powerpc-test.orig/arch/powerpc/mm/hash_low_64.S
+++ powerpc-test/arch/powerpc/mm/hash_low_64.S
@@ -34,14 +34,6 @@
  * |   CR save area(SP + 8)
  * SP ---> +-- Back chain  (SP + 0)
  */
-#define STACKFRAMESIZE 256
-
-/* Save parameters offsets */
-#define STK_PARM(i)(STACKFRAMESIZE + 48 + ((i)-3)*8)
-
-/* Save non-volatile offsets */
-#define STK_REG(i) (112 + ((i)-14)*8)
-
 
 #ifndef CONFIG_PPC_64K_PAGES
 
@@ -64,9 +56,9 @@ _GLOBAL(__hash_page_4K)
std r0,16(r1)
stdur1,-STACKFRAMESIZE(r1)
/* Save all params that we need after a function call */
-   std r6,STK_PARM(R6)(r1)
-   std r8,STK_PARM(R8)(r1)
-   std r9,STK_PARM(R9)(r1)
+   std r6,STK_PARAM(R6)(r1)
+   std r8,STK_PARAM(R8)(r1)
+   std r9,STK_PARAM(R9)(r1)

/* Save non-volatile registers.
 * r31 will hold "old PTE"
@@ -162,7 +154,7 @@ END_FTR_SECTION(CPU_FTR_NOEXECUTE|CPU_FT
/* At this point, r3 contains new PP bits, save them in
 * place of "access" in the param area (sic)
 */
-   std r3,STK_PARM(R4)(r1)
+   std r3,STK_PARAM(R4)(r1)
 
/* Get htab_hash_mask */
ld  r4,htab_hash_mask@got(2)
@@ -192,11 +184,11 @@ htab_insert_pte:
rldicr  r3,r0,3,63-3/* r3 = (hash & mask) << 3 */
 
/* Call ppc_md.hpte_insert */
-   ld  r6,STK_PARM(R4)(r1) /* Retrieve new pp bits */
+   ld  r6,STK_PARAM(R4)(r1)/* Retrieve new pp bits */
mr  r4,r29  /* Retrieve va */
li  r7,0/* !bolted, !secondary */
li  r8,MMU_PAGE_4K  /* page size */
-   ld  r9,STK_PARM(R9)(r1) /* segment size */
+   ld  r9,STK_PARAM(R9)(r1)/* segment size */
 _GLOBAL(htab_call_hpte_insert1)

[PATCH 6/18] powerpc/pasemi: move lbz/stbciz to ppc-opcode.h

2012-06-20 Thread Michael Neuling 
move lbz/stbciz to ppc-opcode.h.

Signed-off-by: Michael Neuling 
---

 arch/powerpc/include/asm/ppc-opcode.h |7 +++
 arch/powerpc/kernel/misc_64.S |5 -
 2 files changed, 7 insertions(+), 5 deletions(-)

Index: powerpc-test/arch/powerpc/include/asm/ppc-opcode.h
===
--- powerpc-test.orig/arch/powerpc/include/asm/ppc-opcode.h
+++ powerpc-test/arch/powerpc/include/asm/ppc-opcode.h
@@ -140,6 +140,8 @@
 #define PPC_INST_NEG   0x7cd0
 #define PPC_INST_BRANCH0x4800
 #define PPC_INST_BRANCH_COND   0x4080
+#define PPC_INST_LBZCIX0x7c0006aa
+#define PPC_INST_STBCIX0x7c0007aa
 
 /* macros to insert fields into opcodes */
 #define __PPC_RA(a)(((a) & 0x1f) << 16)
@@ -219,6 +221,11 @@
__PPC_RS(t) | __PPC_RA(a) | __PPC_RB(b))
 #define PPC_SLBFEE_DOT(t, b)   stringify_in_c(.long PPC_INST_SLBFEE | \
__PPC_RT(t) | __PPC_RB(b))
+/* PASemi instructions */
+#define LBZCIX(t,a,b)  stringify_in_c(.long PPC_INST_LBZCIX | \
+  __PPC_RT(t) | __PPC_RA(a) | __PPC_RB(b))
+#define STBCIX(s,a,b)  stringify_in_c(.long PPC_INST_STBCIX | \
+  __PPC_RS(s) | __PPC_RA(a) | __PPC_RB(b))
 
 /*
  * Define what the VSX XX1 form instructions will look like, then add
Index: powerpc-test/arch/powerpc/kernel/misc_64.S
===
--- powerpc-test.orig/arch/powerpc/kernel/misc_64.S
+++ powerpc-test/arch/powerpc/kernel/misc_64.S
@@ -301,11 +301,6 @@ _GLOBAL(real_writeb)
 
 #ifdef CONFIG_PPC_PASEMI
 
-/* No support in all binutils for these yet, so use defines */
-#define LBZCIX(RT,RA,RB)  .long (0x7c0006aa|(RT<<21)|(RA<<16)|(RB << 11))
-#define STBCIX(RS,RA,RB)  .long (0x7c0007aa|(RS<<21)|(RA<<16)|(RB << 11))
-
-
 _GLOBAL(real_205_readb)
mfmsr   r7
ori r0,r7,MSR_DR
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[PATCH 5/18] powerpc: convert to %r for all GPR usage

2012-06-20 Thread Michael Neuling 
Now all the fixes are in place, let's rock-n-roll!

Signed-off-by: Michael Neuling 
---

 arch/powerpc/include/asm/ppc_asm.h |   72 -
 1 file changed, 39 insertions(+), 33 deletions(-)

Index: powerpc-test/arch/powerpc/include/asm/ppc_asm.h
===
--- powerpc-test.orig/arch/powerpc/include/asm/ppc_asm.h
+++ powerpc-test/arch/powerpc/include/asm/ppc_asm.h
@@ -490,40 +490,46 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601)
 #definecr7 7
 
 
-/* General Purpose Registers (GPRs) */
+/*
+ * General Purpose Registers (GPRs)
+ *
+ * The lower case r0-r31 should be used in preference to the upper
+ * case R0-R31 as they provide more error checking in the assembler.
+ * Use R0-31 only when really nessesary.
+ */
 
-#definer0  0
-#definer1  1
-#definer2  2
-#definer3  3
-#definer4  4
-#definer5  5
-#definer6  6
-#definer7  7
-#definer8  8
-#definer9  9
-#definer10 10
-#definer11 11
-#definer12 12
-#definer13 13
-#definer14 14
-#definer15 15
-#definer16 16
-#definer17 17
-#definer18 18
-#definer19 19
-#definer20 20
-#definer21 21
-#definer22 22
-#definer23 23
-#definer24 24
-#definer25 25
-#definer26 26
-#definer27 27
-#definer28 28
-#definer29 29
-#definer30 30
-#definer31 31
+#definer0  %r0
+#definer1  %r1
+#definer2  %r2
+#definer3  %r3
+#definer4  %r4
+#definer5  %r5
+#definer6  %r6
+#definer7  %r7
+#definer8  %r8
+#definer9  %r9
+#definer10 %r10
+#definer11 %r11
+#definer12 %r12
+#definer13 %r13
+#definer14 %r14
+#definer15 %r15
+#definer16 %r16
+#definer17 %r17
+#definer18 %r18
+#definer19 %r19
+#definer20 %r20
+#definer21 %r21
+#definer22 %r22
+#definer23 %r23
+#definer24 %r24
+#definer25 %r25
+#definer26 %r26
+#definer27 %r27
+#definer28 %r28
+#definer29 %r29
+#definer30 %r30
+#definer31 %r31
 
 
 /* Floating Point Registers (FPRs) */
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[PATCH 4/18] powerpc/kvm: sldi should be sld

2012-06-20 Thread Michael Neuling 
Since we are taking a registers, this should never have been an sldi.
Talking to paulus offline, this is the correct fix.

Was introduced by:
 commit 19ccb76a1938ab364a412253daec64613acbf3df
 Author: Paul Mackerras 
 Date:   Sat Jul 23 17:42:46 2011 +1000

Talking to paulus, this shouldn't be a literal.

Signed-off-by: Michael Neuling 
---

 arch/powerpc/kvm/book3s_hv_rmhandlers.S |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Index: powerpc-test/arch/powerpc/kvm/book3s_hv_rmhandlers.S
===
--- powerpc-test.orig/arch/powerpc/kvm/book3s_hv_rmhandlers.S
+++ powerpc-test/arch/powerpc/kvm/book3s_hv_rmhandlers.S
@@ -810,7 +810,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
lwz r3,VCORE_NAPPING_THREADS(r5)
lwz r4,VCPU_PTID(r9)
li  r0,1
-   sldir0,r0,r4
+   sld r0,r0,r4
andc.   r3,r3,r0/* no sense IPI'ing ourselves */
beq 43f
mulli   r4,r4,PACA_SIZE /* get paca for thread 0 */
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[PATCH 2/18] powerpc: modify macro ready for %r0 register change

2012-06-20 Thread Michael Neuling 
The assembler doesn't take %r0 register arguments in braces, so remove them.

Signed-off-by: Michael Neuling 
---

 arch/powerpc/include/asm/ppc_asm.h |   18 +-
 1 file changed, 9 insertions(+), 9 deletions(-)

Index: powerpc-test/arch/powerpc/include/asm/ppc_asm.h
===
--- powerpc-test.orig/arch/powerpc/include/asm/ppc_asm.h
+++ powerpc-test/arch/powerpc/include/asm/ppc_asm.h
@@ -295,14 +295,14 @@ n:
  */
 #ifdef __powerpc64__
 #define LOAD_REG_IMMEDIATE(reg,expr)   \
-   lis (reg),(expr)@highest;   \
-   ori (reg),(reg),(expr)@higher;  \
-   rldicr  (reg),(reg),32,31;  \
-   oris(reg),(reg),(expr)@h;   \
-   ori (reg),(reg),(expr)@l;
+   lis reg,(expr)@highest; \
+   ori reg,reg,(expr)@higher;  \
+   rldicr  reg,reg,32,31;  \
+   orisreg,reg,(expr)@h;   \
+   ori reg,reg,(expr)@l;
 
 #define LOAD_REG_ADDR(reg,name)\
-   ld  (reg),name@got(r2)
+   ld  reg,name@got(r2)
 
 #define LOAD_REG_ADDRBASE(reg,name)LOAD_REG_ADDR(reg,name)
 #define ADDROFF(name)  0
@@ -313,12 +313,12 @@ n:
 #else /* 32-bit */
 
 #define LOAD_REG_IMMEDIATE(reg,expr)   \
-   lis (reg),(expr)@ha;\
-   addi(reg),(reg),(expr)@l;
+   lis reg,(expr)@ha;  \
+   addireg,reg,(expr)@l;
 
 #define LOAD_REG_ADDR(reg,name)LOAD_REG_IMMEDIATE(reg, name)
 
-#define LOAD_REG_ADDRBASE(reg, name)   lis (reg),name@ha
+#define LOAD_REG_ADDRBASE(reg, name)   lis reg,name@ha
 #define ADDROFF(name)  name@l
 
 /* offsets for stack frame layout */
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[PATCH 1/18] powerpc: Add defines for R0-R31

2012-06-20 Thread Michael Neuling 
We are going to use these later and convert r0 to %r0 etc.

Signed-off-by: Michael Neuling 
---

 arch/powerpc/include/asm/ppc-opcode.h |   33 +
 1 file changed, 33 insertions(+)

Index: powerpc-test/arch/powerpc/include/asm/ppc-opcode.h
===
--- powerpc-test.orig/arch/powerpc/include/asm/ppc-opcode.h
+++ powerpc-test/arch/powerpc/include/asm/ppc-opcode.h
@@ -15,6 +15,39 @@
 #include 
 #include 
 
+#defineR0  0
+#defineR1  1
+#defineR2  2
+#defineR3  3
+#defineR4  4
+#defineR5  5
+#defineR6  6
+#defineR7  7
+#defineR8  8
+#defineR9  9
+#defineR10 10
+#defineR11 11
+#defineR12 12
+#defineR13 13
+#defineR14 14
+#defineR15 15
+#defineR16 16
+#defineR17 17
+#defineR18 18
+#defineR19 19
+#defineR20 20
+#defineR21 21
+#defineR22 22
+#defineR23 23
+#defineR24 24
+#defineR25 25
+#defineR26 26
+#defineR27 27
+#defineR28 28
+#defineR29 29
+#defineR30 30
+#defineR31 31
+
 /* sorted alphabetically */
 #define PPC_INST_DCBA  0x7c0005ec
 #define PPC_INST_DCBA_MASK 0xfc0007fe
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[PATCH 0/18] powerpc: convert GPR usage to %r0-31 and R0-31

2012-06-20 Thread Michael Neuling 
First 5 patches convert us to %r0-31.

Next 12 convert make using R0-31 required in macros.

Last 2 convert instructions where ra = r0 we use 0 rather than the
register value (as suggested by Andreas).

Version 3 adds:
  Fixes for chroma (moved some defines ppc_asm.h -> ppc-opcode.h)
  Fixed comment in sldi patch to reflect new change (thanks Segher)

Version 2 adds:
  ra = 0 idea (as Andreas suggested)
  Fixes for 32bit KVM (added ppc44x_defconfig to my testing)
  Based on mpe's next tree which has Antons power7 copy patches which
needed fixes for this

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Re: [PATCH] i2c: let the core register devices from devicetree

2012-06-20 Thread Barry Song 
2012/6/14 Wolfram Sang :
> Currently, every driver has to do it on its own, but it should be done
> in the core, like we already do with board_info structs.
>
> Signed-off-by: Wolfram Sang 

Acked-by: Barry Song 

> ---
>
> Based on v3.5-rc2. Only build tested, I don't have a OF based device
> around at the moment.
>
> @Peter: Why does ocores do the device registration manually via
> platform_data instead of using board_info?
>
>  drivers/i2c/busses/i2c-cpm.c                |    5 -
>  drivers/i2c/busses/i2c-designware-platdrv.c |    1 -
>  drivers/i2c/busses/i2c-gpio.c               |    2 --
>  drivers/i2c/busses/i2c-ibm_iic.c            |    3 ---
>  drivers/i2c/busses/i2c-imx.c                |    2 --
>  drivers/i2c/busses/i2c-mpc.c                |    1 -
>  drivers/i2c/busses/i2c-mxs.c                |    2 --
>  drivers/i2c/busses/i2c-ocores.c             |    2 --
>  drivers/i2c/busses/i2c-omap.c               |    2 --
>  drivers/i2c/busses/i2c-pnx.c                |    2 --
>  drivers/i2c/busses/i2c-pxa.c                |    1 -
>  drivers/i2c/busses/i2c-s3c2410.c            |    1 -
>  drivers/i2c/busses/i2c-sh_mobile.c          |    1 -
>  drivers/i2c/busses/i2c-tegra.c              |    2 --
>  drivers/i2c/busses/i2c-versatile.c          |    1 -
>  drivers/i2c/busses/i2c-xiic.c               |    2 --
>  drivers/i2c/i2c-core.c                      |    3 +++
>  17 files changed, 3 insertions(+), 30 deletions(-)

-barry
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Re: [PATCH] PPC: PCI: Fix pcibios_io_space_offset() so it works for 32-bit ptr/64-bit rsrcs

2012-06-20 Thread Bjorn Helgaas 
On Mon, Jun 18, 2012 at 2:39 PM, Benjamin Herrenschmidt
 wrote:
> On Mon, 2012-06-18 at 09:23 -0600, Bjorn Helgaas wrote:
>> Ooh, sorry about that.  Who's going to push this fix?  I don't see it
>> in Linus' tree yet.  If you want me to, please forward me the original
>> patch.
>
> I want to double check something. We are still printing something wrong
> in the kernel log, so it looks like we have some incorrect carry in some
> arithmetic happening somewhere.

Probably not related to whatever you're seeing, but just FYI, I think
the core has a sign-extension bug related to P2P bridge I/O windows:

http://marc.info/?l=linux-pci&m=134023801524895&w=2
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Re: [PATCH] MIPS: fix bug.h MIPS build regression

2012-06-20 Thread Ralf Baechle 
On Wed, Jun 20, 2012 at 03:27:59PM +0900, Yoichi Yuasa wrote:

> Commit: 3777808873b0c49c5cf27e44c948dfb02675d578 breaks all MIPS builds.

Thanks, fix applied.

  Ralf
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Re: Build regressions/improvements in v3.5-rc3

2012-06-20 Thread Giuseppe CAVALLARO 
Hello Paul

On 6/20/2012 5:59 AM, Paul Mundt wrote:
> On Sun, Jun 17, 2012 at 09:56:59PM +0200, Geert Uytterhoeven wrote:
>> On Sun, Jun 17, 2012 at 9:46 PM, Geert Uytterhoeven
>>  wrote:
>>> JFYI, when comparing v3.5-rc3 to v3.5-rc2[3], the summaries are:
>>> ??- build errors: +235/-10
>>
>> Truckloads of powerpc "Unrecognized opcode" breakage, and
>>
> That was my fault, should be fixed up by 2603efa31a.
> 
>>   + drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c: error: implicit
>> declaration of function 'pci_iomap'
>> [-Werror=implicit-function-declaration]:  => 90:3
>>   + drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c: error: implicit
>> declaration of function 'pci_iounmap'
>> [-Werror=implicit-function-declaration]:  => 142:2
>>
> Not sure about this one, it should find everything alright via:
> 
>   linux/io.h -> asm/io.h -> asm-generic/iomap.h -> asm-generic/pci_iomap.h
> 
> in the case that PCI is enabled. None of allyesconfig/modconfig enable
> PCI for me though, so I'm unsure of how you got in to this configuration
> to begin with?

Trying to reproduce the problem, I've also re-built the mainstream
kernel 3.5-rc3 for se7724_defconfig platform plus the stmmac (pltf and
pci) but all compiles fine.

I've also verified that there is the 33d5e332b9c5 commit that is the
latest one discussed/tested/committed in the network mailing list.

Can you tell me how to reproduce the problem? How can I help?

Pls let me know,
Peppe
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Re: [PATCH] MIPS: fix bug.h MIPS build regression

2012-06-20 Thread John Crispin 
On 20/06/12 08:27, Yoichi Yuasa wrote:
> Commit: 3777808873b0c49c5cf27e44c948dfb02675d578 breaks all MIPS builds.
> 

Hi Yoichi,

I stumbled across the same build regression last night and came up with
almost the same fix :-)

Tested-by: John Crispin 

Thanks,
John
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Re: [PATCH] MIPS: fix bug.h MIPS build regression

2012-06-20 Thread Sergei Shtylyov 

Hello.

On 20-06-2012 10:27, Yoichi Yuasa wrote:


Commit: 3777808873b0c49c5cf27e44c948dfb02675d578


   Please also specify the summary of that commit in parens.


breaks all MIPS builds.


[...]


Signed-off-by: Yoichi Yuasa


WBR, Sergei

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Re: linux-next: build failure after merge of the final tree (powerpc related)

2012-06-20 Thread Benjamin Herrenschmidt 
On Wed, 2012-06-20 at 17:50 +1000, Stephen Rothwell wrote:
> Hi all,
> 
> After merging the final tree, today's linux-next build (powerpc
> allyesconfig) failed like this:

I hate our ABI is a good answer ? :-)

I'll see what I can do tomorrow. Poke me when I'm in the office.

Cheers,
Ben.

> powerpc64-linux-ld: arch/powerpc/net/built-in.o: In function 
> `bpf_slow_path_word':
> (.text+0x90): sibling call optimization to `skb_copy_bits' does not allow 
> automatic multiple TOCs; recompile with -mminimal-toc or 
> -fno-optimize-sibling-calls, or make `skb_copy_bits' extern
> powerpc64-linux-ld: arch/powerpc/net/built-in.o: In function 
> `bpf_slow_path_half':
> (.text+0xe0): sibling call optimization to `skb_copy_bits' does not allow 
> automatic multiple TOCs; recompile with -mminimal-toc or 
> -fno-optimize-sibling-calls, or make `skb_copy_bits' extern
> powerpc64-linux-ld: arch/powerpc/net/built-in.o: In function 
> `bpf_slow_path_byte':
> (.text+0x130): sibling call optimization to `skb_copy_bits' does not allow 
> automatic multiple TOCs; recompile with -mminimal-toc or 
> -fno-optimize-sibling-calls, or make `skb_copy_bits' extern
> powerpc64-linux-ld: arch/powerpc/net/built-in.o: In function 
> `bpf_slow_path_byte_msh':
> (.text+0x180): sibling call optimization to `skb_copy_bits' does not allow 
> automatic multiple TOCs; recompile with -mminimal-toc or 
> -fno-optimize-sibling-calls, or make `skb_copy_bits' extern
> powerpc64-linux-ld: arch/powerpc/net/built-in.o: In function 
> `sk_load_word_negative_offset':
> (.text+0x1dc): sibling call optimization to 
> `bpf_internal_load_pointer_neg_helper' does not allow automatic multiple 
> TOCs; recompile with -mminimal-toc or -fno-optimize-sibling-calls, or make 
> `bpf_internal_load_pointer_neg_helper' extern
> powerpc64-linux-ld: arch/powerpc/net/built-in.o: In function 
> `sk_load_half_negative_offset':
> (.text+0x238): sibling call optimization to 
> `bpf_internal_load_pointer_neg_helper' does not allow automatic multiple 
> TOCs; recompile with -mminimal-toc or -fno-optimize-sibling-calls, or make 
> `bpf_internal_load_pointer_neg_helper' extern
> powerpc64-linux-ld: arch/powerpc/net/built-in.o: In function 
> `sk_load_byte_negative_offset':
> (.text+0x294): sibling call optimization to 
> `bpf_internal_load_pointer_neg_helper' does not allow automatic multiple 
> TOCs; recompile with -mminimal-toc or -fno-optimize-sibling-calls, or make 
> `bpf_internal_load_pointer_neg_helper' extern
> powerpc64-linux-ld: arch/powerpc/net/built-in.o: In function 
> `sk_load_byte_msh_negative_offset':
> (.text+0x2f0): sibling call optimization to 
> `bpf_internal_load_pointer_neg_helper' does not allow automatic multiple 
> TOCs; recompile with -mminimal-toc or -fno-optimize-sibling-calls, or make 
> `bpf_internal_load_pointer_neg_helper' extern
> powerpc64-linux-ld: final link failed: Bad value
> 
> I started building with gcc 4.6.3/binutils 2.22 today.  gcc
> 4.6.0/binutils 2.21 do not produce this error, it produces this instead
> (which has been happening for a long time):
> 
> powerpc64-linux-ld: TOC section size exceeds 64k
> 


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Re: Build regressions/improvements in v3.5-rc3

2012-06-20 Thread Geert Uytterhoeven 
On Wed, Jun 20, 2012 at 5:59 AM, Paul Mundt  wrote:
> On Sun, Jun 17, 2012 at 09:56:59PM +0200, Geert Uytterhoeven wrote:
>> On Sun, Jun 17, 2012 at 9:46 PM, Geert Uytterhoeven
>>  wrote:
>> > JFYI, when comparing v3.5-rc3 to v3.5-rc2[3], the summaries are:
>> > ??- build errors: +235/-10
>>
>> Truckloads of powerpc "Unrecognized opcode" breakage, and
>>
> That was my fault, should be fixed up by 2603efa31a.
>
>>   + drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c: error: implicit
>> declaration of function 'pci_iomap'
>> [-Werror=implicit-function-declaration]:  => 90:3
>>   + drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c: error: implicit
>> declaration of function 'pci_iounmap'
>> [-Werror=implicit-function-declaration]:  => 142:2
>>
> Not sure about this one, it should find everything alright via:
>
>        linux/io.h -> asm/io.h -> asm-generic/iomap.h -> 
> asm-generic/pci_iomap.h
>
> in the case that PCI is enabled. None of allyesconfig/modconfig enable
> PCI for me though, so I'm unsure of how you got in to this configuration
> to begin with?

These were xtensa, not sh.

The ones above ("error: expected expression before 'do'") were sh.

>>   + error: "__ashrdi3" [fs/ntfs/ntfs.ko] undefined!:  => N/A
>>   + error: "__lshrdi3" [fs/ntfs/ntfs.ko] undefined!:  => N/A
>>
>> sh4/landisk_defconfig
>>
>>   + error: "__ashrdi3" [fs/xfs/xfs.ko] undefined!:  => N/A
>>   + error: "__lshrdi3" [drivers/mtd/mtd.ko] undefined!:  => N/A
>>   + error: "__lshrdi3" [fs/xfs/xfs.ko] undefined!:  => N/A
>>
> These seem to be the same issue on both platforms, EXPORT_SYMBOL()
> doesn't work from lib-y. While it's straightforward to fix, I'm not able
> to reproduce __lshrdi3/__ashrdi3 references in any of the above, which
> compiler are you using?

http://kisskb.ellerman.id.au/kisskb/buildresult/6543287/ says
sh4-linux-gcc (GCC) 4.6.3

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds
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linux-next: build failure after merge of the final tree (powerpc related)

2012-06-20 Thread Stephen Rothwell 
Hi all,

After merging the final tree, today's linux-next build (powerpc
allyesconfig) failed like this:

powerpc64-linux-ld: arch/powerpc/net/built-in.o: In function 
`bpf_slow_path_word':
(.text+0x90): sibling call optimization to `skb_copy_bits' does not allow 
automatic multiple TOCs; recompile with -mminimal-toc or 
-fno-optimize-sibling-calls, or make `skb_copy_bits' extern
powerpc64-linux-ld: arch/powerpc/net/built-in.o: In function 
`bpf_slow_path_half':
(.text+0xe0): sibling call optimization to `skb_copy_bits' does not allow 
automatic multiple TOCs; recompile with -mminimal-toc or 
-fno-optimize-sibling-calls, or make `skb_copy_bits' extern
powerpc64-linux-ld: arch/powerpc/net/built-in.o: In function 
`bpf_slow_path_byte':
(.text+0x130): sibling call optimization to `skb_copy_bits' does not allow 
automatic multiple TOCs; recompile with -mminimal-toc or 
-fno-optimize-sibling-calls, or make `skb_copy_bits' extern
powerpc64-linux-ld: arch/powerpc/net/built-in.o: In function 
`bpf_slow_path_byte_msh':
(.text+0x180): sibling call optimization to `skb_copy_bits' does not allow 
automatic multiple TOCs; recompile with -mminimal-toc or 
-fno-optimize-sibling-calls, or make `skb_copy_bits' extern
powerpc64-linux-ld: arch/powerpc/net/built-in.o: In function 
`sk_load_word_negative_offset':
(.text+0x1dc): sibling call optimization to 
`bpf_internal_load_pointer_neg_helper' does not allow automatic multiple TOCs; 
recompile with -mminimal-toc or -fno-optimize-sibling-calls, or make 
`bpf_internal_load_pointer_neg_helper' extern
powerpc64-linux-ld: arch/powerpc/net/built-in.o: In function 
`sk_load_half_negative_offset':
(.text+0x238): sibling call optimization to 
`bpf_internal_load_pointer_neg_helper' does not allow automatic multiple TOCs; 
recompile with -mminimal-toc or -fno-optimize-sibling-calls, or make 
`bpf_internal_load_pointer_neg_helper' extern
powerpc64-linux-ld: arch/powerpc/net/built-in.o: In function 
`sk_load_byte_negative_offset':
(.text+0x294): sibling call optimization to 
`bpf_internal_load_pointer_neg_helper' does not allow automatic multiple TOCs; 
recompile with -mminimal-toc or -fno-optimize-sibling-calls, or make 
`bpf_internal_load_pointer_neg_helper' extern
powerpc64-linux-ld: arch/powerpc/net/built-in.o: In function 
`sk_load_byte_msh_negative_offset':
(.text+0x2f0): sibling call optimization to 
`bpf_internal_load_pointer_neg_helper' does not allow automatic multiple TOCs; 
recompile with -mminimal-toc or -fno-optimize-sibling-calls, or make 
`bpf_internal_load_pointer_neg_helper' extern
powerpc64-linux-ld: final link failed: Bad value

I started building with gcc 4.6.3/binutils 2.22 today.  gcc
4.6.0/binutils 2.21 do not produce this error, it produces this instead
(which has been happening for a long time):

powerpc64-linux-ld: TOC section size exceeds 64k

-- 
Cheers,
Stephen Rothwells...@canb.auug.org.au


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[PATCH] MIPS: fix bug.h MIPS build regression

2012-06-20 Thread Yoichi Yuasa 
Commit: 3777808873b0c49c5cf27e44c948dfb02675d578 breaks all MIPS builds.

  CC  arch/mips/kernel/machine_kexec.o
In file included from include/linux/kernel.h:20:0,
 from include/asm-generic/bug.h:35,
 from 
/home/yuasa/src/linux/kernel/git/linux-2.6/arch/mips/include/asm/bug.h:41,
 from 
/home/yuasa/src/linux/kernel/git/linux-2.6/arch/mips/include/asm/bitops.h:20,
 from include/linux/bitops.h:22,
 from include/linux/signal.h:38,
 from include/linux/elfcore.h:5,
 from include/linux/kexec.h:60,
 from arch/mips/kernel/machine_kexec.c:9:
include/linux/log2.h: In function '__ilog2_u32':
include/linux/log2.h:34:2: error: implicit declaration of function 'fls' 
[-Werror=implicit-function-declaration]
include/linux/log2.h: In function '__ilog2_u64':
include/linux/log2.h:42:2: error: implicit declaration of function 'fls64' 
[-Werror=implicit-function-declaration]
include/linux/log2.h: In function '__roundup_pow_of_two':
include/linux/log2.h:63:2: error: implicit declaration of function 'fls_long' 
[-Werror=implicit-function-declaration]
In file included from include/linux/bitops.h:22:0,
 from include/linux/signal.h:38,
 from include/linux/elfcore.h:5,
 from include/linux/kexec.h:60,
 from arch/mips/kernel/machine_kexec.c:9:
/home/yuasa/src/linux/kernel/git/linux-2.6/arch/mips/include/asm/bitops.h: At 
top level:
/home/yuasa/src/linux/kernel/git/linux-2.6/arch/mips/include/asm/bitops.h:615:19:
 error: static declaration of 'fls' follows non-static declaration
include/linux/log2.h:34:9: note: previous implicit declaration of 'fls' was here
In file included from 
/home/yuasa/src/linux/kernel/git/linux-2.6/arch/mips/include/asm/bitops.h:651:0,
 from include/linux/bitops.h:22,
 from include/linux/signal.h:38,
 from include/linux/elfcore.h:5,
 from include/linux/kexec.h:60,
 from arch/mips/kernel/machine_kexec.c:9:
include/asm-generic/bitops/fls64.h:18:28: error: static declaration of 'fls64' 
follows non-static declaration
include/linux/log2.h:42:9: note: previous implicit declaration of 'fls64' was 
here
In file included from include/linux/signal.h:38:0,
 from include/linux/elfcore.h:5,
 from include/linux/kexec.h:60,
 from arch/mips/kernel/machine_kexec.c:9:
include/linux/bitops.h:160:24: error: conflicting types for 'fls_long'
include/linux/log2.h:63:16: note: previous implicit declaration of 'fls_long' 
was here
cc1: all warnings being treated as errors

make[2]: *** [arch/mips/kernel/machine_kexec.o] Error 1

Signed-off-by: Yoichi Yuasa 
---
 arch/mips/include/asm/bitops.h |1 -
 arch/mips/include/asm/io.h |1 +
 2 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h
index 2e1ad4c..82ad35c 100644
--- a/arch/mips/include/asm/bitops.h
+++ b/arch/mips/include/asm/bitops.h
@@ -17,7 +17,6 @@
 #include 
 #include 
 #include 
-#include 
 #include  /* sigh ... */
 #include 
 #include 
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index 37a8379..100f9a3 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -17,6 +17,7 @@
 #include 
 
 #include 
+#include 
 #include 
 #include 
 #include 
-- 
1.7.0.4

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