Re: [powerpc:next 24/29] drivers/atm/fore200e.h:263:3: error: redefinition of typedef 'opcode_t' with different type
(CC'ing Dave and Meelis who from the git history *might* have HW access to test a possible patch). I do have the hardware and can test patches, but it usually takes several days until I happen to go where it is and connect the machine. -- Meelis Roos (mr...@linux.ee) ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [RFC PATCH V6 10/19] memory-hotplug: add memory_block_release
On 2012-8-3 15:49, we...@cn.fujitsu.com wrote:
From: Yasuaki Ishimatsu isimatu.yasu...@jp.fujitsu.com
When calling remove_memory_block(), the function shows following message at
device_release().
Device 'memory528' does not have a release() function, it is broken and must
be fixed.
I found this warning too when doing memory-hotplug,
why not send as a bug fix patch?
The same as [RFC PATCH V6 18/19] memory-hotplug: add node_device_release
remove_memory_block() calls kfree(mem). I think it shouled be called from
device_release(). So the patch implements memory_block_release()
CC: David Rientjes rient...@google.com
CC: Jiang Liu liu...@gmail.com
CC: Len Brown len.br...@intel.com
CC: Benjamin Herrenschmidt b...@kernel.crashing.org
CC: Paul Mackerras pau...@samba.org
CC: Christoph Lameter c...@linux.com
Cc: Minchan Kim minchan@gmail.com
CC: Andrew Morton a...@linux-foundation.org
CC: KOSAKI Motohiro kosaki.motoh...@jp.fujitsu.com
CC: Wen Congyang we...@cn.fujitsu.com
Signed-off-by: Yasuaki Ishimatsu isimatu.yasu...@jp.fujitsu.com
---
drivers/base/memory.c | 11 ++-
1 files changed, 10 insertions(+), 1 deletions(-)
diff --git a/drivers/base/memory.c b/drivers/base/memory.c
index 038be73..1cd3ef3 100644
--- a/drivers/base/memory.c
+++ b/drivers/base/memory.c
@@ -109,6 +109,15 @@ bool is_memblk_offline(unsigned long start, unsigned
long size)
}
EXPORT_SYMBOL(is_memblk_offline);
+#define to_memory_block(device) container_of(device, struct memory_block,
dev)
+
+static void release_memory_block(struct device *dev)
+{
+ struct memory_block *mem = to_memory_block(dev);
+
+ kfree(mem);
+}
+
/*
* register_memory - Setup a sysfs device for a memory block
*/
@@ -119,6 +128,7 @@ int register_memory(struct memory_block *memory)
memory-dev.bus = memory_subsys;
memory-dev.id = memory-start_section_nr / sections_per_block;
+ memory-dev.release = release_memory_block;
error = device_register(memory-dev);
return error;
@@ -674,7 +684,6 @@ int remove_memory_block(unsigned long node_id, struct
mem_section *section,
mem_remove_simple_file(mem, phys_device);
mem_remove_simple_file(mem, removable);
unregister_memory(mem);
- kfree(mem);
} else
kobject_put(mem-dev.kobj);
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linux-next: build failure after merge of the final tree (powerpc tree related)
Hi all,
After merging the final tree, today's linux-next build (powerpc allyesconfig)
failed like this:
In file included from drivers/atm/fore200e.c:70:0:
drivers/atm/fore200e.h:263:3: error: redefinition of typedef 'opcode_t' with
different type
arch/powerpc/include/asm/probes.h:25:13: note: previous declaration of
'opcode_t' was here
Caused by commit 7118e7e648e0 (powerpc: Consolidate {k,u}probe
definitions) from the powerpc tree.
I have reverted that commit (and the two following:
41ab5266c362powerpc: Add trap_nr to thread_struct
8b7b80b9ebb4powerpc: Uprobes port to powerpc)
for today.
--
Cheers,
Stephen Rothwells...@canb.auug.org.au
pgp88dPx4Isth.pgp
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Re: [RFC v9 PATCH 20/21] memory-hotplug: clear hwpoisoned flag when onlining pages
2012/9/5 we...@cn.fujitsu.com
From: Wen Congyang we...@cn.fujitsu.com
hwpoisoned may set when we offline a page by the sysfs interface
/sys/devices/system/memory/soft_offline_page or
/sys/devices/system/memory/hard_offline_page. If we don't clear
this flag when onlining pages, this page can't be freed, and will
not in free list. So we can't offline these pages again. So we
should clear this flag when onlining pages.
CC: David Rientjes rient...@google.com
CC: Jiang Liu liu...@gmail.com
CC: Len Brown len.br...@intel.com
CC: Benjamin Herrenschmidt b...@kernel.crashing.org
CC: Paul Mackerras pau...@samba.org
CC: Christoph Lameter c...@linux.com
Cc: Minchan Kim minchan@gmail.com
CC: Andrew Morton a...@linux-foundation.org
CC: KOSAKI Motohiro kosaki.motoh...@jp.fujitsu.com
CC: Yasuaki Ishimatsu isimatu.yasu...@jp.fujitsu.com
Signed-off-by: Wen Congyang we...@cn.fujitsu.com
---
mm/memory_hotplug.c |5 +
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/mm/memory_hotplug.c b/mm/memory_hotplug.c
index 270c249..140c080 100644
--- a/mm/memory_hotplug.c
+++ b/mm/memory_hotplug.c
@@ -661,6 +661,11 @@ EXPORT_SYMBOL_GPL(__online_page_increment_counters);
void __online_page_free(struct page *page)
{
+#ifdef CONFIG_MEMORY_FAILURE
+ /* The page may be marked HWPoisoned by soft/hard offline page */
+ ClearPageHWPoison(page);
Hi Congyang,
I think you should decrease mce_bad_pages counter her
atomic_long_sub(1, mce_bad_pages);
+#endif
+
ClearPageReserved(page);
init_page_count(page);
__free_page(page);
--
1.7.1
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[PATCH] Rename opcode_t in probes.h to ppc_opcode_t
On Thu, Sep 06, 2012 at 12:56:12PM +1000, Benjamin Herrenschmidt wrote: On Thu, 2012-09-06 at 10:19 +0800, Fengguang Wu wrote: Hi Ananth, FYI, kernel build failed on tree: git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc.git next head: 8b64a9dfb091f1eca8b7e58da82f1e7d1d5fe0ad commit: 8b7b80b9ebb46dd88fbb94e918297295cf312b59 [24/29] powerpc: Uprobes port to powerpc config: powerpc-allmodconfig (attached as .config) All related error/warning messages: In file included from drivers/atm/fore200e.c:70:0: drivers/atm/fore200e.h:263:3: error: redefinition of typedef 'opcode_t' with different type arch/powerpc/include/asm/probes.h:25:13: note: previous declaration of 'opcode_t' was here This is a bit more annoying. Ananth, do we need that to be called opcode_t for generic reasons or can we make it ppc_opcode_t ? If it has to remain, I suppose we can try to change that ATM driver to use a different type name... We can make it ppc_opcode_t. Attached is the patch that fixes this. Regards, Ananth --- From: Ananth N Mavinakayanahalli ana...@in.ibm.com tree: git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc.git next head: 8b64a9dfb091f1eca8b7e58da82f1e7d1d5fe0ad commit: 8b7b80b9ebb46dd88fbb94e918297295cf312b59 [24/29] powerpc: Uprobes port to powerpc config: powerpc-allmodconfig (attached as .config) All related error/warning messages: In file included from drivers/atm/fore200e.c:70:0: drivers/atm/fore200e.h:263:3: error: redefinition of typedef 'opcode_t' with different type arch/powerpc/include/asm/probes.h:25:13: note: previous declaration of 'opcode_t' was here Fix the namespace clash by making opcode_t in probes.h to ppc_opcode_t. Signed-off-by: Ananth N Mavinakayanahalli ana...@in.ibm.com --- Index: linux-tip-22aug/arch/powerpc/include/asm/probes.h === --- linux-tip-22aug.orig/arch/powerpc/include/asm/probes.h 2012-09-04 20:00:19.747069793 +0530 +++ linux-tip-22aug/arch/powerpc/include/asm/probes.h 2012-09-04 20:42:08.147286718 +0530 @@ -22,7 +22,7 @@ */ #include linux/types.h -typedef u32 opcode_t; +typedef u32 ppc_opcode_t; #define BREAKPOINT_INSTRUCTION 0x7fe8 /* trap */ /* Trap definitions per ISA */ Index: linux-tip-22aug/arch/powerpc/include/asm/uprobes.h === --- linux-tip-22aug.orig/arch/powerpc/include/asm/uprobes.h 2012-09-04 20:01:30.617071747 +0530 +++ linux-tip-22aug/arch/powerpc/include/asm/uprobes.h 2012-09-04 20:42:26.657287349 +0530 @@ -25,7 +25,7 @@ #include linux/notifier.h #include asm/probes.h -typedef opcode_t uprobe_opcode_t; +typedef ppc_opcode_t uprobe_opcode_t; #define MAX_UINSN_BYTES4 #define UPROBE_XOL_SLOT_BYTES (MAX_UINSN_BYTES) Index: linux-tip-22aug/arch/powerpc/include/asm/kprobes.h === --- linux-tip-22aug.orig/arch/powerpc/include/asm/kprobes.h 2012-09-04 20:00:19.747069793 +0530 +++ linux-tip-22aug/arch/powerpc/include/asm/kprobes.h 2012-09-04 20:42:15.557286955 +0530 @@ -36,7 +36,7 @@ struct pt_regs; struct kprobe; -typedef opcode_t kprobe_opcode_t; +typedef ppc_opcode_t kprobe_opcode_t; #define MAX_INSN_SIZE 1 #ifdef CONFIG_PPC64 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: linux-next: build failure after merge of the final tree (powerpc tree related)
On Thu, Sep 06, 2012 at 05:11:53PM +1000, Stephen Rothwell wrote:
Hi all,
After merging the final tree, today's linux-next build (powerpc allyesconfig)
failed like this:
In file included from drivers/atm/fore200e.c:70:0:
drivers/atm/fore200e.h:263:3: error: redefinition of typedef 'opcode_t' with
different type
arch/powerpc/include/asm/probes.h:25:13: note: previous declaration of
'opcode_t' was here
Caused by commit 7118e7e648e0 (powerpc: Consolidate {k,u}probe
definitions) from the powerpc tree.
I have reverted that commit (and the two following:
41ab5266c362 powerpc: Add trap_nr to thread_struct
8b7b80b9ebb4 powerpc: Uprobes port to powerpc)
for today.
Hi Stephen,
I have just posted a patch [1] to fix the issue.
Ananth
[1] https://lists.ozlabs.org/pipermail/linuxppc-dev/2012-September/100813.html
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Re: [RFC v9 PATCH 20/21] memory-hotplug: clear hwpoisoned flag when onlining pages
At 09/06/2012 03:27 PM, andywu106建国 Wrote:
2012/9/5 we...@cn.fujitsu.com
From: Wen Congyang we...@cn.fujitsu.com
hwpoisoned may set when we offline a page by the sysfs interface
/sys/devices/system/memory/soft_offline_page or
/sys/devices/system/memory/hard_offline_page. If we don't clear
this flag when onlining pages, this page can't be freed, and will
not in free list. So we can't offline these pages again. So we
should clear this flag when onlining pages.
CC: David Rientjes rient...@google.com
CC: Jiang Liu liu...@gmail.com
CC: Len Brown len.br...@intel.com
CC: Benjamin Herrenschmidt b...@kernel.crashing.org
CC: Paul Mackerras pau...@samba.org
CC: Christoph Lameter c...@linux.com
Cc: Minchan Kim minchan@gmail.com
CC: Andrew Morton a...@linux-foundation.org
CC: KOSAKI Motohiro kosaki.motoh...@jp.fujitsu.com
CC: Yasuaki Ishimatsu isimatu.yasu...@jp.fujitsu.com
Signed-off-by: Wen Congyang we...@cn.fujitsu.com
---
mm/memory_hotplug.c |5 +
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/mm/memory_hotplug.c b/mm/memory_hotplug.c
index 270c249..140c080 100644
--- a/mm/memory_hotplug.c
+++ b/mm/memory_hotplug.c
@@ -661,6 +661,11 @@ EXPORT_SYMBOL_GPL(__online_page_increment_counters);
void __online_page_free(struct page *page)
{
+#ifdef CONFIG_MEMORY_FAILURE
+ /* The page may be marked HWPoisoned by soft/hard offline page */
+ ClearPageHWPoison(page);
Hi Congyang,
I think you should decrease mce_bad_pages counter her
atomic_long_sub(1, mce_bad_pages);
Yes, thanks for pointing it out.
Thanks
Wen Congyang
+#endif
+
ClearPageReserved(page);
init_page_count(page);
__free_page(page);
--
1.7.1
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Re: [PATCH v2] powerpc: fix personality handling in ppc64_personality()
On Thu, 6 Sep 2012, Benjamin Herrenschmidt wrote: actually commit 7256a5d2da56 seems to contain the correct PER_LINUX handling, so seems like you picked the right one :) Odd, they looked different around the use of PER_MASK when I looked but The original patch had personality = ~PER_LINUX | PER_LINUX32; Which is bogus, exactly because ~PER_LINUX is -1. I then used personality = (personality ~PER_MASK) | PER_LINUX32; which is correct and perhaps a little bit more descriptive, and that is what you have merged, so all is fine. I was tired jet lagged, so I might have just had a brain fail... Probably just missed that the first patch used PER_LINUX and the second one PER_MASK, or whatever. Anyway, thanks. -- Jiri Kosina SUSE Labs ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] [v2] sata_fsl: add workaround for data length mismatch on freescale V2 controller
Hello.
On 06-09-2012 8:28, Shaohui Xie wrote:
The freescale V2 SATA controller checks if the received data length matches
the programmed length 'ttl', if not, it assumes that this is an error.
In ATAPI, the 'ttl' is based on max allocation length and not the actual
data transfer length, controller will raise 'DLM' (Data length Mismatch)
error bit in Hstatus register. Along with 'DLM', DE (Device error) and
FE (fatal Error) bits are also set in Hstatus register, 'E' (Internal Error)
bit is set in Serror register and CE (Command Error) and DE (Device error)
registers have the corresponding bit set. In this condition, we need to
clear errors in following way: in the service routine, based on 'DLM' flag,
HCONTROL[27] operation clears Hstatus, CE and DE registers, clear Serror
register.
Signed-off-by: Shaohui Xie shaohui@freescale.com
Signed-off-by: Anju Bhartiya anju.bhart...@freescale.com
---
changes for V2:
1. remove the using of quirk;
2. wrap errata codes in condition;
drivers/ata/sata_fsl.c | 40 +++-
1 files changed, 35 insertions(+), 5 deletions(-)
diff --git a/drivers/ata/sata_fsl.c b/drivers/ata/sata_fsl.c
index d6577b9..6b7b73e 100644
--- a/drivers/ata/sata_fsl.c
+++ b/drivers/ata/sata_fsl.c
[...]
@@ -1180,26 +1181,55 @@ static void sata_fsl_host_intr(struct ata_port *ap)
void __iomem *hcr_base = host_priv-hcr_base;
u32 hstatus, done_mask = 0;
struct ata_queued_cmd *qc;
- u32 SError;
+ u32 SError, tag;
+ u32 status_mask = INT_ON_ERROR;
hstatus = ioread32(hcr_base + HSTATUS);
sata_fsl_scr_read(ap-link, SCR_ERROR, SError);
+ /* Read command completed register */
+ done_mask = ioread32(hcr_base + CC);
+
+ /* Workaround for data length mismatch errata */
+ if (unlikely(hstatus INT_ON_DATA_LENGTH_MISMATCH)) {
+ for (tag = 0; tag ATA_MAX_QUEUE; tag++) {
+ qc = ata_qc_from_tag(ap, tag);
+ if (qc ata_is_atapi(qc-tf.protocol)) {
+ u32 Hcontrol;
No uppercase in variable names please. Besides, you have 'hstatus'
variable already and that would be inconsistent.
+#define HCONTROL_CLEAR_ERROR (1 27)
+ /* Set HControl[27] to clear error registers */
+ Hcontrol = ioread32(hcr_base + HCONTROL);
+ iowrite32(Hcontrol | HCONTROL_CLEAR_ERROR,
+ hcr_base + HCONTROL);
+
+ /* Clear HControl[27] */
+ iowrite32(Hcontrol (~HCONTROL_CLEAR_ERROR),
Parens not needed around ~HCONTROL_CLEAR_ERROR.
+ hcr_base + HCONTROL);
MBR, Sergei
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RE: [PATCH] [v2] sata_fsl: add workaround for data length mismatch on freescale V2 controller
hstatus = ioread32(hcr_base + HSTATUS);
sata_fsl_scr_read(ap-link, SCR_ERROR, SError);
+ /* Read command completed register */
+ done_mask = ioread32(hcr_base + CC);
+
+ /* Workaround for data length mismatch errata */
+ if (unlikely(hstatus INT_ON_DATA_LENGTH_MISMATCH)) {
+ for (tag = 0; tag ATA_MAX_QUEUE; tag++) {
+ qc = ata_qc_from_tag(ap, tag);
+ if (qc ata_is_atapi(qc-tf.protocol)) {
+ u32 Hcontrol;
No uppercase in variable names please.
[S.H] OK.
Besides, you have 'hstatus'
variable already and that would be inconsistent.
[S.H] Yes, but I ignored fatal error and device error, so this won't be an
issue.
+#define HCONTROL_CLEAR_ERROR (1 27)
+ /* Set HControl[27] to clear error registers */
+ Hcontrol = ioread32(hcr_base + HCONTROL);
+ iowrite32(Hcontrol | HCONTROL_CLEAR_ERROR,
+ hcr_base + HCONTROL);
+
+ /* Clear HControl[27] */
+ iowrite32(Hcontrol (~HCONTROL_CLEAR_ERROR),
Parens not needed around ~HCONTROL_CLEAR_ERROR.
[S.H] OK.
Best Regards,
Shaohui Xie
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[PATCH] powerpc64: restore VDSO information on critical exception
Critical exception on 64-bit booke uses user-visible SPRG3 as scratch.
Restore VDSO information in SPRG3 on exception prolog.
Use a common sprg3 field in PACA for all powerpc64 architectures.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
arch/powerpc/include/asm/kvm_book3s_asm.h |1 -
arch/powerpc/include/asm/paca.h |1 +
arch/powerpc/kernel/asm-offsets.c |2 +-
arch/powerpc/kernel/exceptions-64e.S |4 +++-
arch/powerpc/kernel/vdso.c|4 +---
arch/powerpc/kvm/book3s_hv_rmhandlers.S |2 +-
6 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/arch/powerpc/include/asm/kvm_book3s_asm.h
b/arch/powerpc/include/asm/kvm_book3s_asm.h
index bfcd00c..88609b2 100644
--- a/arch/powerpc/include/asm/kvm_book3s_asm.h
+++ b/arch/powerpc/include/asm/kvm_book3s_asm.h
@@ -74,7 +74,6 @@ struct kvmppc_host_state {
ulong vmhandler;
ulong scratch0;
ulong scratch1;
- ulong sprg3;
u8 in_guest;
u8 restore_hid5;
u8 napping;
diff --git a/arch/powerpc/include/asm/paca.h b/arch/powerpc/include/asm/paca.h
index daf813f..7796519 100644
--- a/arch/powerpc/include/asm/paca.h
+++ b/arch/powerpc/include/asm/paca.h
@@ -136,6 +136,7 @@ struct paca_struct {
u8 io_sync; /* writel() needs spin_unlock sync */
u8 irq_work_pending;/* IRQ_WORK interrupt while
soft-disable */
u8 nap_state_lost; /* NV GPR values lost in power7_idle */
+ u64 sprg3; /* Saved user-visible sprg */
#ifdef CONFIG_PPC_POWERNV
/* Pointer to OPAL machine check event structure set by the
diff --git a/arch/powerpc/kernel/asm-offsets.c
b/arch/powerpc/kernel/asm-offsets.c
index 85b05c4..72f2616 100644
--- a/arch/powerpc/kernel/asm-offsets.c
+++ b/arch/powerpc/kernel/asm-offsets.c
@@ -205,6 +205,7 @@ int main(void)
DEFINE(PACA_SYSTEM_TIME, offsetof(struct paca_struct, system_time));
DEFINE(PACA_TRAP_SAVE, offsetof(struct paca_struct, trap_save));
DEFINE(PACA_NAPSTATELOST, offsetof(struct paca_struct, nap_state_lost));
+ DEFINE(PACA_SPRG3, offsetof(struct paca_struct, sprg3));
#endif /* CONFIG_PPC64 */
/* RTAS */
@@ -533,7 +534,6 @@ int main(void)
HSTATE_FIELD(HSTATE_VMHANDLER, vmhandler);
HSTATE_FIELD(HSTATE_SCRATCH0, scratch0);
HSTATE_FIELD(HSTATE_SCRATCH1, scratch1);
- HSTATE_FIELD(HSTATE_SPRG3, sprg3);
HSTATE_FIELD(HSTATE_IN_GUEST, in_guest);
HSTATE_FIELD(HSTATE_RESTORE_HID5, restore_hid5);
HSTATE_FIELD(HSTATE_NAPPING, napping);
diff --git a/arch/powerpc/kernel/exceptions-64e.S
b/arch/powerpc/kernel/exceptions-64e.S
index 7476b0a..87a82fb 100644
--- a/arch/powerpc/kernel/exceptions-64e.S
+++ b/arch/powerpc/kernel/exceptions-64e.S
@@ -110,7 +110,9 @@
#define PROLOG_STORE_RESTORE_SCRATCH_CRIT \
mfspr r10,SPRN_SPRG_CRIT_SCRATCH; /* get r13 */ \
- std r10,PACA_EXCRIT+EX_R13(r13)
+ std r10,PACA_EXCRIT+EX_R13(r13);\
+ ld r11,PACA_SPRG3(r13);\
+ mtspr SPRN_SPRG_CRIT_SCRATCH,r11;
/* Variants of the addition argument for the prolog
*/
diff --git a/arch/powerpc/kernel/vdso.c b/arch/powerpc/kernel/vdso.c
index b67db22..1b2076f 100644
--- a/arch/powerpc/kernel/vdso.c
+++ b/arch/powerpc/kernel/vdso.c
@@ -723,9 +723,7 @@ int __cpuinit vdso_getcpu_init(void)
val = (cpu 0xfff) | ((node 0x) 16);
mtspr(SPRN_SPRG3, val);
-#ifdef CONFIG_KVM_BOOK3S_HANDLER
- get_paca()-kvm_hstate.sprg3 = val;
-#endif
+ get_paca()-sprg3 = val;
put_cpu();
diff --git a/arch/powerpc/kvm/book3s_hv_rmhandlers.S
b/arch/powerpc/kvm/book3s_hv_rmhandlers.S
index 5a84c8d..39a21bf 100644
--- a/arch/powerpc/kvm/book3s_hv_rmhandlers.S
+++ b/arch/powerpc/kvm/book3s_hv_rmhandlers.S
@@ -1065,7 +1065,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
mtspr SPRN_DABRX,r6
/* Restore SPRG3 */
- ld r3,HSTATE_SPRG3(r13)
+ ld r3,PACA_SPRG3(r13)
mtspr SPRN_SPRG3,r3
/*
--
1.7.4.1
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Re: [PATCH] usb: gadget: fsl_udc_core: do not immediatly prime STATUS for IN xfer
On Wed, Sep 05, 2012 at 02:10:39AM +, Chen Peter-B29397 wrote: Because the fsl_udc_core driver shares one 'status_req' object for the complete ep0 control transfer, it is not possible to prime the final STATUS phase immediately after the IN transaction. E.g. ch9getstatus() executed: | req = udc-status_req; | ... | list_add_tail(req-queue, ep-queue); | if (ep0_prime_status(udc, EP_DIR_OUT)) | | struct fsl_req *req = udc-status_req; | list_add_tail(req-queue, ep-queue); which corrupts the ep-queue list by inserting 'status_req' twice. This causes a kernel oops e.g. when 'lsusb -v' is executed on the host. Patch delays the final 'ep0_prime_status(udc, EP_DIR_OUT))' by moving it into the ep0 completion handler. Enrico, thanks for pointing this problem. As prime STATUS phase immediately after the IN transaction is followed USB 2.0 spec, to fix this problem, it is better to add data_req for ep0. In fact, it is already at FSL i.mx internal code, just still not mainlined. so, do I get an Acked-by to this patch ? Does it need to go on v3.6-rc or can it wait until v3.7 merge window ? -- balbi signature.asc Description: Digital signature ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] usb: gadget: fsl_udc_core: do not immediatly prime STATUS for IN xfer
Felipe Balbi ba...@ti.com writes: Because the fsl_udc_core driver shares one 'status_req' object for the complete ep0 control transfer, it is not possible to prime the final STATUS phase immediately after the IN transaction. E.g. ch9getstatus() executed: | req = udc-status_req; | ... | list_add_tail(req-queue, ep-queue); | if (ep0_prime_status(udc, EP_DIR_OUT)) | | struct fsl_req *req = udc-status_req; | list_add_tail(req-queue, ep-queue); which corrupts the ep-queue list by inserting 'status_req' twice. This causes a kernel oops e.g. when 'lsusb -v' is executed on the host. Patch delays the final 'ep0_prime_status(udc, EP_DIR_OUT))' by moving it into the ep0 completion handler. Enrico, thanks for pointing this problem. As prime STATUS phase immediately after the IN transaction is followed USB 2.0 spec, to fix this problem, it is better to add data_req for ep0. In fact, it is already at FSL i.mx internal code, just still not mainlined. so, do I get an Acked-by to this patch ? Does it need to go on v3.6-rc or can it wait until v3.7 merge window ? Without this (or the mentioned data_req patch), I can crash a g_multi gadget by executing 'lsusb -v' as root on the host. Should not be exploitable (only a BUG_ON() is triggered) but issue should be fixed asap. Enrico ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] usb: gadget: fsl_udc_core: do not immediatly prime STATUS for IN xfer
Hi, On Thu, Sep 06, 2012 at 04:27:12PM +0200, Enrico Scholz wrote: Felipe Balbi ba...@ti.com writes: Because the fsl_udc_core driver shares one 'status_req' object for the complete ep0 control transfer, it is not possible to prime the final STATUS phase immediately after the IN transaction. E.g. ch9getstatus() executed: | req = udc-status_req; | ... | list_add_tail(req-queue, ep-queue); | if (ep0_prime_status(udc, EP_DIR_OUT)) | | struct fsl_req *req = udc-status_req; | list_add_tail(req-queue, ep-queue); which corrupts the ep-queue list by inserting 'status_req' twice. This causes a kernel oops e.g. when 'lsusb -v' is executed on the host. Patch delays the final 'ep0_prime_status(udc, EP_DIR_OUT))' by moving it into the ep0 completion handler. Enrico, thanks for pointing this problem. As prime STATUS phase immediately after the IN transaction is followed USB 2.0 spec, to fix this problem, it is better to add data_req for ep0. In fact, it is already at FSL i.mx internal code, just still not mainlined. so, do I get an Acked-by to this patch ? Does it need to go on v3.6-rc or can it wait until v3.7 merge window ? Without this (or the mentioned data_req patch), I can crash a g_multi gadget by executing 'lsusb -v' as root on the host. Should not be exploitable (only a BUG_ON() is triggered) but issue should be fixed asap. cool, so I'll apply to my fixes branch as soon as I get Acked-by or Tested-by from someone. cheers -- balbi signature.asc Description: Digital signature ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] usb: gadget: fsl_udc_core: remove mapped flag
Chen Peter-B29397 b29...@freescale.com writes: If the class driver has already mapped this address, the req-req.dma is not DMA_ADDR_INVALID either, in this case, the dma_sync_single_for_cpu is enough. ok; forget the patch then. Thanks Enrico ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] usb: gadget: fsl_udc_core: remove mapped flag
On Thu, Sep 06, 2012 at 04:32:28PM +0200, Enrico Scholz wrote: Chen Peter-B29397 b29...@freescale.com writes: If the class driver has already mapped this address, the req-req.dma is not DMA_ADDR_INVALID either, in this case, the dma_sync_single_for_cpu is enough. ok; forget the patch then. fair enough, when can I get generic map/unmap conversion patch ? -- balbi signature.asc Description: Digital signature ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH -V8 01/11] arch/powerpc: Replace open coded CONTEXT_BITS value
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
To clarify the meaning for future readers, replace the open coded
19 with CONTEXT_BITS
Reviewed-by: Paul Mackerras pau...@samba.org
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
---
arch/powerpc/mm/mmu_context_hash64.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/mm/mmu_context_hash64.c
b/arch/powerpc/mm/mmu_context_hash64.c
index 40677aa..daa076c 100644
--- a/arch/powerpc/mm/mmu_context_hash64.c
+++ b/arch/powerpc/mm/mmu_context_hash64.c
@@ -34,7 +34,7 @@ static DEFINE_IDA(mmu_context_ida);
* Each segment contains 2^28 bytes. Each context maps 2^44 bytes,
* so we can support 2^19-1 contexts (19 == 35 + 28 - 44).
*/
-#define MAX_CONTEXT((1UL 19) - 1)
+#define MAX_CONTEXT((1UL CONTEXT_BITS) - 1)
int __init_new_context(void)
{
--
1.7.10
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[PATCH -V8 0/11] arch/powerpc: Add 64TB support to ppc64
Hi, This patchset include patches for supporting 64TB with ppc64. I haven't booted this on hardware with 64TB memory yet. But they boot fine on real hardware with less memory. Changes extend VSID bits to 38 bits for a 256MB segment and 26 bits for 1TB segments. Changes from V7: * Address review feedback Changes from V6: * rebase to latest upstream (5b716ac728bcc01b1f2a7ed6e437196602237c27) Changes from v5: * Address review feedback Changes from v4: * Drop patch arch/powerpc: properly offset the context bits for 1T segemnts based on review feedback * split CONTEXT_BITS related changes from patch 12 * Add a new doc update patch Changes from v3: * Address review comments. * Added new patch to ensure proto-VSID isolation between kernel and user space Changes from V2: * Fix few FIXMEs in the patchset. I have added them as separate patch for easier review. That should help us to drop those changes if we don't agree. Changes from V1: * Drop the usage of structure (struct virt_addr) to carry virtual address. We now represent virtual address via vpn which is virtual address shifted right 12 bits. Thanks, -aneesh ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH -V8 03/11] arch/powerpc: Simplify hpte_decode
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
This patch simplify hpte_decode for easy switching of virtual address to
virtual page number in the later patch
Reviewed-by: Paul Mackerras pau...@samba.org
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
---
arch/powerpc/mm/hash_native_64.c | 49 ++
1 file changed, 28 insertions(+), 21 deletions(-)
diff --git a/arch/powerpc/mm/hash_native_64.c b/arch/powerpc/mm/hash_native_64.c
index 90039bc..660b8bb 100644
--- a/arch/powerpc/mm/hash_native_64.c
+++ b/arch/powerpc/mm/hash_native_64.c
@@ -351,9 +351,10 @@ static void native_hpte_invalidate(unsigned long slot,
unsigned long va,
static void hpte_decode(struct hash_pte *hpte, unsigned long slot,
int *psize, int *ssize, unsigned long *va)
{
+ unsigned long avpn, pteg, vpi;
unsigned long hpte_r = hpte-r;
unsigned long hpte_v = hpte-v;
- unsigned long avpn;
+ unsigned long vsid, seg_off;
int i, size, shift, penc;
if (!(hpte_v HPTE_V_LARGE))
@@ -380,32 +381,38 @@ static void hpte_decode(struct hash_pte *hpte, unsigned
long slot,
}
/* This works for all page sizes, and for 256M and 1T segments */
+ *ssize = hpte_v HPTE_V_SSIZE_SHIFT;
shift = mmu_psize_defs[size].shift;
- avpn = (HPTE_V_AVPN_VAL(hpte_v) ~mmu_psize_defs[size].avpnm) 23;
-
- if (shift 23) {
- unsigned long vpi, vsid, pteg;
- pteg = slot / HPTES_PER_GROUP;
- if (hpte_v HPTE_V_SECONDARY)
- pteg = ~pteg;
- switch (hpte_v HPTE_V_SSIZE_SHIFT) {
- case MMU_SEGSIZE_256M:
- vpi = ((avpn 28) ^ pteg) htab_hash_mask;
- break;
- case MMU_SEGSIZE_1T:
- vsid = avpn 40;
+ avpn = (HPTE_V_AVPN_VAL(hpte_v) ~mmu_psize_defs[size].avpnm);
+ pteg = slot / HPTES_PER_GROUP;
+ if (hpte_v HPTE_V_SECONDARY)
+ pteg = ~pteg;
+
+ switch (*ssize) {
+ case MMU_SEGSIZE_256M:
+ /* We only have 28 - 23 bits of seg_off in avpn */
+ seg_off = (avpn 0x1f) 23;
+ vsid= avpn 5;
+ /* We can find more bits from the pteg value */
+ if (shift 23) {
+ vpi = (vsid ^ pteg) htab_hash_mask;
+ seg_off |= vpi shift;
+ }
+ *va = vsid SID_SHIFT | seg_off;
+ case MMU_SEGSIZE_1T:
+ /* We only have 40 - 23 bits of seg_off in avpn */
+ seg_off = (avpn 0x1) 23;
+ vsid= avpn 17;
+ if (shift 23) {
vpi = (vsid ^ (vsid 25) ^ pteg) htab_hash_mask;
- break;
- default:
- avpn = vpi = size = 0;
+ seg_off |= vpi shift;
}
- avpn |= (vpi mmu_psize_defs[size].shift);
+ *va = vsid SID_SHIFT_1T | seg_off;
+ default:
+ *va = size = 0;
}
-
- *va = avpn;
*psize = size;
- *ssize = hpte_v HPTE_V_SSIZE_SHIFT;
}
/*
--
1.7.10
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[PATCH -V8 04/11] arch/powerpc: Convert virtual address to vpn
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
This patch convert different functions to take virtual page number
instead of virtual address. Virtual page number is virtual address
shifted right by VPN_SHIFT (12) bits. This enable us to have an
address range of upto 76 bits.
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/kvm_book3s.h |2 +-
arch/powerpc/include/asm/machdep.h|6 +-
arch/powerpc/include/asm/mmu-hash64.h | 78 +++
arch/powerpc/include/asm/pte-hash64-64k.h | 18 +++--
arch/powerpc/include/asm/tlbflush.h |4 +-
arch/powerpc/kvm/book3s_32_mmu_host.c |8 +-
arch/powerpc/kvm/book3s_64_mmu_host.c | 17 ++--
arch/powerpc/kvm/trace.h | 14 ++--
arch/powerpc/mm/hash_low_64.S | 97 ++-
arch/powerpc/mm/hash_native_64.c | 121 +
arch/powerpc/mm/hash_utils_64.c | 30 +++
arch/powerpc/mm/hugetlbpage-hash64.c | 15 ++--
arch/powerpc/mm/tlb_hash64.c | 11 +--
arch/powerpc/platforms/cell/beat_htab.c | 45 +--
arch/powerpc/platforms/ps3/htab.c | 22 +++---
arch/powerpc/platforms/pseries/lpar.c | 76 --
16 files changed, 324 insertions(+), 240 deletions(-)
diff --git a/arch/powerpc/include/asm/kvm_book3s.h
b/arch/powerpc/include/asm/kvm_book3s.h
index f0e0c6a..7aefdb3 100644
--- a/arch/powerpc/include/asm/kvm_book3s.h
+++ b/arch/powerpc/include/asm/kvm_book3s.h
@@ -59,7 +59,7 @@ struct hpte_cache {
struct hlist_node list_vpte;
struct hlist_node list_vpte_long;
struct rcu_head rcu_head;
- u64 host_va;
+ u64 host_vpn;
u64 pfn;
ulong slot;
struct kvmppc_pte pte;
diff --git a/arch/powerpc/include/asm/machdep.h
b/arch/powerpc/include/asm/machdep.h
index 42ce570..cd63f1a 100644
--- a/arch/powerpc/include/asm/machdep.h
+++ b/arch/powerpc/include/asm/machdep.h
@@ -34,19 +34,19 @@ struct machdep_calls {
char*name;
#ifdef CONFIG_PPC64
void(*hpte_invalidate)(unsigned long slot,
- unsigned long va,
+ unsigned long vpn,
int psize, int ssize,
int local);
long(*hpte_updatepp)(unsigned long slot,
unsigned long newpp,
-unsigned long va,
+unsigned long vpn,
int psize, int ssize,
int local);
void(*hpte_updateboltedpp)(unsigned long newpp,
unsigned long ea,
int psize, int ssize);
long(*hpte_insert)(unsigned long hpte_group,
- unsigned long va,
+ unsigned long vpn,
unsigned long prpn,
unsigned long rflags,
unsigned long vflags,
diff --git a/arch/powerpc/include/asm/mmu-hash64.h
b/arch/powerpc/include/asm/mmu-hash64.h
index 1c65a59..6aeb498 100644
--- a/arch/powerpc/include/asm/mmu-hash64.h
+++ b/arch/powerpc/include/asm/mmu-hash64.h
@@ -154,9 +154,25 @@ struct mmu_psize_def
#define MMU_SEGSIZE_256M 0
#define MMU_SEGSIZE_1T 1
+/*
+ * encode page number shift.
+ * in order to fit the 78 bit va in a 64 bit variable we shift the va by
+ * 12 bits. This enable us to address upto 76 bit va.
+ * For hpt hash from a va we can ignore the page size bits of va and for
+ * hpte encoding we ignore up to 23 bits of va. So ignoring lower 12 bits
ensure
+ * we work in all cases including 4k page size.
+ */
+#define VPN_SHIFT 12
#ifndef __ASSEMBLY__
+static inline int segment_shift(int ssize)
+{
+ if (ssize == MMU_SEGSIZE_256M)
+ return SID_SHIFT;
+ return SID_SHIFT_1T;
+}
+
/*
* The current system page and segment sizes
*/
@@ -180,18 +196,39 @@ extern unsigned long tce_alloc_start, tce_alloc_end;
extern int mmu_ci_restrictions;
/*
+ * This computes the AVPN and B fields of the first dword of a HPTE,
+ * for use when we want to match an existing PTE. The bottom 7 bits
+ * of the returned value are zero.
+ */
+static inline unsigned long hpte_encode_avpn(unsigned long vpn, int psize,
+int ssize)
+{
+ unsigned long v;
+ /*
+* The AVA field omits the low-order 23 bits of the 78 bits VA.
+* These bits are not needed in the PTE, because the
+* low-order b of these bits are part of the byte offset
+*
[PATCH -V8 05/11] arch/powerpc: Make KERN_VIRT_SIZE not dependend on PGTABLE_RANGE
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com As we keep increasing PGTABLE_RANGE we need not increase the virual map area for kernel. Reviewed-by: Paul Mackerras pau...@samba.org Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com --- arch/powerpc/include/asm/pgtable-ppc64.h |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/powerpc/include/asm/pgtable-ppc64.h b/arch/powerpc/include/asm/pgtable-ppc64.h index c420561..8af1cf2 100644 --- a/arch/powerpc/include/asm/pgtable-ppc64.h +++ b/arch/powerpc/include/asm/pgtable-ppc64.h @@ -41,7 +41,7 @@ #else #define KERN_VIRT_START ASM_CONST(0xD000) #endif -#define KERN_VIRT_SIZE PGTABLE_RANGE +#define KERN_VIRT_SIZE ASM_CONST(0x1000) /* * The vmalloc space starts at the beginning of that region, and -- 1.7.10 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH -V8 08/11] arch/powerpc: Use the required number of VSID bits in slbmte
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com ASM_VSID_SCRAMBLE can leave non-zero bits in the high 28 bits of the result for 256MB segment (40 bits for 1T segment). Properly mask them before using the values in slbmte Reviewed-by: Paul Mackerras pau...@samba.org Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com --- arch/powerpc/mm/slb_low.S | 12 ++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/mm/slb_low.S b/arch/powerpc/mm/slb_low.S index e132dc6..3b75f19 100644 --- a/arch/powerpc/mm/slb_low.S +++ b/arch/powerpc/mm/slb_low.S @@ -223,7 +223,11 @@ _GLOBAL(slb_allocate_user) */ slb_finish_load: ASM_VSID_SCRAMBLE(r10,r9,256M) - rldimi r11,r10,SLB_VSID_SHIFT,16 /* combine VSID and flags */ + /* +* bits above VSID_BITS_256M need to be ignored from r10 +* also combine VSID and flags +*/ + rldimi r11,r10,SLB_VSID_SHIFT,(64 - (SLB_VSID_SHIFT + VSID_BITS_256M)) /* r3 = EA, r11 = VSID data */ /* @@ -287,7 +291,11 @@ _GLOBAL(slb_compare_rr_to_size) slb_finish_load_1T: srdir10,r10,40-28 /* get 1T ESID */ ASM_VSID_SCRAMBLE(r10,r9,1T) - rldimi r11,r10,SLB_VSID_SHIFT_1T,16/* combine VSID and flags */ + /* +* bits above VSID_BITS_1T need to be ignored from r10 +* also combine VSID and flags +*/ + rldimi r11,r10,SLB_VSID_SHIFT_1T,(64 - (SLB_VSID_SHIFT_1T + VSID_BITS_1T)) li r10,MMU_SEGSIZE_1T rldimi r11,r10,SLB_VSID_SSIZE_SHIFT,0 /* insert segment size */ -- 1.7.10 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH -V8 02/11] arch/powerpc: Use hpt_va to compute virtual address
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com Don't open code the same Reviewed-by: Paul Mackerras pau...@samba.org Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com --- arch/powerpc/platforms/cell/beat_htab.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/powerpc/platforms/cell/beat_htab.c b/arch/powerpc/platforms/cell/beat_htab.c index 943c9d3..b83077e 100644 --- a/arch/powerpc/platforms/cell/beat_htab.c +++ b/arch/powerpc/platforms/cell/beat_htab.c @@ -259,7 +259,7 @@ static void beat_lpar_hpte_updateboltedpp(unsigned long newpp, u64 dummy0, dummy1; vsid = get_kernel_vsid(ea, MMU_SEGSIZE_256M); - va = (vsid 28) | (ea 0x0fff); + va = hpt_va(ea, vsid, MMU_SEGSIZE_256M); raw_spin_lock(beat_htab_lock); slot = beat_lpar_hpte_find(va, psize); -- 1.7.10 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH -V8 10/11] arch/powerpc: Add 64TB support
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
Increase max addressable range to 64TB. This is not tested on
real hardware yet.
Reviewed-by: Paul Mackerras pau...@samba.org
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/mmu-hash64.h| 42 --
arch/powerpc/include/asm/pgtable-ppc64-4k.h |2 +-
arch/powerpc/include/asm/pgtable-ppc64-64k.h |2 +-
arch/powerpc/include/asm/processor.h |4 +--
arch/powerpc/include/asm/sparsemem.h |4 +--
arch/powerpc/kernel/exceptions-64s.S |4 ++-
arch/powerpc/mm/slb_low.S| 12
7 files changed, 54 insertions(+), 16 deletions(-)
diff --git a/arch/powerpc/include/asm/mmu-hash64.h
b/arch/powerpc/include/asm/mmu-hash64.h
index cbd7edb..de9cfed 100644
--- a/arch/powerpc/include/asm/mmu-hash64.h
+++ b/arch/powerpc/include/asm/mmu-hash64.h
@@ -370,17 +370,21 @@ extern void slb_set_size(u16 size);
* (head.S) and ASM_VSID_SCRAMBLE (below) are changed accordingly.
*/
-#define VSID_MULTIPLIER_256M ASM_CONST(200730139)/* 28-bit prime */
-#define VSID_BITS_256M 36
+/*
+ * This should be computed such that protovosid * vsid_mulitplier
+ * doesn't overflow 64 bits. It should also be co-prime to vsid_modulus
+ */
+#define VSID_MULTIPLIER_256M ASM_CONST(12538073) /* 24-bit prime */
+#define VSID_BITS_256M 38
#define VSID_MODULUS_256M ((1ULVSID_BITS_256M)-1)
#define VSID_MULTIPLIER_1T ASM_CONST(12538073) /* 24-bit prime */
-#define VSID_BITS_1T 24
+#define VSID_BITS_1T 26
#define VSID_MODULUS_1T((1ULVSID_BITS_1T)-1)
#define CONTEXT_BITS 19
-#define USER_ESID_BITS 16
-#define USER_ESID_BITS_1T 4
+#define USER_ESID_BITS 18
+#define USER_ESID_BITS_1T 6
#define USER_VSID_RANGE(1UL (USER_ESID_BITS + SID_SHIFT))
@@ -503,12 +507,32 @@ typedef struct {
})
#endif /* 1 */
-/* This is only valid for addresses = PAGE_OFFSET */
+/*
+ * This is only valid for addresses = PAGE_OFFSET
+ * The proto-VSID space is divided into two class
+ * User: 0 to 2^(CONTEXT_BITS + USER_ESID_BITS) -1
+ * kernel: 2^(CONTEXT_BITS + USER_ESID_BITS) to 2^(VSID_BITS) - 1
+ *
+ * With KERNEL_START at 0xc000, the proto vsid for
+ * the kernel ends up with 0xc (36 bits). With 64TB
+ * support we need to have kernel proto-VSID in the
+ * [2^37 to 2^38 - 1] range due to the increased USER_ESID_BITS.
+ */
static inline unsigned long get_kernel_vsid(unsigned long ea, int ssize)
{
- if (ssize == MMU_SEGSIZE_256M)
- return vsid_scramble(ea SID_SHIFT, 256M);
- return vsid_scramble(ea SID_SHIFT_1T, 1T);
+ unsigned long proto_vsid;
+ /*
+* We need to make sure proto_vsid for the kernel is
+* = 2^(CONTEXT_BITS + USER_ESID_BITS[_1T])
+*/
+ if (ssize == MMU_SEGSIZE_256M) {
+ proto_vsid = ea SID_SHIFT;
+ proto_vsid |= (1UL (CONTEXT_BITS + USER_ESID_BITS));
+ return vsid_scramble(proto_vsid, 256M);
+ }
+ proto_vsid = ea SID_SHIFT_1T;
+ proto_vsid |= (1UL (CONTEXT_BITS + USER_ESID_BITS_1T));
+ return vsid_scramble(proto_vsid, 1T);
}
/* Returns the segment size indicator for a user address */
diff --git a/arch/powerpc/include/asm/pgtable-ppc64-4k.h
b/arch/powerpc/include/asm/pgtable-ppc64-4k.h
index 6eefdcf..b3eccf2 100644
--- a/arch/powerpc/include/asm/pgtable-ppc64-4k.h
+++ b/arch/powerpc/include/asm/pgtable-ppc64-4k.h
@@ -7,7 +7,7 @@
*/
#define PTE_INDEX_SIZE 9
#define PMD_INDEX_SIZE 7
-#define PUD_INDEX_SIZE 7
+#define PUD_INDEX_SIZE 9
#define PGD_INDEX_SIZE 9
#ifndef __ASSEMBLY__
diff --git a/arch/powerpc/include/asm/pgtable-ppc64-64k.h
b/arch/powerpc/include/asm/pgtable-ppc64-64k.h
index 90533dd..be4e287 100644
--- a/arch/powerpc/include/asm/pgtable-ppc64-64k.h
+++ b/arch/powerpc/include/asm/pgtable-ppc64-64k.h
@@ -7,7 +7,7 @@
#define PTE_INDEX_SIZE 12
#define PMD_INDEX_SIZE 12
#define PUD_INDEX_SIZE 0
-#define PGD_INDEX_SIZE 4
+#define PGD_INDEX_SIZE 6
#ifndef __ASSEMBLY__
#define PTE_TABLE_SIZE (sizeof(real_pte_t) PTE_INDEX_SIZE)
diff --git a/arch/powerpc/include/asm/processor.h
b/arch/powerpc/include/asm/processor.h
index 53b6dfa..00bda2f 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -97,8 +97,8 @@ extern struct task_struct *last_task_used_spe;
#endif
#ifdef CONFIG_PPC64
-/* 64-bit user address space is 44-bits (16TB user VM) */
-#define TASK_SIZE_USER64 (0x1000UL)
+/* 64-bit user address space is 46-bits (64TB user VM) */
+#define TASK_SIZE_USER64 (0x4000UL)
/*
* 32-bit user address space is 4GB - 1 page
diff --git a/arch/powerpc/include/asm/sparsemem.h
b/arch/powerpc/include/asm/sparsemem.h
index 0c5fa31..f6fc0ee 100644
---
[PATCH -V8 11/11] arch/powerpc: Update VSID allocation documentation
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com This update the proto-VSID and VSID scramble related information to be more generic by using names instead of current values. Reviewed-by: Paul Mackerras pau...@samba.org Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com --- arch/powerpc/include/asm/mmu-hash64.h | 40 ++--- arch/powerpc/mm/mmu_context_hash64.c |8 --- 2 files changed, 22 insertions(+), 26 deletions(-) diff --git a/arch/powerpc/include/asm/mmu-hash64.h b/arch/powerpc/include/asm/mmu-hash64.h index de9cfed..428f23e 100644 --- a/arch/powerpc/include/asm/mmu-hash64.h +++ b/arch/powerpc/include/asm/mmu-hash64.h @@ -324,51 +324,45 @@ extern void slb_set_size(u16 size); #endif /* __ASSEMBLY__ */ /* - * VSID allocation + * VSID allocation (256MB segment) * - * We first generate a 36-bit proto-VSID. For kernel addresses this - * is equal to the ESID, for user addresses it is: - * (context 15) | (esid 0x7fff) + * We first generate a 38-bit proto-VSID. For kernel addresses this + * is equal to the ESID | 1 37, for user addresses it is: + * (context USER_ESID_BITS) | (esid ((1U USER_ESID_BITS) - 1) * - * The two forms are distinguishable because the top bit is 0 for user - * addresses, whereas the top two bits are 1 for kernel addresses. - * Proto-VSIDs with the top two bits equal to 0b10 are reserved for - * now. + * This splits the proto-VSID into the below range + * 0 - (2^(CONTEXT_BITS + USER_ESID_BITS) - 1) : User proto-VSID range + * 2^(CONTEXT_BITS + USER_ESID_BITS) - 2^(VSID_BITS) : Kernel proto-VSID range + * + * We also have CONTEXT_BITS + USER_ESID_BITS = VSID_BITS - 1 + * That is, we assign half of the space to user processes and half + * to the kernel. * * The proto-VSIDs are then scrambled into real VSIDs with the * multiplicative hash: * * VSID = (proto-VSID * VSID_MULTIPLIER) % VSID_MODULUS - * where VSID_MULTIPLIER = 268435399 = 0xFC7 - * VSID_MODULUS = 2^36-1 = 0xF * - * This scramble is only well defined for proto-VSIDs below - * 0xF, so both proto-VSID and actual VSID 0xF are - * reserved. VSID_MULTIPLIER is prime, so in particular it is + * VSID_MULTIPLIER is prime, so in particular it is * co-prime to VSID_MODULUS, making this a 1:1 scrambling function. * Because the modulus is 2^n-1 we can compute it efficiently without * a divide or extra multiply (see below). * * This scheme has several advantages over older methods: * - * - We have VSIDs allocated for every kernel address + * - We have VSIDs allocated for every kernel address * (i.e. everything above 0xC000), except the very top * segment, which simplifies several things. * - * - We allow for 16 significant bits of ESID and 19 bits of - * context for user addresses. i.e. 16T (44 bits) of address space for - * up to half a million contexts. + * - We allow for USER_ESID_BITS significant bits of ESID and + * CONTEXT_BITS bits of context for user addresses. + * i.e. 64T (46 bits) of address space for up to half a million contexts. * - * - The scramble function gives robust scattering in the hash + * - The scramble function gives robust scattering in the hash * table (at least based on some initial results). The previous * method was more susceptible to pathological cases giving excessive * hash collisions. */ -/* - * WARNING - If you change these you must make sure the asm - * implementations in slb_allocate (slb_low.S), do_stab_bolted - * (head.S) and ASM_VSID_SCRAMBLE (below) are changed accordingly. - */ /* * This should be computed such that protovosid * vsid_mulitplier diff --git a/arch/powerpc/mm/mmu_context_hash64.c b/arch/powerpc/mm/mmu_context_hash64.c index daa076c..40bc5b0 100644 --- a/arch/powerpc/mm/mmu_context_hash64.c +++ b/arch/powerpc/mm/mmu_context_hash64.c @@ -30,9 +30,11 @@ static DEFINE_SPINLOCK(mmu_context_lock); static DEFINE_IDA(mmu_context_ida); /* - * The proto-VSID space has 2^35 - 1 segments available for user mappings. - * Each segment contains 2^28 bytes. Each context maps 2^44 bytes, - * so we can support 2^19-1 contexts (19 == 35 + 28 - 44). + * 256MB segment + * The proto-VSID space has 2^(CONTEX_BITS + USER_ESID_BITS) - 1 segments + * available for user mappings. Each segment contains 2^28 bytes. Each + * context maps 2^46 bytes (64TB) so we can support 2^19-1 contexts + * (19 == 37 + 28 - 46). */ #define MAX_CONTEXT((1UL CONTEXT_BITS) - 1) -- 1.7.10 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH -V8 07/11] arch/powerpc: Make some of the PGTABLE_RANGE dependency explicit
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
slice array size and slice mask size depend on PGTABLE_RANGE. We
can't directly include pgtable.h in these header because there is
a circular dependency. So add compile time check for these values.
Reviewed-by: Paul Mackerras pau...@samba.org
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/mmu-hash64.h| 13 -
arch/powerpc/include/asm/page_64.h | 16
arch/powerpc/include/asm/pgtable-ppc64.h |8
3 files changed, 28 insertions(+), 9 deletions(-)
diff --git a/arch/powerpc/include/asm/mmu-hash64.h
b/arch/powerpc/include/asm/mmu-hash64.h
index 7cbd541..cbd7edb 100644
--- a/arch/powerpc/include/asm/mmu-hash64.h
+++ b/arch/powerpc/include/asm/mmu-hash64.h
@@ -416,6 +416,13 @@ extern void slb_set_size(u16 size);
srdirx,rx,VSID_BITS_##size; /* extract 2^VSID_BITS bit */ \
add rt,rt,rx
+/* 4 bits per slice and we have one slice per 1TB */
+#if 0 /* We can't directly include pgtable.h hence this hack */
+#define SLICE_ARRAY_SIZE (PGTABLE_RANGE 41)
+#else
+/* Right now we only support 64TB */
+#define SLICE_ARRAY_SIZE 32
+#endif
#ifndef __ASSEMBLY__
@@ -460,11 +467,7 @@ typedef struct {
#ifdef CONFIG_PPC_MM_SLICES
u64 low_slices_psize; /* SLB page size encodings */
- /*
-* Right now we support 64TB and 4 bits for each
-* 1TB slice we need 32 bytes for 64TB.
-*/
- unsigned char high_slices_psize[32]; /* 4 bits per slice for now */
+ unsigned char high_slices_psize[SLICE_ARRAY_SIZE];
#else
u16 sllp; /* SLB page size encoding */
#endif
diff --git a/arch/powerpc/include/asm/page_64.h
b/arch/powerpc/include/asm/page_64.h
index 6c9bef4..b55beb4 100644
--- a/arch/powerpc/include/asm/page_64.h
+++ b/arch/powerpc/include/asm/page_64.h
@@ -78,14 +78,22 @@ extern u64 ppc64_pft_size;
#define GET_LOW_SLICE_INDEX(addr) ((addr) SLICE_LOW_SHIFT)
#define GET_HIGH_SLICE_INDEX(addr) ((addr) SLICE_HIGH_SHIFT)
+/* 1 bit per slice and we have one slice per 1TB */
+#if 0 /* We can't directly include pgtable.h hence this hack */
+#define SLICE_MASK_SIZE (PGTABLE_RANGE 43)
+#else
+/*
+ * Right now we support only 64TB.
+ * IF we change this we will have to change the type
+ * of high_slices
+ */
+#define SLICE_MASK_SIZE 8
+#endif
+
#ifndef __ASSEMBLY__
struct slice_mask {
u16 low_slices;
- /*
-* This should be derived out of PGTABLE_RANGE. For the current
-* max 64TB, u64 should be ok.
-*/
u64 high_slices;
};
diff --git a/arch/powerpc/include/asm/pgtable-ppc64.h
b/arch/powerpc/include/asm/pgtable-ppc64.h
index 8af1cf2..dea953f 100644
--- a/arch/powerpc/include/asm/pgtable-ppc64.h
+++ b/arch/powerpc/include/asm/pgtable-ppc64.h
@@ -32,6 +32,14 @@
#endif
#endif
+#if (PGTABLE_RANGE 41) SLICE_ARRAY_SIZE
+#error PGTABLE_RANGE exceeds SLICE_ARRAY_SIZE
+#endif
+
+#if (PGTABLE_RANGE 43) SLICE_MASK_SIZE
+#error PGTABLE_RANGE exceeds slice_mask high_slices size
+#endif
+
/*
* Define the address range of the kernel non-linear virtual area
*/
--
1.7.10
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[PATCH -V8 09/11] arch/powerpc: Use 32bit array for slb cache
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
With larger vsid we need to track more bits of ESID in slb cache
for slb invalidate.
Reviewed-by: Paul Mackerras pau...@samba.org
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/paca.h |2 +-
arch/powerpc/mm/slb_low.S |8
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/include/asm/paca.h b/arch/powerpc/include/asm/paca.h
index daf813f..3e7abba 100644
--- a/arch/powerpc/include/asm/paca.h
+++ b/arch/powerpc/include/asm/paca.h
@@ -100,7 +100,7 @@ struct paca_struct {
/* SLB related definitions */
u16 vmalloc_sllp;
u16 slb_cache_ptr;
- u16 slb_cache[SLB_CACHE_ENTRIES];
+ u32 slb_cache[SLB_CACHE_ENTRIES];
#endif /* CONFIG_PPC_STD_MMU_64 */
#ifdef CONFIG_PPC_BOOK3E
diff --git a/arch/powerpc/mm/slb_low.S b/arch/powerpc/mm/slb_low.S
index 3b75f19..f6a2625 100644
--- a/arch/powerpc/mm/slb_low.S
+++ b/arch/powerpc/mm/slb_low.S
@@ -270,10 +270,10 @@ _GLOBAL(slb_compare_rr_to_size)
bge 1f
/* still room in the slb cache */
- sldir11,r3,1/* r11 = offset * sizeof(u16) */
- rldicl r10,r10,36,28 /* get low 16 bits of the ESID */
- add r11,r11,r13 /* r11 = (u16 *)paca + offset */
- sth r10,PACASLBCACHE(r11) /* paca-slb_cache[offset] = esid */
+ sldir11,r3,2/* r11 = offset * sizeof(u32) */
+ srdir10,r10,28 /* get the 36 bits of the ESID */
+ add r11,r11,r13 /* r11 = (u32 *)paca + offset */
+ stw r10,PACASLBCACHE(r11) /* paca-slb_cache[offset] = esid */
addir3,r3,1 /* offset++ */
b 2f
1: /* offset = SLB_CACHE_ENTRIES */
--
1.7.10
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[PATCH -V8 06/11] arch/powerpc: Increase the slice range to 64TB
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
This patch makes the high psizes mask as an unsigned char array
so that we can have more than 16TB. Currently we support upto
64TB
Reviewed-by: Paul Mackerras pau...@samba.org
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/mmu-hash64.h |6 +-
arch/powerpc/include/asm/page_64.h|6 +-
arch/powerpc/mm/hash_utils_64.c | 15 +++--
arch/powerpc/mm/slb_low.S | 30 ++---
arch/powerpc/mm/slice.c | 107 +
5 files changed, 109 insertions(+), 55 deletions(-)
diff --git a/arch/powerpc/include/asm/mmu-hash64.h
b/arch/powerpc/include/asm/mmu-hash64.h
index 6aeb498..7cbd541 100644
--- a/arch/powerpc/include/asm/mmu-hash64.h
+++ b/arch/powerpc/include/asm/mmu-hash64.h
@@ -460,7 +460,11 @@ typedef struct {
#ifdef CONFIG_PPC_MM_SLICES
u64 low_slices_psize; /* SLB page size encodings */
- u64 high_slices_psize; /* 4 bits per slice for now */
+ /*
+* Right now we support 64TB and 4 bits for each
+* 1TB slice we need 32 bytes for 64TB.
+*/
+ unsigned char high_slices_psize[32]; /* 4 bits per slice for now */
#else
u16 sllp; /* SLB page size encoding */
#endif
diff --git a/arch/powerpc/include/asm/page_64.h
b/arch/powerpc/include/asm/page_64.h
index fed85e6..6c9bef4 100644
--- a/arch/powerpc/include/asm/page_64.h
+++ b/arch/powerpc/include/asm/page_64.h
@@ -82,7 +82,11 @@ extern u64 ppc64_pft_size;
struct slice_mask {
u16 low_slices;
- u16 high_slices;
+ /*
+* This should be derived out of PGTABLE_RANGE. For the current
+* max 64TB, u64 should be ok.
+*/
+ u64 high_slices;
};
struct mm_struct;
diff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c
index 74c5479..13e0ccf 100644
--- a/arch/powerpc/mm/hash_utils_64.c
+++ b/arch/powerpc/mm/hash_utils_64.c
@@ -804,16 +804,19 @@ unsigned int hash_page_do_lazy_icache(unsigned int pp,
pte_t pte, int trap)
#ifdef CONFIG_PPC_MM_SLICES
unsigned int get_paca_psize(unsigned long addr)
{
- unsigned long index, slices;
+ u64 lpsizes;
+ unsigned char *hpsizes;
+ unsigned long index, mask_index;
if (addr SLICE_LOW_TOP) {
- slices = get_paca()-context.low_slices_psize;
+ lpsizes = get_paca()-context.low_slices_psize;
index = GET_LOW_SLICE_INDEX(addr);
- } else {
- slices = get_paca()-context.high_slices_psize;
- index = GET_HIGH_SLICE_INDEX(addr);
+ return (lpsizes (index * 4)) 0xF;
}
- return (slices (index * 4)) 0xF;
+ hpsizes = get_paca()-context.high_slices_psize;
+ index = GET_HIGH_SLICE_INDEX(addr);
+ mask_index = index 0x1;
+ return (hpsizes[index 1] (mask_index * 4)) 0xF;
}
#else
diff --git a/arch/powerpc/mm/slb_low.S b/arch/powerpc/mm/slb_low.S
index b9ee79ce..e132dc6 100644
--- a/arch/powerpc/mm/slb_low.S
+++ b/arch/powerpc/mm/slb_low.S
@@ -108,17 +108,31 @@ END_MMU_FTR_SECTION_IFCLR(MMU_FTR_1T_SEGMENT)
* between 4k and 64k standard page size
*/
#ifdef CONFIG_PPC_MM_SLICES
+ /* r10 have esid */
cmpldi r10,16
-
- /* Get the slice index * 4 in r11 and matching slice size mask in r9 */
- ld r9,PACALOWSLICESPSIZE(r13)
- sldir11,r10,2
+ /* below SLICE_LOW_TOP */
blt 5f
- ld r9,PACAHIGHSLICEPSIZE(r13)
- srdir11,r10,(SLICE_HIGH_SHIFT - SLICE_LOW_SHIFT - 2)
- andi. r11,r11,0x3c
+ /*
+* Handle hpsizes,
+* r9 is get_paca()-context.high_slices_psize[index], r11 is mask_index
+*/
+ srdir11,r10,(SLICE_HIGH_SHIFT - SLICE_LOW_SHIFT + 1) /* index */
+ addir9,r11,PACAHIGHSLICEPSIZE
+ lbzxr9,r13,r9 /* r9 is hpsizes[r11] */
+ /* r11 = (r10 (SLICE_HIGH_SHIFT - SLICE_LOW_SHIFT)) 0x1 */
+ rldicl r11,r10,(64 - (SLICE_HIGH_SHIFT - SLICE_LOW_SHIFT)),63
+ b 6f
-5: /* Extract the psize and multiply to get an array offset */
+5:
+ /*
+* Handle lpsizes
+* r9 is get_paca()-context.low_slices_psize, r11 is index
+*/
+ ld r9,PACALOWSLICESPSIZE(r13)
+ mr r11,r10
+6:
+ sldir11,r11,2 /* index * 4 */
+ /* Extract the psize and multiply to get an array offset */
srd r9,r9,r11
andi. r9,r9,0xf
mulli r9,r9,MMUPSIZEDEFSIZE
diff --git a/arch/powerpc/mm/slice.c b/arch/powerpc/mm/slice.c
index 73709f7..b4e996a 100644
--- a/arch/powerpc/mm/slice.c
+++ b/arch/powerpc/mm/slice.c
@@ -42,7 +42,7 @@ int _slice_debug = 1;
static void slice_print_mask(const char *label, struct slice_mask mask)
{
- char*p, buf[16 + 3 + 16 + 1];
+ char*p, buf[16 + 3 + 64 + 1];
int i;
[PATCH] powerpc: Fix build dependencies for c files requiring libfdt.h
Several files in obj-plat depend on libfdt header file. Sometimes when building one can see the following issue. This patch adds libfdt as dependency to those object files | In file included from arch/powerpc/boot/treeboot-iss4xx.c:33:0: | arch/powerpc/boot/libfdt.h:854:1: error: unterminated comment | In file included from arch/powerpc/boot/treeboot-iss4xx.c:33:0: | arch/powerpc/boot/libfdt.h:1:0: error: unterminated #ifndef | BOOTCC arch/powerpc/boot/inffast.o | make[1]: *** [arch/powerpc/boot/treeboot-iss4xx.o] Error 1 | make[1]: *** Waiting for unfinished jobs | BOOTCC arch/powerpc/boot/inflate.o | make: *** [uImage] Error 2 | ERROR: oe_runmake failed | ERROR: Function failed: do_compile (see /srv/home/pokybuild/yocto-autobuilder/yocto-slave/p1022ds/build/build/tmp/work/p1022ds-poky-linux-gnuspe/linux-qoriq-sdk-3.0.34-r5/temp/log.do_compile.2167 for further information) NOTE: recipe linux-qoriq-sdk-3.0.34-r5: task do_compile: Failed Signed-off-by: Matthew McClintock m...@freescale.com --- arch/powerpc/boot/Makefile |1 + 1 file changed, 1 insertion(+) diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile index b7d8333..6a15c96 100644 --- a/arch/powerpc/boot/Makefile +++ b/arch/powerpc/boot/Makefile @@ -107,6 +107,7 @@ src-boot := $(addprefix $(obj)/, $(src-boot)) obj-boot := $(addsuffix .o, $(basename $(src-boot))) obj-wlib := $(addsuffix .o, $(basename $(addprefix $(obj)/, $(src-wlib obj-plat := $(addsuffix .o, $(basename $(addprefix $(obj)/, $(src-plat +obj-plat: $(libfdt) quiet_cmd_copy_zlib = COPY$@ cmd_copy_zlib = sed s@__used@@;s@linux/\([^]*\).*@\\1\@ $ $@ -- 1.7.9.7 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] KVM: PPC: BookE: HV: Fix compile
On 25.07.2012, at 20:31, Michael Neuling wrote: Alexander Graf ag...@suse.de wrote: After merging the register type check patches from Ben's tree, the hv enabled booke implementation ceased to compile. This patch fixes things up so everyone's happy again. Is there a defconfig which catches this? Hrm. I don't think a defconfig gets you there, as KVM isn't enabled by default. Just configure your kernel with support for e500mc and enable KVM :). Alex ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH -V8 04/11] arch/powerpc: Convert virtual address to vpn
On Thu, Sep 06, 2012 at 08:59:04PM +0530, Aneesh Kumar K.V wrote: From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com This patch convert different functions to take virtual page number instead of virtual address. Virtual page number is virtual address shifted right by VPN_SHIFT (12) bits. This enable us to have an address range of upto 76 bits. Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com Reviewed-by: Paul Mackerras pau...@samba.org ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 2/2][v2] powerpc/perf: Sample only if SIAR-Valid bit is set in P7+
On Mon, 2012-07-16 at 14:22 -0700, Sukadev Bhattiprolu wrote:
From: Sukadev Bhattiprolu suka...@linux.vnet.ibm.com
Date: Mon, 2 Jul 2012 08:06:14 -0700
Subject: [PATCH 2/2][v2] powerpc/perf: Sample only if SIAR-Valid bit is set
in P7+
On POWER7+ two new bits (mmcra[35] and mmcra[36]) indicate whether the
contents of SIAR and SDAR are valid.
For marked instructions on P7+, we must save the contents of SIAR and
SDAR registers only if these new bits are set.
This code/check for the SIAR-Valid bit is specific to P7+, so rather than
waste a CPU-feature bit use the PVR flag.
This appears to be based on an ancient code base. The code has changed
significantly in that area and this patch doesn't apply at all.
I have applied the first patch and renamed PV_ to PVR_ since we've
renamed them all since then. This will show up in powerpc-next later
today. Please rebase your perf patch on top of that.
Cheers,
Ben.
Note that Carl Love proposed a similar change for oprofile:
https://lkml.org/lkml/2012/6/22/309
Changelog[v2]:
- [Gabriel Paubert] Rename PV_POWER7P to PV_POWER7p.
Signed-off-by: Sukadev Bhattiprolu suka...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/perf_event_server.h |1 +
arch/powerpc/include/asm/reg.h |4 +++
arch/powerpc/perf/core-book3s.c | 38 ++---
arch/powerpc/perf/power7-pmu.c |3 ++
4 files changed, 41 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/include/asm/perf_event_server.h
b/arch/powerpc/include/asm/perf_event_server.h
index 078019b..9710be3 100644
--- a/arch/powerpc/include/asm/perf_event_server.h
+++ b/arch/powerpc/include/asm/perf_event_server.h
@@ -49,6 +49,7 @@ struct power_pmu {
#define PPMU_ALT_SIPR2 /* uses alternate posn for
SIPR/HV */
#define PPMU_NO_SIPR 4 /* no SIPR/HV in MMCRA at all */
#define PPMU_NO_CONT_SAMPLING8 /* no continuous sampling */
+#define PPMU_SIAR_VALID 16 /* Processor has SIAR Valid bit
*/
/*
* Values for flags to get_alternatives()
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 65b6164..a7a9a8b 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -601,6 +601,10 @@
#define POWER6_MMCRA_SIPR 0x0200ULL
#define POWER6_MMCRA_THRM 0x0020UL
#define POWER6_MMCRA_OTHER 0x000EUL
+
+#define POWER7P_MMCRA_SIAR_VALID 0x1000/* P7+ SIAR contents
valid */
+#define POWER7P_MMCRA_SDAR_VALID 0x0800/* P7+ SDAR contents
valid */
+
#define SPRN_PMC1787
#define SPRN_PMC2788
#define SPRN_PMC3789
diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c
index 8f84bcb..0a392d8 100644
--- a/arch/powerpc/perf/core-book3s.c
+++ b/arch/powerpc/perf/core-book3s.c
@@ -103,14 +103,20 @@ static inline unsigned long perf_ip_adjust(struct
pt_regs *regs)
* If we're not doing instruction sampling, give them the SDAR
* (sampled data address). If we are doing instruction sampling, then
* only give them the SDAR if it corresponds to the instruction
- * pointed to by SIAR; this is indicated by the [POWER6_]MMCRA_SDSYNC
- * bit in MMCRA.
+ * pointed to by SIAR; this is indicated by the [POWER6_]MMCRA_SDSYNC or
+ * the [POWER7P_]MMCRA_SDAR_VALID bit in MMCRA.
*/
static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp)
{
unsigned long mmcra = regs-dsisr;
- unsigned long sdsync = (ppmu-flags PPMU_ALT_SIPR) ?
- POWER6_MMCRA_SDSYNC : MMCRA_SDSYNC;
+ unsigned long sdsync;
+
+ if (ppmu-flags PPMU_SIAR_VALID)
+ sdsync = POWER7P_MMCRA_SDAR_VALID;
+ else if (ppmu-flags PPMU_ALT_SIPR)
+ sdsync = POWER6_MMCRA_SDSYNC;
+ else
+ sdsync = MMCRA_SDSYNC;
if (!(mmcra MMCRA_SAMPLE_ENABLE) || (mmcra sdsync))
*addrp = mfspr(SPRN_SDAR);
@@ -1248,6 +1254,25 @@ struct pmu power_pmu = {
.event_idx = power_pmu_event_idx,
};
+
+/*
+ * On processors like P7+ that have the SIAR-Valid bit, marked instructions
+ * must be sampled only if the SIAR-valid bit is set.
+ *
+ * For unmarked instructions and for processors that don't have the
SIAR-Valid
+ * bit, assume that SIAR is valid.
+ */
+static inline int siar_valid(struct pt_regs *regs)
+{
+ unsigned long mmcra = regs-dsisr;
+ int marked = mmcra MMCRA_SAMPLE_ENABLE;
+
+ if ((ppmu-flags PPMU_SIAR_VALID) marked)
+ return mmcra POWER7P_MMCRA_SIAR_VALID;
+
+ return 1;
+}
+
/*
* A counter has overflowed; update its count and record
* things if requested. Note that interrupts are hard-disabled
@@ -1281,7 +1306,7 @@ static void record_and_restart(struct perf_event
*event, unsigned long val,
left += period;
Re: [PATCH v2 1/2] [powerpc] Change memory_limit from phys_addr_t to unsigned long long
On Tue, 2012-08-21 at 17:12 +0530, Suzuki K. Poulose wrote: There are some device-tree nodes, whose values are of type phys_addr_t. The phys_addr_t is variable sized based on the CONFIG_PHSY_T_64BIT. Change these to a fixed unsigned long long for consistency. This patch does the change only for memory_limit. The following is a list of such variables which need the change: 1) kernel_end, crashk_size - in arch/powerpc/kernel/machine_kexec.c 2) (struct resource *)crashk_res.start - We could export a local static variable from machine_kexec.c. Changing the above values might break the kexec-tools. So, I will fix kexec-tools first to handle the different sized values and then change the above. Suggested-by: Benjamin Herrenschmidt b...@kernel.crashing.org Signed-off-by: Suzuki K. Poulose suz...@in.ibm.com --- Breaks the build on some configs (with 32-bit phys_addr_t): /home/benh/linux-powerpc-test/arch/powerpc/kernel/prom.c: In function 'early_init_devtree': /home/benh/linux-powerpc-test/arch/powerpc/kernel/prom.c:664:25: error: comparison of distinct pointer types lacks a cast I'm fixing that myself this time but please be more careful. Cheers, Ben. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH -V8 0/11] arch/powerpc: Add 64TB support to ppc64
On Thu, 2012-09-06 at 20:59 +0530, Aneesh Kumar K.V wrote: Hi, This patchset include patches for supporting 64TB with ppc64. I haven't booted this on hardware with 64TB memory yet. But they boot fine on real hardware with less memory. Changes extend VSID bits to 38 bits for a 256MB segment and 26 bits for 1TB segments. Your series breaks the embedded 64-bit build. You seem to be hard wiring dependencies on slice stuff all over 64-bit stuff regardless of the MMU type or the value of CONFIG_MM_SLICES. Also all these: +/* 4 bits per slice and we have one slice per 1TB */ +#if 0 /* We can't directly include pgtable.h hence this hack */ +#define SLICE_ARRAY_SIZE (PGTABLE_RANGE 41) +#else +/* Right now we only support 64TB */ +#define SLICE_ARRAY_SIZE 32 +#endif Things are just too horrible. Find a different way of doing it, if necessary create a new range define somewhere, whatever but don't leave that crap as-is, it's too wrong. Dropping the series for now. Cheers, Ben. Changes from V7: * Address review feedback Changes from V6: * rebase to latest upstream (5b716ac728bcc01b1f2a7ed6e437196602237c27) Changes from v5: * Address review feedback Changes from v4: * Drop patch arch/powerpc: properly offset the context bits for 1T segemnts based on review feedback * split CONTEXT_BITS related changes from patch 12 * Add a new doc update patch Changes from v3: * Address review comments. * Added new patch to ensure proto-VSID isolation between kernel and user space Changes from V2: * Fix few FIXMEs in the patchset. I have added them as separate patch for easier review. That should help us to drop those changes if we don't agree. Changes from V1: * Drop the usage of structure (struct virt_addr) to carry virtual address. We now represent virtual address via vpn which is virtual address shifted right 12 bits. Thanks, -aneesh ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 4/5] powerpc: Rework set_dabr so it can take a DABRX value as well
Geert Uytterhoeven ge...@linux-m68k.org wrote:
On Thu, Sep 6, 2012 at 7:17 AM, Michael Neuling mi...@neuling.org wrote:
Rework set_dabr to take a DABRX value as well. We are not actually
changing any functionality at this stage, just preparing for that.
You are changing functionality.
You are right.. I'll fix that up.. Sorry.
#define DABRX_USER (1UL 0)
#define DABRX_KERNEL (1UL 1)
+#define DABRX_HYP(1UL 2)
+#define DABRX_BTI(1UL 3)
+#define DABRX_ALL (DABRX_BTI | DABRX_HYP | DABRX_KERNEL | DABRX_USER)
--- a/arch/powerpc/platforms/cell/beat.c
+++ b/arch/powerpc/platforms/cell/beat.c
@@ -136,9 +136,9 @@ ssize_t beat_nvram_get_size(void)
return BEAT_NVRAM_SIZE;
}
-int beat_set_xdabr(unsigned long dabr)
+int beat_set_xdabr(unsigned long dabr, unsigned long dabrx)
{
- if (beat_set_dabr(dabr, DABRX_KERNEL | DABRX_USER))
+ if (beat_set_dabr(dabr, dabrx))
return -1;
return 0;
}
--- a/arch/powerpc/platforms/ps3/setup.c
+++ b/arch/powerpc/platforms/ps3/setup.c
@@ -184,11 +184,9 @@ early_param(ps3flash, early_parse_ps3flash);
#define prealloc_ps3flash_bounce_buffer() do { } while (0)
#endif
-static int ps3_set_dabr(unsigned long dabr)
+static int ps3_set_dabr(unsigned long dabr, unsigned long dabrx)
{
- enum {DABR_USER = 1, DABR_KERNEL = 2,};
-
- return lv1_set_dabr(dabr, DABR_KERNEL | DABR_USER) ? -1 : 0;
+ return lv1_set_dabr(dabr, dabrx) ? -1 : 0;
}
- set_dabr(dabr.address | (dabr.enabled 7));
+ set_dabr(dabr.address | (dabr.enabled 7), DABRX_ALL);
Before, beat_set_dabr() and lv1_set_dabr() would have been called with dabrx
= 3
(DABRX_KERNEL | DABRX_USER). Now they're called with dabrx = 15
(DABRX_ALL = DABRX_BTI | DABRX_HYP | DABRX_KERNEL | DABRX_USER).
No idea what's the impact of this...
Do you know if the ps3 hypervisor will allow us to set DABRX_BTI or
DABRX_HYP? phyp wont.
Mikey
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Re: [PATCH] powerpc/booke-64: fix tlbsrx. path in bolted tlb handler
On Tue, 2012-06-12 at 17:02 -0500, Scott Wood wrote: It was branching to the cleanup part of the non-bolted handler, which would have been bad if there were any chips with tlbsrx. that use the bolted handler. Still relevant ? It doesn't apply anymore :-) Cheers, Ben. Signed-off-by: Scott Wood sc...@tyr.buserror.net --- arch/powerpc/mm/tlb_low_64e.S |3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/arch/powerpc/mm/tlb_low_64e.S b/arch/powerpc/mm/tlb_low_64e.S index ff672bd..efe0f33 100644 --- a/arch/powerpc/mm/tlb_low_64e.S +++ b/arch/powerpc/mm/tlb_low_64e.S @@ -128,7 +128,7 @@ BEGIN_MMU_FTR_SECTION */ PPC_TLBSRX_DOT(0,r16) ldx r14,r14,r15 /* grab pgd entry */ - beq normal_tlb_miss_done/* tlb exists already, bail */ + beq tlb_miss_done_bolted/* tlb exists already, bail */ MMU_FTR_SECTION_ELSE ldx r14,r14,r15 /* grab pgd entry */ ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_USE_TLBRSRV) @@ -184,6 +184,7 @@ ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_USE_TLBRSRV) mtspr SPRN_MAS7_MAS3,r15 tlbwe +tlb_miss_done_bolted: TLB_MISS_STATS_X(MMSTAT_TLB_MISS_NORM_OK) tlb_epilog_bolted rfi ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 2/2] powerpc/e6500: TLB miss handler with hardware tablewalk support
On Thu, 2012-06-14 at 18:41 -0500, Scott Wood wrote:
There are a few things that make the existing hw tablewalk handlers
unsuitable for e6500:
- Indirect entries go in TLB1 (though the resulting direct entries go in
TLB0).
- It has threads, but no tlbsrx. -- so we need a spinlock and
a normal tlbsx. Because we need this lock, hardware tablewalk
is mandatory on e6500 unless we want to add spinlock+tlbsx to
the normal bolted TLB miss handler.
- TLB1 has no HES (nor next-victim hint) so we need software round robin
(TODO: integrate this round robin data with hugetlb/KVM)
- The existing tablewalk handlers map half of a page table at a time,
because IBM hardware has a fixed 1MiB indirect page size. e6500
has variable size indirect entries, with a minimum of 2MiB.
So we can't do the half-page indirect mapping, and even if we
could it would be less efficient than mapping the full page.
- Like on e5500, the linear mapping is bolted, so we don't need the
overhead of supporting nested tlb misses.
Note that hardware tablewalk does not work in rev1 of e6500.
We do not expect to support e6500 rev1 in mainline Linux.
Signed-off-by: Scott Wood scottw...@freescale.com
---
arch/powerpc/include/asm/mmu-book3e.h | 13 +++
arch/powerpc/include/asm/mmu.h| 21 ++--
arch/powerpc/include/asm/paca.h |6 +
arch/powerpc/kernel/asm-offsets.c | 10 ++
arch/powerpc/kernel/paca.c|5 +
arch/powerpc/kernel/setup_64.c| 33 +++
arch/powerpc/mm/fsl_booke_mmu.c |8 ++
arch/powerpc/mm/tlb_low_64e.S | 167
+
arch/powerpc/mm/tlb_nohash.c | 109 --
9 files changed, 335 insertions(+), 37 deletions(-)
diff --git a/arch/powerpc/include/asm/mmu-book3e.h
b/arch/powerpc/include/asm/mmu-book3e.h
index eeabcdb..3072aa0 100644
--- a/arch/powerpc/include/asm/mmu-book3e.h
+++ b/arch/powerpc/include/asm/mmu-book3e.h
@@ -264,8 +264,21 @@ extern struct mmu_psize_def
mmu_psize_defs[MMU_PAGE_COUNT];
extern int mmu_linear_psize;
extern int mmu_vmemmap_psize;
+struct book3e_tlb_per_core {
+ /* For software way selection, as on Freescale TLB1 */
+ u8 esel_next, esel_max, esel_first;
+
+ /* Per-core spinlock for e6500 TLB handlers (no tlbsrx.) */
+ u8 lock;
+};
I'm no fan of the name ... tlb_core_data ? Probably don't even need the
book3e prefix really.
#ifdef CONFIG_PPC64
extern unsigned long linear_map_top;
+extern int book3e_htw_mode;
+
+#define PPC_HTW_NONE 0
+#define PPC_HTW_IBM 1
+#define PPC_HTW_E65002
Sad :-( Wonder why we bother with an architecture, really ...
/*
* 64-bit booke platforms don't load the tlb in the tlb miss handler code.
diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h
index a9e9ec6..63d97eb 100644
--- a/arch/powerpc/include/asm/mmu.h
+++ b/arch/powerpc/include/asm/mmu.h
@@ -170,16 +170,17 @@ extern u64 ppc64_rma_size;
#define MMU_PAGE_64K_AP 3 /* Admixed pages (hash64 only) */
#define MMU_PAGE_256K4
#define MMU_PAGE_1M 5
-#define MMU_PAGE_4M 6
-#define MMU_PAGE_8M 7
-#define MMU_PAGE_16M 8
-#define MMU_PAGE_64M 9
-#define MMU_PAGE_256M10
-#define MMU_PAGE_1G 11
-#define MMU_PAGE_16G 12
-#define MMU_PAGE_64G 13
-
-#define MMU_PAGE_COUNT 14
+#define MMU_PAGE_2M 6
+#define MMU_PAGE_4M 7
+#define MMU_PAGE_8M 8
+#define MMU_PAGE_16M 9
+#define MMU_PAGE_64M 10
+#define MMU_PAGE_256M11
+#define MMU_PAGE_1G 12
+#define MMU_PAGE_16G 13
+#define MMU_PAGE_64G 14
+
+#define MMU_PAGE_COUNT 15
Let's pray that won't hit a funny bug on server :-)
#if defined(CONFIG_PPC_STD_MMU_64)
/* 64-bit classic hash table MMU */
diff --git a/arch/powerpc/include/asm/paca.h b/arch/powerpc/include/asm/paca.h
index daf813f..4e18bb5 100644
--- a/arch/powerpc/include/asm/paca.h
+++ b/arch/powerpc/include/asm/paca.h
@@ -108,6 +108,12 @@ struct paca_struct {
/* Keep pgd in the same cacheline as the start of extlb */
pgd_t *pgd __attribute__((aligned(0x80))); /* Current PGD */
pgd_t *kernel_pgd; /* Kernel PGD */
+
+ struct book3e_tlb_per_core tlb_per_core;
+
+ /* Points to the tlb_per_core of the first thread on this core. */
+ struct book3e_tlb_per_core *tlb_per_core_ptr;
+
That's gross. Can't you allocate them elsewhere and then populate the
PACA pointers ?
/* We can have up to 3 levels of reentrancy in the TLB miss handler */
u64 extlb[3][EX_TLB_SIZE / sizeof(u64)];
u64 exmc[8];/* used for machine checks */
diff --git a/arch/powerpc/kernel/asm-offsets.c
b/arch/powerpc/kernel/asm-offsets.c
index 52c7ad7..61f4634 100644
--- a/arch/powerpc/kernel/asm-offsets.c
+++ b/arch/powerpc/kernel/asm-offsets.c
@@ -168,6 +168,16 @@ int main(void)
DEFINE(PACA_MC_STACK,
Re: [PATCH 4/5] powerpc: Rework set_dabr so it can take a DABRX value as well
Hi Mikey,
On Fri, 7 Sep 2012, Michael Neuling wrote:
Geert Uytterhoeven ge...@linux-m68k.org wrote:
On Thu, Sep 6, 2012 at 7:17 AM, Michael Neuling mi...@neuling.org wrote:
Rework set_dabr to take a DABRX value as well. We are not actually
changing any functionality at this stage, just preparing for that.
You are changing functionality.
You are right.. I'll fix that up.. Sorry.
#define DABRX_USER (1UL 0)
#define DABRX_KERNEL (1UL 1)
+#define DABRX_HYP(1UL 2)
+#define DABRX_BTI(1UL 3)
+#define DABRX_ALL (DABRX_BTI | DABRX_HYP | DABRX_KERNEL |
DABRX_USER)
--- a/arch/powerpc/platforms/cell/beat.c
+++ b/arch/powerpc/platforms/cell/beat.c
@@ -136,9 +136,9 @@ ssize_t beat_nvram_get_size(void)
return BEAT_NVRAM_SIZE;
}
-int beat_set_xdabr(unsigned long dabr)
+int beat_set_xdabr(unsigned long dabr, unsigned long dabrx)
{
- if (beat_set_dabr(dabr, DABRX_KERNEL | DABRX_USER))
+ if (beat_set_dabr(dabr, dabrx))
return -1;
return 0;
}
--- a/arch/powerpc/platforms/ps3/setup.c
+++ b/arch/powerpc/platforms/ps3/setup.c
@@ -184,11 +184,9 @@ early_param(ps3flash, early_parse_ps3flash);
#define prealloc_ps3flash_bounce_buffer() do { } while (0)
#endif
-static int ps3_set_dabr(unsigned long dabr)
+static int ps3_set_dabr(unsigned long dabr, unsigned long dabrx)
{
- enum {DABR_USER = 1, DABR_KERNEL = 2,};
-
- return lv1_set_dabr(dabr, DABR_KERNEL | DABR_USER) ? -1 : 0;
+ return lv1_set_dabr(dabr, dabrx) ? -1 : 0;
}
- set_dabr(dabr.address | (dabr.enabled 7));
+ set_dabr(dabr.address | (dabr.enabled 7), DABRX_ALL);
Before, beat_set_dabr() and lv1_set_dabr() would have been called with
dabrx = 3
(DABRX_KERNEL | DABRX_USER). Now they're called with dabrx = 15
(DABRX_ALL = DABRX_BTI | DABRX_HYP | DABRX_KERNEL | DABRX_USER).
No idea what's the impact of this...
Do you know if the ps3 hypervisor will allow us to set DABRX_BTI or
DABRX_HYP? phyp wont.
According to the documenation, all bits but DABRX_USER, DABRX_KERNEL, and
DABRX_BTI must be zero. This implies DABRX_HYP cannot be set.
BTW, the requirement that DABRX_USER and DABRX_KERNEL cannot both be zero
at the same time is also there, cfr. your comment and check in
pseries_set_xdabr().
Unfortunately, I cannot test it.
With kind regards,
Geert Uytterhoeven
Software Architect
Technology and Software Centre Europe
Sony Belgium, bijkantoor van Sony Europe Limited.
Da Vincilaan 7-D1 · B-1935 Zaventem · Belgium
Phone: +32 (0)2 700 8453
Fax:+32 (0)2 700 8622
E-mail: geert.uytterhoe...@sonycom.com
Sony Europe Limited. A company registered in England and Wales.
Registered office: The Heights, Brooklands, Weybridge, Surrey. KT13 0XW.
United Kingdom
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Re: [PATCH -V8 0/11] arch/powerpc: Add 64TB support to ppc64
Benjamin Herrenschmidt b...@kernel.crashing.org writes: On Thu, 2012-09-06 at 20:59 +0530, Aneesh Kumar K.V wrote: Hi, This patchset include patches for supporting 64TB with ppc64. I haven't booted this on hardware with 64TB memory yet. But they boot fine on real hardware with less memory. Changes extend VSID bits to 38 bits for a 256MB segment and 26 bits for 1TB segments. Your series breaks the embedded 64-bit build. You seem to be hard wiring dependencies on slice stuff all over 64-bit stuff regardless of the MMU type or the value of CONFIG_MM_SLICES. Also all these: +/* 4 bits per slice and we have one slice per 1TB */ +#if 0 /* We can't directly include pgtable.h hence this hack */ +#define SLICE_ARRAY_SIZE (PGTABLE_RANGE 41) +#else +/* Right now we only support 64TB */ +#define SLICE_ARRAY_SIZE 32 +#endif Things are just too horrible. Find a different way of doing it, if necessary create a new range define somewhere, whatever but don't leave that crap as-is, it's too wrong. Dropping the series for now. How about the change below. If you are ok moving the range details to new header, I can fold this into patch 7 and send a new series -aneesh diff --git a/arch/powerpc/include/asm/mmu-hash64.h b/arch/powerpc/include/asm/mmu-hash64.h index 428f23e..057a12a 100644 --- a/arch/powerpc/include/asm/mmu-hash64.h +++ b/arch/powerpc/include/asm/mmu-hash64.h @@ -14,6 +14,7 @@ #include asm/asm-compat.h #include asm/page.h +#include asm/pgtable-ppc64-range.h /* * Segment table @@ -415,12 +416,7 @@ extern void slb_set_size(u16 size); add rt,rt,rx /* 4 bits per slice and we have one slice per 1TB */ -#if 0 /* We can't directly include pgtable.h hence this hack */ #define SLICE_ARRAY_SIZE (PGTABLE_RANGE 41) -#else -/* Right now we only support 64TB */ -#define SLICE_ARRAY_SIZE 32 -#endif #ifndef __ASSEMBLY__ diff --git a/arch/powerpc/include/asm/page_64.h b/arch/powerpc/include/asm/page_64.h index b55beb4..01ab518 100644 --- a/arch/powerpc/include/asm/page_64.h +++ b/arch/powerpc/include/asm/page_64.h @@ -78,16 +78,14 @@ extern u64 ppc64_pft_size; #define GET_LOW_SLICE_INDEX(addr) ((addr) SLICE_LOW_SHIFT) #define GET_HIGH_SLICE_INDEX(addr) ((addr) SLICE_HIGH_SHIFT) -/* 1 bit per slice and we have one slice per 1TB */ -#if 0 /* We can't directly include pgtable.h hence this hack */ -#define SLICE_MASK_SIZE (PGTABLE_RANGE 43) -#else -/* +/* 1 bit per slice and we have one slice per 1TB * Right now we support only 64TB. * IF we change this we will have to change the type * of high_slices */ #define SLICE_MASK_SIZE 8 +#if (PGTABLE_RANGE 43) SLICE_MASK_SIZE +#error PGTABLE_RANGE exceeds slice_mask high_slices size #endif #ifndef __ASSEMBLY__ diff --git a/arch/powerpc/include/asm/pgtable-ppc64-range.h b/arch/powerpc/include/asm/pgtable-ppc64-range.h new file mode 100644 index 000..04a825c --- /dev/null +++ b/arch/powerpc/include/asm/pgtable-ppc64-range.h @@ -0,0 +1,16 @@ +#ifndef _ASM_POWERPC_PGTABLE_PPC64_RANGE_H_ +#define _ASM_POWERPC_PGTABLE_PPC64_RANGE_H_ + +#ifdef CONFIG_PPC_64K_PAGES +#include asm/pgtable-ppc64-64k.h +#else +#include asm/pgtable-ppc64-4k.h +#endif + +/* + * Size of EA range mapped by our pagetables. + */ +#define PGTABLE_EADDR_SIZE (PTE_INDEX_SIZE + PMD_INDEX_SIZE + \ + PUD_INDEX_SIZE + PGD_INDEX_SIZE + PAGE_SHIFT) +#define PGTABLE_RANGE (ASM_CONST(1) PGTABLE_EADDR_SIZE) +#endif diff --git a/arch/powerpc/include/asm/pgtable-ppc64.h b/arch/powerpc/include/asm/pgtable-ppc64.h index dea953f..ee783b4 100644 --- a/arch/powerpc/include/asm/pgtable-ppc64.h +++ b/arch/powerpc/include/asm/pgtable-ppc64.h @@ -13,13 +13,7 @@ #define FIRST_USER_ADDRESS 0 -/* - * Size of EA range mapped by our pagetables. - */ -#define PGTABLE_EADDR_SIZE (PTE_INDEX_SIZE + PMD_INDEX_SIZE + \ - PUD_INDEX_SIZE + PGD_INDEX_SIZE + PAGE_SHIFT) -#define PGTABLE_RANGE (ASM_CONST(1) PGTABLE_EADDR_SIZE) - +#include asm/pgtable-ppc64-range.h /* Some sanity checking */ #if TASK_SIZE_USER64 PGTABLE_RANGE @@ -32,14 +26,6 @@ #endif #endif -#if (PGTABLE_RANGE 41) SLICE_ARRAY_SIZE -#error PGTABLE_RANGE exceeds SLICE_ARRAY_SIZE -#endif - -#if (PGTABLE_RANGE 43) SLICE_MASK_SIZE -#error PGTABLE_RANGE exceeds slice_mask high_slices size -#endif - /* * Define the address range of the kernel non-linear virtual area */ ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 4/5] powerpc: Rework set_dabr so it can take a DABRX value as well
Geert Uytterhoeven geert.uytterhoe...@sonycom.com wrote:
Hi Mikey,
On Fri, 7 Sep 2012, Michael Neuling wrote:
Geert Uytterhoeven ge...@linux-m68k.org wrote:
On Thu, Sep 6, 2012 at 7:17 AM, Michael Neuling mi...@neuling.org wrote:
Rework set_dabr to take a DABRX value as well. We are not actually
changing any functionality at this stage, just preparing for that.
You are changing functionality.
You are right.. I'll fix that up.. Sorry.
#define DABRX_USER (1UL 0)
#define DABRX_KERNEL (1UL 1)
+#define DABRX_HYP(1UL 2)
+#define DABRX_BTI(1UL 3)
+#define DABRX_ALL (DABRX_BTI | DABRX_HYP | DABRX_KERNEL |
DABRX_USER)
--- a/arch/powerpc/platforms/cell/beat.c
+++ b/arch/powerpc/platforms/cell/beat.c
@@ -136,9 +136,9 @@ ssize_t beat_nvram_get_size(void)
return BEAT_NVRAM_SIZE;
}
-int beat_set_xdabr(unsigned long dabr)
+int beat_set_xdabr(unsigned long dabr, unsigned long dabrx)
{
- if (beat_set_dabr(dabr, DABRX_KERNEL | DABRX_USER))
+ if (beat_set_dabr(dabr, dabrx))
return -1;
return 0;
}
--- a/arch/powerpc/platforms/ps3/setup.c
+++ b/arch/powerpc/platforms/ps3/setup.c
@@ -184,11 +184,9 @@ early_param(ps3flash, early_parse_ps3flash);
#define prealloc_ps3flash_bounce_buffer() do { } while (0)
#endif
-static int ps3_set_dabr(unsigned long dabr)
+static int ps3_set_dabr(unsigned long dabr, unsigned long dabrx)
{
- enum {DABR_USER = 1, DABR_KERNEL = 2,};
-
- return lv1_set_dabr(dabr, DABR_KERNEL | DABR_USER) ? -1 : 0;
+ return lv1_set_dabr(dabr, dabrx) ? -1 : 0;
}
- set_dabr(dabr.address | (dabr.enabled 7));
+ set_dabr(dabr.address | (dabr.enabled 7), DABRX_ALL);
Before, beat_set_dabr() and lv1_set_dabr() would have been called with
dabrx = 3
(DABRX_KERNEL | DABRX_USER). Now they're called with dabrx = 15
(DABRX_ALL = DABRX_BTI | DABRX_HYP | DABRX_KERNEL | DABRX_USER).
No idea what's the impact of this...
Do you know if the ps3 hypervisor will allow us to set DABRX_BTI or
DABRX_HYP? phyp wont.
According to the documenation, all bits but DABRX_USER, DABRX_KERNEL, and
DABRX_BTI must be zero. This implies DABRX_HYP cannot be set.
BTW, the requirement that DABRX_USER and DABRX_KERNEL cannot both be zero
at the same time is also there, cfr. your comment and check in
pseries_set_xdabr().
Unfortunately, I cannot test it.
OK thanks, I'll mask appropriately.
Any place we can get a copy of the PS3 HV doc you're quoting from?
Mikey
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