[PATCH 5/5] perf: Create a sysfs entry for Power event format
Create a sysfs entry, '/sys/bus/event_source/devices/cpu/format/event'
which describes the format of a POWER cpu.
The format of the event is the same for all POWER cpus at least in
(Power6, Power7), so bulk of this change is common in the code common
to POWER cpus.
This code is based on corresponding code in x86.
Changelog[v2]: [Jiri Osla] Use PMU_FORMAT_ATTR() rather than duplicating it.
Signed-off-by: Sukadev Bhattiprolu
---
arch/powerpc/include/asm/perf_event_server.h |6 ++
arch/powerpc/perf/core-book3s.c | 12
arch/powerpc/perf/power7-pmu.c |1 +
3 files changed, 19 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/include/asm/perf_event_server.h
b/arch/powerpc/include/asm/perf_event_server.h
index 4315bc9..f8f7240 100644
--- a/arch/powerpc/include/asm/perf_event_server.h
+++ b/arch/powerpc/include/asm/perf_event_server.h
@@ -136,3 +136,9 @@ extern ssize_t power_events_sysfs_show(struct device *dev,
#definePOWER_EVENT_ATTR(_name, _id)EVENT_ATTR(PM_##_name, _id, _p)
#definePOWER_EVENT_PTR(_id)EVENT_PTR(_id, _p)
+
+/*
+ * Format of a perf event is the same on all POWER cpus. Declare a
+ * common sysfs attribute group that individual POWER cpus can share.
+ */
+extern struct attribute_group power_pmu_format_group;
diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c
index fa476d5..4ae044b 100644
--- a/arch/powerpc/perf/core-book3s.c
+++ b/arch/powerpc/perf/core-book3s.c
@@ -1315,6 +1315,18 @@ ssize_t power_events_sysfs_show(struct device *dev,
return sprintf(page, "event=0x%02llx\n", pmu_attr->id);
}
+PMU_FORMAT_ATTR(event, "config:0-20");
+
+static struct attribute *power_pmu_format_attr[] = {
+ &format_attr_event.attr,
+ NULL,
+};
+
+struct attribute_group power_pmu_format_group = {
+ .name = "format",
+ .attrs = power_pmu_format_attr,
+};
+
struct pmu power_pmu = {
.pmu_enable = power_pmu_enable,
.pmu_disable= power_pmu_disable,
diff --git a/arch/powerpc/perf/power7-pmu.c b/arch/powerpc/perf/power7-pmu.c
index 5627940..5fb3c9b 100644
--- a/arch/powerpc/perf/power7-pmu.c
+++ b/arch/powerpc/perf/power7-pmu.c
@@ -410,6 +410,7 @@ static struct attribute_group power7_pmu_events_group = {
};
static const struct attribute_group *power7_pmu_attr_groups[] = {
+ &power_pmu_format_group,
&power7_pmu_events_group,
NULL,
};
--
1.7.1
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[PATCH 4/5] perf/POWER7: Make some POWER7 events available in sysfs
Make some POWER7-specific perf events available in sysfs.
$ /bin/ls -1 /sys/bus/event_source/devices/cpu/events/
branch-instructions
branch-misses
cache-misses
cache-references
cpu-cycles
instructions
PM_BRU_FIN
PM_BRU_MPRED
PM_CMPLU_STALL
PM_CYC
PM_GCT_NOSLOT_CYC
PM_INST_CMPL
PM_LD_MISS_L1
PM_LD_REF_L1
stalled-cycles-backend
stalled-cycles-frontend
where the 'PM_*' events are POWER specific and the others are the
generic events.
This will enable users to specify these events with their symbolic
names rather than with their raw code.
perf stat -e 'cpu/PM_CYC' ...
Signed-off-by: Sukadev Bhattiprolu
---
arch/powerpc/include/asm/perf_event_server.h |2 ++
arch/powerpc/perf/power7-pmu.c | 18 ++
2 files changed, 20 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/include/asm/perf_event_server.h
b/arch/powerpc/include/asm/perf_event_server.h
index 20ca90f..4315bc9 100644
--- a/arch/powerpc/include/asm/perf_event_server.h
+++ b/arch/powerpc/include/asm/perf_event_server.h
@@ -134,3 +134,5 @@ extern ssize_t power_events_sysfs_show(struct device *dev,
#defineGENERIC_EVENT_ATTR(_name, _id) EVENT_ATTR(_name, _id, _g)
#defineGENERIC_EVENT_PTR(_id) EVENT_PTR(_id, _g)
+#definePOWER_EVENT_ATTR(_name, _id)EVENT_ATTR(PM_##_name, _id, _p)
+#definePOWER_EVENT_PTR(_id)EVENT_PTR(_id, _p)
diff --git a/arch/powerpc/perf/power7-pmu.c b/arch/powerpc/perf/power7-pmu.c
index ae5d757..5627940 100644
--- a/arch/powerpc/perf/power7-pmu.c
+++ b/arch/powerpc/perf/power7-pmu.c
@@ -373,6 +373,15 @@ GENERIC_EVENT_ATTR(cache-misses, LD_MISS_L1);
GENERIC_EVENT_ATTR(branch-instructions,BRU_FIN);
GENERIC_EVENT_ATTR(branch-misses, BRU_MPRED);
+POWER_EVENT_ATTR(CYC, CYC);
+POWER_EVENT_ATTR(GCT_NOSLOT_CYC, GCT_NOSLOT_CYC);
+POWER_EVENT_ATTR(CMPLU_STALL, CMPLU_STALL);
+POWER_EVENT_ATTR(INST_CMPL,INST_CMPL);
+POWER_EVENT_ATTR(LD_REF_L1,LD_REF_L1);
+POWER_EVENT_ATTR(LD_MISS_L1, LD_MISS_L1);
+POWER_EVENT_ATTR(BRU_FIN, BRU_FIN)
+POWER_EVENT_ATTR(BRU_MPRED,BRU_MPRED);
+
static struct attribute *power7_events_attr[] = {
GENERIC_EVENT_PTR(CYC),
GENERIC_EVENT_PTR(GCT_NOSLOT_CYC),
@@ -382,6 +391,15 @@ static struct attribute *power7_events_attr[] = {
GENERIC_EVENT_PTR(LD_MISS_L1),
GENERIC_EVENT_PTR(BRU_FIN),
GENERIC_EVENT_PTR(BRU_MPRED),
+
+ POWER_EVENT_PTR(CYC),
+ POWER_EVENT_PTR(GCT_NOSLOT_CYC),
+ POWER_EVENT_PTR(CMPLU_STALL),
+ POWER_EVENT_PTR(INST_CMPL),
+ POWER_EVENT_PTR(LD_REF_L1),
+ POWER_EVENT_PTR(LD_MISS_L1),
+ POWER_EVENT_PTR(BRU_FIN),
+ POWER_EVENT_PTR(BRU_MPRED),
NULL
};
--
1.7.1
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[PATCH 3/5] perf/POWER7: Make generic event translations available in sysfs
[PATCH 3/5] perf/POWER7: Make generic event translations available in sysfs
Make the generic perf events in POWER7 available via sysfs.
$ ls /sys/bus/event_source/devices/cpu/events
branch-instructions
branch-misses
cache-misses
cache-references
cpu-cycles
instructions
stalled-cycles-backend
stalled-cycles-frontend
$ cat /sys/bus/event_source/devices/cpu/events/cache-misses
event=0x400f0
This patch is based on commits that implement this functionality on x86.
Eg:
commit a47473939db20e3961b200eb00acf5fcf084d755
Author: Jiri Olsa
Date: Wed Oct 10 14:53:11 2012 +0200
perf/x86: Make hardware event translations available in sysfs
Signed-off-by: Sukadev Bhattiprolu
---
arch/powerpc/include/asm/perf_event_server.h | 25 +++
arch/powerpc/perf/core-book3s.c | 12 +
arch/powerpc/perf/power7-pmu.c | 34 ++
3 files changed, 71 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/include/asm/perf_event_server.h
b/arch/powerpc/include/asm/perf_event_server.h
index 9710be3..20ca90f 100644
--- a/arch/powerpc/include/asm/perf_event_server.h
+++ b/arch/powerpc/include/asm/perf_event_server.h
@@ -11,6 +11,7 @@
#include
#include
+#include
#define MAX_HWEVENTS 8
#define MAX_EVENT_ALTERNATIVES 8
@@ -35,6 +36,7 @@ struct power_pmu {
void(*disable_pmc)(unsigned int pmc, unsigned long mmcr[]);
int (*limited_pmc_event)(u64 event_id);
u32 flags;
+ const struct attribute_group**attr_groups;
int n_generic;
int *generic_events;
int (*cache_events)[PERF_COUNT_HW_CACHE_MAX]
@@ -109,3 +111,26 @@ extern unsigned long perf_instruction_pointer(struct
pt_regs *regs);
* If an event_id is not subject to the constraint expressed by a particular
* field, then it will have 0 in both the mask and value for that field.
*/
+
+extern ssize_t power_events_sysfs_show(struct device *dev,
+ struct device_attribute *attr, char *page);
+
+/*
+ * EVENT_VAR() is same as PMU_EVENT_VAR with a suffix.
+ *
+ * Having a suffix allows us to have aliases in sysfs - eg: the generic
+ * event 'cpu-cycles' can have two entries in sysfs: 'cpu-cycles' and
+ * 'PM_CYC' where the latter is the name by which the event is known in
+ * POWER CPU specification.
+ */
+#defineEVENT_VAR(_id, _suffix) event_attr_##_id##_suffix
+#defineEVENT_PTR(_id, _suffix) PMU_EVENT_PTR(EVENT_VAR(_id,
_suffix))
+#defineEVENT_ID(_id) PME_PM_##_id
+
+#defineEVENT_ATTR(_name, _id, _suffix)
\
+ PMU_EVENT_ATTR(_name, EVENT_VAR(_id, _suffix), EVENT_ID(_id), \
+ power_events_sysfs_show)
+
+#defineGENERIC_EVENT_ATTR(_name, _id) EVENT_ATTR(_name, _id, _g)
+#defineGENERIC_EVENT_PTR(_id) EVENT_PTR(_id, _g)
+
diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c
index aa2465e..fa476d5 100644
--- a/arch/powerpc/perf/core-book3s.c
+++ b/arch/powerpc/perf/core-book3s.c
@@ -1305,6 +1305,16 @@ static int power_pmu_event_idx(struct perf_event *event)
return event->hw.idx;
}
+ssize_t power_events_sysfs_show(struct device *dev,
+ struct device_attribute *attr, char *page)
+{
+ struct perf_pmu_events_attr *pmu_attr;
+
+ pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr);
+
+ return sprintf(page, "event=0x%02llx\n", pmu_attr->id);
+}
+
struct pmu power_pmu = {
.pmu_enable = power_pmu_enable,
.pmu_disable= power_pmu_disable,
@@ -1537,6 +1547,8 @@ int __cpuinit register_power_pmu(struct power_pmu *pmu)
pr_info("%s performance monitor hardware support registered\n",
pmu->name);
+ power_pmu.attr_groups = ppmu->attr_groups;
+
#ifdef MSR_HV
/*
* Use FCHV to ignore kernel events if MSR.HV is set.
diff --git a/arch/powerpc/perf/power7-pmu.c b/arch/powerpc/perf/power7-pmu.c
index 44e70d2..ae5d757 100644
--- a/arch/powerpc/perf/power7-pmu.c
+++ b/arch/powerpc/perf/power7-pmu.c
@@ -363,6 +363,39 @@ static int
power7_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
},
};
+
+GENERIC_EVENT_ATTR(cpu-cycles, CYC);
+GENERIC_EVENT_ATTR(stalled-cycles-frontend,GCT_NOSLOT_CYC);
+GENERIC_EVENT_ATTR(stalled-cycles-backend, CMPLU_STALL);
+GENERIC_EVENT_ATTR(instructions, INST_CMPL);
+GENERIC_EVENT_ATTR(cache-references, LD_REF_L1);
+GENERIC_EVENT_ATTR(cache-misses, LD_MISS_L1);
+GENERIC_EVENT_ATTR(branch-instructions,BRU_FIN);
+GENERIC_EVENT_ATTR(branch-misses, BRU_MPRED);
+
+static struct attribute *power7_even
[PATCH 2/5] perf: Make EVENT_ATTR and EVENT_PTR global
Rename EVENT_ATTR() and EVENT_PTR() PMU_EVENT_ATTR() and PMU_EVENT_PTR().
Make them global so they are available to all architectures.
Further to allow architectures flexibility, have PMU_EVENT_PTR() pass in the
variable name as a parameter.
Signed-off-by: Sukadev Bhattiprolu
---
arch/x86/kernel/cpu/perf_event.c | 17 +
include/linux/perf_event.h | 13 +
2 files changed, 18 insertions(+), 12 deletions(-)
diff --git a/arch/x86/kernel/cpu/perf_event.c b/arch/x86/kernel/cpu/perf_event.c
index 4428fd1..24bc505 100644
--- a/arch/x86/kernel/cpu/perf_event.c
+++ b/arch/x86/kernel/cpu/perf_event.c
@@ -1316,11 +1316,6 @@ static struct attribute_group x86_pmu_format_group = {
.attrs = NULL,
};
-struct perf_pmu_events_attr {
- struct device_attribute attr;
- u64 id;
-};
-
/*
* Remove all undefined events (x86_pmu.event_map(id) == 0)
* out of events_attr attributes.
@@ -1351,14 +1346,12 @@ static ssize_t events_sysfs_show(struct device *dev,
struct device_attribute *at
return x86_pmu.events_sysfs_show(page, config);
}
-#define EVENT_VAR(_id) event_attr_##_id
-#define EVENT_PTR(_id) &event_attr_##_id.attr.attr
+#define EVENT_VAR(_id) event_attr_##_id
+#define EVENT_ID(_id) PERF_COUNT_HW_##_id
+#define EVENT_PTR(_id) PMU_EVENT_PTR(EVENT_VAR(_id))
-#define EVENT_ATTR(_name, _id) \
-static struct perf_pmu_events_attr EVENT_VAR(_id) = { \
- .attr = __ATTR(_name, 0444, events_sysfs_show, NULL), \
- .id = PERF_COUNT_HW_##_id, \
-};
+#define EVENT_ATTR(_name, _id) \
+ PMU_EVENT_ATTR(_name, EVENT_VAR(_id), EVENT_ID(_id), events_sysfs_show)
EVENT_ATTR(cpu-cycles, CPU_CYCLES );
EVENT_ATTR(instructions, INSTRUCTIONS);
diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h
index 6bfb2fa..31692cb 100644
--- a/include/linux/perf_event.h
+++ b/include/linux/perf_event.h
@@ -817,6 +817,19 @@ do {
\
} while (0)
+struct perf_pmu_events_attr {
+ struct device_attribute attr;
+ u64 id;
+};
+
+#define PMU_EVENT_PTR(_var)&_var.attr.attr
+
+#define PMU_EVENT_ATTR(_name, _var, _id, _show)
\
+static struct perf_pmu_events_attr _var = {\
+ .attr = __ATTR(_name, 0444, _show, NULL), \
+ .id = _id, \
+};
+
#define PMU_FORMAT_ATTR(_name, _format)
\
static ssize_t \
_name##_show(struct device *dev, \
--
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[PATCH 1/5] perf/Power7: Use macros to identify perf events
Define and use macros to identify perf events codes This would make it
easier and more readable when these event codes need to be used in more
than one place.
Signed-off-by: Sukadev Bhattiprolu
---
arch/powerpc/perf/power7-pmu.c | 28
1 files changed, 20 insertions(+), 8 deletions(-)
diff --git a/arch/powerpc/perf/power7-pmu.c b/arch/powerpc/perf/power7-pmu.c
index 441af08..44e70d2 100644
--- a/arch/powerpc/perf/power7-pmu.c
+++ b/arch/powerpc/perf/power7-pmu.c
@@ -51,6 +51,18 @@
#define MMCR1_PMCSEL_MSK 0xff
/*
+ * Power7 event codes.
+ */
+#definePME_PM_CYC 0x1e
+#definePME_PM_GCT_NOSLOT_CYC 0x100f8
+#definePME_PM_CMPLU_STALL 0x4000a
+#definePME_PM_INST_CMPL0x2
+#definePME_PM_LD_REF_L10xc880
+#definePME_PM_LD_MISS_L1 0x400f0
+#definePME_PM_BRU_FIN 0x10068
+#definePME_PM_BRU_MPRED0x400f6
+
+/*
* Layout of constraint bits:
* 554433221100
* 3210987654321098765432109876543210987654321098765432109876543210
@@ -296,14 +308,14 @@ static void power7_disable_pmc(unsigned int pmc, unsigned
long mmcr[])
}
static int power7_generic_events[] = {
- [PERF_COUNT_HW_CPU_CYCLES] = 0x1e,
- [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x100f8, /* GCT_NOSLOT_CYC */
- [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 0x4000a, /* CMPLU_STALL */
- [PERF_COUNT_HW_INSTRUCTIONS] = 2,
- [PERF_COUNT_HW_CACHE_REFERENCES] = 0xc880, /* LD_REF_L1_LSU*/
- [PERF_COUNT_HW_CACHE_MISSES] = 0x400f0, /* LD_MISS_L1 */
- [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x10068, /* BRU_FIN */
- [PERF_COUNT_HW_BRANCH_MISSES] = 0x400f6,/* BR_MPRED */
+ [PERF_COUNT_HW_CPU_CYCLES] =PME_PM_CYC,
+ [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = PME_PM_GCT_NOSLOT_CYC,
+ [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =PME_PM_CMPLU_STALL,
+ [PERF_COUNT_HW_INSTRUCTIONS] = PME_PM_INST_CMPL,
+ [PERF_COUNT_HW_CACHE_REFERENCES] = PME_PM_LD_REF_L1,
+ [PERF_COUNT_HW_CACHE_MISSES] = PME_PM_LD_MISS_L1,
+ [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = PME_PM_BRU_FIN,
+ [PERF_COUNT_HW_BRANCH_MISSES] = PME_PM_BRU_MPRED,
};
#define C(x) PERF_COUNT_HW_CACHE_##x
--
1.7.1
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[PATCH] powerpc: Add support for context switching the TAR register
From: Ian Munsie
This patch adds support for enabling and context switching the Target
Address Register in Power8. The TAR is a new special purpose register
that can be used for computed branches with the bctar[l] (branch
conditional to TAR) instruction in the same manner as the count and link
registers.
Signed-off-by: Ian Munsie
Signed-off-by: Matt Evans
---
arch/powerpc/include/asm/cputable.h |3 ++-
arch/powerpc/include/asm/processor.h |1 +
arch/powerpc/include/asm/reg.h|3 +++
arch/powerpc/kernel/asm-offsets.c |1 +
arch/powerpc/kernel/cpu_setup_power.S |7 +++
arch/powerpc/kernel/entry_64.S| 16
6 files changed, 30 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/include/asm/cputable.h
b/arch/powerpc/include/asm/cputable.h
index 74458e69..cbbec56a 100644
--- a/arch/powerpc/include/asm/cputable.h
+++ b/arch/powerpc/include/asm/cputable.h
@@ -172,6 +172,7 @@ extern const char *powerpc_base_platform;
#define CPU_FTR_ICSWX LONG_ASM_CONST(0x1000)
#define CPU_FTR_VMX_COPY LONG_ASM_CONST(0x2000)
#define CPU_FTR_TM LONG_ASM_CONST(0x4000)
+#define CPU_FTR_BCTAR LONG_ASM_CONST(0x8000)
#ifndef __ASSEMBLY__
@@ -417,7 +418,7 @@ extern const char *powerpc_base_platform;
CPU_FTR_DSCR | CPU_FTR_SAO | \
CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
- CPU_FTR_DBELL | CPU_FTR_TM_COMP)
+ CPU_FTR_DBELL | CPU_FTR_TM_COMP | CPU_FTR_BCTAR)
#define CPU_FTRS_CELL (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
diff --git a/arch/powerpc/include/asm/processor.h
b/arch/powerpc/include/asm/processor.h
index 8b2bf7a..cbbd82d 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -275,6 +275,7 @@ struct thread_struct {
unsigned long dscr;
int dscr_inherit;
#endif
+ unsigned long tar;
};
#define ARCH_MIN_TASKALIGN 16
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 5c9fe38..1fa8a56 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -257,6 +257,9 @@
#define SPRN_HRMOR 0x139 /* Real mode offset register */
#define SPRN_HSRR0 0x13A /* Hypervisor Save/Restore 0 */
#define SPRN_HSRR1 0x13B /* Hypervisor Save/Restore 1 */
+#define SPRN_FSCR 0x099 /* Facility Status & Control Register */
+#define FSCR_TAR (1<<8) /* Enable Target Adress Register */
+#define SPRN_TAR 0x32f /* Target Address Register */
#define SPRN_LPCR 0x13E /* LPAR Control Register */
#define LPCR_VPM0(1ul << (63-0))
#define LPCR_VPM1(1ul << (63-1))
diff --git a/arch/powerpc/kernel/asm-offsets.c
b/arch/powerpc/kernel/asm-offsets.c
index 42a4243..77e941e 100644
--- a/arch/powerpc/kernel/asm-offsets.c
+++ b/arch/powerpc/kernel/asm-offsets.c
@@ -145,6 +145,7 @@ int main(void)
DEFINE(TM_FRAME_SIZE, STACK_FRAME_OVERHEAD +
sizeof(struct pt_regs) + 16);
#endif /* CONFIG_TRANSACTIONAL_MEM */
+ DEFINE(THREAD_TAR, offsetof(struct thread_struct, tar));
DEFINE(TI_FLAGS, offsetof(struct thread_info, flags));
DEFINE(TI_LOCAL_FLAGS, offsetof(struct thread_info, local_flags));
diff --git a/arch/powerpc/kernel/cpu_setup_power.S
b/arch/powerpc/kernel/cpu_setup_power.S
index 57cf140..d29facb 100644
--- a/arch/powerpc/kernel/cpu_setup_power.S
+++ b/arch/powerpc/kernel/cpu_setup_power.S
@@ -56,6 +56,7 @@ _GLOBAL(__setup_cpu_power8)
mfspr r3,SPRN_LPCR
orisr3, r3, LPCR_AIL_3@h
bl __init_LPCR
+ bl __init_FSCR
bl __init_TLB
mtlrr11
blr
@@ -112,6 +113,12 @@ __init_LPCR:
isync
blr
+__init_FSCR:
+ mfspr r3,SPRN_FSCR
+ ori r3,r3,FSCR_TAR
+ mtspr SPRN_FSCR,r3
+ blr
+
__init_TLB:
/* Clear the TLB */
li r6,128
diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S
index b3590c3..253885d 100644
--- a/arch/powerpc/kernel/entry_64.S
+++ b/arch/powerpc/kernel/entry_64.S
@@ -451,6 +451,17 @@ END_FTR_SECTION_IFSET(CPU_FTR_DSCR)
std r23,_CCR(r1)
std r1,KSP(r3) /* Set old stack pointer */
+BEGIN_FTR_SECTION
+ /*
+* Back up the TAR across context switches. Note that the TAR is not
+* available for use in the kernel. (To provide this, the TAR should
+* be backed up/restored on exception entry/exit instead, and be in
+* pt_regs. FIXME, this should be in pt_regs anyway (for debug).)
+*/
+ mfspr r0,SPRN_TAR
+ std r0,THREAD_TAR(r3)
+END
Re: [PATCH 1/3] powerpc/book3e: load critical/machine/debug exception stack
On Thu, Oct 25, 2012 at 1:43 AM, Tiejun Chen wrote: > We always alloc critical/machine/debug check exceptions. This is > different from the normal exception. So we should load these exception > stack properly like we did for booke. Tiejun, I'm a little confused by these patches, because the actual critical exception handlers are still commented out: /* Critical Input Interrupt */ START_EXCEPTION(critical_input); CRIT_EXCEPTION_PROLOG(0x100, BOOKE_INTERRUPT_CRITICAL, PROLOG_ADDITION_NONE) // EXCEPTION_COMMON(0x100, PACA_EXCRIT, INTS_DISABLE) // bl special_reg_save_crit // CHECK_NAPPING(); // addir3,r1,STACK_FRAME_OVERHEAD // bl .critical_exception // b ret_from_crit_except b . Are you working on fixing this? I'm trying to fix it, too, but I think you're way ahead of me. -- Timur Tabi Linux kernel developer at Freescale ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [git pull] Please pull powerpc.git next branch
On Mon, Dec 17, 2012 at 3:31 PM, Benjamin Herrenschmidt wrote: > On Sat, 2012-12-15 at 07:44 +1100, Benjamin Herrenschmidt wrote: >> Hi Linus ! >> >> Finally managed to get my head away from some other distractions >> to put this pull request together, sorry for the lateness :-) >> >> The main highlight is probably some base POWER8 support. There's >> more to come such as transactional memory support but that will >> wait for the next one. (next merge window) >> >> Overall it's pretty quiet, or rather I've been pretty poor at >> picking things up from patchwork and reviewing them this time >> around and Kumar no better on the FSL side it seems... > > So it looks like I'm an idiot and totally failed to put your email > address on the CC list of that pull request :-) .. yeah, that helps. Anyway, I've pulled it in, but got a conflict on the kernel_thread cleanups from Al. And since the conflict was in the powerpc assembly code that I don't really know the details of, I did the straightforward resolve of it, but I'd like you to check it out. (I haven't pushed it out yet, I'm waiting for the allmodconfig to finish compiling, so if you see this email quickly, but don't see the powerpc merge yet, just wait a few minutes) Linus ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] powerpc: POWER7 optimised memcpy using VMX and enhanced prefetch
On Tue, 2012-12-18 at 07:28 -0600, Jimi Xenidis wrote:
> On Dec 17, 2012, at 6:26 PM, Peter Bergner wrote:
> > Jimi, are you using an "old" binutils from before my patch that
> > changed the operand order for these types of instructions?
> >
> >http://sourceware.org/ml/binutils/2009-02/msg00044.html
>
> Actually, this confused me as well, that embedded has the same instruction
> encoding but different mnemonic.
The mnemonic is the same (ie, dcbtst), and yes, the encoding is the same.
All that is different is the accepted operand ordering...and yes, it is
very unfortunate the operand ordering is different between embedded and
server. :(
> I was under the impression that the assembler made no instruction decisions
> based on CPU. So your only hint would be that '0b' prefix.
> Does AS even see that?
GAS definitely makes decisions based on CPU (ie, -m option). Below is
the GAS code used in recognizing the dcbtst instruction. This shows that
the "server" operand ordering is enabled for POWER4 and later cpus while
the "embedded" operand ordering is enabled for pre POWER4 cpus (yes, not
exactly a server versus embedded trigger, but that's we agreed on to
mitigate breaking any old asm code out there).
{"dcbtst", X(31,246), X_MASK, POWER4,PPCNONE,{RA0,
RB, CT}},
{"dcbtst", X(31,246), X_MASK, PPC|PPCVLE, POWER4,{CT,
RA0, RB}},
GAS doesn't look at how the operands are written to try and guess what
operand ordering you are attempting to use. Rather, it knows what ordering
it expects and the values had better match that ordering.
Peter
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RE: [PATCH] powerpc: POWER7 optimised memcpy using VMX and enhanced prefetch
> >>dcbtr0,r8,0b01010 /* GO */ > >> .machine pop > > > > Jimi, are you using an "old" binutils from before my patch that > > changed the operand order for these types of instructions? > > > >http://sourceware.org/ml/binutils/2009-02/msg00044.html > > Actually, this confused me as well, that embedded has the same > instruction encoding but different mnemonic. That it utterly horrid! > I was under the impression that the assembler made no instruction decisions > based on CPU. > So your only hint would be that '0b' prefix. > Does AS even see that? Or maybe see the 'r' prefix. I know they tend to be absent making ppc asm even more unreadable. It isn't as though the mnemonics were designed at a time when the source file size or difference in decode time (or code space) would be significant. Otherwise it is a complete recipe for disaster. David ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] powerpc: POWER7 optimised memcpy using VMX and enhanced prefetch
On Dec 17, 2012, at 6:26 PM, Peter Bergner wrote: > On Mon, 2012-12-17 at 22:33 +1100, Anton Blanchard wrote: >> Hi Jimi, >> >>> I know this is a little late, but shouldn't these power7 specific >>> thingies be in "obj-$(CONFIG_PPC_BOOK3S_64)". The reason I ask is >>> that my compiler pukes on "dcbtst" and as I deal with that I wanted >>> to point this out. >> >> I guess we could do that. It's a bit strange your assembler is >> complaining about the dcbtst instructions since we wrap them with >> power4: >> >> .machine push >> .machine "power4" >>dcbtr0,r4,0b01000 >>dcbtr0,r7,0b01010 >>dcbtst r0,r9,0b01000 >>dcbtst r0,r10,0b01010 >>eieio >>dcbtr0,r8,0b01010 /* GO */ >> .machine pop > > Jimi, are you using an "old" binutils from before my patch that > changed the operand order for these types of instructions? > >http://sourceware.org/ml/binutils/2009-02/msg00044.html Actually, this confused me as well, that embedded has the same instruction encoding but different mnemonic. I was under the impression that the assembler made no instruction decisions based on CPU. So your only hint would be that '0b' prefix. Does AS even see that? If not, then without a _normalizing_ macro, I think will need that obj-$(CONFIG_PPC_BOOK3S_64) and .S files with the two can never be shared. -jx > > Peter > > ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] powerpc: POWER7 optimised memcpy using VMX and enhanced prefetch
On Dec 17, 2012, at 5:33 AM, Anton Blanchard wrote: > > Hi Jimi, > >> I know this is a little late, but shouldn't these power7 specific >> thingies be in "obj-$(CONFIG_PPC_BOOK3S_64)". The reason I ask is >> that my compiler pukes on "dcbtst" and as I deal with that I wanted >> to point this out. > > I guess we could do that. I think it is the right idea since it is unclear that your optimizations would actually help an embedded system where most of these cache prefetches are NOPs and only wait decode/dispatch cycles. > It's a bit strange your assembler is > complaining about the dcbtst instructions since we wrap them with > power4: Not really, the binutils is a little old (RHEL 6.2), unfortunately it _is_ the toolchain most people are using at the moment. It will take me a while to get everyone using newer ones since most are scientists using the packages they get. My suggestion was really for correctness, My current patches for BG/Q introduce a macro replacement. -jx > > .machine push > .machine "power4" >dcbtr0,r4,0b01000 >dcbtr0,r7,0b01010 >dcbtst r0,r9,0b01000 >dcbtst r0,r10,0b01010 >eieio >dcbtr0,r8,0b01010 /* GO */ > .machine pop > > Anton ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH]powerpc: Corrected include header path in kvm_para.h
On 18.12.2012, at 12:21, Bharat Bhushan wrote:
> The include/uapi/asm/kvm_para.h includes
> but the correct reference
> should be as this is the place
> where make install_header installs the header files for
> userspace.
>
> Signed-off-by: Bharat Bhushan
Thanks, applied to kvm-ppc-next (with CC to stable@vger).
Alex
> ---
> arch/powerpc/include/uapi/asm/kvm_para.h |2 +-
> 1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/arch/powerpc/include/uapi/asm/kvm_para.h
> b/arch/powerpc/include/uapi/asm/kvm_para.h
> index ed0e025..e3af328 100644
> --- a/arch/powerpc/include/uapi/asm/kvm_para.h
> +++ b/arch/powerpc/include/uapi/asm/kvm_para.h
> @@ -78,7 +78,7 @@ struct kvm_vcpu_arch_shared {
>
> #define KVM_HCALL_TOKEN(num) _EV_HCALL_TOKEN(EV_KVM_VENDOR_ID, num)
>
> -#include
> +#include
>
> #define KVM_FEATURE_MAGIC_PAGE1
>
> --
> 1.7.0.4
>
>
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[PATCH]powerpc: Corrected include header path in kvm_para.h
The include/uapi/asm/kvm_para.h includes
but the correct reference
should be as this is the place
where make install_header installs the header files for
userspace.
Signed-off-by: Bharat Bhushan
---
arch/powerpc/include/uapi/asm/kvm_para.h |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/include/uapi/asm/kvm_para.h
b/arch/powerpc/include/uapi/asm/kvm_para.h
index ed0e025..e3af328 100644
--- a/arch/powerpc/include/uapi/asm/kvm_para.h
+++ b/arch/powerpc/include/uapi/asm/kvm_para.h
@@ -78,7 +78,7 @@ struct kvm_vcpu_arch_shared {
#define KVM_HCALL_TOKEN(num) _EV_HCALL_TOKEN(EV_KVM_VENDOR_ID, num)
-#include
+#include
#define KVM_FEATURE_MAGIC_PAGE 1
--
1.7.0.4
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Re: tqm5200s phy link toggles between up and down
>> This is not really a new kernel.
Yes this is right. But it is the first Kernel which supports our
wireless card without problems.
>> Is it a PHY or a switch? If is a switch you need to configure a fixed
>> link to the switch. This can be done via dts file.
According to the marvell website it is a switch with integrated phy.
> Here is an example:
> http://lxr.linux.no/#linux+v3.7.1/arch/powerpc/boot/dts/charon.dts#L129
I had a look at this example and compared it to my *.dtb file. The
difference was, the fixed-link tag in the section ethernet@3000 { ...
};.
I added "fixed-link = <1 1 100 0 0>;" to my tqm5200.dtb and now it works.
I am new to powerpc development and I hope it is ok to ask what this
fixed-link with the numbers "1 1 100 0 0" does? Is it the address to
the PHY?
2012/12/18 Wolfgang Grandegger :
> On 12/18/2012 10:57 AM, Wolfgang Grandegger wrote:
>> On 12/18/2012 10:44 AM, Johannes Braun wrote:
>>> Hello,
>>>
>>> I hope someone could help me with my problem. Currently I am porting
>>> a new kernel (3.3.8) for a tqm5200s based board.
>>
>> This is not really a new kernel.
>>
>>> The previous kernel was 2.6.23. The new kernel version is needed because
>>> of support for a wireless card.
>>>
>>> The new kernel has problems with my ethernet PHY. The problem occurs only
>>> with our hardware. Not with the TQ eval board.
>>> The eval board uses a Intel PHY. Our board uses a Marvel 88E6085 PHY.
>>
>> Is it a PHY or a switch? If is a switch you need to configure a fixed
>> link to the switch. This can be done via dts file.
>
> Here is an example:
>
> http://lxr.linux.no/#linux+v3.7.1/arch/powerpc/boot/dts/charon.dts#L129
>
>> Note the the DSA also supports this chip.
>
> See http://lwn.net/Articles/302333/. But I think it lacks device tree
> support.
>
> Wolfgang.
>
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Re: tqm5200s phy link toggles between up and down
On 12/18/2012 10:44 AM, Johannes Braun wrote: > Hello, > > I hope someone could help me with my problem. Currently I am porting > a new kernel (3.3.8) for a tqm5200s based board. This is not really a new kernel. > The previous kernel was 2.6.23. The new kernel version is needed because > of support for a wireless card. > > The new kernel has problems with my ethernet PHY. The problem occurs only > with our hardware. Not with the TQ eval board. > The eval board uses a Intel PHY. Our board uses a Marvel 88E6085 PHY. Is it a PHY or a switch? If is a switch you need to configure a fixed link to the switch. This can be done via dts file. Note the the DSA also supports this chip. Wolfgang. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: tqm5200s phy link toggles between up and down
On 12/18/2012 10:57 AM, Wolfgang Grandegger wrote: > On 12/18/2012 10:44 AM, Johannes Braun wrote: >> Hello, >> >> I hope someone could help me with my problem. Currently I am porting >> a new kernel (3.3.8) for a tqm5200s based board. > > This is not really a new kernel. > >> The previous kernel was 2.6.23. The new kernel version is needed because >> of support for a wireless card. >> >> The new kernel has problems with my ethernet PHY. The problem occurs only >> with our hardware. Not with the TQ eval board. >> The eval board uses a Intel PHY. Our board uses a Marvel 88E6085 PHY. > > Is it a PHY or a switch? If is a switch you need to configure a fixed > link to the switch. This can be done via dts file. Here is an example: http://lxr.linux.no/#linux+v3.7.1/arch/powerpc/boot/dts/charon.dts#L129 > Note the the DSA also supports this chip. See http://lwn.net/Articles/302333/. But I think it lacks device tree support. Wolfgang. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
tqm5200s phy link toggles between up and down
Hello,
I hope someone could help me with my problem. Currently I am porting
a new kernel (3.3.8) for a tqm5200s based board.
The previous kernel was 2.6.23. The new kernel version is needed because
of support for a wireless card.
The new kernel has problems with my ethernet PHY. The problem occurs only
with our hardware. Not with the TQ eval board.
The eval board uses a Intel PHY. Our board uses a Marvel 88E6085 PHY.
I have tested the new kernel on the eval board and everything runs fine.
But After booting the kernel on our hardware, the ethernet connection is
going up and down and loops between these two states.
This is the log output:
[ 38.608305] PHY: f0003000:00 - Link is Down
[ 41.708310] PHY: f0003000:00 - Link is Up - 10/Half
[ 43.744304] PHY: f0003000:00 - Link is Down
[ 46.844309] PHY: f0003000:00 - Link is Up - 10/Half
I also had a look inside the driver in
Drivers/net/ethernet/freescale/fec_mpc52xx.c
and made a printk output to the link adjust method,
which is called everytime before the link is going down.
/* based on generic_adjust_link from fs_enet-main.c */
static void
mpc52xx_fec_adjust_link(struct net_device *dev)
{
struct mpc52xx_fec_priv *priv = netdev_priv(dev);
struct phy_device *phydev = priv->phydev;
int new_state = 0;
printk( KERN_INFO "%s->%s: entering...",
__FILE__, __func__ );
if (phydev->link != PHY_DOWN) {
if (phydev->duplex != priv->duplex) {
struct mpc52xx_fec __iomem *fec = priv->fec;
u32 rcntrl;
u32 tcntrl;
...
...
This is the output with the above printk:
[ 35.589485] PHY: f0003000:00 - Link is Down
[ 40.752753] drivers/net/ethernet/freescale/fec_mpc52xx.c
->mpc52xx_fec_adjust_link: entering...
[ 40.761494] PHY: f0003000:00 - Link is Up - 10/Half
[ 42.796746] drivers/net/ethernet/freescale/fec_mpc52xx.c
->mpc52xx_fec_adjust_link: entering...
[ 42.805485] PHY: f0003000:00 - Link is Down
[ 49.000755] drivers/net/ethernet/freescale/fec_mpc52xx.c
->mpc52xx_fec_adjust_link: entering...
[ 49.009497] PHY: f0003000:00 - Link is Up - 10/Half
As I noticed the problem occurs also with a 2.6.24 kernel.
Seems that the driver was rewritten and moved from drivers/net/fec_mpc52xx/
to drivers/net/ethernet/freescale/fec_mpc52xx.c.
I am note shure where to search for the problem. The PHY link seems to be in
some kind of auto-negotiating loop of going up and down? Has anyone had this
problem before, or does someone has a tip to fix this problem?
Best regards
Johannes
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