Re: [PATCH 3/3] powerpc: Set default VGA device
On Mon, 2013-04-08 at 15:21 +1000, Michael Ellerman wrote: Looking at x86, ia64 and ours, there's a fair bit of difference. x86/ia64 both walk up the parents checking PCI_BRIDGE_CTL_VGA, which powerpc doesn't (though maybe it should?). Unclear for several reasons. That bit indicates that the bridge forwards the hard coded legacy VGA IO ports and memory aperture. These are not necessary to get modern video cards going. Only if legacy modes are used. On x86, that tends to be the case (is it always even with EFI nowadays ?). On other architectures that is not necessarily the case. The firmware can (and will) initialize the card using MMIO entirely and even if possible disabling the legacy stuff, which means that turning those bits on in the bridge is also unnecessary. In fact, on such setups, the isn't really a concept of a primary video card to begin with. On the other hand, that also means that a video card initialized like that is pretty much out of the grasp of the vga arbiter which has no effect on it either. Also be careful that while it may be relevant on x86, the VGA fwd bit is not on the PCIe root complex on IBM machines. Finally, P8 has no IO space at all... x86/ia64 set IORESOURCE_ROM_SHADOW, which powerpc doesn't. ia64 doesn't call vga_set_default_device(), x86 and powerpc do. So we'll merge this and maybe someone can tease out the common bits, but personally I don't see that there's an obvious chunk of generic logic. Cheers, Ben. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[git pull] Please pull another powerpc fix
The following changes since commit 875b7679abbb232b584f2eec59fa6e45690dd6c4: Merge git://git.kernel.org/pub/scm/virt/kvm/kvm (2013-04-07 13:01:25 -0700) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/sfr/next-fixes.git tags/for-linus for you to fetch changes up to 9fb2640159f9d4f5a2a9d60e490482d4cbecafdb: powerpc: pSeries_lpar_hpte_remove fails from Adjunct partition being performed before the ANDCOND test (2013-04-08 15:19:09 +1000) A single BUG_ON fix for a condition that could happen for machines with certain hardware installed. Michael Wolf (1): powerpc: pSeries_lpar_hpte_remove fails from Adjunct partition being performed before the ANDCOND test arch/powerpc/platforms/pseries/lpar.c | 8 +++- 1 file changed, 7 insertions(+), 1 deletion(-) -- Cheers, Stephen Rothwells...@canb.auug.org.au pgpV_wtUOmkJX.pgp Description: PGP signature ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [RFC][PATCH 2/2] powerpc/fsl-pci Make PCIe hotplug work with Freescale
Up to now the PCIe link status on Freescale PCIe controllers was only
checked once at boot time. So hotplug did not work. With this patch the
link status is checked on every config read. PCIe devices not present at
boot time are found after doing 'echo 1 /sys/bus/pci/rescan'.
Signed-off-by: Rojhalat Ibrahim i...@rtschenk.de
---
arch/powerpc/include/asm/pci-bridge.h |6
arch/powerpc/sysdev/fsl_pci.c | 51 +-
arch/powerpc/sysdev/indirect_pci.c| 10 ++
3 files changed, 54 insertions(+), 13 deletions(-)
diff --git a/arch/powerpc/include/asm/pci-bridge.h
b/arch/powerpc/include/asm/pci-bridge.h
index c0278f0..ffbc5fd 100644
--- a/arch/powerpc/include/asm/pci-bridge.h
+++ b/arch/powerpc/include/asm/pci-bridge.h
@@ -120,6 +120,12 @@ extern void setup_indirect_pci(struct pci_controller* hose,
resource_size_t cfg_addr,
resource_size_t cfg_data, u32 flags);
+extern int indirect_read_config(struct pci_bus *bus, unsigned int devfn,
+ int offset, int len, u32 *val);
+
+extern int indirect_write_config(struct pci_bus *bus, unsigned int devfn,
+int offset, int len, u32 val);
+
static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus)
{
return bus-sysdata;
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 83918c3..82e3317 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -54,12 +54,22 @@ static void quirk_fsl_pcie_header(struct pci_dev *dev)
return;
}
-static int __init fsl_pcie_check_link(struct pci_controller *hose)
+static int fsl_indirect_read_config(struct pci_bus *, unsigned int,
+ int, int, u32 *);
+
+static int fsl_pcie_check_link(struct pci_controller *hose)
{
- u32 val;
+ u32 val = 0;
if (hose-indirect_type PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK) {
- early_read_config_dword(hose, 0, 0, PCIE_LTSSM, val);
+ if (hose-ops-read == fsl_indirect_read_config) {
+ struct pci_bus bus;
+ bus.number = 0;
+ bus.sysdata = hose;
+ bus.ops = hose-ops;
+ indirect_read_config(bus, 0, PCIE_LTSSM, 4, val);
+ } else
+ early_read_config_dword(hose, 0, 0, PCIE_LTSSM, val);
if (val PCIE_LTSSM_L0)
return 1;
} else {
@@ -74,6 +84,33 @@ static int __init fsl_pcie_check_link(struct pci_controller
*hose)
return 0;
}
+static int fsl_indirect_read_config(struct pci_bus *bus, unsigned int devfn,
+ int offset, int len, u32 *val)
+{
+ struct pci_controller *hose = pci_bus_to_host(bus);
+
+ if (fsl_pcie_check_link(hose))
+ hose-indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
+ else
+ hose-indirect_type = ~PPC_INDIRECT_TYPE_NO_PCIE_LINK;
+
+ return indirect_read_config(bus, devfn, offset, len, val);
+}
+
+static struct pci_ops fsl_indirect_pci_ops =
+{
+ .read = fsl_indirect_read_config,
+ .write = indirect_write_config,
+};
+
+static void __init fsl_setup_indirect_pci(struct pci_controller* hose,
+ resource_size_t cfg_addr,
+ resource_size_t cfg_data, u32 flags)
+{
+ setup_indirect_pci(hose, cfg_addr, cfg_data, flags);
+ hose-ops = fsl_indirect_pci_ops;
+}
+
#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
#define MAX_PHYS_ADDR_BITS 40
@@ -469,8 +506,8 @@ int __init fsl_add_bridge(struct platform_device *pdev, int
is_primary)
if (!hose-private_data)
goto no_bridge;
- setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
- PPC_INDIRECT_TYPE_BIG_ENDIAN);
+ fsl_setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
+ PPC_INDIRECT_TYPE_BIG_ENDIAN);
if (in_be32(pci-block_rev1) PCIE_IP_REV_3_0)
hose-indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK;
@@ -779,8 +816,8 @@ int __init mpc83xx_add_bridge(struct device_node *dev)
if (ret)
goto err0;
} else {
- setup_indirect_pci(hose, rsrc_cfg.start,
- rsrc_cfg.start + 4, 0);
+ fsl_setup_indirect_pci(hose, rsrc_cfg.start,
+ rsrc_cfg.start + 4, 0);
}
printk(KERN_INFO Found FSL PCI host bridge at 0x%016llx.
diff --git a/arch/powerpc/sysdev/indirect_pci.c
b/arch/powerpc/sysdev/indirect_pci.c
index 82fdad8..c6c8b52 100644
--- a/arch/powerpc/sysdev/indirect_pci.c
+++ b/arch/powerpc/sysdev/indirect_pci.c
@@ -20,9 +20,8 @@
#include
Re: [RFC][PATCH 1/2] powerpc/fsl-pci: Keep PCI SoC controller registers in
On Wednesday 13 March 2013 14:07:15 Kumar Gala wrote:
Move to keeping the SoC registers that control and config the PCI
controllers on FSL SoCs in the pci_controller struct. This allows us to
not need to ioremap() the registers in multiple different places that
use them.
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
Acked-by: Rojhalat Ibrahim i...@rtschenk.de
---
arch/powerpc/include/asm/pci-bridge.h |5 ++-
arch/powerpc/sysdev/fsl_pci.c | 69
++--- 2 files changed, 34 insertions(+), 40
deletions(-)
diff --git a/arch/powerpc/include/asm/pci-bridge.h
b/arch/powerpc/include/asm/pci-bridge.h index 025a130..c0278f0 100644
--- a/arch/powerpc/include/asm/pci-bridge.h
+++ b/arch/powerpc/include/asm/pci-bridge.h
@@ -70,6 +70,8 @@ struct pci_controller {
* BIG_ENDIAN - cfg_addr is a big endian register
* BROKEN_MRM - the 440EPx/GRx chips have an errata that causes hangs
on
* the PLB4. Effectively disable MRM commands by setting this.
+ * FSL_CFG_REG_LINK - Freescale controller version in which the PCIe
+ * link status is in a RC PCIe cfg register (vs being a SoC register)
*/
#define PPC_INDIRECT_TYPE_SET_CFG_TYPE 0x0001
#define PPC_INDIRECT_TYPE_EXT_REG0x0002
@@ -77,6 +79,7 @@ struct pci_controller {
#define PPC_INDIRECT_TYPE_NO_PCIE_LINK 0x0008
#define PPC_INDIRECT_TYPE_BIG_ENDIAN 0x0010
#define PPC_INDIRECT_TYPE_BROKEN_MRM 0x0020
+#define PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK 0x0040
u32 indirect_type;
/* Currently, we limit ourselves to 1 IO range and 3 mem
* ranges since the common pci_bus structure can't handle more
@@ -90,9 +93,9 @@ struct pci_controller {
#ifdef CONFIG_PPC64
unsigned long buid;
+#endif /* CONFIG_PPC64 */
void *private_data;
-#endif /* CONFIG_PPC64 */
};
/* These are used for config access before all the PCI probing
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 3271177..41bbcc4 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -54,34 +54,22 @@ static void quirk_fsl_pcie_header(struct pci_dev *dev)
return;
}
-static int __init fsl_pcie_check_link(struct pci_controller *hose,
- struct resource *rsrc)
+static int __init fsl_pcie_check_link(struct pci_controller *hose)
{
- struct ccsr_pci __iomem *pci = NULL;
u32 val;
- /* for PCIe IP rev 3.0 or greater use CSR0 for link state */
- if (rsrc) {
- pr_debug(PCI memory map start 0x%016llx, size 0x%016llx\n,
- (u64)rsrc-start, (u64)rsrc-end - (u64)rsrc-start + 1);
- pci = ioremap(rsrc-start, rsrc-end - rsrc-start + 1);
- if (!pci) {
- dev_err(hose-parent, Unable to map PCIe registers\n);
- return -ENOMEM;
- }
- if (in_be32(pci-block_rev1) = PCIE_IP_REV_3_0) {
- val = (in_be32(pci-pex_csr0) PEX_CSR0_LTSSM_MASK)
- PEX_CSR0_LTSSM_SHIFT;
- if (val != PEX_CSR0_LTSSM_L0)
- return 1;
- iounmap(pci);
- return 0;
- }
- iounmap(pci);
+ if (hose-indirect_type PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK) {
+ early_read_config_dword(hose, 0, 0, PCIE_LTSSM, val);
+ if (val PCIE_LTSSM_L0)
+ return 1;
+ } else {
+ struct ccsr_pci __iomem *pci = hose-private_data;
+ /* for PCIe IP rev 3.0 or greater use CSR0 for link state */
+ val = (in_be32(pci-pex_csr0) PEX_CSR0_LTSSM_MASK)
+ PEX_CSR0_LTSSM_SHIFT;
+ if (val != PEX_CSR0_LTSSM_L0)
+ return 1;
}
- early_read_config_dword(hose, 0, 0, PCIE_LTSSM, val);
- if (val PCIE_LTSSM_L0)
- return 1;
return 0;
}
@@ -148,10 +136,9 @@ static int setup_one_atmu(struct ccsr_pci __iomem *pci,
}
/* atmu setup for fsl pci/pcie controller */
-static void setup_pci_atmu(struct pci_controller *hose,
- struct resource *rsrc)
+static void setup_pci_atmu(struct pci_controller *hose)
{
- struct ccsr_pci __iomem *pci;
+ struct ccsr_pci __iomem *pci = hose-private_data;
int i, j, n, mem_log, win_idx = 3, start_idx = 1, end_idx = 4;
u64 mem, sz, paddr_hi = 0;
u64 paddr_lo = ULLONG_MAX;
@@ -162,15 +149,6 @@ static void setup_pci_atmu(struct pci_controller *hose,
const u64 *reg;
int len;
- pr_debug(PCI memory map start 0x%016llx, size 0x%016llx\n,
- (u64)rsrc-start, (u64)resource_size(rsrc));
-
- pci = ioremap(rsrc-start, resource_size(rsrc));
Re: [RFC PATCH v2 2/6] powerpc: Exception hooks for context tracking subsystem
On Fri, 2013-04-05 at 13:50 +1100, Paul Mackerras wrote: On Fri, Mar 29, 2013 at 06:00:17PM +0800, Li Zhong wrote: This is the exception hooks for context tracking subsystem, including data access, program check, single step, instruction breakpoint, machine check, alignment, fp unavailable, altivec assist, unknown exception, whose handlers might use RCU. This patch corresponds to [PATCH] x86: Exception hooks for userspace RCU extended QS commit 6ba3c97a38803883c2eee489505796cb0a727122 Signed-off-by: Li Zhong zh...@linux.vnet.ibm.com Hi Paul, Thanks for your review! Please check my answers below, and correct me if any errors. Is there a reason why you didn't put the exception_exit() call in ret_from_except_lite in entry_64.S, and the exception_entry() call in EXCEPTION_PROLOG_COMMON? That would seem to catch all these cases in a more centralized place. It seems to me that ret_from_except_lite and EXCEPTION_PROLOG_COMMON are also used by interrupts, where I think we don't need the hooks. So using this way could help to avoid adding overhead to these code path (interrupts, and some exit path of syscall). And I think adding the hook on higher level code seems a little easier for reading and checking. It seems that some exceptions don't use EXCEPTION_PROLOG_COMMON, and some don't go ret_from_except_lite exit path (like fp unavailable might go directly to fast_exception_return ). Maybe fast_exception_return is a centralized place for us to return to user space? But it still adds some overheads which is not necessarily needed. And I think it also makes the implementation here consistent with the style that x86 uses. Also, I notice that with the exception_exit calls where they are, we can still deliver signals (thus possibly taking a page fault) or call schedule() for preemption after the exception_exit() call. Is that OK, or is it a potential problem? If I understand correctly, I guess you are talking about the cases where we might return to user space without context state correctly being set as in user? There is user_enter() called in do_notify_resume() in patch #3, so after handling the signals we always call user_enter(). There are also some changes of the context_tracking code from Frederic, which might be related: ( they are now in tip tree, and url of the patches for your convenience https://lkml.org/lkml/2013/3/1/266 ) 6c1e0256fad84a843d915414e4b5973b7443d48d context_tracking: Restore correct previous context state on exception exit. With this patch, if a later exception happened after user_enter(), before the CPU actually returns to user space, the correct context state(in user) is saved and restored when handling the later exception. Patch #6 converts the code to use these new APIs, which is currently not available in powerpc tree. b22366cd54c6fe05db426f20adb10f461c19ec06 context_tracking: Restore preempted context state after preempt_schedule_irq With this patch, the user context state could be correctly restored after schedule returns. Thanks, Zhong Paul. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH V5] powerpc/85xx: Add machine check handler to fix PCIe erratum on mpc85xx
A PCIe erratum of mpc85xx may causes a core hang when a link of PCIe
goes down. when the link goes down, Non-posted transactions issued
via the ATMU requiring completion result in an instruction stall.
At the same time a machine-check exception is generated to the core
to allow further processing by the handler. We implements the handler
which skips the instruction caused the stall.
This patch depends on patch:
powerpc/85xx: Add platform_device declaration to fsl_pci.h
Signed-off-by: Zhao Chenhui b35...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Liu Shuo soniccat@gmail.com
Signed-off-by: Jia Hongtao hongtao@freescale.com
---
Changes for V4:
* Fill rd with all-Fs if the skipped instruction is load and emulate the
instruction.
* Let KVM/QEMU deal with the exception if the machine check comes from KVM.
arch/powerpc/kernel/cpu_setup_fsl_booke.S | 2 +-
arch/powerpc/kernel/traps.c | 3 +
arch/powerpc/sysdev/fsl_pci.c | 121 ++
arch/powerpc/sysdev/fsl_pci.h | 6 ++
4 files changed, 131 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/kernel/cpu_setup_fsl_booke.S
b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
index dcd8819..f1bde90 100644
--- a/arch/powerpc/kernel/cpu_setup_fsl_booke.S
+++ b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
@@ -66,7 +66,7 @@ _GLOBAL(__setup_cpu_e500v2)
bl __e500_icache_setup
bl __e500_dcache_setup
bl __setup_e500_ivors
-#ifdef CONFIG_FSL_RIO
+#if defined(CONFIG_FSL_RIO) || defined(CONFIG_FSL_PCI)
/* Ensure that RFXE is set */
mfspr r3,SPRN_HID1
orisr3,r3,HID1_RFXE@h
diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
index a008cf5..dd275a4 100644
--- a/arch/powerpc/kernel/traps.c
+++ b/arch/powerpc/kernel/traps.c
@@ -59,6 +59,7 @@
#include asm/fadump.h
#include asm/switch_to.h
#include asm/debug.h
+#include sysdev/fsl_pci.h
#if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC)
int (*__debugger)(struct pt_regs *regs) __read_mostly;
@@ -556,6 +557,8 @@ int machine_check_e500(struct pt_regs *regs)
if (reason MCSR_BUS_RBERR) {
if (fsl_rio_mcheck_exception(regs))
return 1;
+ if (fsl_pci_mcheck_exception(regs))
+ return 1;
}
printk(Machine check in kernel mode.\n);
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 682084d..48326cd 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -26,11 +26,14 @@
#include linux/memblock.h
#include linux/log2.h
#include linux/slab.h
+#include linux/uaccess.h
#include asm/io.h
#include asm/prom.h
#include asm/pci-bridge.h
+#include asm/ppc-pci.h
#include asm/machdep.h
+#include asm/disassemble.h
#include sysdev/fsl_soc.h
#include sysdev/fsl_pci.h
@@ -826,6 +829,124 @@ u64 fsl_pci_immrbar_base(struct pci_controller *hose)
return 0;
}
+#ifdef CONFIG_E500
+
+#define OP_LWZ 32
+#define OP_LWZU 33
+#define OP_LBZ 34
+#define OP_LBZU 35
+#define OP_LHZ 40
+#define OP_LHZU 41
+#define OP_LHA 42
+#define OP_LHAU 43
+
+static int mcheck_handle_load(struct pt_regs *regs, u32 inst)
+{
+ unsigned int rd, ra, d;
+
+ rd = get_rt(inst);
+ ra = get_ra(inst);
+ d = get_d(inst);
+
+ switch (get_op(inst)) {
+ case OP_LWZ:
+ regs-gpr[rd] = 0x;
+ break;
+
+ case OP_LWZU:
+ regs-gpr[rd] = 0x;
+ regs-gpr[ra] += (s16)d;
+ break;
+
+ case OP_LBZ:
+ regs-gpr[rd] = 0xff;
+ break;
+
+ case OP_LBZU:
+ regs-gpr[rd] = 0xff;
+ regs-gpr[ra] += (s16)d;
+ break;
+
+ case OP_LHZ:
+ regs-gpr[rd] = 0x;
+ break;
+
+ case OP_LHZU:
+ regs-gpr[rd] = 0x;
+ regs-gpr[ra] += (s16)d;
+ break;
+
+ case OP_LHA:
+ regs-gpr[rd] = 0x;
+ break;
+
+ case OP_LHAU:
+ regs-gpr[rd] = 0x;
+ regs-gpr[ra] += (s16)d;
+ break;
+
+ default:
+ return 0;
+ }
+
+ return 1;
+}
+
+static int is_in_pci_mem_space(phys_addr_t addr)
+{
+ struct pci_controller *hose;
+ struct resource *res;
+ int i;
+
+ list_for_each_entry(hose, hose_list, list_node) {
+ if (!early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP))
+ continue;
+
+ for (i = 0; i 3; i++) {
+ res = hose-mem_resources[i];
+ if ((res-flags IORESOURCE_MEM)
+ addr = res-start addr = res-end)
+ return 1;
+ }
+ }
+ return 0;
+}
+
+int
Re: [PATCH] powerpc: remove unused config 405EP
On Mon, Apr 8, 2013 at 7:27 AM, Paul Bolle pebo...@tiscali.nl wrote: All users of Kconfig symbol 405EP were removed in release v2.6.27. Remove this symbol (and a useless select of it) too. Signed-off-by: Paul Bolle pebo...@tiscali.nl Acked-by: Josh Boyer jwbo...@gmail.com --- 0) Tested by grepping the tree only. 1) There's also a Kconfig symbol EP405. Let's hope no one ever made a typo with either of these two symbols! arch/powerpc/platforms/40x/Kconfig | 4 1 file changed, 4 deletions(-) diff --git a/arch/powerpc/platforms/40x/Kconfig b/arch/powerpc/platforms/40x/Kconfig index 7b7a77c..bd40bbb 100644 --- a/arch/powerpc/platforms/40x/Kconfig +++ b/arch/powerpc/platforms/40x/Kconfig @@ -20,7 +20,6 @@ config HOTFOOT bool Hotfoot depends on 40x default n - select 405EP select PPC40x_SIMPLE select PCI help @@ -105,9 +104,6 @@ config 405GP select IBM405_ERR51 select IBM_EMAC_ZMII -config 405EP - bool - config 405EX bool select IBM_EMAC_EMAC4 -- 1.7.11.7 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 2/2] powerpc: Set default VGA device
Add a PCI quirk for VGA devices on Power to set the default VGA device.
Ensures a default VGA is always set if a graphics adapter is present,
even if firmware did not initialize it. If more than one graphics
adapter is present, ensure the one initialized by firmware is set
as the default VGA device. This ensures that X autoconfiguration
will work.
Signed-off-by: Brian King brk...@linux.vnet.ibm.com
---
arch/powerpc/kernel/pci-common.c | 13 +
1 file changed, 13 insertions(+)
diff -puN arch/powerpc/kernel/pci-common.c~powerpc_vga_default_device
arch/powerpc/kernel/pci-common.c
--- linux/arch/powerpc/kernel/pci-common.c~powerpc_vga_default_device
2013-04-08 06:16:37.0 -0500
+++ linux-bjking1/arch/powerpc/kernel/pci-common.c 2013-04-08
06:16:37.0 -0500
@@ -30,6 +30,7 @@
#include linux/irq.h
#include linux/vmalloc.h
#include linux/slab.h
+#include linux/vgaarb.h
#include asm/processor.h
#include asm/io.h
@@ -1725,3 +1726,15 @@ static void fixup_hide_host_resource_fsl
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA, PCI_ANY_ID,
fixup_hide_host_resource_fsl);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID,
fixup_hide_host_resource_fsl);
+
+static void fixup_vga(struct pci_dev *pdev)
+{
+ u16 cmd;
+
+ pci_read_config_word(pdev, PCI_COMMAND, cmd);
+ if ((cmd (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) ||
!vga_default_device())
+ vga_set_default_device(pdev);
+
+}
+DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
+ PCI_CLASS_DISPLAY_VGA, 8, fixup_vga);
_
___
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[PATCH 1/2] pci: Set dev-dev.type in alloc_pci_dev
Set dev-dev.type in alloc_pci_dev so that archs that have their own versions of pci_setup_device get this set properly in order to ensure things like the boot_vga sysfs parameter get created as expected. Signed-off-by: Brian King brk...@linux.vnet.ibm.com --- drivers/pci/probe.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff -puN drivers/pci/probe.c~pci_set_dev_type_early drivers/pci/probe.c --- linux/drivers/pci/probe.c~pci_set_dev_type_early2013-04-08 06:12:51.0 -0500 +++ linux-bjking1/drivers/pci/probe.c 2013-04-08 06:14:33.0 -0500 @@ -988,7 +988,6 @@ int pci_setup_device(struct pci_dev *dev dev-sysdata = dev-bus-sysdata; dev-dev.parent = dev-bus-bridge; dev-dev.bus = pci_bus_type; - dev-dev.type = pci_dev_type; dev-hdr_type = hdr_type 0x7f; dev-multifunction = !!(hdr_type 0x80); dev-error_state = pci_channel_io_normal; @@ -1208,6 +1207,7 @@ struct pci_dev *alloc_pci_dev(void) return NULL; INIT_LIST_HEAD(dev-bus_list); + dev-dev.type = pci_dev_type; return dev; } _ ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 1/2] pci: Set dev-dev.type in alloc_pci_dev
On Mon, Apr 8, 2013 at 7:05 AM, Brian King brk...@linux.vnet.ibm.com wrote: Set dev-dev.type in alloc_pci_dev so that archs that have their own versions of pci_setup_device get this set properly in order to ensure things like the boot_vga sysfs parameter get created as expected. Signed-off-by: Brian King brk...@linux.vnet.ibm.com Acked-by: Bjorn Helgaas bhelg...@google.com Feel free to put this in the powerpc tree along with the set default VGA device patch. --- drivers/pci/probe.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff -puN drivers/pci/probe.c~pci_set_dev_type_early drivers/pci/probe.c --- linux/drivers/pci/probe.c~pci_set_dev_type_early2013-04-08 06:12:51.0 -0500 +++ linux-bjking1/drivers/pci/probe.c 2013-04-08 06:14:33.0 -0500 @@ -988,7 +988,6 @@ int pci_setup_device(struct pci_dev *dev dev-sysdata = dev-bus-sysdata; dev-dev.parent = dev-bus-bridge; dev-dev.bus = pci_bus_type; - dev-dev.type = pci_dev_type; dev-hdr_type = hdr_type 0x7f; dev-multifunction = !!(hdr_type 0x80); dev-error_state = pci_channel_io_normal; @@ -1208,6 +1207,7 @@ struct pci_dev *alloc_pci_dev(void) return NULL; INIT_LIST_HEAD(dev-bus_list); + dev-dev.type = pci_dev_type; return dev; } _ ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] powerpc: add Book E support to 64-bit hibernation
On 04/06/2013 10:01:45 PM, Wang Dongsheng-B40534 wrote: -Original Message- From: Wood Scott-B07421 Sent: Thursday, April 04, 2013 4:16 AM To: Wang Dongsheng-B40534 Cc: Wood Scott-B07421; Johannes Berg; linuxppc-dev@lists.ozlabs.org Subject: Re: [PATCH] powerpc: add Book E support to 64-bit hibernation On 04/03/2013 12:36:41 AM, Wang Dongsheng-B40534 wrote: -Original Message- From: Wood Scott-B07421 Sent: Wednesday, April 03, 2013 8:35 AM To: Wang Dongsheng-B40534 Cc: Wood Scott-B07421; Johannes Berg; linuxppc-dev@lists.ozlabs.org Subject: Re: [PATCH] powerpc: add Book E support to 64-bit hibernation On 04/02/2013 12:28:40 AM, Wang Dongsheng-B40534 wrote: Hi scott Johannes, Thanks for reviewing. @scott, About this patch, could you please help ack this patch? Please investigate the issue of whether we are loading kernel module code in this step, and whether cache flushing is needed as a result. Sorry, I am not very clear what you mean. When the kernel boot end, modprobe some xx.ko? Suppose, before the kernel was suspended, modules had been loaded. At what point do those modules get restored, and when does the cache get flushed? Before the kernel was suspended, modules had been loaded, the modules is already in memory. They *were* in memory, until the hardware was powered down. And /lib/modules/* is belong to vfs. Huh? I'm talking about modules that have been loaded, not where in the filesystem they were loaded from. Loading a module is not like mmap()ing a file. When suspend to disk, all used pages will be saved.(Include VFS, Loaded modules) When restore, the kernel will not modprobe again. Of course it won't modprobe again. Still, at some point during the resume process, the code has to be loaded from disk into RAM. What I don't know is if this is where that happens. The non-bootcpu will restore all pages.(Include VFS, Loaded modules) I don't know what non-bootcpu has to do with anything. What matters is what piece of code does the restoring, and if the cache flush properly happens then. -Scott ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v3 1/4] powerpc/mpic: add irq_set_wake support
Add irq_set_wake support. Just add IRQF_NO_SUSPEND to desc-action-flag.
So the wake up interrupt will not be disable in suspend_device_irqs.
Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com
---
v3:
* Modify: Change EINVAL to ENXIO in mpic_irq_set_wake()
v2:
* Add: Check freescale chip in mpic_irq_set_wake().
* Remove: Support mpic_irq_set_wake() in ht_chip.
arch/powerpc/sysdev/mpic.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index 3b2efd4..ae709d2 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -920,6 +920,22 @@ int mpic_set_irq_type(struct irq_data *d, unsigned int
flow_type)
return IRQ_SET_MASK_OK_NOCOPY;
}
+static int mpic_irq_set_wake(struct irq_data *d, unsigned int on)
+{
+ struct irq_desc *desc = container_of(d, struct irq_desc, irq_data);
+ struct mpic *mpic = mpic_from_irq_data(d);
+
+ if (!(mpic-flags MPIC_FSL))
+ return -ENXIO;
+
+ if (on)
+ desc-action-flags |= IRQF_NO_SUSPEND;
+ else
+ desc-action-flags = ~IRQF_NO_SUSPEND;
+
+ return 0;
+}
+
void mpic_set_vector(unsigned int virq, unsigned int vector)
{
struct mpic *mpic = mpic_from_irq(virq);
@@ -957,6 +973,7 @@ static struct irq_chip mpic_irq_chip = {
.irq_unmask = mpic_unmask_irq,
.irq_eoi= mpic_end_irq,
.irq_set_type = mpic_set_irq_type,
+ .irq_set_wake = mpic_irq_set_wake,
};
#ifdef CONFIG_SMP
@@ -971,6 +988,7 @@ static struct irq_chip mpic_tm_chip = {
.irq_mask = mpic_mask_tm,
.irq_unmask = mpic_unmask_tm,
.irq_eoi= mpic_end_irq,
+ .irq_set_wake = mpic_irq_set_wake,
};
#ifdef CONFIG_MPIC_U3_HT_IRQS
--
1.8.0
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[PATCH v3 2/4] powerpc/mpic: add global timer support
The MPIC global timer is a hardware timer inside the Freescale PIC complying
with OpenPIC standard. When the specified interval times out, the hardware
timer generates an interrupt. The driver currently is only tested on fsl chip,
but it can potentially support other global timers complying to OpenPIC
standard.
The two independent groups of global timer on fsl chip, group A and group B,
are identical in their functionality, except that they appear at different
locations within the PIC register map. The hardware timer can be cascaded to
create timers larger than the default 31-bit global timers. Timer cascade
fields allow configuration of up to two 63-bit timers. But These two groups
of timers cannot be cascaded together.
It can be used as a wakeup source for low power modes. It also could be used
as periodical timer for protocols, drivers and etc.
Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
---
v2:
* Modify: Set timer clock frequency in timer_group_get_freq().
* Modify: Change some of the comments.
arch/powerpc/include/asm/mpic_timer.h | 46 +++
arch/powerpc/platforms/Kconfig| 12 +
arch/powerpc/sysdev/Makefile | 1 +
arch/powerpc/sysdev/mpic_timer.c | 593 ++
4 files changed, 652 insertions(+)
create mode 100644 arch/powerpc/include/asm/mpic_timer.h
create mode 100644 arch/powerpc/sysdev/mpic_timer.c
diff --git a/arch/powerpc/include/asm/mpic_timer.h
b/arch/powerpc/include/asm/mpic_timer.h
new file mode 100644
index 000..0e23cd4
--- /dev/null
+++ b/arch/powerpc/include/asm/mpic_timer.h
@@ -0,0 +1,46 @@
+/*
+ * arch/powerpc/include/asm/mpic_timer.h
+ *
+ * Header file for Mpic Global Timer
+ *
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * Author: Wang Dongsheng dongsheng.w...@freescale.com
+ *Li Yang le...@freescale.com
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __MPIC_TIMER__
+#define __MPIC_TIMER__
+
+#include linux/interrupt.h
+#include linux/time.h
+
+struct mpic_timer {
+ void*dev;
+ struct cascade_priv *cascade_handle;
+ unsigned intnum;
+ unsigned intirq;
+};
+
+#ifdef CONFIG_MPIC_TIMER
+struct mpic_timer *mpic_request_timer(irq_handler_t fn, void *dev,
+ const struct timeval *time);
+void mpic_start_timer(struct mpic_timer *handle);
+void mpic_stop_timer(struct mpic_timer *handle);
+void mpic_get_remain_time(struct mpic_timer *handle, struct timeval *time);
+void mpic_free_timer(struct mpic_timer *handle);
+#else
+struct mpic_timer *mpic_request_timer(irq_handler_t fn, void *dev,
+ const struct timeval *time) { return NULL; }
+void mpic_start_timer(struct mpic_timer *handle) { }
+void mpic_stop_timer(struct mpic_timer *handle) { }
+void mpic_get_remain_time(struct mpic_timer *handle, struct timeval *time) { }
+void mpic_free_timer(struct mpic_timer *handle) { }
+#endif
+
+#endif
diff --git a/arch/powerpc/platforms/Kconfig b/arch/powerpc/platforms/Kconfig
index 48a920d..c447b3c 100644
--- a/arch/powerpc/platforms/Kconfig
+++ b/arch/powerpc/platforms/Kconfig
@@ -87,6 +87,18 @@ config MPIC
bool
default n
+config MPIC_TIMER
+ bool MPIC Global Timer
+ depends on MPIC FSL_SOC
+ default n
+ help
+ The MPIC global timer is a hardware timer inside the
+ Freescale PIC complying with OpenPIC standard. When the
+ specified interval times out, the hardware timer generates
+ an interrupt. The driver currently is only tested on fsl
+ chip, but it can potentially support other global timers
+ complying with the OpenPIC standard.
+
config PPC_EPAPR_HV_PIC
bool
default n
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index a57600b..ff6184a 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -4,6 +4,7 @@ ccflags-$(CONFIG_PPC64) := -mno-minimal-toc
mpic-msi-obj-$(CONFIG_PCI_MSI) += mpic_msi.o mpic_u3msi.o mpic_pasemi_msi.o
obj-$(CONFIG_MPIC) += mpic.o $(mpic-msi-obj-y)
+obj-$(CONFIG_MPIC_TIMER)+= mpic_timer.o
mpic-msgr-obj-$(CONFIG_MPIC_MSGR) += mpic_msgr.o
obj-$(CONFIG_MPIC) += mpic.o $(mpic-msi-obj-y) $(mpic-msgr-obj-y)
obj-$(CONFIG_PPC_EPAPR_HV_PIC) += ehv_pic.o
diff --git a/arch/powerpc/sysdev/mpic_timer.c b/arch/powerpc/sysdev/mpic_timer.c
new file mode 100644
index 000..c06db92
--- /dev/null
+++ b/arch/powerpc/sysdev/mpic_timer.c
@@ -0,0 +1,593 @@
+/*
+ * MPIC timer driver
+ *
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ * Author: Dongsheng Wang dongsheng.w...@freescale.com
+ *Li Yang le...@freescale.com
+ *
RE: [PATCH 1/4][v2] powerpc/fsl-booke: Add initial silicon device tree files for B4860 and B4420
-Original Message- From: Linuxppc-dev [mailto:linuxppc-dev- bounces+poonam.aggrwal=freescale@lists.ozlabs.org] On Behalf Of Leekha Shaveta-B20052 Sent: Monday, April 08, 2013 10:18 AM To: Kumar Gala Cc: linuxppc-dev@lists.ozlabs.org list Subject: RE: [PATCH 1/4][v2] powerpc/fsl-booke: Add initial silicon device tree files for B4860 and B4420 -Original Message- From: Leekha Shaveta-B20052 Sent: Friday, April 05, 2013 9:13 PM To: 'Kumar Gala' Cc: linuxppc-dev@lists.ozlabs.org list Subject: RE: [PATCH 1/4][v2] powerpc/fsl-booke: Add initial silicon device tree files for B4860 and B4420 -Original Message- From: Kumar Gala [mailto:ga...@kernel.crashing.org] Sent: Friday, April 05, 2013 7:53 PM To: Leekha Shaveta-B20052 Cc: linuxppc-dev@lists.ozlabs.org list Subject: Re: [PATCH 1/4][v2] powerpc/fsl-booke: Add initial silicon device tree files for B4860 and B4420 On Apr 5, 2013, at 1:33 AM, Shaveta Leekha wrote: B4860 and B4420 are similar that share some commonalities * common features have been added in b4si-pre.dtsi and b4si-post.dtsi * differences are added in respective silicon files of B4860 and B4420 There are several things missing from the device trees of B4860 and B4420: * DPAA related nodes (Qman, Bman, Fman, Rman) * DSP related nodes/information * serdes, sfp(security fuse processor), thermal, gpio, maple, cpri, quad timers nodes Signed-off-by: Shaveta Leekha shav...@freescale.com Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com Signed-off-by: Li Yang le...@freescale.com Signed-off-by: Tang Yuantian yuantian.t...@freescale.com Signed-off-by: Varun Sethi varun.se...@freescale.com Signed-off-by: Minghuan Lian minghuan.l...@freescale.com Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com Signed-off-by: Kumar Gala ga...@kernel.crashing.org Signed-off-by: Andy Fleming aflem...@freescale.com Signed-off-by: Vakul Garg va...@freescale.com --- v2: - incorporated review comments on commits message - change unit address of cpu nodes to match the reg property arch/powerpc/boot/dts/fsl/b4420si-post.dtsi | 94 ++ arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi | 49 + arch/powerpc/boot/dts/fsl/b4860si-post.dtsi | 138 ++ arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi | 59 ++ arch/powerpc/boot/dts/fsl/b4si-post.dtsi| 262 +++ arch/powerpc/boot/dts/fsl/b4si-pre.dtsi | 65 +++ 6 files changed, 667 insertions(+), 0 deletions(-) create mode 100644 arch/powerpc/boot/dts/fsl/b4420si-post.dtsi create mode 100644 arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi create mode 100644 arch/powerpc/boot/dts/fsl/b4860si-post.dtsi create mode 100644 arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi create mode 100644 arch/powerpc/boot/dts/fsl/b4si-post.dtsi create mode 100644 arch/powerpc/boot/dts/fsl/b4si-pre.dtsi Is there a reason you didn't get rid of b4si-pre.dtsi and just merge it into b4860si-pre.dtsi b4420-pre.dtsi? [SL] No particular reason. I have just tried to re-factored these files as you have suggested. Hence managed the commonalities in B4 files and differences in B4860's and B4420's respective files to reduce duplicity. Regards, Shaveta [SL] Kumar, please suggest. Please suggest , if this re-factoring for pre-si dtsi should not be required. This was done to keep things uniform. Accordingly we will send a re-spin if required. Regards Poonam Regards, Shaveta ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
