Re: [RFC PATCH powerpc] make CONFIG_NUMA depends on CONFIG_SMP
On Fri, 2013-04-19 at 10:10 +0800, Li Zhong wrote: On Thu, 2013-04-18 at 11:46 +1000, Michael Ellerman wrote: On Wed, May 30, 2012 at 05:31:58PM +0800, Li Zhong wrote: I'm not sure whether it makes sense to add this dependency to avoid CONFI_NUMA !CONFIG_SMP. I want to do this because I saw some build errors on next-tree when compiling with CONFIG_SMP disabled, and it seems they are caused by some codes under the CONFIG_NUMA #ifdefs. This seems to make sense to me. Can you please repost with a better changelog and a description of the actual build error you were seeing. I tried it today, but didn't find any build errors any more, guess those errors should have already been fixed. But it seems to me by disabling CONFIG_NUMA when CONFIG_SMP is disabled, could at least prevent some unnecessary code being compiled into the kernel. (After building a kernel with/without CONFIG_NUMA just now, it seems that the vmlinux is ~100K smaller without CONFIG_NUMA). I'm not sure whether this is still needed. Yeah we'll leave your patch out. Unless someone cares deeply about the size of the UP build, I think it's better to just leave them as separate options. cheers ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH v7 3/3] of/pci: mips: convert to common of_pci_range_parser
2013.04.18. 15:09 keltezéssel, Jason Cooper írta: On Thu, Apr 18, 2013 at 01:59:10PM +0100, Andrew Murray wrote: On Wed, Apr 17, 2013 at 04:42:48PM +0100, Linus Walleij wrote: On Tue, Apr 16, 2013 at 12:18 PM, Andrew Murray andrew.mur...@arm.com wrote: This patch converts the pci_load_of_ranges function to use the new common of_pci_range_parser. Signed-off-by: Andrew Murray andrew.mur...@arm.com Signed-off-by: Liviu Dudau liviu.du...@arm.com Reviewed-by: Rob Herring rob.herr...@calxeda.com Tested-by: Linus Walleij linus.wall...@linaro.org Jason - you may not have seen this, but here (Linus Walleij) is another Tested-by to add to this patch in your tree (if you can). Thanks, I saw it. Unfortunately, the PR was already sent, and the branch is now pulled into arm-soc. Sorry I had no time earlier, but I have tested this now on MIPS. The patch causes build errors unfortunately. Given the fact that this has been merged already, I will send a fixup patch. -Gabor ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH] powerpc/fsl: Enable CONFIG_E1000E in mpc85xx_smp_defconfig
On the most boards of Freescale platform, they use the PCI-Express Intel(R) PRO/1000 gigabit ethernet card to work. So enable the corresponding driver for it. Signed-off-by: Chunhe Lan chunhe@freescale.com --- arch/powerpc/configs/mpc85xx_smp_defconfig |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/configs/mpc85xx_smp_defconfig b/arch/powerpc/configs/mpc85xx_smp_defconfig index 8d00ea5b..6996ea3 100644 --- a/arch/powerpc/configs/mpc85xx_smp_defconfig +++ b/arch/powerpc/configs/mpc85xx_smp_defconfig @@ -114,6 +114,7 @@ CONFIG_DUMMY=y CONFIG_FS_ENET=y CONFIG_UCC_GETH=y CONFIG_GIANFAR=y +CONFIG_E1000E=y CONFIG_MARVELL_PHY=y CONFIG_DAVICOM_PHY=y CONFIG_CICADA_PHY=y -- 1.7.6.5 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 3/3] powerpc/powernv: Patch MSI EOI handler on P8
The EOI handler of MSI/MSI-X interrupts for P8 (PHB3) need additional
steps to handle the P/Q bits in IVE before EOIing the corresponding
interrupt. The patch changes the EOI handler to cover that.
Signed-off-by: Gavin Shan sha...@linux.vnet.ibm.com
---
arch/powerpc/platforms/powernv/pci-ioda.c | 33 +
arch/powerpc/platforms/powernv/pci.c | 19
arch/powerpc/platforms/powernv/pci.h |1 +
arch/powerpc/sysdev/xics/icp-native.c | 33 -
4 files changed, 85 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c
b/arch/powerpc/platforms/powernv/pci-ioda.c
index d8d5baa..de4a4a9 100644
--- a/arch/powerpc/platforms/powernv/pci-ioda.c
+++ b/arch/powerpc/platforms/powernv/pci-ioda.c
@@ -645,6 +645,37 @@ static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb,
struct pci_dev *dev,
return 0;
}
+static int pnv_pci_ioda_msi_eoi(struct pnv_phb *phb, unsigned int hw_irq)
+{
+ u8 p_bit = 1, q_bit = 1;
+ long rc;
+
+ while (p_bit || q_bit) {
+ rc = opal_pci_get_xive_reissue(phb-opal_id,
+ hw_irq - phb-msi_base, p_bit, q_bit);
+ if (rc) {
+ pr_warning(%s: Failed to get P/Q bits of IRQ#%d
+ on PHB#%d, rc=%ld\n, __func__, hw_irq,
+ phb-hose-global_number, rc);
+ return -EIO;
+ }
+ if (!p_bit !q_bit)
+ break;
+
+ rc = opal_pci_set_xive_reissue(phb-opal_id,
+ hw_irq - phb-msi_base, p_bit, q_bit);
+ if (rc) {
+ pr_warning(%s: Failed to clear P/Q (%01d/%01d) of
+ IRQ#%d on PHB#%d, rc=%ld\n, __func__,
+ p_bit, q_bit, hw_irq,
+ phb-hose-global_number, rc);
+ return -EIO;
+ }
+ }
+
+ return 0;
+}
+
static void pnv_pci_init_ioda_msis(struct pnv_phb *phb)
{
unsigned int bmap_size;
@@ -667,6 +698,8 @@ static void pnv_pci_init_ioda_msis(struct pnv_phb *phb)
return;
}
phb-msi_setup = pnv_pci_ioda_msi_setup;
+ if (phb-type == PNV_PHB_IODA2)
+ phb-msi_eoi = pnv_pci_ioda_msi_eoi;
phb-msi32_support = 1;
pr_info( Allocated bitmap for %d MSIs (base IRQ 0x%x)\n,
phb-msi_count, phb-msi_base);
diff --git a/arch/powerpc/platforms/powernv/pci.c
b/arch/powerpc/platforms/powernv/pci.c
index e088dc7..439dfc5 100644
--- a/arch/powerpc/platforms/powernv/pci.c
+++ b/arch/powerpc/platforms/powernv/pci.c
@@ -148,6 +148,25 @@ static void pnv_teardown_msi_irqs(struct pci_dev *pdev)
irq_dispose_mapping(entry-irq);
}
}
+
+int pnv_pci_msi_eoi(unsigned int hw_irq)
+{
+ struct pci_controller *hose, *tmp;
+ struct pnv_phb *phb = NULL;
+
+ list_for_each_entry_safe(hose, tmp, hose_list, list_node) {
+ phb = hose-private_data;
+ if (hw_irq = phb-msi_base
+ hw_irq phb-msi_base + phb-msi_count) {
+ if (!phb-msi_eoi)
+ return -EEXIST;
+ return phb-msi_eoi(phb, hw_irq);
+ }
+ }
+
+ /* For LSI interrupts, we needn't do it */
+ return 0;
+}
#endif /* CONFIG_PCI_MSI */
static void pnv_pci_dump_p7ioc_diag_data(struct pnv_phb *phb)
diff --git a/arch/powerpc/platforms/powernv/pci.h
b/arch/powerpc/platforms/powernv/pci.h
index fcd5135..4ae015b 100644
--- a/arch/powerpc/platforms/powernv/pci.h
+++ b/arch/powerpc/platforms/powernv/pci.h
@@ -101,6 +101,7 @@ struct pnv_phb {
int (*msi_setup)(struct pnv_phb *phb, struct pci_dev *dev,
unsigned int hwirq, unsigned int is_64,
struct msi_msg *msg);
+ int (*msi_eoi)(struct pnv_phb *phb, unsigned int hw_irq);
void (*dma_dev_setup)(struct pnv_phb *phb, struct pci_dev *pdev);
void (*fixup_phb)(struct pci_controller *hose);
u32 (*bdfn_to_pe)(struct pnv_phb *phb, struct pci_bus *bus, u32 devfn);
diff --git a/arch/powerpc/sysdev/xics/icp-native.c
b/arch/powerpc/sysdev/xics/icp-native.c
index 48861d3..289355e 100644
--- a/arch/powerpc/sysdev/xics/icp-native.c
+++ b/arch/powerpc/sysdev/xics/icp-native.c
@@ -27,6 +27,10 @@
#include asm/xics.h
#include asm/kvm_ppc.h
+#if defined(CONFIG_PPC_POWERNV) defined(CONFIG_PCI_MSI)
+extern int pnv_pci_msi_eoi(unsigned int hw_irq);
+#endif
+
struct icp_ipl {
union {
u32 word;
@@ -89,6 +93,24 @@ static void icp_native_eoi(struct irq_data *d)
icp_native_set_xirr((xics_pop_cppr() 24) | hw_irq);
}
+static void icp_p8_native_eoi(struct irq_data *d)
+{
+ unsigned int hw_irq = (unsigned
[PATCH 1/3] powerpc/powernv: Supports PHB3
The patch intends to initialize PHB3 during system boot stage. The
flag PNV_PHB_MODEL_PHB3 is introduced to differentiate IODA2
compatible PHB3 from other types of PHBs.
Signed-off-by: Benjamin Herrenschmidt b...@kernel.crashing.org
---
arch/powerpc/platforms/powernv/pci-ioda.c | 62 +++--
arch/powerpc/platforms/powernv/pci.c |7 +++-
arch/powerpc/platforms/powernv/pci.h |8 ++-
3 files changed, 43 insertions(+), 34 deletions(-)
diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c
b/arch/powerpc/platforms/powernv/pci-ioda.c
index 8e90e89..8993242 100644
--- a/arch/powerpc/platforms/powernv/pci-ioda.c
+++ b/arch/powerpc/platforms/powernv/pci-ioda.c
@@ -852,18 +852,19 @@ static u32 pnv_ioda_bdfn_to_pe(struct pnv_phb *phb,
struct pci_bus *bus,
return phb-ioda.pe_rmap[(bus-number 8) | devfn];
}
-void __init pnv_pci_init_ioda1_phb(struct device_node *np)
+void __init pnv_pci_init_ioda_phb(struct device_node *np, int ioda_type)
{
struct pci_controller *hose;
static int primary = 1;
struct pnv_phb *phb;
unsigned long size, m32map_off, iomap_off, pemap_off;
const u64 *prop64;
+ const u32 *prop32;
u64 phb_id;
void *aux;
long rc;
- pr_info( Initializing IODA OPAL PHB %s\n, np-full_name);
+ pr_info( Initializing IODA%d OPAL PHB %s\n, ioda_type, np-full_name);
prop64 = of_get_property(np, ibm,opal-phbid, NULL);
if (!prop64) {
@@ -890,37 +891,34 @@ void __init pnv_pci_init_ioda1_phb(struct device_node *np)
hose-last_busno = 0xff;
hose-private_data = phb;
phb-opal_id = phb_id;
- phb-type = PNV_PHB_IODA1;
+ phb-type = ioda_type;
/* Detect specific models for error handling */
if (of_device_is_compatible(np, ibm,p7ioc-pciex))
phb-model = PNV_PHB_MODEL_P7IOC;
+ else if (of_device_is_compatible(np, ibm,p8-pciex))
+ phb-model = PNV_PHB_MODEL_PHB3;
else
phb-model = PNV_PHB_MODEL_UNKNOWN;
- /* We parse ranges now since we need to deduce the register base
-* from the IO base
-*/
+ /* Parse 32-bit and IO ranges (if any) */
pci_process_bridge_OF_ranges(phb-hose, np, primary);
primary = 0;
- /* Magic formula from Milton */
+ /* Get registers */
phb-regs = of_iomap(np, 0);
if (phb-regs == NULL)
pr_err( Failed to map registers !\n);
-
- /* XXX This is hack-a-thon. This needs to be changed so that:
-* - we obtain stuff like PE# etc... from device-tree
-* - we properly re-allocate M32 ourselves
-*(the OFW one isn't very good)
-*/
-
/* Initialize more IODA stuff */
- phb-ioda.total_pe = 128;
+ prop32 = of_get_property(np, ibm,opal-num-pes, NULL);
+ if (!prop32)
+ phb-ioda.total_pe = 1;
+ else
+ phb-ioda.total_pe = *prop32;
phb-ioda.m32_size = resource_size(hose-mem_resources[0]);
- /* OFW Has already off top 64k of M32 space (MSI space) */
+ /* FW Has already off top 64k of M32 space (MSI space) */
phb-ioda.m32_size += 0x1;
phb-ioda.m32_segsize = phb-ioda.m32_size / phb-ioda.total_pe;
@@ -930,7 +928,10 @@ void __init pnv_pci_init_ioda1_phb(struct device_node *np)
phb-ioda.io_segsize = phb-ioda.io_size / phb-ioda.total_pe;
phb-ioda.io_pci_base = 0; /* XXX calculate this ? */
- /* Allocate aux data arrays */
+ /* Allocate aux data arrays
+*
+* XXX TODO: Don't allocate io segmap on PHB3
+*/
size = _ALIGN_UP(phb-ioda.total_pe / 8, sizeof(unsigned long));
m32map_off = size;
size += phb-ioda.total_pe * sizeof(phb-ioda.m32_segmap[0]);
@@ -960,7 +961,7 @@ void __init pnv_pci_init_ioda1_phb(struct device_node *np)
hose-mem_resources[2].start = 0;
hose-mem_resources[2].end = 0;
-#if 0
+#if 0 /* We should really do that ... */
rc = opal_pci_set_phb_mem_window(opal-phb_id,
window_type,
window_num,
@@ -974,16 +975,6 @@ void __init pnv_pci_init_ioda1_phb(struct device_node *np)
phb-ioda.m32_size, phb-ioda.m32_segsize,
phb-ioda.io_size, phb-ioda.io_segsize);
- if (phb-regs) {
- pr_devel( BUID = 0x%016llx\n, in_be64(phb-regs + 0x100));
- pr_devel( PHB2_CR = 0x%016llx\n, in_be64(phb-regs + 0x160));
- pr_devel( IO_BAR = 0x%016llx\n, in_be64(phb-regs + 0x170));
- pr_devel( IO_BAMR = 0x%016llx\n, in_be64(phb-regs + 0x178));
- pr_devel( IO_SAR = 0x%016llx\n, in_be64(phb-regs + 0x180));
- pr_devel( M32_BAR = 0x%016llx\n, in_be64(phb-regs + 0x190));
- pr_devel( M32_BAMR = 0x%016llx\n, in_be64(phb-regs + 0x198));
[PATCH 2/3] powerpc/powernv: Configure IODA2 tables explicitly
The PHB3, which is compatible with IODA2, have lots of tables (RTT/
PETLV/PEST/IVT/RBA) in system memory and have corresponding BARs to
trace the system memory address. The patch configures the addresses
of variable tables explicitly through OPAL API.
Signed-off-by: Gavin Shan sha...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/opal.h |5 +--
arch/powerpc/platforms/powernv/pci-ioda.c | 32 +
arch/powerpc/platforms/powernv/pci.h | 25 ++
3 files changed, 59 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/include/asm/opal.h b/arch/powerpc/include/asm/opal.h
index a4b28f1..0af7ba0 100644
--- a/arch/powerpc/include/asm/opal.h
+++ b/arch/powerpc/include/asm/opal.h
@@ -491,9 +491,8 @@ int64_t opal_pci_map_pe_mmio_window(uint64_t phb_id,
uint16_t pe_number,
uint16_t window_type, uint16_t window_num,
uint16_t segment_num);
int64_t opal_pci_set_phb_table_memory(uint64_t phb_id, uint64_t rtt_addr,
- uint64_t ivt_addr, uint64_t ivt_len,
- uint64_t reject_array_addr,
- uint64_t peltv_addr);
+ uint64_t peltv_addr, uint64_t pest_addr,
+ uint64_t ivt_addr, uint64_t rba_addr);
int64_t opal_pci_set_pe(uint64_t phb_id, uint64_t pe_number, uint64_t
bus_dev_func,
uint8_t bus_compare, uint8_t dev_compare, uint8_t
func_compare,
uint8_t pe_action);
diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c
b/arch/powerpc/platforms/powernv/pci-ioda.c
index 8993242..d8d5baa 100644
--- a/arch/powerpc/platforms/powernv/pci-ioda.c
+++ b/arch/powerpc/platforms/powernv/pci-ioda.c
@@ -998,6 +998,38 @@ void __init pnv_pci_init_ioda_phb(struct device_node *np,
int ioda_type)
ppc_md.pcibios_window_alignment = pnv_pci_window_alignment;
pci_add_flags(PCI_REASSIGN_ALL_RSRC);
+ /*
+* Initialize variable tables for IODA2. We might share the table
+* size between firmware and Linux someday. For now, we have fixed
+* values for them
+*/
+ if (ioda_type == PNV_PHB_IODA2) {
+ phb-ioda.tbl_rtt = alloc_bootmem_align(PNV_PHB3_RTT_TBL_SIZE,
+ PNV_PHB3_RTT_TBL_SIZE);
+ phb-ioda.tbl_peltv =
alloc_bootmem_align(PNV_PHB3_PELTV_TBL_SIZE,
+ PNV_PHB3_PELTV_TBL_SIZE);
+ phb-ioda.tbl_pest = alloc_bootmem_align(PNV_PHB3_PEST_TBL_SIZE,
+ PNV_PHB3_PEST_TBL_SIZE);
+ phb-ioda.tbl_ivt = alloc_bootmem_align(PNV_PHB3_IVT_TBL_SIZE,
+ PNV_PHB3_IVT_TBL_SIZE);
+ phb-ioda.tbl_rba = alloc_bootmem_align(PNV_PHB3_RBA_TBL_SIZE,
+ PNV_PHB3_RBA_TBL_SIZE);
+ if (!phb-ioda.tbl_rtt || !phb-ioda.tbl_peltv ||
+ !phb-ioda.tbl_pest || !phb-ioda.tbl_ivt ||
+ !phb-ioda.tbl_rba)
+ pr_warning( No memory for IODA2 tables\n);
+ else {
+ rc = opal_pci_set_phb_table_memory(phb_id,
+ __pa(phb-ioda.tbl_rtt),
+ __pa(phb-ioda.tbl_peltv),
+ __pa(phb-ioda.tbl_pest),
+ __pa(phb-ioda.tbl_ivt),
+ __pa(phb-ioda.tbl_rba));
+ if (rc != OPAL_SUCCESS)
+ pr_warning( Failed to set IODA2 tables\n);
+ }
+ }
+
/* Reset IODA tables to a clean state */
rc = opal_pci_reset(phb_id, OPAL_PCI_IODA_TABLE_RESET,
OPAL_ASSERT_RESET);
if (rc)
diff --git a/arch/powerpc/platforms/powernv/pci.h
b/arch/powerpc/platforms/powernv/pci.h
index 4ce91f5..fcd5135 100644
--- a/arch/powerpc/platforms/powernv/pci.h
+++ b/arch/powerpc/platforms/powernv/pci.h
@@ -64,6 +64,24 @@ struct pnv_ioda_pe {
struct list_headlist;
};
+/*
+ * The sizes of variable PHB3 tables. The IVT table size is variable
+ * and depends on the IVE stride (16-bytes or 128-bytes)
+ */
+#define PNV_PHB3_IVT_TBL_IVE_16B
+
+#define PNV_PHB3_RTT_TBL_SIZE 0x2
+#define PNV_PHB3_PELTV_TBL_SIZE0x2000
+#define PNV_PHB3_PEST_TBL_SIZE 0x1000
+#ifdef PNV_PHB3_IVT_TBL_IVE_16B
+#define PNV_PHB3_IVT_TBL_SIZE 0x8000
+#define PNV_PHB3_IVT_TBL_STRIDE2 /* double-words */
+#else
+#define PNV_PHB3_IVT_TBL_SIZE 0x4
+#define PNV_PHB3_IVT_TBL_STRIDE16 /* double-words */
+#endif
+#define PNV_PHB3_RBA_TBL_SIZE 0x1000
+
struct pnv_phb {
[PATCH v2 01/15] powerpc/85xx: cache operations for Freescale SoCs based on BOOK3E
These cache operations support Freescale SoCs based on BOOK3E.
Move L1 cache operations to fsl_booke_cache.S in order to maintain
easily. And, add cache operations for backside L2 cache and platform cache.
The backside L2 cache appears on e500mc and e5500 core. The platform cache
supported by this patch is L2 Look-Aside Cache, which appears on SoCs
with e500v1/e500v2 core, such as MPC8572, P1020, etc.
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
---
arch/powerpc/include/asm/cacheflush.h |8 ++
arch/powerpc/kernel/Makefile |1 +
arch/powerpc/kernel/fsl_booke_cache.S | 210 +
arch/powerpc/kernel/head_fsl_booke.S | 74
4 files changed, 219 insertions(+), 74 deletions(-)
create mode 100644 arch/powerpc/kernel/fsl_booke_cache.S
diff --git a/arch/powerpc/include/asm/cacheflush.h
b/arch/powerpc/include/asm/cacheflush.h
index b843e35..bc3f937 100644
--- a/arch/powerpc/include/asm/cacheflush.h
+++ b/arch/powerpc/include/asm/cacheflush.h
@@ -32,6 +32,14 @@ extern void flush_dcache_page(struct page *page);
extern void __flush_disable_L1(void);
+#ifdef CONFIG_FSL_SOC_BOOKE
+void flush_dcache_L1(void);
+void flush_backside_L2_cache(void);
+void disable_backside_L2_cache(void);
+void flush_disable_L2(void);
+void invalidate_enable_L2(void);
+#endif
+
extern void __flush_icache_range(unsigned long, unsigned long);
static inline void flush_icache_range(unsigned long start, unsigned long stop)
{
diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile
index f960a79..4acf739 100644
--- a/arch/powerpc/kernel/Makefile
+++ b/arch/powerpc/kernel/Makefile
@@ -87,6 +87,7 @@ extra-$(CONFIG_8xx) := head_8xx.o
extra-y+= vmlinux.lds
obj-$(CONFIG_RELOCATABLE_PPC32)+= reloc_32.o
+obj-$(CONFIG_FSL_SOC_BOOKE)+= fsl_booke_cache.o
obj-$(CONFIG_PPC32)+= entry_32.o setup_32.o
obj-$(CONFIG_PPC64)+= dma-iommu.o iommu.o
diff --git a/arch/powerpc/kernel/fsl_booke_cache.S
b/arch/powerpc/kernel/fsl_booke_cache.S
new file mode 100644
index 000..232c47b
--- /dev/null
+++ b/arch/powerpc/kernel/fsl_booke_cache.S
@@ -0,0 +1,210 @@
+/*
+ * Copyright 2009-2013 Freescale Semiconductor, Inc.
+ * Scott Wood scottw...@freescale.com
+ * Dave Liu dave...@freescale.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include asm/reg.h
+#include asm/page.h
+#include asm/ppc_asm.h
+#include asm/asm-offsets.h
+
+ .section .text
+
+/L1 Cache/
+
+/* flush L1 d-cache */
+_GLOBAL(flush_dcache_L1)
+ mfspr r3,SPRN_L1CFG0
+
+ rlwinm r5,r3,9,3 /* Extract cache block size */
+ twlgti r5,1/* Only 32 and 64 byte cache blocks
+* are currently defined.
+*/
+ li r4,32
+ subfic r6,r5,2 /* r6 = log2(1KiB / cache block size) -
+* log2(number of ways)
+*/
+ slw r5,r4,r5/* r5 = cache block size */
+
+ rlwinm r7,r3,0,0xff/* Extract number of KiB in the cache */
+ mulli r7,r7,13/* An 8-way cache will require 13
+* loads per set.
+*/
+ slw r7,r7,r6
+
+ /* save off HID0 and set DCFA */
+ mfspr r8,SPRN_HID0
+ ori r9,r8,HID0_DCFA@l
+ mtspr SPRN_HID0,r9
+ isync
+
+ LOAD_REG_IMMEDIATE(r4, KERNELBASE)
+ mtctr r7
+
+1: lwz r3,0(r4)/* Load... */
+ add r4,r4,r5
+ bdnz1b
+
+ msync
+ LOAD_REG_IMMEDIATE(r4, KERNELBASE)
+ mtctr r7
+
+1: dcbf0,r4/* ...and flush. */
+ add r4,r4,r5
+ bdnz1b
+
+ /* restore HID0 */
+ mtspr SPRN_HID0,r8
+ isync
+
+ blr
+
+/* Flush L1 d-cache, invalidate and disable d-cache and i-cache */
+_GLOBAL(__flush_disable_L1)
+ mflrr10
+ bl flush_dcache_L1 /* Flush L1 d-cache */
+ mtlrr10
+
+ msync
+ mfspr r4, SPRN_L1CSR0 /* Invalidate and disable d-cache */
+ li r5, 2
+ rlwimi r4, r5, 0, 3
+
+ msync
+ isync
+ mtspr SPRN_L1CSR0, r4
+ isync
+
+ msync
+1: mfspr r4, SPRN_L1CSR0 /* Wait for the invalidate to finish */
+ andi. r4, r4, 2
+ bne 1b
+
+ msync
+ mfspr r4, SPRN_L1CSR1 /* Invalidate and disable i-cache */
+ li r5, 2
+ rlwimi r4, r5, 0, 3
+
+ msync
+ isync
+ mtspr SPRN_L1CSR1, r4
+ isync
+ msync
+
+ blr
+
+/
[PATCH v2 02/15] powerpc/85xx: add sleep and deep sleep support
Some Freescale SoCs like MPC8536 and P1022 has the deep sleep mode in addtion to the sleep mode. In sleep PM mode, the clocks of e500 core and unused IP blocks is turned off. IP blocks which are allowed to wake up the processor are still running. While in deep sleep PM mode, additionally, the power supply is removed from e500 core and most IP blocks. Only the blocks needed to wake up the chip out of deep sleep are ON. This patch supports 32-bit and 36-bit address space. The sleep mode is equal to the Standby state in Linux. The deep sleep mode is equal to the Suspend-to-RAM state of Linux Power Management. Command to enter sleep mode. echo standby /sys/power/state Command to enter deep sleep mode. echo mem /sys/power/state Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com Signed-off-by: Li Yang le...@freescale.com --- arch/powerpc/platforms/85xx/Makefile |1 + arch/powerpc/platforms/85xx/sleep.S | 621 ++ arch/powerpc/sysdev/fsl_pmc.c| 98 +- arch/powerpc/sysdev/fsl_soc.h|5 + 4 files changed, 707 insertions(+), 18 deletions(-) create mode 100644 arch/powerpc/platforms/85xx/sleep.S diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/platforms/85xx/Makefile index 2eab37e..a35bab7 100644 --- a/arch/powerpc/platforms/85xx/Makefile +++ b/arch/powerpc/platforms/85xx/Makefile @@ -2,6 +2,7 @@ # Makefile for the PowerPC 85xx linux kernel. # obj-$(CONFIG_SMP) += smp.o +obj-$(CONFIG_FSL_PMC) += sleep.o obj-y += common.o diff --git a/arch/powerpc/platforms/85xx/sleep.S b/arch/powerpc/platforms/85xx/sleep.S new file mode 100644 index 000..5a43adb --- /dev/null +++ b/arch/powerpc/platforms/85xx/sleep.S @@ -0,0 +1,621 @@ +/* + * Enter and leave deep sleep/sleep state on MPC85xx + * + * Author: Scott Wood scottw...@freescale.com + * + * Copyright (C) 2006-2013 Freescale Semiconductor, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include asm/page.h +#include asm/ppc_asm.h +#include asm/reg.h +#include asm/asm-offsets.h +#include asm/mmu.h + +#define CCSR_ADDR 0xf000 + +#define L2C_OFFSET 0x2 /* L2 Cache Controller offset */ + +#define BPTR_OFFSET0x20 /* Boot Page Translation Register */ +#define BPTR_EN0x8000 + +#define PMRCCR_OFFSET 0xe0084 +#define PMRCCR_VRCNT_PRE_MASK 0x1f00 +#define PMRCCR_VRCNT_MASK 0x00ff + +#define POWMGTSCR_OFFSET 0xe0080 +#define POWMGTSCR_DPSLP0x0010 /* deep sleep mode */ + +#define SS_TB 0x00 +#define SS_HID 0x08 /* 2 HIDs */ +#define SS_IAC 0x10 /* 2 IACs */ +#define SS_DAC 0x18 /* 2 DACs */ +#define SS_DBCR0x20 /* 3 DBCRs */ +#define SS_PID 0x2c /* 3 PIDs */ +#define SS_SPRG0x38 /* 8 SPRGs */ +#define SS_IVOR0x58 /* 20 interrupt vectors */ +#define SS_TCR 0xa8 +#define SS_BUCSR 0xac +#define SS_L1CSR 0xb0 /* 2 L1CSRs */ +#define SS_MSR 0xb8 +#define SS_USPRG 0xbc +#define SS_GPREG 0xc0 /* r12-r31 */ +#define SS_LR 0x110 +#define SS_CR 0x114 +#define SS_SP 0x118 +#define SS_CURRENT 0x11c +#define SS_IVPR0x120 +#define SS_BPTR0x124 + +#define STATE_SAVE_SIZE 0x128 + + .section .data + .align 5 +mpc85xx_sleep_save_area: + .space STATE_SAVE_SIZE +ccsrbase_low: + .long 0 +ccsrbase_high: + .long 0 +powmgtreq: + .long 0 + + .section .text + .align 12 + + /* +* r3 = high word of physical address of CCSR +* r4 = low word of physical address of CCSR +* r5 = JOG or deep sleep request +* JOG-0x0020, deep sleep-0x0010 +*/ +_GLOBAL(mpc85xx_enter_deep_sleep) + lis r6, ccsrbase_low@ha + stw r4, ccsrbase_low@l(r6) + lis r6, ccsrbase_high@ha + stw r3, ccsrbase_high@l(r6) + + lis r6, powmgtreq@ha + stw r5, powmgtreq@l(r6) + + lis r10, mpc85xx_sleep_save_area@h + ori r10, r10, mpc85xx_sleep_save_area@l + + mfspr r5, SPRN_HID0 + mfspr r6, SPRN_HID1 + + stw r5, SS_HID+0(r10) + stw r6, SS_HID+4(r10) + + mfspr r4, SPRN_IAC1 + mfspr r5, SPRN_IAC2 + mfspr r6, SPRN_DAC1 + mfspr r7, SPRN_DAC2 + + stw r4, SS_IAC+0(r10) + stw r5, SS_IAC+4(r10) + stw r6, SS_DAC+0(r10) + stw r7, SS_DAC+4(r10) + + mfspr r4, SPRN_DBCR0 + mfspr r5, SPRN_DBCR1 + mfspr r6, SPRN_DBCR2 + + stw r4, SS_DBCR+0(r10) + stw r5, SS_DBCR+4(r10) + stw r6, SS_DBCR+8(r10) + + mfspr r4, SPRN_PID0 +
[PATCH v2 03/15] fsl_pmc: Add API to enable device as wakeup event source
From: chenhui zhao chenhui.z...@freescale.com
Add APIs for setting wakeup source and lossless Ethernet in low power modes.
These APIs can be used by wake-on-packet feature.
Change-Id: I1803dcd4571af1eac49b43d99c578e7f99e2c278
Signed-off-by: Dave Liu dave...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Jin Qing b24...@freescale.com
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
---
arch/powerpc/sysdev/fsl_pmc.c | 72 -
arch/powerpc/sysdev/fsl_soc.h | 11 ++
2 files changed, 82 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/sysdev/fsl_pmc.c b/arch/powerpc/sysdev/fsl_pmc.c
index 6c2c8b3..94ae476 100644
--- a/arch/powerpc/sysdev/fsl_pmc.c
+++ b/arch/powerpc/sysdev/fsl_pmc.c
@@ -38,6 +38,7 @@ struct pmc_regs {
__be32 powmgtcsr;
#define POWMGTCSR_SLP 0x0002
#define POWMGTCSR_DPSLP0x0010
+#define POWMGTCSR_LOSSLESS 0x0040
__be32 res3[2];
/* 0xe008c: Power management clock disable register */
__be32 pmcdr;
@@ -48,6 +49,75 @@ static unsigned int pmc_flag;
#define PMC_SLEEP 0x1
#define PMC_DEEP_SLEEP 0x2
+#define PMC_LOSSLESS 0x4
+
+/**
+ * mpc85xx_pmc_set_wake - enable devices as wakeup event source
+ * @dev: a device affected
+ * @enable: True to enable event generation; false to disable
+ *
+ * This enables the device as a wakeup event source, or disables it.
+ *
+ * RETURN VALUE:
+ * 0 is returned on success.
+ * -EINVAL is returned if device is not supposed to wake up the system.
+ * -ENODEV is returned if PMC is unavailable.
+ * Error code depending on the platform is returned if both the platform and
+ * the native mechanism fail to enable the generation of wake-up events
+ */
+int mpc85xx_pmc_set_wake(struct device *dev, bool enable)
+{
+ int ret = 0;
+ struct device_node *clk_np;
+ const u32 *prop;
+ u32 pmcdr_mask;
+
+ if (!pmc_regs) {
+ dev_err(dev, %s: PMC is unavailable\n, __func__);
+ return -ENODEV;
+ }
+
+ if (enable !device_may_wakeup(dev))
+ return -EINVAL;
+
+ clk_np = of_parse_phandle(dev-of_node, fsl,pmc-handle, 0);
+ if (!clk_np)
+ return -EINVAL;
+
+ prop = of_get_property(clk_np, fsl,pmcdr-mask, NULL);
+ if (!prop) {
+ ret = -EINVAL;
+ goto out;
+ }
+ pmcdr_mask = be32_to_cpup(prop);
+
+ if (enable)
+ /* clear to enable clock in low power mode */
+ clrbits32(pmc_regs-pmcdr, pmcdr_mask);
+ else
+ setbits32(pmc_regs-pmcdr, pmcdr_mask);
+
+out:
+ of_node_put(clk_np);
+ return ret;
+}
+EXPORT_SYMBOL_GPL(mpc85xx_pmc_set_wake);
+
+/**
+ * mpc85xx_pmc_set_lossless_ethernet - enable lossless ethernet
+ * in (deep) sleep mode
+ * @enable: True to enable event generation; false to disable
+ */
+void mpc85xx_pmc_set_lossless_ethernet(int enable)
+{
+ if (pmc_flag PMC_LOSSLESS) {
+ if (enable)
+ setbits32(pmc_regs-powmgtcsr, POWMGTCSR_LOSSLESS);
+ else
+ clrbits32(pmc_regs-powmgtcsr, POWMGTCSR_LOSSLESS);
+ }
+}
+EXPORT_SYMBOL_GPL(mpc85xx_pmc_set_lossless_ethernet);
static int pmc_suspend_enter(suspend_state_t state)
{
@@ -122,7 +192,7 @@ static int pmc_probe(struct platform_device *pdev)
pmc_flag |= PMC_DEEP_SLEEP;
if (of_device_is_compatible(np, fsl,p1022-pmc))
- pmc_flag |= PMC_DEEP_SLEEP;
+ pmc_flag |= PMC_DEEP_SLEEP | PMC_LOSSLESS;
suspend_set_ops(pmc_suspend_ops);
diff --git a/arch/powerpc/sysdev/fsl_soc.h b/arch/powerpc/sysdev/fsl_soc.h
index 949377d..e58f4dd 100644
--- a/arch/powerpc/sysdev/fsl_soc.h
+++ b/arch/powerpc/sysdev/fsl_soc.h
@@ -21,6 +21,17 @@ struct device_node;
extern void fsl_rstcr_restart(char *cmd);
+#ifdef CONFIG_FSL_PMC
+int mpc85xx_pmc_set_wake(struct device *dev, bool enable);
+void mpc85xx_pmc_set_lossless_ethernet(int enable);
+#else
+static inline int mpc85xx_pmc_set_wake(struct device *dev, bool enable)
+{
+ return -ENODEV;
+}
+#define mpc85xx_pmc_set_lossless_ethernet(enable) do { } while (0)
+#endif
+
#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
/* The different ports that the DIU can be connected to */
--
1.7.3
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[PATCH v2 04/15] pm: add power node to dts
The Power Management device tree stub indicated that the platform
supports Power Management feature.
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
---
arch/powerpc/boot/dts/fsl/mpc8536si-post.dtsi | 14 ++-
arch/powerpc/boot/dts/fsl/mpc8544si-post.dtsi |2 +
arch/powerpc/boot/dts/fsl/mpc8548si-post.dtsi |2 +
arch/powerpc/boot/dts/fsl/mpc8572si-post.dtsi |2 +
arch/powerpc/boot/dts/fsl/p1010si-post.dtsi |8
arch/powerpc/boot/dts/fsl/p1020si-post.dtsi |5 +++
arch/powerpc/boot/dts/fsl/p1021si-post.dtsi |5 +++
arch/powerpc/boot/dts/fsl/p1022si-post.dtsi | 11 --
arch/powerpc/boot/dts/fsl/p2020si-post.dtsi | 14 +++
arch/powerpc/boot/dts/fsl/pq3-power.dtsi | 48 +
10 files changed, 106 insertions(+), 5 deletions(-)
create mode 100644 arch/powerpc/boot/dts/fsl/pq3-power.dtsi
diff --git a/arch/powerpc/boot/dts/fsl/mpc8536si-post.dtsi
b/arch/powerpc/boot/dts/fsl/mpc8536si-post.dtsi
index c8b2daa..900f117 100644
--- a/arch/powerpc/boot/dts/fsl/mpc8536si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/mpc8536si-post.dtsi
@@ -199,6 +199,10 @@
/include/ pq3-dma-0.dtsi
/include/ pq3-etsec1-0.dtsi
+ enet0: ethernet@24000 {
+ fsl,wake-on-filer;
+ fsl,pmc-handle = etsec1_clk;
+ };
/include/ pq3-etsec1-timer-0.dtsi
usb@22000 {
@@ -222,9 +226,10 @@
};
/include/ pq3-etsec1-2.dtsi
-
- ethernet@26000 {
+ enet2: ethernet@26000 {
cell-index = 1;
+ fsl,wake-on-filer;
+ fsl,pmc-handle = etsec3_clk;
};
usb@2b000 {
@@ -249,4 +254,9 @@
reg = 0xe 0x1000;
fsl,has-rstcr;
};
+
+/include/ pq3-power.dtsi
+ power@e0070 {
+ compatible = fsl,mpc8536-pmc, fsl,mpc8548-pmc;
+ };
};
diff --git a/arch/powerpc/boot/dts/fsl/mpc8544si-post.dtsi
b/arch/powerpc/boot/dts/fsl/mpc8544si-post.dtsi
index b68eb11..ea7416a 100644
--- a/arch/powerpc/boot/dts/fsl/mpc8544si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/mpc8544si-post.dtsi
@@ -188,4 +188,6 @@
reg = 0xe 0x1000;
fsl,has-rstcr;
};
+
+/include/ pq3-power.dtsi
};
diff --git a/arch/powerpc/boot/dts/fsl/mpc8548si-post.dtsi
b/arch/powerpc/boot/dts/fsl/mpc8548si-post.dtsi
index 579d76c..dddb737 100644
--- a/arch/powerpc/boot/dts/fsl/mpc8548si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/mpc8548si-post.dtsi
@@ -156,4 +156,6 @@
reg = 0xe 0x1000;
fsl,has-rstcr;
};
+
+/include/ pq3-power.dtsi
};
diff --git a/arch/powerpc/boot/dts/fsl/mpc8572si-post.dtsi
b/arch/powerpc/boot/dts/fsl/mpc8572si-post.dtsi
index d44e25a..7313351 100644
--- a/arch/powerpc/boot/dts/fsl/mpc8572si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/mpc8572si-post.dtsi
@@ -193,4 +193,6 @@
reg = 0xe 0x1000;
fsl,has-rstcr;
};
+
+/include/ pq3-power.dtsi
};
diff --git a/arch/powerpc/boot/dts/fsl/p1010si-post.dtsi
b/arch/powerpc/boot/dts/fsl/p1010si-post.dtsi
index af12ead..01c8c33 100644
--- a/arch/powerpc/boot/dts/fsl/p1010si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p1010si-post.dtsi
@@ -171,6 +171,8 @@
/include/ pq3-etsec2-0.dtsi
enet0: ethernet@b {
+ fsl,pmc-handle = etsec1_clk;
+
queue-group@b {
fsl,rx-bit-map = 0xff;
fsl,tx-bit-map = 0xff;
@@ -179,6 +181,8 @@
/include/ pq3-etsec2-1.dtsi
enet1: ethernet@b1000 {
+ fsl,pmc-handle = etsec2_clk;
+
queue-group@b1000 {
fsl,rx-bit-map = 0xff;
fsl,tx-bit-map = 0xff;
@@ -187,6 +191,8 @@
/include/ pq3-etsec2-2.dtsi
enet2: ethernet@b2000 {
+ fsl,pmc-handle = etsec3_clk;
+
queue-group@b2000 {
fsl,rx-bit-map = 0xff;
fsl,tx-bit-map = 0xff;
@@ -199,4 +205,6 @@
reg = 0xe 0x1000;
fsl,has-rstcr;
};
+
+/include/ pq3-power.dtsi
};
diff --git a/arch/powerpc/boot/dts/fsl/p1020si-post.dtsi
b/arch/powerpc/boot/dts/fsl/p1020si-post.dtsi
index 68cc5e7..410e6e5 100644
--- a/arch/powerpc/boot/dts/fsl/p1020si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p1020si-post.dtsi
@@ -162,14 +162,17 @@
/include/ pq3-etsec2-0.dtsi
enet0: enet0_grp2: ethernet@b {
+ fsl,pmc-handle = etsec1_clk;
};
/include/ pq3-etsec2-1.dtsi
enet1: enet1_grp2: ethernet@b1000 {
+ fsl,pmc-handle = etsec2_clk;
};
/include/ pq3-etsec2-2.dtsi
enet2: enet2_grp2: ethernet@b2000 {
+ fsl,pmc-handle = etsec3_clk;
};
global-utilities@e {
@@ -177,6 +180,8 @@
reg = 0xe 0x1000;
fsl,has-rstcr;
};
+
+/include/ pq3-power.dtsi
};
/include/ pq3-etsec2-grp2-0.dtsi
[PATCH v2 05/15] fsl_pmc: update device bindings
From: Li Yang le...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
---
.../devicetree/bindings/powerpc/fsl/pmc.txt| 59 +++
1 files changed, 34 insertions(+), 25 deletions(-)
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/pmc.txt
b/Documentation/devicetree/bindings/powerpc/fsl/pmc.txt
index 07256b7..f1f749f 100644
--- a/Documentation/devicetree/bindings/powerpc/fsl/pmc.txt
+++ b/Documentation/devicetree/bindings/powerpc/fsl/pmc.txt
@@ -9,15 +9,20 @@ Properties:
fsl,mpc8548-pmc should be listed for any chip whose PMC is
compatible. fsl,mpc8536-pmc should also be listed for any chip
- whose PMC is compatible, and implies deep-sleep capability.
+ whose PMC is compatible, and implies deep-sleep capability and
+ wake on user defined packet(wakeup on ARP).
+
+ fsl,p1022-pmc should be listed for any chip whose PMC is
+ compatible, and implies lossless Ethernet capability during sleep.
fsl,mpc8641d-pmc should be listed for any chip whose PMC is
compatible; all statements below that apply to fsl,mpc8548-pmc also
apply to fsl,mpc8641d-pmc.
Compatibility does not include bit assignments in SCCR/PMCDR/DEVDISR; these
- bit assignments are indicated via the sleep specifier in each device's
- sleep property.
+ bit assignments are indicated via the clock nodes. Device which has a
+ controllable clock source should have a fsl,pmc-handle property pointing
+ to the clock node.
- reg: For devices compatible with fsl,mpc8349-pmc, the first resource
is the PMC block, and the second resource is the Clock Configuration
@@ -33,31 +38,35 @@ Properties:
this is a phandle to an fsl,gtm node on which timer 4 can be used as
a wakeup source from deep sleep.
-Sleep specifiers:
+Clock nodes:
+The clock nodes are to describe the masks in PM controller registers for each
+soc clock.
+- fsl,pmcdr-mask: For fsl,mpc8548-pmc-compatible devices, the mask will be
+ ORed into PMCDR before suspend if the device using this clock is the wake-up
+ source and need to be running during low power mode; clear the mask if
+ otherwise.
- fsl,mpc8349-pmc: Sleep specifiers consist of one cell. For each bit
- that is set in the cell, the corresponding bit in SCCR will be saved
- and cleared on suspend, and restored on resume. This sleep controller
- supports disabling and resuming devices at any time.
+- fsl,sccr-mask: For fsl,mpc8349-pmc-compatible devices, the corresponding
+ bit specified by the mask in SCCR will be saved and cleared on suspend, and
+ restored on resume.
- fsl,mpc8536-pmc: Sleep specifiers consist of three cells, the third of
- which will be ORed into PMCDR upon suspend, and cleared from PMCDR
- upon resume. The first two cells are as described for fsl,mpc8578-pmc.
- This sleep controller only supports disabling devices during system
- sleep, or permanently.
-
- fsl,mpc8548-pmc: Sleep specifiers consist of one or two cells, the
- first of which will be ORed into DEVDISR (and the second into
- DEVDISR2, if present -- this cell should be zero or absent if the
- hardware does not have DEVDISR2) upon a request for permanent device
- disabling. This sleep controller does not support configuring devices
- to disable during system sleep (unless supported by another compatible
- match), or dynamically.
+- fsl,devdisr-mask: Contain one or two cells, depending on the availability of
+ DEVDISR2 register. For compatible devices, the mask will be ORed into
DEVDISR
+ or DEVDISR2 when the clock should be permenently disabled.
Example:
- power@b00 {
- compatible = fsl,mpc8313-pmc, fsl,mpc8349-pmc;
- reg = 0xb00 0x100 0xa00 0x100;
- interrupts = 80 8;
+ power@e0070 {
+ compatible = fsl,mpc8536-pmc, fsl,mpc8548-pmc;
+ reg = 0xe0070 0x20;
+
+ etsec1_clk: soc-clk@24 {
+ fsl,pmcdr-mask = 0x0080;
+ };
+ etsec2_clk: soc-clk@25 {
+ fsl,pmcdr-mask = 0x0040;
+ };
+ etsec3_clk: soc-clk@26 {
+ fsl,pmcdr-mask = 0x0020;
+ };
};
--
1.7.3
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[PATCH v2 06/15] powerpc/85xx: add support to JOG feature using cpufreq interface
From: chenhui zhao chenhui.z...@freescale.com Some 85xx silicons like MPC8536 and P1022 have a JOG feature, which provides a dynamic mechanism to lower or raise the CPU core clock at runtime. This patch adds the support to change CPU frequency using the standard cpufreq interface. The ratio CORE to CCB can be 1:1(except MPC8536), 3:2, 2:1, 5:2, 3:1, 7:2 and 4:1. Two CPU cores on P1022 must not in the low power state during the frequency transition. The driver uses a atomic counter to meet the requirement. The jog mode frequency transition process on the MPC8536 is similar to the deep sleep process. The driver need save the CPU state and restore it after CPU warm reset. Note: * The I/O peripherals such as PCIe and eTSEC may lose packets during the jog mode frequency transition. * The driver doesn't support MPC8536 Rev 1.0 due to a JOG erratum. Subsequent revisions of MPC8536 have corrected the erratum. Signed-off-by: Dave Liu dave...@freescale.com Signed-off-by: Li Yang le...@freescale.com Signed-off-by: Jerry Huang chang-ming.hu...@freescale.com Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com CC: Scott Wood scottw...@freescale.com --- arch/powerpc/platforms/85xx/Makefile |1 + drivers/cpufreq/Kconfig.powerpc | 10 + drivers/cpufreq/Makefile |1 + drivers/cpufreq/mpc85xx-cpufreq.c| 390 ++ 4 files changed, 402 insertions(+), 0 deletions(-) create mode 100644 drivers/cpufreq/mpc85xx-cpufreq.c diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/platforms/85xx/Makefile index a35bab7..da53bde 100644 --- a/arch/powerpc/platforms/85xx/Makefile +++ b/arch/powerpc/platforms/85xx/Makefile @@ -3,6 +3,7 @@ # obj-$(CONFIG_SMP) += smp.o obj-$(CONFIG_FSL_PMC) += sleep.o +obj-$(CONFIG_CPU_FREQ_MPC85xx) += sleep.o obj-y += common.o diff --git a/drivers/cpufreq/Kconfig.powerpc b/drivers/cpufreq/Kconfig.powerpc index e76992f..ba06a00 100644 --- a/drivers/cpufreq/Kconfig.powerpc +++ b/drivers/cpufreq/Kconfig.powerpc @@ -5,3 +5,13 @@ config CPU_FREQ_MAPLE help This adds support for frequency switching on Maple 970FX Evaluation Board and compatible boards (IBM JS2x blades). + +config CPU_FREQ_MPC85xx + bool Support for Freescale MPC85xx CPU freq + depends on PPC_85xx PPC32 !PPC_E500MC + select CPU_FREQ_TABLE + help + This adds support for dynamic frequency switching on + Freescale MPC85xx by cpufreq interface. MPC8536 and P1022 + have a JOG feature, which provides a dynamic mechanism + to lower or raise the CPU core clock at runtime. diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile index 863fd18..e7aecc5 100644 --- a/drivers/cpufreq/Makefile +++ b/drivers/cpufreq/Makefile @@ -61,3 +61,4 @@ obj-$(CONFIG_ARM_IMX6Q_CPUFREQ) += imx6q-cpufreq.o ## # PowerPC platform drivers obj-$(CONFIG_CPU_FREQ_MAPLE) += maple-cpufreq.o +obj-$(CONFIG_CPU_FREQ_MPC85xx) += mpc85xx-cpufreq.o diff --git a/drivers/cpufreq/mpc85xx-cpufreq.c b/drivers/cpufreq/mpc85xx-cpufreq.c new file mode 100644 index 000..f56c826 --- /dev/null +++ b/drivers/cpufreq/mpc85xx-cpufreq.c @@ -0,0 +1,390 @@ +/* + * Copyright (C) 2008-2012 Freescale Semiconductor, Inc. + * Author: Dave Liu dave...@freescale.com + * Modifier: Chenhui Zhao chenhui.z...@freescale.com + * + * The cpufreq driver is for Freescale 85xx processor, + * based on arch/powerpc/platforms/cell/cbe_cpufreq.c + * (C) Copyright IBM Deutschland Entwicklung GmbH 2005-2007 + * Christian Krafft kra...@de.ibm.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include linux/module.h +#include linux/cpufreq.h +#include linux/of_platform.h +#include linux/suspend.h +#include linux/cpu.h +#include linux/time.h +#include linux/io.h +#include linux/smp.h + +#include asm/prom.h +#include asm/reg.h +#include asm/machdep.h + +#include sysdev/fsl_soc.h + +static DEFINE_MUTEX(mpc85xx_switch_mutex); +static void __iomem *guts; + +static u32 sysfreq; +static unsigned int max_pll[2]; +static atomic_t in_jog_process; +static struct cpufreq_frequency_table *mpc85xx_freqs; +static int (*set_pll)(unsigned int cpu, unsigned int pll); + +static struct
[PATCH v2 08/15] powerpc/85xx: add cpu hotplug support for e500mc/e5500
From: Chen-Hui Zhao chenhui.z...@freescale.com
Add support to disable and re-enable individual cores at runtime.
This supports e500mc/e5500 core based SoCs.
To prevent the register access race, only read/write RCPM registers
in platform_cpu_die() on the boot cpu instead of accessing by individual
cpus. Platform implementations can override the platform_cpu_die().
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Andy Fleming aflem...@freescale.com
---
arch/powerpc/Kconfig |2 +-
arch/powerpc/include/asm/smp.h|1 +
arch/powerpc/kernel/smp.c | 16 ++-
arch/powerpc/platforms/85xx/smp.c | 56 ++--
4 files changed, 69 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 0e11a09..b6851be 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -347,7 +347,7 @@ config SWIOTLB
config HOTPLUG_CPU
bool Support for enabling/disabling CPUs
depends on SMP HOTPLUG (PPC_PSERIES || \
- PPC_PMAC || PPC_POWERNV || (PPC_85xx !PPC_E500MC))
+ PPC_PMAC || PPC_POWERNV || PPC_85xx)
---help---
Say Y here to be able to disable and re-enable individual
CPUs at runtime on SMP machines.
diff --git a/arch/powerpc/include/asm/smp.h b/arch/powerpc/include/asm/smp.h
index 195ce2a..95be584 100644
--- a/arch/powerpc/include/asm/smp.h
+++ b/arch/powerpc/include/asm/smp.h
@@ -60,6 +60,7 @@ extern void smp_generic_take_timebase(void);
DECLARE_PER_CPU(unsigned int, cpu_pvr);
#ifdef CONFIG_HOTPLUG_CPU
+void platform_cpu_die(unsigned int cpu);
extern void migrate_irqs(void);
int generic_cpu_disable(void);
void generic_cpu_die(unsigned int cpu);
diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c
index 76bd9da..386c7ea 100644
--- a/arch/powerpc/kernel/smp.c
+++ b/arch/powerpc/kernel/smp.c
@@ -381,14 +381,28 @@ int generic_cpu_disable(void)
return 0;
}
+/**
+ * platform_cpu_die() - do platform related operations on the boot cpu
+ * after CPU_DEAD is assigned to the variable cpu_state of the dying cpu.
+ * Platform implementations can override this.
+ *
+ * @cpu: the cpu to die
+ */
+void __attribute__ ((weak)) platform_cpu_die(unsigned int cpu)
+{
+ return;
+}
+
void generic_cpu_die(unsigned int cpu)
{
int i;
for (i = 0; i 100; i++) {
smp_rmb();
- if (per_cpu(cpu_state, cpu) == CPU_DEAD)
+ if (per_cpu(cpu_state, cpu) == CPU_DEAD) {
+ platform_cpu_die(cpu);
return;
+ }
msleep(100);
}
printk(KERN_ERR CPU%d didn't die...\n, cpu);
diff --git a/arch/powerpc/platforms/85xx/smp.c
b/arch/powerpc/platforms/85xx/smp.c
index 6c2fe6b..6eae2e0 100644
--- a/arch/powerpc/platforms/85xx/smp.c
+++ b/arch/powerpc/platforms/85xx/smp.c
@@ -40,7 +40,7 @@ struct epapr_spin_table {
u32 pir;
};
-static struct ccsr_guts __iomem *guts;
+static void __iomem *guts_regs;
static u64 timebase;
static int tb_req;
static int tb_valid;
@@ -62,7 +62,7 @@ static inline u32 get_phy_cpu_mask(void)
static void mpc85xx_timebase_freeze(int freeze)
{
- struct ccsr_rcpm __iomem *rcpm = (typeof(rcpm))guts;
+ struct ccsr_rcpm __iomem *rcpm = guts_regs;
u32 mask = get_phy_cpu_mask();
if (freeze)
@@ -76,6 +76,7 @@ static void mpc85xx_timebase_freeze(int freeze)
#else
static void mpc85xx_timebase_freeze(int freeze)
{
+ struct ccsr_guts __iomem *guts = guts_regs;
uint32_t mask;
mask = CCSR_GUTS_DEVDISR_TB0 | CCSR_GUTS_DEVDISR_TB1;
@@ -84,6 +85,7 @@ static void mpc85xx_timebase_freeze(int freeze)
else
clrbits32(guts-devdisr, mask);
+ /* read back to push the previous write */
in_be32(guts-devdisr);
}
#endif
@@ -128,7 +130,45 @@ static void mpc85xx_take_timebase(void)
local_irq_restore(flags);
}
+static void core_reset_erratum(int hw_cpu)
+{
+#ifdef CONFIG_PPC_E500MC
+ struct ccsr_rcpm __iomem *rcpm = guts_regs;
+
+ clrbits32(rcpm-cnapcr, 1 hw_cpu);
+#endif
+}
+
#ifdef CONFIG_HOTPLUG_CPU
+#ifdef CONFIG_PPC_E500MC
+static void __cpuinit smp_85xx_mach_cpu_die(void)
+{
+ unsigned int cpu = smp_processor_id();
+
+ local_irq_disable();
+ idle_task_exit();
+ mb();
+
+ mtspr(SPRN_TCR, 0);
+
+ __flush_disable_L1();
+ disable_backside_L2_cache();
+
+ generic_set_cpu_dead(cpu);
+
+ while (1);
+}
+
+void platform_cpu_die(unsigned int cpu)
+{
+ unsigned int hw_cpu = get_hard_smp_processor_id(cpu);
+ struct ccsr_rcpm __iomem *rcpm = guts_regs;
+
+ /* Core Nap Operation */
+ setbits32(rcpm-cnapcr, 1 hw_cpu);
+}
+#else
+/* for e500v1 and e500v2 */
static void __cpuinit smp_85xx_mach_cpu_die(void)
{
unsigned int cpu =
[PATCH v2 09/15] powerpc/rcpm: add sleep feature for SoCs using RCPM
The SoCs which have a RCPM (Run Control/Power Management) module
support power management feature. This patch implements sleep feature.
In sleep mode, the clocks of cores and unused IP blocks will be
turned off. The IP blocks which are allowed to wake up the system
are still running.
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
---
arch/powerpc/Kconfig|4 +-
arch/powerpc/include/asm/fsl_guts.h |1 +
arch/powerpc/platforms/85xx/Kconfig |1 +
arch/powerpc/sysdev/Kconfig |5 ++
arch/powerpc/sysdev/Makefile|1 +
arch/powerpc/sysdev/fsl_rcpm.c | 101 +++
6 files changed, 111 insertions(+), 2 deletions(-)
create mode 100644 arch/powerpc/sysdev/fsl_rcpm.c
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index b6851be..0ad6e30 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -220,7 +220,7 @@ config ARCH_HIBERNATION_POSSIBLE
config ARCH_SUSPEND_POSSIBLE
def_bool y
depends on ADB_PMU || PPC_EFIKA || PPC_LITE5200 || PPC_83xx || \
- (PPC_85xx !PPC_E500MC) || PPC_86xx || PPC_PSERIES \
+ FSL_SOC_BOOKE || PPC_86xx || PPC_PSERIES \
|| 44x || 40x
config PPC_DCR_NATIVE
@@ -694,7 +694,7 @@ config FSL_PCI
config FSL_PMC
bool
default y
- depends on SUSPEND (PPC_85xx || PPC_86xx)
+ depends on SUSPEND ((PPC_85xx !PPC_E500MC) || PPC_86xx)
help
Freescale MPC85xx/MPC86xx power management controller support
(suspend/resume). For MPC83xx see platforms/83xx/suspend.c
diff --git a/arch/powerpc/include/asm/fsl_guts.h
b/arch/powerpc/include/asm/fsl_guts.h
index 4eac1cf..b8a08d5 100644
--- a/arch/powerpc/include/asm/fsl_guts.h
+++ b/arch/powerpc/include/asm/fsl_guts.h
@@ -124,6 +124,7 @@ struct ccsr_rcpm {
u8 res0038[4];
__be32 cwdtdsr;/* 0x003c - Core watchdog detect status
register */
__be32 powmgtcsr; /* 0x0040 - Power Mangement Control Status
Register */
+#define RCPM_POWMGTCSR_SLP 0x0002
u8 res0044[12];
__be32 ippdexpcr; /* 0x0050 - IP Powerdown Exception Control
Register */
u8 res0054[16];
diff --git a/arch/powerpc/platforms/85xx/Kconfig
b/arch/powerpc/platforms/85xx/Kconfig
index 8f02b05..c0aa36e 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -8,6 +8,7 @@ menuconfig FSL_SOC_BOOKE
select FSL_PCI if PCI
select SERIAL_8250_EXTENDED if SERIAL_8250
select SERIAL_8250_SHARE_IRQ if SERIAL_8250
+ select FSL_CORENET_RCPM if SUSPEND PPC_E500MC
default y
if FSL_SOC_BOOKE
diff --git a/arch/powerpc/sysdev/Kconfig b/arch/powerpc/sysdev/Kconfig
index a84fecf..6c22d91 100644
--- a/arch/powerpc/sysdev/Kconfig
+++ b/arch/powerpc/sysdev/Kconfig
@@ -33,3 +33,8 @@ config SCOM_DEBUGFS
config GE_FPGA
bool
default n
+
+config FSL_CORENET_RCPM
+ bool
+ help
+This option enables support for RCPM (Run Control/Power Management).
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index b0a518e..f12b856 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_MMIO_NVRAM) += mmio_nvram.o
obj-$(CONFIG_FSL_SOC) += fsl_soc.o fsl_mpic_err.o
obj-$(CONFIG_FSL_PCI) += fsl_pci.o $(fsl-msi-obj-y)
obj-$(CONFIG_FSL_PMC) += fsl_pmc.o
+obj-$(CONFIG_FSL_CORENET_RCPM) += fsl_rcpm.o
obj-$(CONFIG_FSL_LBC) += fsl_lbc.o
obj-$(CONFIG_FSL_IFC) += fsl_ifc.o
obj-$(CONFIG_FSL_GTM) += fsl_gtm.o
diff --git a/arch/powerpc/sysdev/fsl_rcpm.c b/arch/powerpc/sysdev/fsl_rcpm.c
new file mode 100644
index 000..fd789da
--- /dev/null
+++ b/arch/powerpc/sysdev/fsl_rcpm.c
@@ -0,0 +1,101 @@
+/*
+ * RCPM(Run Control/Power Management) support
+ *
+ * Copyright 2012-2013 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+#include linux/types.h
+#include linux/errno.h
+#include linux/suspend.h
+#include linux/device.h
+#include linux/delay.h
+#include linux/of_platform.h
+
+#include asm/io.h
+#include asm/cacheflush.h
+#include asm/fsl_guts.h
+
+static struct ccsr_rcpm __iomem *rcpm_regs;
+
+static int rcpm_suspend_enter(suspend_state_t state)
+{
+ int ret = 0;
+
+ switch (state) {
+ case PM_SUSPEND_STANDBY:
+
+ flush_dcache_L1();
+ flush_backside_L2_cache();
+
+ setbits32(rcpm_regs-powmgtcsr, RCPM_POWMGTCSR_SLP);
+
+ /* At this point, the device is in sleep mode. */
+
+ /* Upon resume, wait for SLP bit to be
[PATCH v2 10/15] powerpc/85xx: fix 64-bit support for cpu hotplug
From: Chen-Hui Zhao chenhui.z...@freescale.com
* The paca[cpu].cpu_start is used as a signal to indicate if the cpu
should start. So it should be cleard in .cpu_die().
* The limit memory routine only needs to be ran once at boot time
by the boot cpu. Prevent other cpus running it again.
* Rearrange the code segment in smp_85xx_kick_cpu() to share codes
between PPC64 and PPC32 as far as possible.
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Andy Fleming aflem...@freescale.com
---
arch/powerpc/Kconfig |2 +-
arch/powerpc/kernel/smp.c |3 +++
arch/powerpc/mm/tlb_nohash.c |6 --
arch/powerpc/platforms/85xx/smp.c | 23 +++
4 files changed, 19 insertions(+), 15 deletions(-)
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 0ad6e30..aa5794b 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -347,7 +347,7 @@ config SWIOTLB
config HOTPLUG_CPU
bool Support for enabling/disabling CPUs
depends on SMP HOTPLUG (PPC_PSERIES || \
- PPC_PMAC || PPC_POWERNV || PPC_85xx)
+ PPC_PMAC || PPC_POWERNV || FSL_SOC_BOOKE)
---help---
Say Y here to be able to disable and re-enable individual
CPUs at runtime on SMP machines.
diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c
index 386c7ea..c8aa739 100644
--- a/arch/powerpc/kernel/smp.c
+++ b/arch/powerpc/kernel/smp.c
@@ -401,6 +401,9 @@ void generic_cpu_die(unsigned int cpu)
smp_rmb();
if (per_cpu(cpu_state, cpu) == CPU_DEAD) {
platform_cpu_die(cpu);
+#ifdef CONFIG_PPC64
+ paca[cpu].cpu_start = 0;
+#endif
return;
}
msleep(100);
diff --git a/arch/powerpc/mm/tlb_nohash.c b/arch/powerpc/mm/tlb_nohash.c
index 6888cad..de7bf06 100644
--- a/arch/powerpc/mm/tlb_nohash.c
+++ b/arch/powerpc/mm/tlb_nohash.c
@@ -627,8 +627,10 @@ static void __early_init_mmu(int boot_cpu)
num_cams = (mfspr(SPRN_TLB1CFG) TLBnCFG_N_ENTRY) / 4;
linear_map_top = map_mem_in_cams(linear_map_top, num_cams);
- /* limit memory so we dont have linear faults */
- memblock_enforce_memory_limit(linear_map_top);
+ if (boot_cpu) {
+ /* limit memory so we dont have linear faults */
+ memblock_enforce_memory_limit(linear_map_top);
+ }
patch_exception(0x1c0, exc_data_tlb_miss_bolted_book3e);
patch_exception(0x1e0, exc_instruction_tlb_miss_bolted_book3e);
diff --git a/arch/powerpc/platforms/85xx/smp.c
b/arch/powerpc/platforms/85xx/smp.c
index 6eae2e0..74d8cde 100644
--- a/arch/powerpc/platforms/85xx/smp.c
+++ b/arch/powerpc/platforms/85xx/smp.c
@@ -251,10 +251,6 @@ static int __cpuinit smp_85xx_kick_cpu(int nr)
spin_table = phys_to_virt(*cpu_rel_addr);
local_irq_save(flags);
-#ifdef CONFIG_PPC32
-#ifdef CONFIG_HOTPLUG_CPU
- /* Corresponding to generic_set_cpu_dead() */
- generic_set_cpu_up(nr);
if (system_state == SYSTEM_RUNNING) {
/*
@@ -298,12 +294,19 @@ static int __cpuinit smp_85xx_kick_cpu(int nr)
/* clear the acknowledge status */
__secondary_hold_acknowledge = -1;
}
-#endif
flush_spin_table(spin_table);
out_be32(spin_table-pir, hw_cpu);
+#ifdef CONFIG_PPC32
out_be32(spin_table-addr_l, __pa(__early_start));
+#else
+ out_be32(spin_table-addr_h,
+ __pa(*(u64 *)generic_secondary_smp_init) 32);
+ out_be32(spin_table-addr_l,
+ __pa(*(u64 *)generic_secondary_smp_init) 0x);
+#endif
flush_spin_table(spin_table);
+#ifdef CONFIG_PPC32
/* Wait a bit for the CPU to ack. */
if (!spin_event_timeout(__secondary_hold_acknowledge == hw_cpu,
1, 100)) {
@@ -312,18 +315,14 @@ static int __cpuinit smp_85xx_kick_cpu(int nr)
ret = -ENOENT;
goto out;
}
-out:
#else
smp_generic_kick_cpu(nr);
-
- flush_spin_table(spin_table);
- out_be32(spin_table-pir, hw_cpu);
- out_be64((u64 *)(spin_table-addr_h),
- __pa((u64)*((unsigned long long *)generic_secondary_smp_init)));
- flush_spin_table(spin_table);
#endif
+ /* Corresponding to generic_set_cpu_dead() */
+ generic_set_cpu_up(nr);
cur_booting_core = hw_cpu;
+out:
local_irq_restore(flags);
if (ioremappable)
--
1.7.3
___
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[PATCH v2 07/15] powerpc/85xx: add time base sync for SoCs based on e500mc/e5500
From: Chen-Hui Zhao chenhui.z...@freescale.com
In the case of SMP, during the time base sync period, all time bases of
online cores must stop, then start simultaneously.
There is a RCPM (Run Control/Power Management) module in CoreNet based SoCs.
Define a struct ccsr_rcpm to describe the register map.
This patch supports SoCs based on e500mc/e5500, such as P4080, P5020,
etc.
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
---
arch/powerpc/include/asm/fsl_guts.h | 38 +++
arch/powerpc/platforms/85xx/smp.c | 32 +
2 files changed, 70 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/include/asm/fsl_guts.h
b/arch/powerpc/include/asm/fsl_guts.h
index 77ced0b..4eac1cf 100644
--- a/arch/powerpc/include/asm/fsl_guts.h
+++ b/arch/powerpc/include/asm/fsl_guts.h
@@ -106,6 +106,44 @@ struct ccsr_guts {
/* Alternate function signal multiplex control */
#define MPC85xx_PMUXCR_QE(x) (0x8000 (x))
+struct ccsr_rcpm {
+ u8 res[4];
+ __be32 cdozsr; /* 0x0004 - Core Doze Status Register */
+ u8 res0008[4];
+ __be32 cdozcr; /* 0x000c - Core Doze Control Register */
+ u8 res0010[4];
+ __be32 cnapsr; /* 0x0014 - Core Nap Status Register */
+ u8 res0018[4];
+ __be32 cnapcr; /* 0x001c - Core Nap Control Register */
+ u8 res0020[4];
+ __be32 cdozpsr;/* 0x0024 - Core Doze Previous Status Register
*/
+ u8 res0028[4];
+ __be32 cnappsr;/* 0x002c - Core Nap Previous Status Register */
+ u8 res0030[4];
+ __be32 cwaitsr;/* 0x0034 - Core Wait Status Register */
+ u8 res0038[4];
+ __be32 cwdtdsr;/* 0x003c - Core watchdog detect status
register */
+ __be32 powmgtcsr; /* 0x0040 - Power Mangement Control Status
Register */
+ u8 res0044[12];
+ __be32 ippdexpcr; /* 0x0050 - IP Powerdown Exception Control
Register */
+ u8 res0054[16];
+ __be32 cpmimr; /* 0x0064 - Core PM IRQ Mask Register */
+ u8 res0068[4];
+ __be32 cpmcimr;/* 0x006c - Core PM Critical IRQ Mask Register
*/
+ u8 res0070[4];
+ __be32 cpmmcmr;/* 0x0074 - Core PM Machine Check Mask Register
*/
+ u8 res0078[4];
+ __be32 cpmnmimr; /* 0x007c - Core PM NMI Mask Register */
+ u8 res0080[4];
+ __be32 ctbenr; /* 0x0084 - Core Time Base Enable Register */
+ u8 res0088[4];
+ __be32 ctbckselr; /* 0x008c - Core Time Base Clock Select
Register */
+ u8 res0090[4];
+ __be32 ctbhltcr; /* 0x0094 - Core Time Base Halt Control
Register */
+ u8 res0098[4];
+ __be32 cmcpmaskcr; /* 0x00a4 - Core machine check mask control
register */
+};
+
#ifdef CONFIG_PPC_86xx
#define CCSR_GUTS_DMACR_DEV_SSI0 /* DMA controller/channel set
to SSI */
diff --git a/arch/powerpc/platforms/85xx/smp.c
b/arch/powerpc/platforms/85xx/smp.c
index 6a17599..6c2fe6b 100644
--- a/arch/powerpc/platforms/85xx/smp.c
+++ b/arch/powerpc/platforms/85xx/smp.c
@@ -44,7 +44,36 @@ static struct ccsr_guts __iomem *guts;
static u64 timebase;
static int tb_req;
static int tb_valid;
+static u32 cur_booting_core;
+#ifdef CONFIG_PPC_E500MC
+/* get a physical mask of online cores and booting core */
+static inline u32 get_phy_cpu_mask(void)
+{
+ u32 mask;
+ int cpu;
+
+ mask = 1 cur_booting_core;
+ for_each_online_cpu(cpu)
+ mask |= 1 get_hard_smp_processor_id(cpu);
+
+ return mask;
+}
+
+static void mpc85xx_timebase_freeze(int freeze)
+{
+ struct ccsr_rcpm __iomem *rcpm = (typeof(rcpm))guts;
+ u32 mask = get_phy_cpu_mask();
+
+ if (freeze)
+ clrbits32(rcpm-ctbenr, mask);
+ else
+ setbits32(rcpm-ctbenr, mask);
+
+ /* read back to push the previos write */
+ in_be32(rcpm-ctbenr);
+}
+#else
static void mpc85xx_timebase_freeze(int freeze)
{
uint32_t mask;
@@ -57,6 +86,7 @@ static void mpc85xx_timebase_freeze(int freeze)
in_be32(guts-devdisr);
}
+#endif
static void mpc85xx_give_timebase(void)
{
@@ -244,6 +274,7 @@ out:
__pa((u64)*((unsigned long long *)generic_secondary_smp_init)));
flush_spin_table(spin_table);
#endif
+ cur_booting_core = hw_cpu;
local_irq_restore(flags);
@@ -378,6 +409,7 @@ static const struct of_device_id mpc85xx_smp_guts_ids[] = {
{ .compatible = fsl,p1022-guts, },
{ .compatible = fsl,p1023-guts, },
{ .compatible = fsl,p2020-guts, },
+ { .compatible = fsl,qoriq-rcpm-1.0, },
{},
};
--
1.7.3
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[PATCH v2 11/15] powerpc/rcpm: add struct ccsr_rcpm_v2
From: Chen-Hui Zhao chenhui.z...@freescale.com
Add struct ccsr_rcpm_v2 to descibe the v2 RCPM register map on some SoCs,
such as T4240, etc.
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Andy Fleming aflem...@freescale.com
---
arch/powerpc/include/asm/fsl_guts.h | 66 +++
1 files changed, 66 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/include/asm/fsl_guts.h
b/arch/powerpc/include/asm/fsl_guts.h
index b8a08d5..193d1f1 100644
--- a/arch/powerpc/include/asm/fsl_guts.h
+++ b/arch/powerpc/include/asm/fsl_guts.h
@@ -145,6 +145,72 @@ struct ccsr_rcpm {
__be32 cmcpmaskcr; /* 0x00a4 - Core machine check mask control
register */
};
+struct ccsr_rcpm_v2 {
+ u8 res_00[12];
+ u32 tph10sr0; /* Thread PH10 Status Register */
+ u8 res_10[12];
+ u32 tph10setr0; /* Thread PH10 Set Control Register */
+ u8 res_20[12];
+ u32 tph10clrr0; /* Thread PH10 Clear Control Register */
+ u8 res_30[12];
+ u32 tph10psr0; /* Thread PH10 Previous Status Register */
+ u8 res_40[12];
+ u32 twaitsr0; /* Thread Wait Status Register */
+ u8 res_50[96];
+ u32 pcph15sr; /* Physical Core PH15 Status Register */
+ u32 pcph15setr; /* Physical Core PH15 Set Control Register */
+ u32 pcph15clrr; /* Physical Core PH15 Clear Control Register */
+ u32 pcph15psr; /* Physical Core PH15 Prev Status Register */
+ u8 res_c0[16];
+ u32 pcph20sr; /* Physical Core PH20 Status Register */
+ u32 pcph20setr; /* Physical Core PH20 Set Control Register */
+ u32 pcph20clrr; /* Physical Core PH20 Clear Control Register */
+ u32 pcph20psr; /* Physical Core PH20 Prev Status Register */
+ u32 pcpw20sr; /* Physical Core PW20 Status Register */
+ u8 res_e0[12];
+ u32 pcph30sr; /* Physical Core PH30 Status Register */
+ u32 pcph30setr; /* Physical Core PH30 Set Control Register */
+ u32 pcph30clrr; /* Physical Core PH30 Clear Control Register */
+ u32 pcph30psr; /* Physical Core PH30 Prev Status Register */
+ u8 res_100[32];
+ u32 ippwrgatecr;/* IP Power Gating Control Register */
+ u8 res_124[12];
+ u32 powmgtcsr; /* Power Management Control Status Reg */
+#define RCPM_POWMGTCSR_LPM20_RQ0x0010
+#define RCPM_POWMGTCSR_LPM20_ST0x0200
+#define RCPM_POWMGTCSR_P_LPM20_ST 0x0100
+ u8 res_134[12];
+ u32 ippdexpcr[4]; /* IP Powerdown Exception Control Reg */
+ u8 res_150[12];
+ u32 tpmimr0;/* Thread PM Interrupt Mask Reg */
+ u8 res_160[12];
+ u32 tpmcimr0; /* Thread PM Crit Interrupt Mask Reg */
+ u8 res_170[12];
+ u32 tpmmcmr0; /* Thread PM Machine Check Interrupt Mask Reg */
+ u8 res_180[12];
+ u32 tpmnmimr0; /* Thread PM NMI Mask Reg */
+ u8 res_190[12];
+ u32 tmcpmaskcr0;/* Thread Machine Check Mask Control Reg */
+ u32 pctbenr;/* Physical Core Time Base Enable Reg */
+ u32 pctbclkselr;/* Physical Core Time Base Clock Select */
+ u32 tbclkdivr; /* Time Base Clock Divider Register */
+ u8 res_1ac[4];
+ u32 ttbhltcr[4];/* Thread Time Base Halt Control Register */
+ u32 clpcl10sr; /* Cluster PCL10 Status Register */
+ u32 clpcl10setr;/* Cluster PCL30 Set Control Register */
+ u32 clpcl10clrr;/* Cluster PCL30 Clear Control Register */
+ u32 clpcl10psr; /* Cluster PCL30 Prev Status Register */
+ u32 cddslpsetr; /* Core Domain Deep Sleep Set Register */
+ u32 cddslpclrr; /* Core Domain Deep Sleep Clear Register */
+ u32 cdpwroksetr;/* Core Domain Power OK Set Register */
+ u32 cdpwrokclrr;/* Core Domain Power OK Clear Register */
+ u32 cdpwrensr; /* Core Domain Power Enable Status Register */
+ u32 cddslsr;/* Core Domain Deep Sleep Status Register */
+ u8 res_1e8[8];
+ u32 dslpcntcr[8]; /* Deep Sleep Counter Cfg Register */
+ u8 res_300[3568];
+};
+
#ifdef CONFIG_PPC_86xx
#define CCSR_GUTS_DMACR_DEV_SSI0 /* DMA controller/channel set
to SSI */
--
1.7.3
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[PATCH v2 13/15] powerpc/85xx: add support for e6500 L1 cache operation
From: Chen-Hui Zhao chenhui.z...@freescale.com The L1 Data Cache of e6500 contains no modified data, no flush is required. Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com Signed-off-by: Li Yang le...@freescale.com Signed-off-by: Andy Fleming aflem...@freescale.com --- arch/powerpc/kernel/fsl_booke_cache.S | 11 ++- 1 files changed, 10 insertions(+), 1 deletions(-) diff --git a/arch/powerpc/kernel/fsl_booke_cache.S b/arch/powerpc/kernel/fsl_booke_cache.S index 232c47b..24a52bb 100644 --- a/arch/powerpc/kernel/fsl_booke_cache.S +++ b/arch/powerpc/kernel/fsl_booke_cache.S @@ -65,13 +65,22 @@ _GLOBAL(flush_dcache_L1) blr +#define PVR_E6500 0x8040 + /* Flush L1 d-cache, invalidate and disable d-cache and i-cache */ _GLOBAL(__flush_disable_L1) +/* L1 Data Cache of e6500 contains no modified data, no flush is required */ + mfspr r3, SPRN_PVR + rlwinm r4, r3, 16, 0x + lis r5, 0 + ori r5, r5, PVR_E6500@l + cmpwr4, r5 + beq 2f mflrr10 bl flush_dcache_L1 /* Flush L1 d-cache */ mtlrr10 - msync +2: msync mfspr r4, SPRN_L1CSR0 /* Invalidate and disable d-cache */ li r5, 2 rlwimi r4, r5, 0, 3 -- 1.7.3 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v2 14/15] powerpc/smp: add cpu hotplug support for e6500
From: Chen-Hui Zhao chenhui.z...@freescale.com
* Only if two threads of one core are offline, the core can
enter PH20 state.
* Clear PH20 bits before core reset, or core will not restart.
* Introduced a variable l2cache_type in the struce cpu_spec to
indentify the type of L2 cache.
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Andy Fleming aflem...@freescale.com
---
arch/powerpc/include/asm/cputable.h | 10
arch/powerpc/kernel/cputable.c |5
arch/powerpc/platforms/85xx/smp.c | 40 +-
3 files changed, 49 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/include/asm/cputable.h
b/arch/powerpc/include/asm/cputable.h
index f326444..3715def 100644
--- a/arch/powerpc/include/asm/cputable.h
+++ b/arch/powerpc/include/asm/cputable.h
@@ -33,6 +33,13 @@ enum powerpc_pmc_type {
PPC_PMC_G4 = 3,
};
+enum powerpc_l2cache_type {
+ PPC_L2_CACHE_DEFAULT = 0,
+ PPC_L2_CACHE_CORE= 1, /* L2 cache used exclusively by one core */
+ PPC_L2_CACHE_CLUSTER = 2, /* L2 cache shared by a core cluster */
+ PPC_L2_CACHE_SOC = 3, /* L2 cache shared by all cores */
+};
+
struct pt_regs;
extern int machine_check_generic(struct pt_regs *regs);
@@ -58,6 +65,9 @@ struct cpu_spec {
unsigned inticache_bsize;
unsigned intdcache_bsize;
+ /* L2 cache type */
+ enum powerpc_l2cache_type l2cache_type;
+
/* number of performance monitor counters */
unsigned intnum_pmcs;
enum powerpc_pmc_type pmc_type;
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index cc39139..a7329c1 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -2004,6 +2004,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
.cpu_setup = __setup_cpu_e500v1,
.machine_check = machine_check_e500,
.platform = ppc8540,
+ .l2cache_type = PPC_L2_CACHE_SOC,
},
{ /* e500v2 */
.pvr_mask = 0x,
@@ -2023,6 +2024,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
.cpu_setup = __setup_cpu_e500v2,
.machine_check = machine_check_e500,
.platform = ppc8548,
+ .l2cache_type = PPC_L2_CACHE_SOC,
},
{ /* e500mc */
.pvr_mask = 0x,
@@ -2040,6 +2042,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
.cpu_setup = __setup_cpu_e500mc,
.machine_check = machine_check_e500mc,
.platform = ppce500mc,
+ .l2cache_type = PPC_L2_CACHE_CORE,
},
#endif /* CONFIG_PPC32 */
{ /* e5500 */
@@ -2061,6 +2064,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
#endif
.machine_check = machine_check_e500mc,
.platform = ppce5500,
+ .l2cache_type = PPC_L2_CACHE_CORE,
},
{ /* e6500 */
.pvr_mask = 0x,
@@ -2082,6 +2086,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
#endif
.machine_check = machine_check_e500mc,
.platform = ppce6500,
+ .l2cache_type = PPC_L2_CACHE_CLUSTER,
},
#ifdef CONFIG_PPC32
{ /* default match */
diff --git a/arch/powerpc/platforms/85xx/smp.c
b/arch/powerpc/platforms/85xx/smp.c
index 5f3eee3..a8b4df7 100644
--- a/arch/powerpc/platforms/85xx/smp.c
+++ b/arch/powerpc/platforms/85xx/smp.c
@@ -166,13 +166,31 @@ static void core_reset_erratum(int hw_cpu)
{
#ifdef CONFIG_PPC_E500MC
struct ccsr_rcpm __iomem *rcpm = guts_regs;
+ struct ccsr_rcpm_v2 __iomem *rcpm_v2 = guts_regs;
- clrbits32(rcpm-cnapcr, 1 hw_cpu);
+ if (rcpmv2)
+ setbits32(rcpm_v2-pcph20clrr,
+ 1 cpu_core_index_of_thread(hw_cpu));
+ else
+ clrbits32(rcpm-cnapcr, 1 hw_cpu);
#endif
}
#ifdef CONFIG_HOTPLUG_CPU
#ifdef CONFIG_PPC_E500MC
+static inline bool is_core_down(unsigned int thread)
+{
+ cpumask_t thd_mask;
+
+ if (!smt_capable())
+ return true;
+
+ cpumask_shift_left(thd_mask, threads_core_mask,
+ cpu_core_index_of_thread(thread) * threads_per_core);
+
+ return !cpumask_intersects(thd_mask, cpu_online_mask);
+}
+
static void __cpuinit smp_85xx_mach_cpu_die(void)
{
unsigned int cpu = smp_processor_id();
@@ -183,8 +201,11 @@ static void __cpuinit smp_85xx_mach_cpu_die(void)
mtspr(SPRN_TCR, 0);
- __flush_disable_L1();
- disable_backside_L2_cache();
+
[PATCH v2 15/15] powerpc/rcpm: add sleep support for T4/B4 chips
From: Chen-Hui Zhao chenhui.z...@freescale.com
RCPM unit controls the power managment of T4/B4 chips. Software can
access RCPM registers to put specific thread/core in PH10/PH15/PH20/PH30
state or put the device in LPM10/LPM20/LPM40 mode.
The RCPM unit supports several wake up sources through internal timers
and internal and external interrupts.
When the device enter sleep state, it will be put in LPM20 mode.
The command is echo standby /sys/power/state.
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Andy Fleming aflem...@freescale.com
---
arch/powerpc/sysdev/fsl_rcpm.c | 54 +---
1 files changed, 50 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/sysdev/fsl_rcpm.c b/arch/powerpc/sysdev/fsl_rcpm.c
index fd789da..10e5cb3 100644
--- a/arch/powerpc/sysdev/fsl_rcpm.c
+++ b/arch/powerpc/sysdev/fsl_rcpm.c
@@ -20,6 +20,7 @@
#include asm/fsl_guts.h
static struct ccsr_rcpm __iomem *rcpm_regs;
+static struct ccsr_rcpm_v2 __iomem *rcpm2_regs;
static int rcpm_suspend_enter(suspend_state_t state)
{
@@ -53,6 +54,41 @@ static int rcpm_suspend_enter(suspend_state_t state)
return ret;
}
+static int rcpm_v2_suspend_enter(suspend_state_t state)
+{
+ int ret = 0;
+
+ switch (state) {
+ case PM_SUSPEND_STANDBY:
+
+ /* clear previous LPM20 status */
+ setbits32(rcpm2_regs-powmgtcsr, RCPM_POWMGTCSR_P_LPM20_ST);
+ /* enter LPM20 status */
+ setbits32(rcpm2_regs-powmgtcsr, RCPM_POWMGTCSR_LPM20_RQ);
+
+ /* At this point, the device is in LPM20 status. */
+
+ /* resume ... */
+ ret = spin_event_timeout(
+ (in_be32(rcpm2_regs-powmgtcsr)
RCPM_POWMGTCSR_LPM20_ST)
+ == 0, 1, 10);
+ if (!ret) {
+ pr_err(%s: timeout waiting for LPM20 bit to be
cleared\n,
+ __func__);
+ ret = -EINVAL;
+ }
+
+ break;
+
+ default:
+ ret = -EINVAL;
+
+ }
+
+ return ret;
+
+}
+
static int rcpm_suspend_valid(suspend_state_t state)
{
if (state == PM_SUSPEND_STANDBY)
@@ -63,16 +99,25 @@ static int rcpm_suspend_valid(suspend_state_t state)
static const struct platform_suspend_ops rcpm_suspend_ops = {
.valid = rcpm_suspend_valid,
- .enter = rcpm_suspend_enter,
};
static int rcpm_probe(struct platform_device *pdev)
{
struct device_node *np = pdev-dev.of_node;
- rcpm_regs = of_iomap(np, 0);
- if (!rcpm_regs)
- return -ENOMEM;
+ if (of_device_is_compatible(np, fsl,qoriq-rcpm-2.0)) {
+ rcpm2_regs = of_iomap(np, 0);
+ if (!rcpm2_regs)
+ return -ENOMEM;
+
+ rcpm_suspend_ops.enter = rcpm_v2_suspend_enter;
+ } else {
+ rcpm_regs = of_iomap(np, 0);
+ if (!rcpm_regs)
+ return -ENOMEM;
+
+ rcpm_suspend_ops.enter = rcpm_suspend_enter;
+ }
suspend_set_ops(rcpm_suspend_ops);
@@ -82,6 +127,7 @@ static int rcpm_probe(struct platform_device *pdev)
static const struct of_device_id rcpm_ids[] = {
{ .compatible = fsl,qoriq-rcpm-1.0, },
+ { .compatible = fsl,qoriq-rcpm-2.0, },
{ },
};
--
1.7.3
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[PATCH v2 12/15] powerpc/85xx: add time base sync support for e6500
From: Chen-Hui Zhao chenhui.z...@freescale.com
For e6500, two threads in one core share one time base. Just need
to do time base sync on first thread of one core, and skip it on
the other thread.
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Andy Fleming aflem...@freescale.com
---
arch/powerpc/platforms/85xx/smp.c | 52 +++-
1 files changed, 44 insertions(+), 8 deletions(-)
diff --git a/arch/powerpc/platforms/85xx/smp.c
b/arch/powerpc/platforms/85xx/smp.c
index 74d8cde..5f3eee3 100644
--- a/arch/powerpc/platforms/85xx/smp.c
+++ b/arch/powerpc/platforms/85xx/smp.c
@@ -26,6 +26,7 @@
#include asm/cacheflush.h
#include asm/dbell.h
#include asm/fsl_guts.h
+#include asm/cputhreads.h
#include sysdev/fsl_soc.h
#include sysdev/mpic.h
@@ -45,6 +46,7 @@ static u64 timebase;
static int tb_req;
static int tb_valid;
static u32 cur_booting_core;
+static bool rcpmv2;
#ifdef CONFIG_PPC_E500MC
/* get a physical mask of online cores and booting core */
@@ -53,26 +55,40 @@ static inline u32 get_phy_cpu_mask(void)
u32 mask;
int cpu;
- mask = 1 cur_booting_core;
- for_each_online_cpu(cpu)
- mask |= 1 get_hard_smp_processor_id(cpu);
+ if (smt_capable()) {
+ /* two threads in one core share one time base */
+ mask = 1 cpu_core_index_of_thread(cur_booting_core);
+ for_each_online_cpu(cpu)
+ mask |= 1 cpu_core_index_of_thread(
+ get_hard_smp_processor_id(cpu));
+ } else {
+ mask = 1 cur_booting_core;
+ for_each_online_cpu(cpu)
+ mask |= 1 get_hard_smp_processor_id(cpu);
+ }
return mask;
}
static void mpc85xx_timebase_freeze(int freeze)
{
- struct ccsr_rcpm __iomem *rcpm = guts_regs;
+ u32 *addr;
u32 mask = get_phy_cpu_mask();
+ if (rcpmv2)
+ addr = ((struct ccsr_rcpm_v2 *)guts_regs)-pctbenr;
+ else
+ addr = ((struct ccsr_rcpm *)guts_regs)-ctbenr;
+
if (freeze)
- clrbits32(rcpm-ctbenr, mask);
+ clrbits32(addr, mask);
else
- setbits32(rcpm-ctbenr, mask);
+ setbits32(addr, mask);
- /* read back to push the previos write */
- in_be32(rcpm-ctbenr);
+ /* read back to push the previous write */
+ in_be32(addr);
}
+
#else
static void mpc85xx_timebase_freeze(int freeze)
{
@@ -94,6 +110,16 @@ static void mpc85xx_give_timebase(void)
{
unsigned long flags;
+#ifdef CONFIG_PPC_E500MC
+ /*
+* If the booting thread is not the first thread of the core,
+* skip time base sync.
+*/
+ if (smt_capable()
+ cur_booting_core != cpu_first_thread_sibling(cur_booting_core))
+ return;
+#endif
+
local_irq_save(flags);
while (!tb_req)
@@ -117,6 +143,12 @@ static void mpc85xx_take_timebase(void)
{
unsigned long flags;
+#ifdef CONFIG_PPC_E500MC
+ if (smt_capable()
+ cur_booting_core != cpu_first_thread_sibling(cur_booting_core))
+ return;
+#endif
+
local_irq_save(flags);
tb_req = 1;
@@ -457,6 +489,7 @@ static const struct of_device_id mpc85xx_smp_guts_ids[] = {
{ .compatible = fsl,p1023-guts, },
{ .compatible = fsl,p2020-guts, },
{ .compatible = fsl,qoriq-rcpm-1.0, },
+ { .compatible = fsl,qoriq-rcpm-2.0, },
{},
};
@@ -483,6 +516,9 @@ void __init mpc85xx_smp_init(void)
np = of_find_matching_node(NULL, mpc85xx_smp_guts_ids);
if (np) {
+ if (of_device_is_compatible(np, fsl,qoriq-rcpm-2.0))
+ rcpmv2 = true;
+
guts_regs = of_iomap(np, 0);
of_node_put(np);
if (!guts_regs) {
--
1.7.3
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[PATCH] powerpc/fsl-pci: fix setup_pci_atmu() parameter issue
setup_pci_atmu() only has one parameter and remove the extra one, or build will fail due to un-match. Signed-off-by: Roy Zang tie-fei.z...@freescale.com --- arch/powerpc/sysdev/fsl_pci.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c index 40ffe29..f823304 100644 --- a/arch/powerpc/sysdev/fsl_pci.c +++ b/arch/powerpc/sysdev/fsl_pci.c @@ -978,7 +978,7 @@ static int fsl_pci_resume(struct device *dev) return -ENODEV; } - setup_pci_atmu(hose, pci_rsrc); + setup_pci_atmu(hose); return 0; } -- 1.7.9.5 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] powerpc/fsl-pci: fix setup_pci_atmu() parameter issue
On 04/20/2013 02:55 AM, Roy Zang wrote: setup_pci_atmu() only has one parameter and remove the extra one, or build will fail due to un-match. Signed-off-by: Roy Zang tie-fei.z...@freescale.com --- based on Kumar's next branch. Roy ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH] powerpc/rtas_flash: New return code to indicate FW entitlement expiry
Add new return code to rtas_flash to indicate firmware entitlement expiry. This will be used by the update_flash script to return appropriate message to the user. Signed-off-by: Ananth N Mavinakayanahalli ana...@in.ibm.com Signed-off-by: Vasant Hegde hegdevas...@linux.vnet.ibm.com --- arch/powerpc/kernel/rtas_flash.c |1 + 1 file changed, 1 insertion(+) diff --git a/arch/powerpc/kernel/rtas_flash.c b/arch/powerpc/kernel/rtas_flash.c index a7020d2..0a12c16 100644 --- a/arch/powerpc/kernel/rtas_flash.c +++ b/arch/powerpc/kernel/rtas_flash.c @@ -64,6 +64,7 @@ #define VALIDATE_TMP_COMMIT_DL 4 /* Validate Return Status */ #define VALIDATE_TMP_COMMIT5 /* Validate Return Status */ #define VALIDATE_TMP_UPDATE_DL 6 /* Validate Return Status */ +#define VALIDATE_OUT_OF_WRNTY 7 /* Validate Return Status */ /* ibm,manage-flash-image operation tokens */ #define RTAS_REJECT_TMP_IMG 0 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH RESEND] powerpc/rtas_flash: Free kmem upon module exit
Memory allocated to flash_block_list in rtas_flash_write
is not freed during module exit. We hit below call trace
if we unload rtas_flash module after loading new firmware
image and before rebooting the system.
Feb 6 08:42:10 eagle3 kernel: kmem_cache_destroy rtas_flash_cache: Slab cache
still has objects
Feb 6 08:42:10 eagle3 kernel: Call Trace:
Feb 6 08:42:10 eagle3 kernel: [c0001c303b40] [c0014940]
.show_stack+0x70/0x1c0 (unreliable)
Feb 6 08:42:10 eagle3 kernel: [c0001c303bf0] [c0199bec]
.kmem_cache_destroy+0x15c/0x170
Feb 6 08:42:10 eagle3 kernel: [c0001c303c90] [d6fa1208]
.rtas_flash_cleanup+0x3c/0x80 [rtas_flash]
Feb 6 08:42:10 eagle3 kernel: [c0001c303e30] [c0009954]
syscall_exit+0x0/0x94
Signed-off-by: Vasant Hegde hegdevas...@linux.vnet.ibm.com
---
arch/powerpc/kernel/rtas_flash.c |5 +
1 file changed, 5 insertions(+)
diff --git a/arch/powerpc/kernel/rtas_flash.c b/arch/powerpc/kernel/rtas_flash.c
index c642f01..a7020d2 100644
--- a/arch/powerpc/kernel/rtas_flash.c
+++ b/arch/powerpc/kernel/rtas_flash.c
@@ -790,6 +790,11 @@ static void __exit rtas_flash_cleanup(void)
{
rtas_flash_term_hook = NULL;
+ if (rtas_firmware_flash_list) {
+ free_flash_list(rtas_firmware_flash_list);
+ rtas_firmware_flash_list = NULL;
+ }
+
if (flash_block_cache)
kmem_cache_destroy(flash_block_cache);
___
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