Re: [PATCH v2 2/6] PCI/MSI: Factor out pci_get_msi_cap() interface
On Wed, Sep 18, 2013 at 12:30:23AM +1000, Michael Ellerman wrote: How about no? We have a small number of MSIs available, limited by hardware firmware, if we don't impose a quota then the first device that probes will get most/all of the MSIs and other devices miss out. Out of curiosity - how pSeries has had done it without quotas before 448e2ca (powerpc/pseries: Implement a quota system for MSIs)? Anyway I don't see what problem you're trying to solve? I agree the -ve/0/+ve return value pattern is ugly, but it's hardly the end of the world. Well, the interface recently has been re-classified from ugly to unnecessarily complex and actively harmful in Tejun's words ;) Indeed, I checked most of the drivers and it is incredible how people are creative in misusing the interface: from innocent pci_disable_msix() calls when if pci_enable_msix() failed to assuming MSI-Xs were enabled if pci_enable_msix() returned a positive value (apparently untested). Roughly third of the drivers just do not care and bail out once pci_enable_msix() has not succeeded. Not sure how many of these are mandated by the hardware. Another quite common pattern is a call to pci_enable_msix() to figure out the number of MSI-Xs available and a repeated call of pci_enable_msix() to enable those MSI-Xs, this time. The last pattern makes most of sense to me and could be updated with a more clear sequence - a call to (bit modified) pci_msix_table_size() followed by a call to pci_enable_msix(). I think this pattern can effectively supersede the currently recommended loop practice. But as pSeries quota is still required I propose to introduce a new interface pci_get_msix_limit() that combines pci_msix_table_size() and (also new) arch_get_msix_limit(). The latter would check the quota thing in case of pSeries and none in case of all other architectures. The recommended practice would be: /* * Retrieving 'nvec' by means other than pci_msix_table_size() */ rc = pci_get_msix_limit(pdev); if (rc 0) return rc; /* * nvec = min(rc, nvec); */ for (i = 0; i nvec; i++) msix_entry[i].entry = i; rc = pci_enable_msix(pdev, msix_entry, nvec); if (rc) return rc; Thoughts? cheers -- Regards, Alexander Gordeev agord...@redhat.com ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v10 0/3] DMA: Freescale: Add support for 8-channel DMA engine
From: Hongbo Zhang hongbo.zh...@freescale.com Hi DMA and DT maintainers, please have a look at these V10 patches. Freescale QorIQ T4 and B4 introduce new 8-channel DMA engines, this patch set adds support this DMA engine. V9-V10 changes: - update binding description text, mainly about the reg property and also Elo3 DMA controller specification V8-V9 changes: - add Acked-by: Mark Rutland mark.rutl...@arm.com into patch [1/3] - update reg entry 0x100300 0x4 0x100600 0x4 to two seperate ones 0x100300 0x4, 0x100600 0x4 in patch [2/3] - and also use QorIQ Elo3 DMA to mention previous QorIQ DMA in [2/3] V7-V8 changes: - change the word mapping to specifier for reg and interrupts description V6-V7 changes: - only remove unnecessary CHIP-dma explanations in [1/3] V5-V6 changes: - minor updates of descriptions in binding document and Kconfig - remove [4/4], that should be another patch in future V4-V5 changes: - update description in the dt binding document, to make it more resonable - add new patch [4/4] to eliminate a compiling warning which already exists for a long time V3-V4 changes: - introduce new patch [1/3] to revise the legacy dma binding document - and then add new paragraph to describe new dt node binding in [2/3] - rebase to latest kernel v3.11-rc1 V2-V3 changes: - edit Documentation/devicetree/bindings/powerpc/fsl/dma.txt - edit text string in Kconfig and the driver files, using elo series to mention all the current elo* V1-V2 changes: - removed the codes handling the register dgsr1, since it isn't used currently - renamed the DMA DT compatible to fsl,elo3-dma - renamed the new dts files to elo3-dma-n.dtsi Hongbo Zhang (3): DMA: Freescale: revise device tree binding document DMA: Freescale: Add new 8-channel DMA engine device tree nodes DMA: Freescale: update driver to support 8-channel DMA engine .../devicetree/bindings/powerpc/fsl/dma.txt| 137 ++-- arch/powerpc/boot/dts/fsl/b4si-post.dtsi |4 +- arch/powerpc/boot/dts/fsl/elo3-dma-0.dtsi | 82 arch/powerpc/boot/dts/fsl/elo3-dma-1.dtsi | 82 arch/powerpc/boot/dts/fsl/t4240si-post.dtsi|4 +- drivers/dma/Kconfig|9 +- drivers/dma/fsldma.c |9 +- drivers/dma/fsldma.h |2 +- 8 files changed, 280 insertions(+), 49 deletions(-) create mode 100644 arch/powerpc/boot/dts/fsl/elo3-dma-0.dtsi create mode 100644 arch/powerpc/boot/dts/fsl/elo3-dma-1.dtsi -- 1.7.9.5 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v10 1/3] DMA: Freescale: revise device tree binding document
From: Hongbo Zhang hongbo.zh...@freescale.com This patch updates the discription of each type of DMA controller and its channels, it is preparation for adding another new DMA controller binding, it also fixes some defects of indent for text alignment at the same time. Signed-off-by: Hongbo Zhang hongbo.zh...@freescale.com Acked-by: Mark Rutland mark.rutl...@arm.com --- .../devicetree/bindings/powerpc/fsl/dma.txt| 68 +--- 1 file changed, 31 insertions(+), 37 deletions(-) diff --git a/Documentation/devicetree/bindings/powerpc/fsl/dma.txt b/Documentation/devicetree/bindings/powerpc/fsl/dma.txt index 2a4b4bc..0584168 100644 --- a/Documentation/devicetree/bindings/powerpc/fsl/dma.txt +++ b/Documentation/devicetree/bindings/powerpc/fsl/dma.txt @@ -1,33 +1,30 @@ -* Freescale 83xx DMA Controller +* Freescale DMA Controllers -Freescale PowerPC 83xx have on chip general purpose DMA controllers. +** Freescale Elo DMA Controller + This is a little-endian 4-channel DMA controller, used in Freescale mpc83xx + series chips such as mpc8315, mpc8349, mpc8379 etc. Required properties: -- compatible: compatible list, contains 2 entries, first is -fsl,CHIP-dma, where CHIP is the processor -(mpc8349, mpc8360, etc.) and the second is -fsl,elo-dma -- reg : registers mapping for DMA general status reg -- ranges : Should be defined as specified in 1) to describe the - DMA controller channels. +- compatible: must include fsl,elo-dma +- reg : DMA General Status Register, i.e. DGSR which contains + status for all the 4 DMA channels +- ranges: describes the mapping between the address space of the + DMA channels and the address space of the DMA controller - cell-index: controller index. 0 for controller @ 0x8100 -- interrupts: interrupt mapping for DMA IRQ +- interrupts: interrupt specifier for DMA IRQ - interrupt-parent : optional, if needed for interrupt mapping - - DMA channel nodes: -- compatible: compatible list, contains 2 entries, first is -fsl,CHIP-dma-channel, where CHIP is the processor -(mpc8349, mpc8350, etc.) and the second is -fsl,elo-dma-channel. However, see note below. -- reg : registers mapping for channel -- cell-index: dma channel index starts at 0. +- compatible: must include fsl,elo-dma-channel + However, see note below. +- reg : DMA channel specific registers +- cell-index: DMA channel index starts at 0. Optional properties: -- interrupts: interrupt mapping for DMA channel IRQ - (on 83xx this is expected to be identical to - the interrupts property of the parent node) +- interrupts: interrupt specifier for DMA channel IRQ + (on 83xx this is expected to be identical to + the interrupts property of the parent node) - interrupt-parent : optional, if needed for interrupt mapping Example: @@ -70,30 +67,27 @@ Example: }; }; -* Freescale 85xx/86xx DMA Controller - -Freescale PowerPC 85xx/86xx have on chip general purpose DMA controllers. +** Freescale EloPlus DMA Controller + This is a 4-channel DMA controller with extended addresses and chaining, + mainly used in Freescale mpc85xx/86xx, Pxxx and BSC series chips, such as + mpc8540, mpc8641 p4080, bsc9131 etc. Required properties: -- compatible: compatible list, contains 2 entries, first is -fsl,CHIP-dma, where CHIP is the processor -(mpc8540, mpc8540, etc.) and the second is -fsl,eloplus-dma -- reg : registers mapping for DMA general status reg +- compatible: must include fsl,eloplus-dma +- reg : DMA General Status Register, i.e. DGSR which contains + status for all the 4 DMA channels - cell-index: controller index. 0 for controller @ 0x21000, 1 for controller @ 0xc000 -- ranges : Should be defined as specified in 1) to describe the - DMA controller channels. +- ranges: describes the mapping between the address space of the + DMA channels and the address space of the DMA controller - DMA channel nodes: -- compatible: compatible list, contains 2 entries, first is -fsl,CHIP-dma-channel, where CHIP is the processor -(mpc8540, mpc8560, etc.) and the second is -fsl,eloplus-dma-channel. However, see note below. --
[PATCH v10 2/3] DMA: Freescale: Add new 8-channel DMA engine device tree nodes
From: Hongbo Zhang hongbo.zh...@freescale.com
Freescale QorIQ T4 and B4 introduce new 8-channel DMA engines, this patch adds
the device tree nodes for them.
Signed-off-by: Hongbo Zhang hongbo.zh...@freescale.com
---
.../devicetree/bindings/powerpc/fsl/dma.txt| 69
arch/powerpc/boot/dts/fsl/b4si-post.dtsi |4 +-
arch/powerpc/boot/dts/fsl/elo3-dma-0.dtsi | 82
arch/powerpc/boot/dts/fsl/elo3-dma-1.dtsi | 82
arch/powerpc/boot/dts/fsl/t4240si-post.dtsi|4 +-
5 files changed, 237 insertions(+), 4 deletions(-)
create mode 100644 arch/powerpc/boot/dts/fsl/elo3-dma-0.dtsi
create mode 100644 arch/powerpc/boot/dts/fsl/elo3-dma-1.dtsi
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/dma.txt
b/Documentation/devicetree/bindings/powerpc/fsl/dma.txt
index 0584168..414fe42 100644
--- a/Documentation/devicetree/bindings/powerpc/fsl/dma.txt
+++ b/Documentation/devicetree/bindings/powerpc/fsl/dma.txt
@@ -128,6 +128,75 @@ Example:
};
};
+** Freescale Elo3 DMA Controller
+ DMA controller which has same function as EloPlus except that Elo3 has 8
+ channels while EloPlus has only 4, it is used in Freescale Txxx and Bxxx
+ series chips, such as t1040, t4240, b4860.
+
+Required properties:
+
+- compatible: must include fsl,elo3-dma
+- reg : DMA General Status Registers, i.e. DGSR0 which contains
+ status for channel 1~4, and DGSR1 for channel 5~8
+- ranges: describes the mapping between the address space of the
+ DMA channels and the address space of the DMA controller
+
+- DMA channel nodes:
+- compatible: must include fsl,eloplus-dma-channel
+- reg : DMA channel specific registers
+- interrupts: interrupt specifier for DMA channel IRQ
+- interrupt-parent : optional, if needed for interrupt mapping
+
+Example:
+dma@100300 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = fsl,elo3-dma;
+ reg = 0x100300 0x4,
+ 0x100600 0x4;
+ ranges = 0x0 0x100100 0x500;
+ dma-channel@0 {
+ compatible = fsl,eloplus-dma-channel;
+ reg = 0x0 0x80;
+ interrupts = 28 2 0 0;
+ };
+ dma-channel@80 {
+ compatible = fsl,eloplus-dma-channel;
+ reg = 0x80 0x80;
+ interrupts = 29 2 0 0;
+ };
+ dma-channel@100 {
+ compatible = fsl,eloplus-dma-channel;
+ reg = 0x100 0x80;
+ interrupts = 30 2 0 0;
+ };
+ dma-channel@180 {
+ compatible = fsl,eloplus-dma-channel;
+ reg = 0x180 0x80;
+ interrupts = 31 2 0 0;
+ };
+ dma-channel@300 {
+ compatible = fsl,eloplus-dma-channel;
+ reg = 0x300 0x80;
+ interrupts = 76 2 0 0;
+ };
+ dma-channel@380 {
+ compatible = fsl,eloplus-dma-channel;
+ reg = 0x380 0x80;
+ interrupts = 77 2 0 0;
+ };
+ dma-channel@400 {
+ compatible = fsl,eloplus-dma-channel;
+ reg = 0x400 0x80;
+ interrupts = 78 2 0 0;
+ };
+ dma-channel@480 {
+ compatible = fsl,eloplus-dma-channel;
+ reg = 0x480 0x80;
+ interrupts = 79 2 0 0;
+ };
+};
+
Note on DMA channel compatible properties: The compatible property must say
fsl,elo-dma-channel or fsl,eloplus-dma-channel to be used by the Elo DMA
driver (fsldma). Any DMA channel used by fsldma cannot be used by another
diff --git a/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
b/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
index 7399154..ea53ea1 100644
--- a/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
@@ -223,13 +223,13 @@
reg = 0xe2000 0x1000;
};
-/include/ qoriq-dma-0.dtsi
+/include/ elo3-dma-0.dtsi
dma@100300 {
fsl,iommu-parent = pamu0;
fsl,liodn-reg = guts 0x580; /* DMA1LIODNR */
};
-/include/ qoriq-dma-1.dtsi
+/include/ elo3-dma-1.dtsi
dma@101300 {
fsl,iommu-parent = pamu0;
fsl,liodn-reg = guts 0x584; /* DMA2LIODNR */
diff --git a/arch/powerpc/boot/dts/fsl/elo3-dma-0.dtsi
b/arch/powerpc/boot/dts/fsl/elo3-dma-0.dtsi
new file mode 100644
index 000..3c210e0
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/elo3-dma-0.dtsi
@@ -0,0 +1,82 @@
+/*
+ * QorIQ Elo3 DMA device tree stub [ controller @ offset 0x10 ]
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+
[PATCH v10 3/3] DMA: Freescale: update driver to support 8-channel DMA engine
From: Hongbo Zhang hongbo.zh...@freescale.com
This patch adds support to 8-channel DMA engine, thus the driver works for both
the new 8-channel and the legacy 4-channel DMA engines.
Signed-off-by: Hongbo Zhang hongbo.zh...@freescale.com
---
drivers/dma/Kconfig |9 +
drivers/dma/fsldma.c |9 ++---
drivers/dma/fsldma.h |2 +-
3 files changed, 12 insertions(+), 8 deletions(-)
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index 6825957..3979c65 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -89,14 +89,15 @@ config AT_HDMAC
Support the Atmel AHB DMA controller.
config FSL_DMA
- tristate Freescale Elo and Elo Plus DMA support
+ tristate Freescale Elo series DMA support
depends on FSL_SOC
select DMA_ENGINE
select ASYNC_TX_ENABLE_CHANNEL_SWITCH
---help---
- Enable support for the Freescale Elo and Elo Plus DMA controllers.
- The Elo is the DMA controller on some 82xx and 83xx parts, and the
- Elo Plus is the DMA controller on 85xx and 86xx parts.
+ Enable support for the Freescale Elo series DMA controllers.
+ The Elo is the DMA controller on some mpc82xx and mpc83xx parts, the
+ EloPlus is on mpc85xx and mpc86xx and Pxxx parts, and the Elo3 is on
+ some Txxx and Bxxx parts.
config MPC512X_DMA
tristate Freescale MPC512x built-in DMA engine support
diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c
index 49e8fbd..16a9a48 100644
--- a/drivers/dma/fsldma.c
+++ b/drivers/dma/fsldma.c
@@ -1261,7 +1261,9 @@ static int fsl_dma_chan_probe(struct fsldma_device *fdev,
WARN_ON(fdev-feature != chan-feature);
chan-dev = fdev-dev;
- chan-id = ((res.start - 0x100) 0xfff) 7;
+ chan-id = (res.start 0xfff) 0x300 ?
+ ((res.start - 0x100) 0xfff) 7 :
+ ((res.start - 0x200) 0xfff) 7;
if (chan-id = FSL_DMA_MAX_CHANS_PER_DEVICE) {
dev_err(fdev-dev, too many channels for device\n);
err = -EINVAL;
@@ -1434,6 +1436,7 @@ static int fsldma_of_remove(struct platform_device *op)
}
static const struct of_device_id fsldma_of_ids[] = {
+ { .compatible = fsl,elo3-dma, },
{ .compatible = fsl,eloplus-dma, },
{ .compatible = fsl,elo-dma, },
{}
@@ -1455,7 +1458,7 @@ static struct platform_driver fsldma_of_driver = {
static __init int fsldma_init(void)
{
- pr_info(Freescale Elo / Elo Plus DMA driver\n);
+ pr_info(Freescale Elo series DMA driver\n);
return platform_driver_register(fsldma_of_driver);
}
@@ -1467,5 +1470,5 @@ static void __exit fsldma_exit(void)
subsys_initcall(fsldma_init);
module_exit(fsldma_exit);
-MODULE_DESCRIPTION(Freescale Elo / Elo Plus DMA driver);
+MODULE_DESCRIPTION(Freescale Elo series DMA driver);
MODULE_LICENSE(GPL);
diff --git a/drivers/dma/fsldma.h b/drivers/dma/fsldma.h
index f5c3879..1ffc244 100644
--- a/drivers/dma/fsldma.h
+++ b/drivers/dma/fsldma.h
@@ -112,7 +112,7 @@ struct fsldma_chan_regs {
};
struct fsldma_chan;
-#define FSL_DMA_MAX_CHANS_PER_DEVICE 4
+#define FSL_DMA_MAX_CHANS_PER_DEVICE 8
struct fsldma_device {
void __iomem *regs; /* DGSR register base */
--
1.7.9.5
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Re: [PATCH 8/8][v4] powerpc/perf: Export Power7 memory hierarchy info to user space.
On 09/14/2013 06:19 AM, Sukadev Bhattiprolu wrote: On Power7, the DCACHE_SRC field in MMCRA register identifies the memory hierarchy level (eg: L2, L3 etc) from which a data-cache miss for a marked instruction was satisfied. Use the 'perf_mem_data_src' object to export this hierarchy level to user space. Some memory hierarchy levels in Power7 don't map into the arch-neutral levels. However, since newer generation of the processor (i.e. Power8) uses fewer levels than in Power7, we don't really need to define new hierarchy levels just for Power7. We instead, map as many levels as possible and approximate the rest. See comments near dcache-src_map[] in the patch. Usage: perf record -d -e 'cpu/PM_MRK_GRP_CMPL/' application perf report -n --mem-mode --sort=mem,sym,dso,symbol_daddr,dso_daddr For samples involving load/store instructions, the memory hierarchy level is shown as L1 hit, Remote RAM hit etc. # or perf record --data application perf report -D Sample records contain a 'data_src' field which encodes the memory hierarchy level: Eg: data_src 0x442 indicates MEM_OP_LOAD, MEM_LVL_HIT, MEM_LVL_L2 (i.e load hit L2). Successfully built and boot tested this entire patchset both on a P7 and P8 system. Running some sample tests with ebizzy micro benchmark. Till now got only 0x142 and 0x0 values for data_src object for the sample records. Will experiment around bit more on P7 and P8 systems and post the results. Regards Anshuman ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 0/2] move of_find_next_cache_node to DT core
From: Sudeep KarkadaNagesha sudeep.karkadanage...@arm.com Hi, The cache bindings are generic and used by many other architectures apart from PPC. These patches fixes and move the existing definition of of_find_next_cache_node to DT common code. Regards, Sudeep Sudeep KarkadaNagesha (2): powerpc: remove big endianness assumption in of_find_next_cache_node of: move definition of of_find_next_cache_node into common code. arch/powerpc/include/asm/prom.h | 3 --- arch/powerpc/kernel/prom.c | 31 --- drivers/of/base.c | 31 +++ include/linux/of.h | 2 ++ 4 files changed, 33 insertions(+), 34 deletions(-) -- 1.8.1.2 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 1/2] powerpc: remove big endianness assumption in of_find_next_cache_node
From: Sudeep KarkadaNagesha sudeep.karkadanage...@arm.com Currently big endianness of the device tree data is assumed in of_find_next_cache_node for 'handle' when calling of_find_node_by_phandle. In preparation to move this function to common code, this patch fixes the endianness using 'be32_to_cpup' Cc: Benjamin Herrenschmidt b...@kernel.crashing.org Cc: Grant Likely grant.lik...@linaro.org Cc: Rob Herring rob.herr...@calxeda.com Signed-off-by: Sudeep KarkadaNagesha sudeep.karkadanage...@arm.com --- arch/powerpc/kernel/prom.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/powerpc/kernel/prom.c b/arch/powerpc/kernel/prom.c index b7634ce..09be275 100644 --- a/arch/powerpc/kernel/prom.c +++ b/arch/powerpc/kernel/prom.c @@ -778,7 +778,7 @@ struct device_node *of_find_next_cache_node(struct device_node *np) handle = of_get_property(np, next-level-cache, NULL); if (handle) - return of_find_node_by_phandle(*handle); + return of_find_node_by_phandle(be32_to_cpup(handle)); /* OF on pmac has nodes instead of properties named l2-cache * beneath CPU nodes. -- 1.8.1.2 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 2/2] of: move definition of of_find_next_cache_node into common code.
From: Sudeep KarkadaNagesha sudeep.karkadanage...@arm.com
Since the definition of_find_next_cache_node is architecture independent,
the existing definition in powerpc can be moved to driver/of/base.c
Cc: Benjamin Herrenschmidt b...@kernel.crashing.org
Cc: Grant Likely grant.lik...@linaro.org
Cc: Rob Herring rob.herr...@calxeda.com
Signed-off-by: Sudeep KarkadaNagesha sudeep.karkadanage...@arm.com
---
arch/powerpc/include/asm/prom.h | 3 ---
arch/powerpc/kernel/prom.c | 31 ---
drivers/of/base.c | 31 +++
include/linux/of.h | 2 ++
4 files changed, 33 insertions(+), 34 deletions(-)
diff --git a/arch/powerpc/include/asm/prom.h b/arch/powerpc/include/asm/prom.h
index 7d0c7f3..bf09e5a 100644
--- a/arch/powerpc/include/asm/prom.h
+++ b/arch/powerpc/include/asm/prom.h
@@ -44,9 +44,6 @@ void of_parse_dma_window(struct device_node *dn, const __be32
*dma_window,
extern void kdump_move_device_tree(void);
-/* cache lookup */
-struct device_node *of_find_next_cache_node(struct device_node *np);
-
#ifdef CONFIG_NUMA
extern int of_node_to_nid(struct device_node *device);
#else
diff --git a/arch/powerpc/kernel/prom.c b/arch/powerpc/kernel/prom.c
index 09be275..4432fd8 100644
--- a/arch/powerpc/kernel/prom.c
+++ b/arch/powerpc/kernel/prom.c
@@ -761,37 +761,6 @@ void __init early_init_devtree(void *params)
***/
/**
- * of_find_next_cache_node - Find a node's subsidiary cache
- * @np:node of type cpu or cache
- *
- * Returns a node pointer with refcount incremented, use
- * of_node_put() on it when done. Caller should hold a reference
- * to np.
- */
-struct device_node *of_find_next_cache_node(struct device_node *np)
-{
- struct device_node *child;
- const phandle *handle;
-
- handle = of_get_property(np, l2-cache, NULL);
- if (!handle)
- handle = of_get_property(np, next-level-cache, NULL);
-
- if (handle)
- return of_find_node_by_phandle(be32_to_cpup(handle));
-
- /* OF on pmac has nodes instead of properties named l2-cache
-* beneath CPU nodes.
-*/
- if (!strcmp(np-type, cpu))
- for_each_child_of_node(np, child)
- if (!strcmp(child-type, cache))
- return child;
-
- return NULL;
-}
-
-/**
* of_get_ibm_chip_id - Returns the IBM chip-id of a device
* @np: device node of the device
*
diff --git a/drivers/of/base.c b/drivers/of/base.c
index 865d3f6..b2cee3d 100644
--- a/drivers/of/base.c
+++ b/drivers/of/base.c
@@ -1884,3 +1884,34 @@ int of_device_is_stdout_path(struct device_node *dn)
return of_stdout == dn;
}
EXPORT_SYMBOL_GPL(of_device_is_stdout_path);
+
+/**
+ * of_find_next_cache_node - Find a node's subsidiary cache
+ * @np:node of type cpu or cache
+ *
+ * Returns a node pointer with refcount incremented, use
+ * of_node_put() on it when done. Caller should hold a reference
+ * to np.
+ */
+struct device_node *of_find_next_cache_node(const struct device_node *np)
+{
+ struct device_node *child;
+ const phandle *handle;
+
+ handle = of_get_property(np, l2-cache, NULL);
+ if (!handle)
+ handle = of_get_property(np, next-level-cache, NULL);
+
+ if (handle)
+ return of_find_node_by_phandle(be32_to_cpup(handle));
+
+ /* OF on pmac has nodes instead of properties named l2-cache
+* beneath CPU nodes.
+*/
+ if (!strcmp(np-type, cpu))
+ for_each_child_of_node(np, child)
+ if (!strcmp(child-type, cache))
+ return child;
+
+ return NULL;
+}
diff --git a/include/linux/of.h b/include/linux/of.h
index f95aee3..c08c07e 100644
--- a/include/linux/of.h
+++ b/include/linux/of.h
@@ -226,6 +226,8 @@ static inline int of_get_child_count(const struct
device_node *np)
return num;
}
+/* cache lookup */
+extern struct device_node *of_find_next_cache_node(const struct device_node *);
extern struct device_node *of_find_node_with_property(
struct device_node *from, const char *prop_name);
#define for_each_node_with_property(dn, prop_name) \
--
1.8.1.2
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[PATCH 1/2] pci: fsl: derive the common PCI driver to drivers/pci/host
The Freescale's Layerscape series processors will use ARM cores.
The LS1's PCIe controllers is the same as T4240's. So it's better
the PCIe controller driver can support PowerPC and ARM
simultaneously. This patch is for this purpose. It derives
the common functions from arch/powerpc/sysdev/fsl_pci.c to
drivers/pci/host/pci-fsl.c and leaves the architecture-specific
functions which should be implemented in arch related files.
Signed-off-by: Minghuan Lian minghuan.l...@freescale.com
---
Based on upstream master.
Based on the discussion of RFC version here
http://patchwork.ozlabs.org/patch/274487/
arch/powerpc/sysdev/fsl_pci.c | 521 +-
arch/powerpc/sysdev/fsl_pci.h | 89
.../sysdev/fsl_pci.c = drivers/pci/host/pci-fsl.c | 591 +
.../sysdev/fsl_pci.h = include/linux/fsl/pci.h| 45 +-
4 files changed, 7 insertions(+), 1239 deletions(-)
copy arch/powerpc/sysdev/fsl_pci.c = drivers/pci/host/pci-fsl.c (54%)
copy arch/powerpc/sysdev/fsl_pci.h = include/linux/fsl/pci.h (79%)
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index ccfb50d..a189ff0 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -27,6 +27,7 @@
#include linux/log2.h
#include linux/slab.h
#include linux/uaccess.h
+#include linux/fsl/pci.h
#include asm/io.h
#include asm/prom.h
@@ -58,57 +59,8 @@ static void quirk_fsl_pcie_header(struct pci_dev *dev)
return;
}
-static int fsl_indirect_read_config(struct pci_bus *, unsigned int,
- int, int, u32 *);
-
-static int fsl_pcie_check_link(struct pci_controller *hose)
-{
- u32 val = 0;
-
- if (hose-indirect_type PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK) {
- if (hose-ops-read == fsl_indirect_read_config) {
- struct pci_bus bus;
- bus.number = hose-first_busno;
- bus.sysdata = hose;
- bus.ops = hose-ops;
- indirect_read_config(bus, 0, PCIE_LTSSM, 4, val);
- } else
- early_read_config_dword(hose, 0, 0, PCIE_LTSSM, val);
- if (val PCIE_LTSSM_L0)
- return 1;
- } else {
- struct ccsr_pci __iomem *pci = hose-private_data;
- /* for PCIe IP rev 3.0 or greater use CSR0 for link state */
- val = (in_be32(pci-pex_csr0) PEX_CSR0_LTSSM_MASK)
-PEX_CSR0_LTSSM_SHIFT;
- if (val != PEX_CSR0_LTSSM_L0)
- return 1;
- }
-
- return 0;
-}
-
-static int fsl_indirect_read_config(struct pci_bus *bus, unsigned int devfn,
- int offset, int len, u32 *val)
-{
- struct pci_controller *hose = pci_bus_to_host(bus);
-
- if (fsl_pcie_check_link(hose))
- hose-indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
- else
- hose-indirect_type = ~PPC_INDIRECT_TYPE_NO_PCIE_LINK;
-
- return indirect_read_config(bus, devfn, offset, len, val);
-}
-
#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
-static struct pci_ops fsl_indirect_pcie_ops =
-{
- .read = fsl_indirect_read_config,
- .write = indirect_write_config,
-};
-
#define MAX_PHYS_ADDR_BITS 40
static u64 pci64_dma_offset = 1ull MAX_PHYS_ADDR_BITS;
@@ -132,291 +84,6 @@ static int fsl_pci_dma_set_mask(struct device *dev, u64
dma_mask)
return 0;
}
-static int setup_one_atmu(struct ccsr_pci __iomem *pci,
- unsigned int index, const struct resource *res,
- resource_size_t offset)
-{
- resource_size_t pci_addr = res-start - offset;
- resource_size_t phys_addr = res-start;
- resource_size_t size = resource_size(res);
- u32 flags = 0x80044000; /* enable mem R/W */
- unsigned int i;
-
- pr_debug(PCI MEM resource start 0x%016llx, size 0x%016llx.\n,
- (u64)res-start, (u64)size);
-
- if (res-flags IORESOURCE_PREFETCH)
- flags |= 0x1000; /* enable relaxed ordering */
-
- for (i = 0; size 0; i++) {
- unsigned int bits = min(ilog2(size),
- __ffs(pci_addr | phys_addr));
-
- if (index + i = 5)
- return -1;
-
- out_be32(pci-pow[index + i].potar, pci_addr 12);
- out_be32(pci-pow[index + i].potear, (u64)pci_addr 44);
- out_be32(pci-pow[index + i].powbar, phys_addr 12);
- out_be32(pci-pow[index + i].powar, flags | (bits - 1));
-
- pci_addr += (resource_size_t)1U bits;
- phys_addr += (resource_size_t)1U bits;
- size -= (resource_size_t)1U bits;
- }
-
- return i;
-}
-
-/* atmu setup for fsl pci/pcie controller */
-static void setup_pci_atmu(struct pci_controller *hose)
-{
-
[PATCH 2/2] pci: fsl: rework PCI driver compatible with Layerscape
The Freescale's Layerscape series processors will use the same PCI
controller but change cores from PowerPC to ARM. This patch is to
rework FSL PCI driver to support PowerPC and ARM simultaneously.
PowerPC uses structure pci_controller to describe PCI controller,
but arm uses structure hw_pci and pci_sys_data. They also have
different architecture implementation and initialization flow.
The architecture-dependent driver will bridge the gap, get the
settings from the common driver and initialize the corresponding
structure and call the related interface to register PCI controller.
The common driver pci-fsl.c removes all the architecture-specific
code and provides structure fsl_pci to store all the controller
settings and the common functionalities that include reading/writing
PCI configuration space, parsing dts node and getting the MEM/IO and
bus number ranges, setting ATMU and check link status.
Signed-off-by: Minghuan Lian minghuan.l...@freescale.com
---
Based on upstream master
Based on the discussion of RFC version here
http://patchwork.ozlabs.org/patch/274488/
The function has been tested on MPC8315ERDB MPC8572DS P5020DS P3041DS
and T4240QDS boards
arch/powerpc/Kconfig | 1 +
arch/powerpc/sysdev/fsl_pci.c | 147 +-
drivers/edac/mpc85xx_edac.c | 16 +-
drivers/pci/host/Kconfig | 7 +
drivers/pci/host/Makefile | 1 +
drivers/pci/host/pci-fsl.c| 653 +++---
include/linux/fsl/pci.h | 69 +
7 files changed, 653 insertions(+), 241 deletions(-)
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 38f3b7e..6fd6348 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -690,6 +690,7 @@ config FSL_SOC
config FSL_PCI
bool
+ select PCI_FSL if FSL_SOC_BOOKE || PPC_86xx
select PPC_INDIRECT_PCI
select PCI_QUIRKS
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index a189ff0..1413257 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -62,7 +62,11 @@ static void quirk_fsl_pcie_header(struct pci_dev *dev)
#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
#define MAX_PHYS_ADDR_BITS 40
-static u64 pci64_dma_offset = 1ull MAX_PHYS_ADDR_BITS;
+
+u64 fsl_arch_pci64_dma_offset(void)
+{
+ return 1ull MAX_PHYS_ADDR_BITS;
+}
static int fsl_pci_dma_set_mask(struct device *dev, u64 dma_mask)
{
@@ -77,17 +81,43 @@ static int fsl_pci_dma_set_mask(struct device *dev, u64
dma_mask)
if ((dev-bus == pci_bus_type)
dma_mask = DMA_BIT_MASK(MAX_PHYS_ADDR_BITS)) {
set_dma_ops(dev, dma_direct_ops);
- set_dma_offset(dev, pci64_dma_offset);
+ set_dma_offset(dev, fsl_arch_pci64_dma_offset());
}
*dev-dma_mask = dma_mask;
return 0;
}
+struct fsl_pci *fsl_arch_sys_to_pci(void *sys)
+{
+ struct pci_controller *hose = sys;
+ struct fsl_pci *pci = hose-private_data;
+
+ /* Update the first bus number */
+ if (pci-first_busno != hose-first_busno)
+ pci-first_busno = hose-first_busno;
+
+ return pci;
+}
+
+struct pci_bus *fsl_arch_fake_pci_bus(struct fsl_pci *pci, int busnr)
+{
+ static struct pci_bus bus;
+ static struct pci_controller hose;
+
+ bus.number = busnr;
+ bus.sysdata = hose;
+ hose.private_data = pci;
+ bus.ops = pci-ops;
+
+ return bus;
+}
+
void fsl_pcibios_fixup_bus(struct pci_bus *bus)
{
struct pci_controller *hose = pci_bus_to_host(bus);
- int i, is_pcie = 0, no_link;
+ int i, is_pcie, no_link;
+ struct fsl_pci *pci = fsl_arch_sys_to_pci(hose);
/* The root complex bridge comes up with bogus resources,
* we copy the PHB ones in.
@@ -97,9 +127,8 @@ void fsl_pcibios_fixup_bus(struct pci_bus *bus)
* tricky.
*/
- if (fsl_pcie_bus_fixup)
- is_pcie = early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP);
- no_link = !!(hose-indirect_type PPC_INDIRECT_TYPE_NO_PCIE_LINK);
+ is_pcie = pci-is_pcie;
+ no_link = fsl_pci_check_link(pci);
if (bus-parent == hose-bus (is_pcie || no_link)) {
for (i = 0; i PCI_BRIDGE_RESOURCE_NUM; ++i) {
@@ -121,6 +150,94 @@ void fsl_pcibios_fixup_bus(struct pci_bus *bus)
}
}
+int fsl_arch_pci_exclude_device(struct fsl_pci *pci, u8 bus, u8 devfn)
+{
+ struct pci_controller *hose = pci-sys;
+
+ if (!hose)
+ return PCIBIOS_SUCCESSFUL;
+
+ if (ppc_md.pci_exclude_device)
+ if (ppc_md.pci_exclude_device(hose, bus, devfn))
+ return PCIBIOS_DEVICE_NOT_FOUND;
+
+ return PCIBIOS_SUCCESSFUL;
+}
+
+int fsl_arch_pci_sys_register(struct fsl_pci *pci)
+{
+ struct pci_controller *hose;
+
+ pci_add_flags(PCI_REASSIGN_ALL_BUS);
+ hose = pcibios_alloc_controller(pci-dn);
+ if (!hose)
+
[PATCH v2 01/10] of/irq: Rework of_irq_count()
The of_irq_to_resource() helper that is used to implement of_irq_count()
tries to resolve interrupts and in fact creates a mapping for resolved
interrupts. That's pretty heavy lifting for something that claims to
just return the number of interrupts requested by a given device node.
Instead, use the more lightweight of_irq_map_one(), which, despite the
name, doesn't create an actual mapping. Perhaps a better name would be
of_irq_translate_one().
Signed-off-by: Thierry Reding tred...@nvidia.com
---
drivers/of/irq.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/of/irq.c b/drivers/of/irq.c
index 1752988..5f44388 100644
--- a/drivers/of/irq.c
+++ b/drivers/of/irq.c
@@ -368,9 +368,10 @@ EXPORT_SYMBOL_GPL(of_irq_to_resource);
*/
int of_irq_count(struct device_node *dev)
{
+ struct of_irq irq;
int nr = 0;
- while (of_irq_to_resource(dev, nr, NULL))
+ while (of_irq_map_one(dev, nr, irq) == 0)
nr++;
return nr;
--
1.8.4
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[PATCH v2 00/10] of/irq: Defer interrupt reference resolution
Hi, This small series allows interrupt references from the device tree to be resolved at driver probe time, rather than at device creation time. The current implementation resolves such references while devices are added during the call to of_platform_populate(), which happens very early in the boot process. This causes probe ordering issues, because all devices that are an interrupt parent for other devices need to have been probed by that time. This is worked around for primary interrupt controllers by initializing them using a device tree specific way (of_irq_init()), but it doesn't work for something like a GPIO controller that is itself a platform device and an interrupt parent for other devices at the same time. Currently such drivers use explicit initcall ordering to force these chips to be probed earlier than other devices, but that only fixes a subset of the problematic cases. It doesn't work if the interrupt user is itself a platform device on the same bus. There are possibly other cases where it doesn't work either. This patch series attempts to fix this by not resolving the interrupt references at device creation time. Instead, some functionality is added to the driver core to resolve them for each device immediately before it is probed. Often this is a lot later than the point at which the device was created, which gives interrupt parents more time and therefore a better chance of being probed. More importantly, however, it allows the driver core to detect when an interrupt parent isn't there yet and cause the device to be queued for deferred probing. After all, resolving probe ordering issues is one of the primary reason for the introduction of deferred probing. Unfortunately the interrupt core code isn't prepared to handle this very well, so some preparatory work is required. Patches 1 and 2 are cleanup. Patch 1 modifies of_irq_count() to not use the heavyweight of_irq_to_resource(), which will actually try to create a mapping. While not usually harmful, it causes a warning during boot if the interrupt parent hasn't registered an IRQ domain yet. Furthermore it is much more than the stated intention of the function, which is to return the number of interrupts that a device node uses. Various uses of the of_irq_to_resource() function are replaced by more simpler versions using irq_of_parse_and_map() in patch 2. Patches 3 introduces the __irq_create_mapping() function, equivalent to its non-__ counterpart except that it returns a negative error code on failure and therefore allows propagation of a precise error code instead of 0 for all errors. This is an important prerequisite for subsequent patches. I would've preferred not to introduce an underscore-prefixed variant but there are about 114 callers and updating them all would've been rather messy. Patch 4 updates irq_create_of_mapping() to return a negative error code on failure instead of 0. The number of the mapped interrupt is returned in an output parameter. All callers of this function are updated. Patch 5 adds an __-prefixed variant of irq_of_parse_and_map() which returns a negative error code on failure instead of 0. The number of the mapped interrupt is returned in an output parameter. Patch 6 modifies of_irq_to_resource() to return a negative error code on failure (so that error can be propagated) and updates all callers. Patch 7 propagates errors from of_irq_to_resource() to users of the of_irq_to_resource_table() function. Patch 8 adds functionality to the platform driver code to resolve interrupt references at probe time. It uses the negative error code of the of_irq_to_resource_table() function to trigger deferred probing. Patch 9 implements similar functionality for I2C devices. Patch 10 serves as an example of the kind of cleanup that can be done after this series. Obviously this will require quite a bit of retesting of working setups, but I think that in the long run we're better off without the kind of explicit probe ordering employed by the gpio-tegra driver and many others. Note that I've only implemented this for platform and I2C devices, but the same can be done for SPI and possibly other subsystems as well. There is another use-case that I'm aware of for which a similar solution could be implemented. IOMMUs on SoCs generally need to hook themselves up to new platform devices. This causes a similar issues as interrupt resolution and should be fixable by extending the of_platform_probe() function introduced in patch 7 of this series. Changes in v2: - use more consistent naming and calling conventions - use less wrappers, update more callers - make of_platform_probe() idempotent The initial version of this patch series can be found here: https://lkml.org/lkml/2013/9/16/111 Thierry Thierry Reding (10): of/irq: Rework of_irq_count() of/irq: Use irq_of_parse_and_map() irqdomain: Introduce __irq_create_mapping() irqdomain: Return errors from irq_create_of_mapping() of/irq: Introduce
[PATCH v2 02/10] of/irq: Use irq_of_parse_and_map()
Replace some instances of of_irq_map_one()/irq_create_of_mapping() and
of_irq_to_resource() by the simpler equivalent irq_of_parse_and_map().
Signed-off-by: Thierry Reding tred...@nvidia.com
---
arch/arm/mach-u300/timer.c | 9 -
arch/powerpc/platforms/cell/celleb_scc_pciex.c | 8 +++-
arch/powerpc/platforms/cell/spider-pic.c | 7 ++-
arch/powerpc/sysdev/fsl_gtm.c| 9 -
arch/powerpc/sysdev/mpic_msgr.c | 6 ++
drivers/crypto/caam/ctrl.c | 2 +-
drivers/crypto/caam/jr.c | 2 +-
drivers/crypto/omap-sham.c | 2 +-
drivers/i2c/busses/i2c-cpm.c | 2 +-
drivers/input/serio/xilinx_ps2.c | 7 ---
drivers/net/ethernet/arc/emac_main.c | 10 +-
drivers/net/ethernet/freescale/fs_enet/mac-fcc.c | 2 +-
drivers/net/ethernet/freescale/fs_enet/mac-fec.c | 2 +-
drivers/net/ethernet/freescale/fs_enet/mac-scc.c | 2 +-
drivers/spi/spi-fsl-espi.c | 6 +++---
drivers/tty/serial/cpm_uart/cpm_uart_core.c | 2 +-
16 files changed, 35 insertions(+), 43 deletions(-)
diff --git a/arch/arm/mach-u300/timer.c b/arch/arm/mach-u300/timer.c
index b5db207..9a5f9fb 100644
--- a/arch/arm/mach-u300/timer.c
+++ b/arch/arm/mach-u300/timer.c
@@ -358,8 +358,7 @@ static struct delay_timer u300_delay_timer;
*/
static void __init u300_timer_init_of(struct device_node *np)
{
- struct resource irq_res;
- int irq;
+ unsigned int irq;
struct clk *clk;
unsigned long rate;
@@ -368,11 +367,11 @@ static void __init u300_timer_init_of(struct device_node
*np)
panic(could not ioremap system timer\n);
/* Get the IRQ for the GP1 timer */
- irq = of_irq_to_resource(np, 2, irq_res);
- if (irq = 0)
+ irq = irq_of_parse_and_map(np, 2);
+ if (!irq)
panic(no IRQ for system timer\n);
- pr_info(U300 GP1 timer @ base: %p, IRQ: %d\n, u300_timer_base, irq);
+ pr_info(U300 GP1 timer @ base: %p, IRQ: %u\n, u300_timer_base, irq);
/* Clock the interrupt controller */
clk = of_clk_get(np, 0);
diff --git a/arch/powerpc/platforms/cell/celleb_scc_pciex.c
b/arch/powerpc/platforms/cell/celleb_scc_pciex.c
index 14be2bd..856ad64 100644
--- a/arch/powerpc/platforms/cell/celleb_scc_pciex.c
+++ b/arch/powerpc/platforms/cell/celleb_scc_pciex.c
@@ -486,8 +486,7 @@ static __init int celleb_setup_pciex(struct device_node
*node,
struct pci_controller *phb)
{
struct resource r;
- struct of_irq oirq;
- int virq;
+ unsigned int virq;
/* SMMIO registers; used inside this file */
if (of_address_to_resource(node, 0, r)) {
@@ -507,12 +506,11 @@ static __init int celleb_setup_pciex(struct device_node
*node,
phb-ops = scc_pciex_pci_ops;
/* internal interrupt handler */
- if (of_irq_map_one(node, 1, oirq)) {
+ virq = irq_of_parse_and_map(node, 1);
+ if (!virq) {
pr_err(PCIEXC:Failed to map irq\n);
goto error;
}
- virq = irq_create_of_mapping(oirq.controller, oirq.specifier,
-oirq.size);
if (request_irq(virq, pciex_handle_internal_irq,
0, pciex, (void *)phb)) {
pr_err(PCIEXC:Failed to request irq\n);
diff --git a/arch/powerpc/platforms/cell/spider-pic.c
b/arch/powerpc/platforms/cell/spider-pic.c
index 8e29944..1f72f4a 100644
--- a/arch/powerpc/platforms/cell/spider-pic.c
+++ b/arch/powerpc/platforms/cell/spider-pic.c
@@ -235,12 +235,9 @@ static unsigned int __init
spider_find_cascade_and_node(struct spider_pic *pic)
/* First, we check whether we have a real interrupts in the device
* tree in case the device-tree is ever fixed
*/
- struct of_irq oirq;
- if (of_irq_map_one(pic-host-of_node, 0, oirq) == 0) {
- virq = irq_create_of_mapping(oirq.controller, oirq.specifier,
-oirq.size);
+ virq = irq_of_parse_and_map(pic-host-of_node, 0);
+ if (virq)
return virq;
- }
/* Now do the horrible hacks */
tmp = of_get_property(pic-host-of_node, #interrupt-cells, NULL);
diff --git a/arch/powerpc/sysdev/fsl_gtm.c b/arch/powerpc/sysdev/fsl_gtm.c
index 0eb871c..dd0d5be 100644
--- a/arch/powerpc/sysdev/fsl_gtm.c
+++ b/arch/powerpc/sysdev/fsl_gtm.c
@@ -401,16 +401,15 @@ static int __init fsl_gtm_init(void)
gtm-clock = *clock;
for (i = 0; i ARRAY_SIZE(gtm-timers); i++) {
- int ret;
- struct resource irq;
+ unsigned int irq;
- ret = of_irq_to_resource(np, i, irq);
- if (ret == NO_IRQ) {
[PATCH v2 03/10] irqdomain: Introduce __irq_create_mapping()
This is a version of irq_create_mapping() that propagates the precise
error code instead of returning 0 for all errors. It will be used in
subsequent patches to allow further propagation of error codes.
To avoid code duplication, implement irq_create_mapping() as a wrapper
around the new __irq_create_mapping().
Signed-off-by: Thierry Reding tred...@nvidia.com
---
kernel/irq/irqdomain.c | 59 +-
1 file changed, 39 insertions(+), 20 deletions(-)
diff --git a/kernel/irq/irqdomain.c b/kernel/irq/irqdomain.c
index 706724e..d2a3b01 100644
--- a/kernel/irq/irqdomain.c
+++ b/kernel/irq/irqdomain.c
@@ -374,30 +374,21 @@ unsigned int irq_create_direct_mapping(struct irq_domain
*domain)
}
EXPORT_SYMBOL_GPL(irq_create_direct_mapping);
-/**
- * irq_create_mapping() - Map a hardware interrupt into linux irq space
- * @domain: domain owning this hardware interrupt or NULL for default domain
- * @hwirq: hardware irq number in that domain space
- *
- * Only one mapping per hardware interrupt is permitted. Returns a linux
- * irq number.
- * If the sense/trigger is to be specified, set_irq_type() should be called
- * on the number returned from that call.
- */
-unsigned int irq_create_mapping(struct irq_domain *domain,
- irq_hw_number_t hwirq)
+static int __irq_create_mapping(struct irq_domain *domain,
+ irq_hw_number_t hwirq, unsigned int *virqp)
{
- unsigned int hint;
- int virq;
+ unsigned int hint, virq;
+ int ret;
- pr_debug(irq_create_mapping(0x%p, 0x%lx)\n, domain, hwirq);
+ pr_debug(__irq_create_mapping(0x%p, 0x%lx, %p)\n, domain, hwirq,
+virqp);
/* Look for default domain if nececssary */
if (domain == NULL)
domain = irq_default_domain;
if (domain == NULL) {
WARN(1, %s(, %lx) called with NULL domain\n, __func__, hwirq);
- return 0;
+ return -ENODEV;
}
pr_debug(- using domain @%p\n, domain);
@@ -405,7 +396,11 @@ unsigned int irq_create_mapping(struct irq_domain *domain,
virq = irq_find_mapping(domain, hwirq);
if (virq) {
pr_debug(- existing mapping on virq %d\n, virq);
- return virq;
+
+ if (virqp)
+ *virqp = virq;
+
+ return 0;
}
/* Allocate a virtual interrupt number */
@@ -417,17 +412,41 @@ unsigned int irq_create_mapping(struct irq_domain *domain,
virq = irq_alloc_desc_from(1, of_node_to_nid(domain-of_node));
if (virq = 0) {
pr_debug(- virq allocation failed\n);
- return 0;
+ return virq ? : -ENOSPC;
}
- if (irq_domain_associate(domain, virq, hwirq)) {
+ ret = irq_domain_associate(domain, virq, hwirq);
+ if (ret) {
irq_free_desc(virq);
- return 0;
+ return ret;
}
pr_debug(irq %lu on domain %s mapped to virtual irq %u\n,
hwirq, of_node_full_name(domain-of_node), virq);
+ if (virqp)
+ *virqp = virq;
+
+ return 0;
+}
+/**
+ * irq_create_mapping() - Map a hardware interrupt into linux irq space
+ * @domain: domain owning this hardware interrupt or NULL for default domain
+ * @hwirq: hardware irq number in that domain space
+ *
+ * Only one mapping per hardware interrupt is permitted. Returns a linux
+ * irq number.
+ * If the sense/trigger is to be specified, set_irq_type() should be called
+ * on the number returned from that call.
+ */
+unsigned int irq_create_mapping(struct irq_domain *domain,
+ irq_hw_number_t hwirq)
+{
+ unsigned int virq;
+
+ if (__irq_create_mapping(domain, hwirq, virq))
+ return 0;
+
return virq;
}
EXPORT_SYMBOL_GPL(irq_create_mapping);
--
1.8.4
___
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[PATCH v2 04/10] irqdomain: Return errors from irq_create_of_mapping()
Instead of returning 0 for all errors, allow the precise error code to
be propagated. This will be used in subsequent patches to allow further
propagation of error codes.
The interrupt number corresponding to the new mapping is returned in an
output parameter so that the return value is reserved to signal success
(== 0) or failure ( 0).
Signed-off-by: Thierry Reding tred...@nvidia.com
---
Changes in v2:
- convert existing callers instead of using compatible wrapper
arch/arm/mach-integrator/pci_v3.c | 8 ++--
arch/microblaze/pci/pci-common.c | 6 --
arch/mips/pci/fixup-lantiq.c | 12 +++
arch/mips/pci/pci-rt3883.c | 9 +
arch/powerpc/kernel/pci-common.c | 7 +--
arch/powerpc/platforms/cell/celleb_scc_sio.c | 8 +---
arch/powerpc/platforms/cell/spu_manage.c | 6 +++---
arch/powerpc/platforms/fsl_uli1575.c | 7 +++
arch/powerpc/platforms/pseries/event_sources.c | 12 ++-
arch/x86/kernel/devicetree.c | 11 +-
drivers/pci/host/pci-mvebu.c | 9 +++--
include/linux/of_irq.h | 6 +++---
kernel/irq/irqdomain.c | 28 --
13 files changed, 78 insertions(+), 51 deletions(-)
diff --git a/arch/arm/mach-integrator/pci_v3.c
b/arch/arm/mach-integrator/pci_v3.c
index bef1005..aa0f867 100644
--- a/arch/arm/mach-integrator/pci_v3.c
+++ b/arch/arm/mach-integrator/pci_v3.c
@@ -847,8 +847,12 @@ static int __init pci_v3_map_irq_dt(const struct pci_dev
*dev, u8 slot, u8 pin)
return 0;
}
- return irq_create_of_mapping(oirq.controller, oirq.specifier,
-oirq.size);
+ ret = irq_create_of_mapping(oirq.controller, oirq.specifier,
+ oirq.size, virq);
+ if (ret)
+ return 0;
+
+ return virq;
}
static int __init pci_v3_dtprobe(struct platform_device *pdev,
diff --git a/arch/microblaze/pci/pci-common.c b/arch/microblaze/pci/pci-common.c
index 1b93bf0..80b6e0f 100644
--- a/arch/microblaze/pci/pci-common.c
+++ b/arch/microblaze/pci/pci-common.c
@@ -246,8 +246,10 @@ int pci_read_irq_line(struct pci_dev *pci_dev)
oirq.size, oirq.specifier[0], oirq.specifier[1],
of_node_full_name(oirq.controller));
- virq = irq_create_of_mapping(oirq.controller, oirq.specifier,
-oirq.size);
+ ret = irq_create_of_mapping(oirq.controller, oirq.specifier,
+ oirq.size, virq);
+ if (ret)
+ virq = 0;
}
if (!virq) {
pr_debug( Failed to map !\n);
diff --git a/arch/mips/pci/fixup-lantiq.c b/arch/mips/pci/fixup-lantiq.c
index 6c829df..dfe7bf1 100644
--- a/arch/mips/pci/fixup-lantiq.c
+++ b/arch/mips/pci/fixup-lantiq.c
@@ -26,15 +26,19 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
struct of_irq dev_irq;
- int irq;
+ unsigned int irq;
+ int err;
if (of_irq_map_pci(dev, dev_irq)) {
dev_err(dev-dev, trying to map irq for unknown slot:%d
pin:%d\n,
slot, pin);
return 0;
}
- irq = irq_create_of_mapping(dev_irq.controller, dev_irq.specifier,
- dev_irq.size);
- dev_info(dev-dev, SLOT:%d PIN:%d IRQ:%d\n, slot, pin, irq);
+ err = irq_create_of_mapping(dev_irq.controller, dev_irq.specifier,
+ dev_irq.size, irq);
+ if (err)
+ return 0;
+
+ dev_info(dev-dev, SLOT:%d PIN:%d IRQ:%u\n, slot, pin, irq);
return irq;
}
diff --git a/arch/mips/pci/pci-rt3883.c b/arch/mips/pci/pci-rt3883.c
index 95c9d41..79b49b5 100644
--- a/arch/mips/pci/pci-rt3883.c
+++ b/arch/mips/pci/pci-rt3883.c
@@ -584,8 +584,8 @@ err_put_intc_node:
int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
struct of_irq dev_irq;
+ unsigned int irq = 0;
int err;
- int irq;
err = of_irq_map_pci(dev, dev_irq);
if (err) {
@@ -594,11 +594,12 @@ int __init pcibios_map_irq(const struct pci_dev *dev, u8
slot, u8 pin)
return 0;
}
- irq = irq_create_of_mapping(dev_irq.controller,
+ err = irq_create_of_mapping(dev_irq.controller,
dev_irq.specifier,
- dev_irq.size);
+ dev_irq.size,
+ irq);
- if (irq == 0)
+ if (err)
pr_crit(pci %s: no irq found for pin %u\n,
pci_name((struct pci_dev *) dev), pin);
else
[PATCH v2 05/10] of/irq: Introduce __irq_of_parse_and_map()
This is a version of irq_of_parse_and_map() that propagates the precise
error code instead of returning 0 for all errors. It will be used in
subsequent patches to allow further propagation of error codes.
To avoid code duplication, implement irq_of_parse_and_map() as a static
inline wrapper around the new __irq_of_parse_and_map(). Note that this
is somewhat complicated by the fact that SPARC implement its own version
of irq_of_parse_and_map(). Make SPARC implement __irq_of_parse_and_map()
so that the static inline wrapper can be used on all platforms.
Signed-off-by: Thierry Reding tred...@nvidia.com
---
Changes in v2:
- rename of_irq_get() to __irq_of_parse_and_map()
arch/sparc/kernel/of_device_common.c | 12
drivers/of/irq.c | 18 --
include/linux/of_irq.h | 19 ++-
3 files changed, 34 insertions(+), 15 deletions(-)
diff --git a/arch/sparc/kernel/of_device_common.c
b/arch/sparc/kernel/of_device_common.c
index de199bf..a69559f 100644
--- a/arch/sparc/kernel/of_device_common.c
+++ b/arch/sparc/kernel/of_device_common.c
@@ -11,16 +11,20 @@
#include of_device_common.h
-unsigned int irq_of_parse_and_map(struct device_node *node, int index)
+int __irq_of_parse_and_map(struct device_node *node, unsigned int index,
+ unsigned int *virqp)
{
struct platform_device *op = of_find_device_by_node(node);
if (!op || index = op-archdata.num_irqs)
- return 0;
+ return !op ? -ENODEV : -EINVAL;
- return op-archdata.irqs[index];
+ if (virqp)
+ *virqp = op-archdata.irqs[index];
+
+ return 0;
}
-EXPORT_SYMBOL(irq_of_parse_and_map);
+EXPORT_SYMBOL(__irq_of_parse_and_map);
int of_address_to_resource(struct device_node *node, int index,
struct resource *r)
diff --git a/drivers/of/irq.c b/drivers/of/irq.c
index 5f44388..6ad46fd 100644
--- a/drivers/of/irq.c
+++ b/drivers/of/irq.c
@@ -27,24 +27,30 @@
#include linux/slab.h
/**
- * irq_of_parse_and_map - Parse and map an interrupt into linux virq space
+ * __irq_of_parse_and_map - Parse and map an interrupt into linux virq space
* @dev: Device node of the device whose interrupt is to be mapped
* @index: Index of the interrupt to map
+ * @virqp: Linux interrupt number filled by this function
*
* This function is a wrapper that chains of_irq_map_one() and
* irq_create_of_mapping() to make things easier to callers
+ *
+ * Returns 0 on success or a negative error code on failure.
*/
-unsigned int irq_of_parse_and_map(struct device_node *dev, int index)
+int __irq_of_parse_and_map(struct device_node *dev, unsigned int index,
+ unsigned int *virqp)
{
struct of_irq oirq;
+ int ret;
- if (of_irq_map_one(dev, index, oirq))
- return 0;
+ ret = of_irq_map_one(dev, index, oirq);
+ if (ret)
+ return ret;
return irq_create_of_mapping(oirq.controller, oirq.specifier,
-oirq.size);
+oirq.size, virqp);
}
-EXPORT_SYMBOL_GPL(irq_of_parse_and_map);
+EXPORT_SYMBOL_GPL(__irq_of_parse_and_map);
/**
* of_irq_find_parent - Given a device node, find its interrupt parent node
diff --git a/include/linux/of_irq.h b/include/linux/of_irq.h
index 138266d..11da949 100644
--- a/include/linux/of_irq.h
+++ b/include/linux/of_irq.h
@@ -11,11 +11,12 @@ struct of_irq;
#include linux/of.h
/*
- * irq_of_parse_and_map() is used by all OF enabled platforms; but SPARC
+ * __irq_of_parse_and_map() is used by all OF enabled platforms; but SPARC
* implements it differently. However, the prototype is the same for all,
* so declare it here regardless of the CONFIG_OF_IRQ setting.
*/
-extern unsigned int irq_of_parse_and_map(struct device_node *node, int index);
+extern int __irq_of_parse_and_map(struct device_node *node, unsigned int index,
+ unsigned int *virqp);
#if defined(CONFIG_OF_IRQ)
/**
@@ -78,10 +79,11 @@ extern void of_irq_init(const struct of_device_id *matches);
#endif /* CONFIG_OF_IRQ */
#else /* !CONFIG_OF */
-static inline unsigned int irq_of_parse_and_map(struct device_node *dev,
- int index)
+static inline int __irq_of_parse_and_map(struct device_node *dev,
+unsigned int index,
+unsigned int *virqp)
{
- return 0;
+ return -ENOSYS;
}
static inline void *of_irq_find_parent(struct device_node *child)
@@ -90,4 +92,11 @@ static inline void *of_irq_find_parent(struct device_node
*child)
}
#endif /* !CONFIG_OF */
+static inline unsigned int irq_of_parse_and_map(struct device_node *node,
+ unsigned int index)
+{
+ unsigned int irq;
+ return
[PATCH v2 06/10] of/irq: Return errors from of_irq_to_resource()
Update of_irq_to_resource() to return 0 on success and a negative error
code on failure. This allows the precise nature of the failure to be
determined in the caller and errors to be propagated appropriately.
While at it, make the index parameter unsigned. Accessing negative
indices is invalid, so we might as well enforce that by using the right
data type.
Signed-off-by: Thierry Reding tred...@nvidia.com
---
Changes in v2:
- convert existing callers instead of using compatible wrapper
arch/powerpc/platforms/83xx/mpc832x_rdb.c | 2 +-
drivers/net/ethernet/marvell/mv643xx_eth.c | 5 +++--
drivers/of/irq.c | 14 +++---
include/linux/of_irq.h | 2 +-
4 files changed, 16 insertions(+), 7 deletions(-)
diff --git a/arch/powerpc/platforms/83xx/mpc832x_rdb.c
b/arch/powerpc/platforms/83xx/mpc832x_rdb.c
index eff5baa..b198e73 100644
--- a/arch/powerpc/platforms/83xx/mpc832x_rdb.c
+++ b/arch/powerpc/platforms/83xx/mpc832x_rdb.c
@@ -89,7 +89,7 @@ static int __init of_fsl_spi_probe(char *type, char
*compatible, u32 sysclk,
goto err;
ret = of_irq_to_resource(np, 0, res[1]);
- if (ret == NO_IRQ)
+ if (ret)
goto err;
pdev = platform_device_alloc(mpc83xx_spi, i);
diff --git a/drivers/net/ethernet/marvell/mv643xx_eth.c
b/drivers/net/ethernet/marvell/mv643xx_eth.c
index 7fb5677..bd713bd 100644
--- a/drivers/net/ethernet/marvell/mv643xx_eth.c
+++ b/drivers/net/ethernet/marvell/mv643xx_eth.c
@@ -2489,9 +2489,10 @@ static int mv643xx_eth_shared_of_add_port(struct
platform_device *pdev,
ppd.shared = pdev;
memset(res, 0, sizeof(res));
- if (!of_irq_to_resource(pnp, 0, res)) {
+ ret = of_irq_to_resource(pnp, 0, res);
+ if (ret) {
dev_err(pdev-dev, missing interrupt on %s\n, pnp-name);
- return -EINVAL;
+ return ret;
}
if (of_property_read_u32(pnp, reg, ppd.port_number)) {
diff --git a/drivers/of/irq.c b/drivers/of/irq.c
index 6ad46fd..e4f38c0 100644
--- a/drivers/of/irq.c
+++ b/drivers/of/irq.c
@@ -341,10 +341,18 @@ EXPORT_SYMBOL_GPL(of_irq_map_one);
* @dev: pointer to device tree node
* @index: zero-based index of the irq
* @r: pointer to resource structure to return result into.
+ *
+ * Returns zero on success or a negative error code on failure.
*/
-int of_irq_to_resource(struct device_node *dev, int index, struct resource *r)
+int of_irq_to_resource(struct device_node *dev, unsigned int index,
+ struct resource *r)
{
- int irq = irq_of_parse_and_map(dev, index);
+ unsigned int irq;
+ int ret;
+
+ ret = __irq_of_parse_and_map(dev, index, irq);
+ if (ret)
+ return ret;
/* Only dereference the resource if both the
* resource and the irq are valid. */
@@ -364,7 +372,7 @@ int of_irq_to_resource(struct device_node *dev, int index,
struct resource *r)
r-name = name ? name : dev-full_name;
}
- return irq;
+ return 0;
}
EXPORT_SYMBOL_GPL(of_irq_to_resource);
diff --git a/include/linux/of_irq.h b/include/linux/of_irq.h
index 11da949..6d62b73 100644
--- a/include/linux/of_irq.h
+++ b/include/linux/of_irq.h
@@ -67,7 +67,7 @@ extern int of_irq_map_one(struct device_node *device, int
index,
extern int irq_create_of_mapping(struct device_node *controller,
const u32 *intspec, unsigned int intsize,
unsigned int *virqp);
-extern int of_irq_to_resource(struct device_node *dev, int index,
+extern int of_irq_to_resource(struct device_node *dev, unsigned int index,
struct resource *r);
extern int of_irq_count(struct device_node *dev);
extern int of_irq_to_resource_table(struct device_node *dev,
--
1.8.4
___
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https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v2 07/10] of/irq: Propagate errors in of_irq_to_resource_table()
Now that all helpers return precise error codes, this function can
propagate these errors to the caller properly.
Signed-off-by: Thierry Reding tred...@nvidia.com
---
Changes in v2:
- return 0 on success or a negative error code on failure
- convert callers to new calling convention
arch/mips/lantiq/irq.c | 2 +-
arch/mips/lantiq/xway/gptu.c | 6 --
drivers/of/irq.c | 14 --
drivers/tty/serial/lantiq.c | 2 +-
4 files changed, 14 insertions(+), 10 deletions(-)
diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c
index eb3e186..5bb7ee6 100644
--- a/arch/mips/lantiq/irq.c
+++ b/arch/mips/lantiq/irq.c
@@ -389,7 +389,7 @@ int __init icu_of_init(struct device_node *node, struct
device_node *parent)
ret = of_irq_to_resource_table(eiu_node,
ltq_eiu_irq, exin_avail);
- if (ret != exin_avail)
+ if (ret 0)
panic(failed to load external irq resources\n);
if (request_mem_region(res.start, resource_size(res),
diff --git a/arch/mips/lantiq/xway/gptu.c b/arch/mips/lantiq/xway/gptu.c
index 850821d..0c4b134 100644
--- a/arch/mips/lantiq/xway/gptu.c
+++ b/arch/mips/lantiq/xway/gptu.c
@@ -137,10 +137,12 @@ static int gptu_probe(struct platform_device *pdev)
{
struct clk *clk;
struct resource *res;
+ int ret;
- if (of_irq_to_resource_table(pdev-dev.of_node, irqres, 6) != 6) {
+ ret = of_irq_to_resource_table(pdev-dev.of_node, irqres, 6);
+ if (ret 0) {
dev_err(pdev-dev, Failed to get IRQ list\n);
- return -EINVAL;
+ return ret;
}
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
diff --git a/drivers/of/irq.c b/drivers/of/irq.c
index e4f38c0..6d7f824 100644
--- a/drivers/of/irq.c
+++ b/drivers/of/irq.c
@@ -397,18 +397,20 @@ int of_irq_count(struct device_node *dev)
* @res: array of resources to fill in
* @nr_irqs: the number of IRQs (and upper bound for num of @res elements)
*
- * Returns the size of the filled in table (up to @nr_irqs).
+ * Returns 0 on success or a negative error code on failure.
*/
int of_irq_to_resource_table(struct device_node *dev, struct resource *res,
int nr_irqs)
{
- int i;
+ int i, ret;
- for (i = 0; i nr_irqs; i++, res++)
- if (!of_irq_to_resource(dev, i, res))
- break;
+ for (i = 0; i nr_irqs; i++, res++) {
+ ret = of_irq_to_resource(dev, i, res);
+ if (ret 0)
+ return ret;
+ }
- return i;
+ return 0;
}
EXPORT_SYMBOL_GPL(of_irq_to_resource_table);
diff --git a/drivers/tty/serial/lantiq.c b/drivers/tty/serial/lantiq.c
index 88d01e0..e59efdc 100644
--- a/drivers/tty/serial/lantiq.c
+++ b/drivers/tty/serial/lantiq.c
@@ -686,7 +686,7 @@ lqasc_probe(struct platform_device *pdev)
mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
ret = of_irq_to_resource_table(node, irqres, 3);
- if (!mmres || (ret != 3)) {
+ if (!mmres || (ret 0)) {
dev_err(pdev-dev,
failed to get memory/irq for serial port\n);
return -ENODEV;
--
1.8.4
___
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[PATCH v2 09/10] of/i2c: Resolve interrupt references at probe time
Instead of resolving interrupt references at device creation time, delay
resolution until probe time. At device creation time, there is nothing
that can be done if an interrupt parent isn't ready yet, and the device
will end up with an invalid interrupt number (0).
If the interrupt reference is resolved at probe time, the device's probe
can be deferred, so that it's interrupt resolution can be retried after
more devices (possibly including its interrupt parent) have been probed.
However, individual drivers shouldn't be required to do that themselves,
over and over again, so this commit implements this functionality within
the I2C core.
Signed-off-by: Thierry Reding tred...@nvidia.com
---
Changes in v2:
- use __irq_of_parse_and_map() instead of of_irq_get()
drivers/i2c/i2c-core.c | 24 ++--
1 file changed, 22 insertions(+), 2 deletions(-)
diff --git a/drivers/i2c/i2c-core.c b/drivers/i2c/i2c-core.c
index 29d3f04..5b4f289 100644
--- a/drivers/i2c/i2c-core.c
+++ b/drivers/i2c/i2c-core.c
@@ -236,6 +236,22 @@ int i2c_recover_bus(struct i2c_adapter *adap)
return adap-bus_recovery_info-recover_bus(adap);
}
+static int of_i2c_probe(struct i2c_client *client)
+{
+ struct device_node *np = client-dev.of_node;
+ int ret;
+
+ /* skip if the device node specifies no interrupts */
+ if (of_get_property(np, interrupts, NULL)) {
+ ret = __irq_of_parse_and_map(client-dev.of_node, 0,
+client-irq);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
static int i2c_device_probe(struct device *dev)
{
struct i2c_client *client = i2c_verify_client(dev);
@@ -254,6 +270,12 @@ static int i2c_device_probe(struct device *dev)
client-flags I2C_CLIENT_WAKE);
dev_dbg(dev, probe\n);
+ if (IS_ENABLED(CONFIG_OF) dev-of_node) {
+ status = of_i2c_probe(client);
+ if (status)
+ return status;
+ }
+
status = driver-probe(client, i2c_match_id(driver-id_table, client));
if (status) {
client-driver = NULL;
@@ -1002,7 +1024,6 @@ static void of_i2c_register_devices(struct i2c_adapter
*adap)
continue;
}
- info.irq = irq_of_parse_and_map(node, 0);
info.of_node = of_node_get(node);
info.archdata = dev_ad;
@@ -1016,7 +1037,6 @@ static void of_i2c_register_devices(struct i2c_adapter
*adap)
dev_err(adap-dev, of_i2c: Failure registering %s\n,
node-full_name);
of_node_put(node);
- irq_dispose_mapping(info.irq);
continue;
}
}
--
1.8.4
___
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[PATCH v2 10/10] gpio: tegra: Use module_platform_driver()
With the driver core now resolving interrupt references at probe time,
it is no longer necessary to force explicit probe ordering using
initcalls.
Signed-off-by: Thierry Reding tred...@nvidia.com
---
Note that there are potentially many more drivers that can be switched
to the generic module_*_driver() interfaces now that interrupts can be
resolved later and deferred probe should be able to handle all the
ordering issues.
drivers/gpio/gpio-tegra.c | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/drivers/gpio/gpio-tegra.c b/drivers/gpio/gpio-tegra.c
index 9a62672..766e6ef 100644
--- a/drivers/gpio/gpio-tegra.c
+++ b/drivers/gpio/gpio-tegra.c
@@ -513,12 +513,7 @@ static struct platform_driver tegra_gpio_driver = {
},
.probe = tegra_gpio_probe,
};
-
-static int __init tegra_gpio_init(void)
-{
- return platform_driver_register(tegra_gpio_driver);
-}
-postcore_initcall(tegra_gpio_init);
+module_platform_driver(tegra_gpio_driver);
#ifdef CONFIG_DEBUG_FS
--
1.8.4
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mpc52xx_uart.c : Possible bug with TTY_OVERRUN and clear error condition?
First of all, sorry for my english (I'm spanish). At our company, we work in various projects in control systems and automation in industrial environment, mostly with embedded custom linux distributions with Freescale PowerPC processors (MPC5200b, MPC5125, P1022, MPC8536E...). In one of our systems, we have a MPC5125 connected with an ARM Cortex processor by serial port (ttyPSCX) using the standard mpc52xx_uart.c driver. Suddently we have encountered a situation in serial communicationes where all the incoming serial traffic has a '\0' in the end of each serial transmission. Looking at the driver in our custom 2.6.33.7 kernel, the insertion of the '\0' is in line 1308, on the Overrun condition(TTY_OVERRUN), but looking at the code, this flag is never cleared (as they arein the line 1297 in clear error condition)until there is some other error condition like TTY_BREAK, TTY_PARITY, TTY_FRAME. We have resolved thisissue adding a clear error condition after the overrun increment in port-icount.overrun++; but perhaps this is not the best solution(dirty hack). It has been discuted in http://linuxppc.10917.n7.nabble.com/mpc52xx-uart-c-Port-Overruns-td53175.html for kernel 2.6.24too. Maybe we can send you a patch for the next commit, or can anyone evaluate it for the next release? As we can see, this is happening in the latest release of the Linus kernel treetoo (3.11). Thank you. Regards, -- Carlos Crisóstomo Vals Operating System Design Director Product Development Arteche Smart-Grid Sistemas Avanzados de Control S.A. Colquide 6, Portal 2, 28230 Las Rozas - Madrid - Spain carlos_DOT_crisostomo_AT_sacnet_DOT_es www.sacnet.es www.arteche.com ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH v2 2/6] PCI/MSI: Factor out pci_get_msi_cap() interface
Hello, On Wed, Sep 18, 2013 at 11:48:00AM +0200, Alexander Gordeev wrote: On Wed, Sep 18, 2013 at 12:30:23AM +1000, Michael Ellerman wrote: How about no? We have a small number of MSIs available, limited by hardware firmware, if we don't impose a quota then the first device that probes will get most/all of the MSIs and other devices miss out. Out of curiosity - how pSeries has had done it without quotas before 448e2ca (powerpc/pseries: Implement a quota system for MSIs)? Hmmm... do we need to treat this any differently? If the platform can't allocate full range of requested MSIs, just failing should be enough regardless of why such allocation can't be met, no? Anyway I don't see what problem you're trying to solve? I agree the -ve/0/+ve return value pattern is ugly, but it's hardly the end of the world. Well, the interface recently has been re-classified from ugly to unnecessarily complex and actively harmful in Tejun's words ;) LOL. :) Indeed, I checked most of the drivers and it is incredible how people are creative in misusing the interface: from innocent pci_disable_msix() calls when if pci_enable_msix() failed to assuming MSI-Xs were enabled if pci_enable_msix() returned a positive value (apparently untested). Roughly third of the drivers just do not care and bail out once pci_enable_msix() has not succeeded. Not sure how many of these are mandated by the hardware. Yeah, I mean, this type of interface is a trap. People have to actively resist to avoid doing silly stuff which is a lot to ask. /* * Retrieving 'nvec' by means other than pci_msix_table_size() */ rc = pci_get_msix_limit(pdev); if (rc 0) return rc; /* * nvec = min(rc, nvec); */ for (i = 0; i nvec; i++) msix_entry[i].entry = i; rc = pci_enable_msix(pdev, msix_entry, nvec); if (rc) return rc; I really think what we should do is * Determine the number of MSIs the controller wants. Don't worry about quotas or limits or anything. Just determine the number necessary to enable enhanced interrupt handling. * Try allocating that number of MSIs. If it fails, then just revert to single interrupt mode. It's not the end of the world and mostly guaranteed to work. Let's please not even try to do partial multiple interrupts. I really don't think it's worth the risk or complexity. Thanks. -- tejun ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH v2 04/10] irqdomain: Return errors from irq_create_of_mapping()
On Wed, Sep 18, 2013 at 03:24:46PM +0200, Thierry Reding wrote: For the MIPS bits: Acked-by: Ralf Baechle r...@linux-mips.org Ralf ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH v2 07/10] of/irq: Propagate errors in of_irq_to_resource_table()
On Wed, Sep 18, 2013 at 03:24:49PM +0200, Thierry Reding wrote: For the MIPS bits: Acked-by: Ralf Baechle r...@linux-mips.org Ralf ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 0/2] move of_find_next_cache_node to DT core
On Wed, 18 Sep 2013 11:53:03 +0100, Sudeep KarkadaNagesha sudeep.karkadanage...@arm.com wrote: From: Sudeep KarkadaNagesha sudeep.karkadanage...@arm.com Hi, The cache bindings are generic and used by many other architectures apart from PPC. These patches fixes and move the existing definition of of_find_next_cache_node to DT common code. Regards, Sudeep Acked-by: Grant Likely grant.lik...@secretlab.ca However, do you have a user for this function on other architectures yet? I'd like to see a user for the function in the same patch series.. g. Sudeep KarkadaNagesha (2): powerpc: remove big endianness assumption in of_find_next_cache_node of: move definition of of_find_next_cache_node into common code. arch/powerpc/include/asm/prom.h | 3 --- arch/powerpc/kernel/prom.c | 31 --- drivers/of/base.c | 31 +++ include/linux/of.h | 2 ++ 4 files changed, 33 insertions(+), 34 deletions(-) -- 1.8.1.2 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 0/2] move of_find_next_cache_node to DT core
On 18/09/13 15:51, Grant Likely wrote: On Wed, 18 Sep 2013 11:53:03 +0100, Sudeep KarkadaNagesha sudeep.karkadanage...@arm.com wrote: From: Sudeep KarkadaNagesha sudeep.karkadanage...@arm.com Hi, The cache bindings are generic and used by many other architectures apart from PPC. These patches fixes and move the existing definition of of_find_next_cache_node to DT common code. Regards, Sudeep Acked-by: Grant Likely grant.lik...@secretlab.ca However, do you have a user for this function on other architectures yet? I'd like to see a user for the function in the same patch series.. Yes I have posted an RFC[1] following this series implementing cacheinfo for ARM similar to x86 implementation. I was not sure if it's good idea to combine it as its still initial RFC version. Regards, Sudeep [1] https://lkml.org/lkml/2013/9/18/340 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH v2 2/6] PCI/MSI: Factor out pci_get_msi_cap() interface
On Wed, Sep 18, 2013 at 09:22:31AM -0500, Tejun Heo wrote: We have a small number of MSIs available, limited by hardware firmware, if we don't impose a quota then the first device that probes will get most/all of the MSIs and other devices miss out. Out of curiosity - how pSeries has had done it without quotas before 448e2ca (powerpc/pseries: Implement a quota system for MSIs)? Hmmm... do we need to treat this any differently? If the platform can't allocate full range of requested MSIs, just failing should be enough regardless of why such allocation can't be met, no? That depends from what full range of requested MSIs is. If that is a maximum number of MSIs the controller advertised, then no. As MSI design essentially allows devices to operate in lower-than-maximum modes it is responsibility of a caller to decide how many vectors to request. So in case of pSeries I think it is completely legitimate to request lessers to overcome the platform limitation and let all devices work. I really think what we should do is * Determine the number of MSIs the controller wants. Don't worry about quotas or limits or anything. Just determine the number necessary to enable enhanced interrupt handling. Actually, I do not see much contradiction with what I proposed. The key words here determine the number of MSIs the controller wants. In general case it is not what pci_msix_table_size() returns (or at least we should not limit ourselves to it) - there could be non- standard means to report number of MSIs: hardcoded, version-dependant, device-specific registers etc. Next, if we opt to determine the number of MSIs by non-MSI standard means then there is no reason not to call pci_get_msix_limit() (or whatever) at this step. The question how I see it - do we want pci_get_msix_limit() interface as part of the MSI framework or do we want it pSeries-specific? * Try allocating that number of MSIs. If it fails, then just revert to single interrupt mode. It's not the end of the world and mostly guaranteed to work. Let's please not even try to do partial multiple interrupts. I really don't think it's worth the risk or complexity. Being Captain Obvious here, but it is up to the device driver to handle a failure. There could be no such option as single MSI mode after all :) Thanks. -- tejun -- Regards, Alexander Gordeev agord...@redhat.com ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] powerpc/mpc85xx:Add initial device tree support of T104x
On Mon, 2013-09-16 at 21:11 -0500, Kushwaha Prabhakar-B32579 wrote: -Original Message- From: Wood Scott-B07421 Sent: Tuesday, September 17, 2013 2:49 AM To: Kushwaha Prabhakar-B32579 Cc: Wood Scott-B07421; linuxppc-dev@lists.ozlabs.org; ga...@kernel.crashing.org; Aggrwal Poonam-B10812; Jain Priyanka-B32167; Sethi Varun-B16395 Subject: Re: [PATCH] powerpc/mpc85xx:Add initial device tree support of T104x On Fri, 2013-09-13 at 02:30 -0500, Kushwaha Prabhakar-B32579 wrote: I also question the need to define separate t1040 compatible values for all of these, if the only difference is whether the onboard switch is enabled or not. so should I use T104x as compatible field. and in T1040 device tree add extra node for l2 switch. I am using T1042 as base dts and T1040 includes T1040 + l2switch. so if I use T1042 in compatible. It will give wrong field for someone working on T1040QDS. What is wrong about it? It is compatible, right? -Scott ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH] Fixed typo on word accounting in kprobes.c in mutliple architectures
Signed-off-by: Anoop Thomas Mathew a...@profoundis.com --- arch/arc/kernel/kprobes.c |2 +- arch/ia64/kernel/kprobes.c|2 +- arch/powerpc/kernel/kprobes.c |2 +- arch/s390/kernel/kprobes.c|2 +- arch/sparc/kernel/kprobes.c |2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arc/kernel/kprobes.c b/arch/arc/kernel/kprobes.c index 72f9782..7446c8d 100644 --- a/arch/arc/kernel/kprobes.c +++ b/arch/arc/kernel/kprobes.c @@ -327,7 +327,7 @@ int __kprobes kprobe_fault_handler(struct pt_regs *regs, unsigned long trapnr) */ /* We increment the nmissed count for accounting, -* we can also use npre/npostfault count for accouting +* we can also use npre/npostfault count for accounting * these specific fault cases. */ kprobes_inc_nmissed_count(cur); diff --git a/arch/ia64/kernel/kprobes.c b/arch/ia64/kernel/kprobes.c index f8280a7..074fde4 100644 --- a/arch/ia64/kernel/kprobes.c +++ b/arch/ia64/kernel/kprobes.c @@ -947,7 +947,7 @@ int __kprobes kprobe_fault_handler(struct pt_regs *regs, int trapnr) case KPROBE_HIT_SSDONE: /* * We increment the nmissed count for accounting, -* we can also use npre/npostfault count for accouting +* we can also use npre/npostfault count for accounting * these specific fault cases. */ kprobes_inc_nmissed_count(cur); diff --git a/arch/powerpc/kernel/kprobes.c b/arch/powerpc/kernel/kprobes.c index 2156ea9..90fab64 100644 --- a/arch/powerpc/kernel/kprobes.c +++ b/arch/powerpc/kernel/kprobes.c @@ -429,7 +429,7 @@ int __kprobes kprobe_fault_handler(struct pt_regs *regs, int trapnr) case KPROBE_HIT_SSDONE: /* * We increment the nmissed count for accounting, -* we can also use npre/npostfault count for accouting +* we can also use npre/npostfault count for accounting * these specific fault cases. */ kprobes_inc_nmissed_count(cur); diff --git a/arch/s390/kernel/kprobes.c b/arch/s390/kernel/kprobes.c index 0ce9fb2..018c1c4 100644 --- a/arch/s390/kernel/kprobes.c +++ b/arch/s390/kernel/kprobes.c @@ -673,7 +673,7 @@ static int __kprobes kprobe_trap_handler(struct pt_regs *regs, int trapnr) case KPROBE_HIT_SSDONE: /* * We increment the nmissed count for accounting, -* we can also use npre/npostfault count for accouting +* we can also use npre/npostfault count for accounting * these specific fault cases. */ kprobes_inc_nmissed_count(p); diff --git a/arch/sparc/kernel/kprobes.c b/arch/sparc/kernel/kprobes.c index e722121..d3d5d38 100644 --- a/arch/sparc/kernel/kprobes.c +++ b/arch/sparc/kernel/kprobes.c @@ -349,7 +349,7 @@ int __kprobes kprobe_fault_handler(struct pt_regs *regs, int trapnr) case KPROBE_HIT_SSDONE: /* * We increment the nmissed count for accounting, -* we can also use npre/npostfault count for accouting +* we can also use npre/npostfault count for accounting * these specific fault cases. */ kprobes_inc_nmissed_count(cur); -- 1.7.9.5 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Linux 2.6.32 PowerPC MTD partition mounted at boot
I am working on bringing up two Linux systems, both based on Freescale PowerPC devices, one is a MPC8349, the other a P1020. I was able to build, install and boot the kernel on both cards. The kernel is 2.6.32 and the toolchains are coming from the LTIBs packages from Freescale. Both cards have a 32 MByte NOR flash memory (AMD) boot flash. I have Uboot, kernel, RAM disk image and DTB in the boot flash and I want to use the spare space (about 20 MBytes) as flash file system. I have the following problem : the P1020 board boots fine using the RAM disk with the flash in the device tree , shows the flash device partitions (JFFS2) and DOESNT try to mount a flash partition as root. The MPC8349 boots fine from the RAM disk but, after identifying the flash partitions, the kernel panics because is looking for a flash partition to mount as root partition and none of them is usable (not formatted). If I remove the flash from the device tree, the card boots fine using the RAM disk. I am not too familiar with Linux boot scripts and I didn't figure out where I can disable this tentative of mounting the MTD partition. I want the boards to boot and mount the RAM disk, as the P1020 board does. The flash partition will be initialized and mounted at a later time, but not as root partition. TIADorin ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
