Re: [PATCH 0/3] of: dts: enable memory@0 quirk for PPC32 only
On Fri, Apr 18, 2014 at 04:28:17PM -0500, Rob Herring wrote: > >> > Apart from the current code permitting recreating a 15+ year old > >> > firmware bug into completely new platform ports? > >> > >> I would prefer to see a "WARN_ON(!IS_ENABLED(CONFIG_PPC32));" added here. > > > > In addition to, or instead of, the QUIRK ifdef? > > Instead of because I don't see how you handle the ARM board > compatibility with the ifdef. (And please, no ifdef for that board). Umm, according to my memory as well as my sent mail folder, I cc:d you on v2 of part 3. Could you have a look at that, please? A WARN_ON would still mean this ancient workaround for a specific ppc32 platform remains enabled on ~10 architectures that don't use it. > >> Really, I would like to see quirks like this fixed up out of line from > >> the normal flow somewhat like how PCI quirks are handled. So in this > >> example, we would just add the missing property to the dtb for the > >> broken platform before doing the memory scan. That does then require > >> libfdt which is something I'm working on. > > > > Getting rid of all this handling from generic code would clearly be > > preferable. Is that code going in in the near future, or could we add > > the quirk as a stopgap? > > Some sort of quirk infrastructure is not going to happen soon. It's > just an idea bouncing in my head ATM. Mmm... > > What would be the effect of the UEFI code adding all its memblocks, > > minus the reserved areas, and then the DT code doing a memblock_add > > of all RAM (including reserved areas)? Would memblock_reserve()s on > > the protected regions suffice to prevent crazy stuff from happening? > > So use UEFI to add the memory, but then add reserved areas with DT? No, to add memory and reserved areas based on UEFI memory map. And then add any memory@0/!type nodes as well, if they're left around. > I'm not sure I follow, but even if I did I don't know memblock code > well enough to say what it would do. If we did end up with stray memory@0/!type nodes, we could initialise memblock multiple times with overlapping but incompatible areas. And I don't know if that would be a problem. Which makes me a little bit nervous. / Leif ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] powerpc/fsl: Updated device trees for platforms with corenet version 2
On Fri, 2014-04-18 at 18:21 +0300, Diana Craciun wrote: > From: Diana Craciun > > Updated the device trees according to the corenet-cf > binding definition. > > Signed-off-by: Diana Craciun > --- > arch/powerpc/boot/dts/b4860emu.dts | 2 +- > arch/powerpc/boot/dts/fsl/b4420si-post.dtsi | 4 > arch/powerpc/boot/dts/fsl/b4860si-post.dtsi | 4 > arch/powerpc/boot/dts/fsl/b4si-post.dtsi| 2 +- > arch/powerpc/boot/dts/fsl/t4240si-post.dtsi | 2 +- > arch/powerpc/boot/dts/t4240emu.dts | 2 +- > 6 files changed, 4 insertions(+), 12 deletions(-) Could you update the corenet version 1 trees as well? -Scott ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH v2] powerpc/fsl: Added binding for Freescale CoreNet coherency fabric (CCF)
On Fri, 2014-04-18 at 18:11 +0300, Diana Craciun wrote: > From: Diana Craciun > > The CoreNet coherency fabric is a fabric-oriented, conectivity > infrastructure that enables the implementation of coherent, multicore > systems. The CCF acts as a central interconnect for cores, > platform-level caches, memory subsystem, peripheral devices and I/O host > bridges in the system. > > Signed-off-by: Diana Craciun > --- > .../devicetree/bindings/powerpc/fsl/ccf.txt| 36 > ++ > 1 file changed, 36 insertions(+) > create mode 100644 Documentation/devicetree/bindings/powerpc/fsl/ccf.txt > > diff --git a/Documentation/devicetree/bindings/powerpc/fsl/ccf.txt > b/Documentation/devicetree/bindings/powerpc/fsl/ccf.txt > new file mode 100644 > index 000..f0b7143 > --- /dev/null > +++ b/Documentation/devicetree/bindings/powerpc/fsl/ccf.txt > @@ -0,0 +1,36 @@ > +Freescale CoreNet Coherency Fabric(CCF) Device Tree Binding > + > +DESCRIPTION > + > +The CoreNet coherency fabric is a fabric-oriented, connectivity > infrastructure > +that enables the implementation of coherent, multicore systems. > + > +Required properties: > + > +- compatible : > + Must include "fsl,corenetX-cf", "fsl,corenet-cf" - CoreNet > coherency > + fabric version X Specify "fsl,corenet1-cf" and "fsl,corenet2-cf" rather than "fsl,corenetX-cf" (given there's nothing in a chip manual that you can correlate with the value of X), and provide example chips for each. Also specify that "fsl,corenet-cf" represents the registers that are common between the two versions (not arbitrary "fsl,corenetX-cf" -- if there's ever an "fsl,corenet3-cf" it may not be compatible with this), and is retained for compatibility reasons. -Scott ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 0/3] of: dts: enable memory@0 quirk for PPC32 only
On Fri, Apr 18, 2014 at 3:13 PM, Leif Lindholm wrote: > On Fri, Apr 18, 2014 at 10:37:58AM -0500, Rob Herring wrote: >> >> But why do you need this? >> > >> > Apart from the current code permitting recreating a 15+ year old >> > firmware bug into completely new platform ports? >> >> I would prefer to see a "WARN_ON(!IS_ENABLED(CONFIG_PPC32));" added here. > > In addition to, or instead of, the QUIRK ifdef? Instead of because I don't see how you handle the ARM board compatibility with the ifdef. (And please, no ifdef for that board). >> Really, I would like to see quirks like this fixed up out of line from >> the normal flow somewhat like how PCI quirks are handled. So in this >> example, we would just add the missing property to the dtb for the >> broken platform before doing the memory scan. That does then require >> libfdt which is something I'm working on. > > Getting rid of all this handling from generic code would clearly be > preferable. Is that code going in in the near future, or could we add > the quirk as a stopgap? Some sort of quirk infrastructure is not going to happen soon. It's just an idea bouncing in my head ATM. >> > Because the UEFI stub for arm/arm64 needs to delete all of the "memory" >> > nodes from the DT. And it would be nice to at least not have to compile >> > the "and also delete anything called memory@0" into the arm64 image. Or >> > any image not including support for affected platforms. >> >> I don't see why you would handle that in the EFI stub. Given our lack >> of validation, I can see there is a chance this happens but I think it >> is pretty small. Given we only have a ARM board, I'd say we are doing >> surprisingly well. > > I'm not too bothered personally, but Mark Rutland handed me a patch to > improve the memory node handling in the stub, and he seemed to really > want this there. You guys can fight it out :) Simply put, we shouldn't put work-arounds in new code for new platforms. > What would be the effect of the UEFI code adding all its memblocks, > minus the reserved areas, and then the DT code doing a memblock_add > of all RAM (including reserved areas)? Would memblock_reserve()s on > the protected regions suffice to prevent crazy stuff from happening? So use UEFI to add the memory, but then add reserved areas with DT? I'm not sure I follow, but even if I did I don't know memblock code well enough to say what it would do. Rob ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 0/3] of: dts: enable memory@0 quirk for PPC32 only
On Fri, Apr 18, 2014 at 10:37:58AM -0500, Rob Herring wrote: > >> But why do you need this? > > > > Apart from the current code permitting recreating a 15+ year old > > firmware bug into completely new platform ports? > > I would prefer to see a "WARN_ON(!IS_ENABLED(CONFIG_PPC32));" added here. In addition to, or instead of, the QUIRK ifdef? > Really, I would like to see quirks like this fixed up out of line from > the normal flow somewhat like how PCI quirks are handled. So in this > example, we would just add the missing property to the dtb for the > broken platform before doing the memory scan. That does then require > libfdt which is something I'm working on. Getting rid of all this handling from generic code would clearly be preferable. Is that code going in in the near future, or could we add the quirk as a stopgap? > > Because the UEFI stub for arm/arm64 needs to delete all of the "memory" > > nodes from the DT. And it would be nice to at least not have to compile > > the "and also delete anything called memory@0" into the arm64 image. Or > > any image not including support for affected platforms. > > I don't see why you would handle that in the EFI stub. Given our lack > of validation, I can see there is a chance this happens but I think it > is pretty small. Given we only have a ARM board, I'd say we are doing > surprisingly well. I'm not too bothered personally, but Mark Rutland handed me a patch to improve the memory node handling in the stub, and he seemed to really want this there. You guys can fight it out :) What would be the effect of the UEFI code adding all its memblocks, minus the reserved areas, and then the DT code doing a memblock_add of all RAM (including reserved areas)? Would memblock_reserve()s on the protected regions suffice to prevent crazy stuff from happening? / Leif ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH] powerpc/mpc85xx: Remove P1023 RDS support
P1023RDS is no longer supported by Freescale while P1023RDB is still supported.
Signed-off-by: Lijun Pan
---
arch/powerpc/boot/dts/p1023rds.dts | 219 -
arch/powerpc/configs/mpc85xx_defconfig | 1 -
arch/powerpc/configs/mpc85xx_smp_defconfig | 1 -
arch/powerpc/platforms/85xx/Kconfig| 6 +-
arch/powerpc/platforms/85xx/Makefile | 2 +-
.../platforms/85xx/{p1023_rds.c => p1023_rdb.c}| 36 +---
6 files changed, 10 insertions(+), 255 deletions(-)
delete mode 100644 arch/powerpc/boot/dts/p1023rds.dts
rename arch/powerpc/platforms/85xx/{p1023_rds.c => p1023_rdb.c} (75%)
diff --git a/arch/powerpc/boot/dts/p1023rds.dts
b/arch/powerpc/boot/dts/p1023rds.dts
deleted file mode 100644
index beb6cb1..000
--- a/arch/powerpc/boot/dts/p1023rds.dts
+++ /dev/null
@@ -1,219 +0,0 @@
-/*
- * P1023 RDS Device Tree Source
- *
- * Copyright 2010-2011 Freescale Semiconductor Inc.
- *
- * Author: Roy Zang
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Freescale Semiconductor nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- *
- * ALTERNATIVELY, this software may be distributed under the terms of the
- * GNU General Public License ("GPL") as published by the Free Software
- * Foundation, either version 2 of that License or (at your option) any
- * later version.
- *
- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/include/ "fsl/p1023si-pre.dtsi"
-
-/ {
- model = "fsl,P1023";
- compatible = "fsl,P1023RDS";
- #address-cells = <2>;
- #size-cells = <2>;
- interrupt-parent = <&mpic>;
-
- memory {
- device_type = "memory";
- };
-
- soc: soc@ff60 {
- ranges = <0x0 0x0 0xff60 0x20>;
-
- i2c@3000 {
- rtc@68 {
- compatible = "dallas,ds1374";
- reg = <0x68>;
- };
- };
-
- spi@7000 {
- fsl_dataflash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "atmel,at45db081d";
- reg = <0>;
- spi-max-frequency = <4000>; /* input clock
*/
- partition@u-boot {
- /* 512KB for u-boot Bootloader Image */
- label = "u-boot-spi";
- reg = <0x 0x0008>;
- read-only;
- };
- partition@dtb {
- /* 512KB for DTB Image */
- label = "dtb-spi";
- reg = <0x0008 0x0008>;
- read-only;
- };
- };
- };
-
- usb@22000 {
- dr_mode = "host";
- phy_type = "ulpi";
- };
- };
-
- lbc: localbus@ff605000 {
- reg = <0 0xff605000 0 0x1000>;
-
- /* NOR Flash, BCSR */
- ranges = <0x0 0x0 0x0 0xee00 0x0200
- 0x1 0x0 0x0 0xe000 0x8000>;
-
- nor@0,0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "cfi
Re: [PATCH 0/3] of: dts: enable memory@0 quirk for PPC32 only
On Fri, Apr 18, 2014 at 7:48 AM, Leif Lindholm wrote: > On Thu, Apr 17, 2014 at 07:43:13PM -0500, Rob Herring wrote: >> On Thu, Apr 17, 2014 at 12:41 PM, Leif Lindholm >> wrote: >> > drivers/of/fdt.c contains a workaround for a missing memory type >> > entry on longtrail firmware. Make that quirk PPC32 only, and while >> > at it - fix up the .dts files in the tree currently working only >> > because of that quirk. >> >> But why do you need this? > > Apart from the current code permitting recreating a 15+ year old > firmware bug into completely new platform ports? I would prefer to see a "WARN_ON(!IS_ENABLED(CONFIG_PPC32));" added here. Really, I would like to see quirks like this fixed up out of line from the normal flow somewhat like how PCI quirks are handled. So in this example, we would just add the missing property to the dtb for the broken platform before doing the memory scan. That does then require libfdt which is something I'm working on. > Because the UEFI stub for arm/arm64 needs to delete all of the "memory" > nodes from the DT. And it would be nice to at least not have to compile > the "and also delete anything called memory@0" into the arm64 image. Or > any image not including support for affected platforms. I don't see why you would handle that in the EFI stub. Given our lack of validation, I can see there is a chance this happens but I think it is pretty small. Given we only have a ARM board, I'd say we are doing surprisingly well. Rob >> > arch/arm/boot/dts/ste-ccu8540.dts |1 + >> > arch/mips/lantiq/dts/easy50712.dts|1 + >> > arch/mips/ralink/dts/mt7620a_eval.dts |1 + >> > arch/mips/ralink/dts/rt2880_eval.dts |1 + >> > arch/mips/ralink/dts/rt3052_eval.dts |1 + >> > arch/mips/ralink/dts/rt3883_eval.dts |1 + >> >> I'm not worried about these MIPS dts files because they are all >> built-in, but you are breaking compatibility with old dtbs for this >> ARM board. > > Yeah, sorry. Sending out a v2 of part 3 shortly. > > / > Leif ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH] powerpc/fsl: Updated device trees for platforms with corenet version 2
From: Diana Craciun
Updated the device trees according to the corenet-cf
binding definition.
Signed-off-by: Diana Craciun
---
arch/powerpc/boot/dts/b4860emu.dts | 2 +-
arch/powerpc/boot/dts/fsl/b4420si-post.dtsi | 4
arch/powerpc/boot/dts/fsl/b4860si-post.dtsi | 4
arch/powerpc/boot/dts/fsl/b4si-post.dtsi| 2 +-
arch/powerpc/boot/dts/fsl/t4240si-post.dtsi | 2 +-
arch/powerpc/boot/dts/t4240emu.dts | 2 +-
6 files changed, 4 insertions(+), 12 deletions(-)
diff --git a/arch/powerpc/boot/dts/b4860emu.dts
b/arch/powerpc/boot/dts/b4860emu.dts
index 7290021..e41e2a2 100644
--- a/arch/powerpc/boot/dts/b4860emu.dts
+++ b/arch/powerpc/boot/dts/b4860emu.dts
@@ -157,7 +157,7 @@
};
corenet-cf@18000 {
- compatible = "fsl,b4-corenet-cf";
+ compatible = "fsl,corenet2-cf", "fsl,corenet-cf";
reg = <0x18000 0x1000>;
interrupts = <16 2 1 0>;
fsl,ccf-num-csdids = <32>;
diff --git a/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
b/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
index 60566f99..d678944 100644
--- a/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
@@ -76,10 +76,6 @@
compatible = "fsl,b4420-l3-cache-controller", "cache";
};
- corenet-cf@18000 {
- compatible = "fsl,b4420-corenet-cf";
- };
-
guts: global-utilities@e {
compatible = "fsl,b4420-device-config",
"fsl,qoriq-device-config-2.0";
};
diff --git a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
index cbc354b..582381d 100644
--- a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
@@ -120,10 +120,6 @@
compatible = "fsl,b4860-l3-cache-controller", "cache";
};
- corenet-cf@18000 {
- compatible = "fsl,b4860-corenet-cf";
- };
-
guts: global-utilities@e {
compatible = "fsl,b4860-device-config",
"fsl,qoriq-device-config-2.0";
};
diff --git a/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
b/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
index 4f6e482..376988c 100644
--- a/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
@@ -158,7 +158,7 @@
};
corenet-cf@18000 {
- compatible = "fsl,b4-corenet-cf";
+ compatible = "fsl,corenet2-cf", "fsl,corenet-cf";
reg = <0x18000 0x1000>;
interrupts = <16 2 1 0>;
fsl,ccf-num-csdids = <32>;
diff --git a/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
b/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
index f99d74f..c13ce99 100644
--- a/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
@@ -343,7 +343,7 @@
};
corenet-cf@18000 {
- compatible = "fsl,corenet-cf";
+ compatible = "fsl,corenet2-cf", "fsl,corenet-cf";
reg = <0x18000 0x1000>;
interrupts = <16 2 1 31>;
fsl,ccf-num-csdids = <32>;
diff --git a/arch/powerpc/boot/dts/t4240emu.dts
b/arch/powerpc/boot/dts/t4240emu.dts
index ee24ab3..c719dcc 100644
--- a/arch/powerpc/boot/dts/t4240emu.dts
+++ b/arch/powerpc/boot/dts/t4240emu.dts
@@ -213,7 +213,7 @@
};
corenet-cf@18000 {
- compatible = "fsl,corenet-cf";
+ compatible = "fsl,corenet2-cf", "fsl, corenet-cf";
reg = <0x18000 0x1000>;
interrupts = <16 2 1 31>;
fsl,ccf-num-csdids = <32>;
--
1.7.11.7
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[PATCH v2] powerpc/fsl: Added binding for Freescale CoreNet coherency fabric (CCF)
From: Diana Craciun
The CoreNet coherency fabric is a fabric-oriented, conectivity
infrastructure that enables the implementation of coherent, multicore
systems. The CCF acts as a central interconnect for cores,
platform-level caches, memory subsystem, peripheral devices and I/O host
bridges in the system.
Signed-off-by: Diana Craciun
---
.../devicetree/bindings/powerpc/fsl/ccf.txt| 36 ++
1 file changed, 36 insertions(+)
create mode 100644 Documentation/devicetree/bindings/powerpc/fsl/ccf.txt
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/ccf.txt
b/Documentation/devicetree/bindings/powerpc/fsl/ccf.txt
new file mode 100644
index 000..f0b7143
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/fsl/ccf.txt
@@ -0,0 +1,36 @@
+Freescale CoreNet Coherency Fabric(CCF) Device Tree Binding
+
+DESCRIPTION
+
+The CoreNet coherency fabric is a fabric-oriented, connectivity infrastructure
+that enables the implementation of coherent, multicore systems.
+
+Required properties:
+
+- compatible :
+ Must include "fsl,corenetX-cf", "fsl,corenet-cf" - CoreNet
coherency
+ fabric version X
+
+- reg :
+ A standard property. Represents the CCF registers.
+
+- interrupts :
+ Interrupt mapping for CCF error interrupt.
+
+- fsl,ccf-num-csdids:
+ Specifies the number of Coherency Subdomain ID Port Mapping
+ Registers that are supported by the CCF.
+
+- fsl,ccf-num-snoopids:
+ Specifies the number of Snoop ID Port Mapping Registers that
+ are supported by CCF.
+
+Example:
+
+ corenet-cf@18000 {
+ compatible = "fsl,corenet2-cf", "fsl,corenet-cf";
+ reg = <0x18000 0x1000>;
+ interrupts = <16 2 1 31>;
+ fsl,ccf-num-csdids = <32>;
+ fsl,ccf-num-snoopids = <32>;
+ };
--
1.7.11.7
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Re: [PATCH 3/3] of: Handle memory@0 node on PPC32 only
Hi Geert,
On Fri, Apr 18, 2014 at 10:04:15AM +0200, Geert Uytterhoeven wrote:
> On Thu, Apr 17, 2014 at 7:42 PM, Leif Lindholm
> wrote:
> > In order to deal with an firmware bug on a specific ppc32 platform
> > (longtrail), early_init_dt_scan_memory() looks for a node called
> > memory@0 on all platforms. Restrict this quirk to ppc32 kernels only.
>
> This breaks backwards compatibilty with old DTSes (at least on ARM/MIPS,
> where you added the missing property in patches 1 and 2 of the series)?
As Rob said in response to 0/3, the MIPSs would likely not be affected,
since they embed the DT.
> For the Longtrail, I don't care much anymore, as mine died in 2004.
> AFAIK, there have never been many users anyway.
There are still a few mentions of it under arch/powerpc/, so I wouldn't
want to be the one to kill it off...
How about the below v2 3/3 to address the ARM platform?
Regards,
Leif
From 6fa0b837ad71780334eb97d63c507165b6c57add Mon Sep 17 00:00:00 2001
From: Leif Lindholm
Date: Thu, 17 Apr 2014 14:24:47 +0100
Subject: [PATCH] of: arm: powerpc: Restrict memory@0 node handling to
affected platforms
In order to deal with a firmware bug on a specific ppc32 platform
(longtrail), early_init_dt_scan_memory() looks for a node called
memory@0 on all platforms, for all nodes lacking a device_type.
Restrict this quirk to ppc32 and the arm mach-ux500 platforms (one of
which has depended on this special handling).
Signed-off-by: Leif Lindholm
Cc: Grant Likely
Cc: Lee Jones
Cc: Mark Rutland
Cc: devicet...@vger.kernel.org
---
arch/arm/mach-ux500/Kconfig |1 +
arch/powerpc/Kconfig|1 +
drivers/of/Kconfig |3 +++
drivers/of/fdt.c| 10 +-
4 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig
index b41a42d..e6b0c3b 100644
--- a/arch/arm/mach-ux500/Kconfig
+++ b/arch/arm/mach-ux500/Kconfig
@@ -13,6 +13,7 @@ config ARCH_U8500
select CLKSRC_NOMADIK_MTU
select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD if SMP
+ select OF_MEMORY_AT_0_QUIRK
select PINCTRL
select PINCTRL_ABX500
select PINCTRL_NOMADIK
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index e099899..d78452d 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -3,6 +3,7 @@ source "arch/powerpc/platforms/Kconfig.cputype"
config PPC32
bool
default y if !PPC64
+ select OF_MEMORY_AT_0_QUIRK
config 32BIT
bool
diff --git a/drivers/of/Kconfig b/drivers/of/Kconfig
index 889005f..230c747 100644
--- a/drivers/of/Kconfig
+++ b/drivers/of/Kconfig
@@ -77,4 +77,7 @@ config OF_RESERVED_MEM
help
Helpers to allow for reservation of memory regions
+config OF_MEMORY_AT_0_QUIRK
+ def_bool n
+
endmenu # OF
diff --git a/drivers/of/fdt.c b/drivers/of/fdt.c
index fa16a91..1b80b94 100644
--- a/drivers/of/fdt.c
+++ b/drivers/of/fdt.c
@@ -887,14 +887,22 @@ int __init early_init_dt_scan_memory(unsigned long node,
const char *uname,
/* We are scanning "memory" nodes only */
if (type == NULL) {
+#ifdef CONFIG_OF_MEMORY_AT_0_QUIRK
/*
* The longtrail doesn't have a device_type on the
* /memory node, so look for the node called /memory@0.
+* Converted to generic quirk to handle later platforms
+* with inforrect DTs that work only because of this
+* special handling.
*/
if (depth != 1 || strcmp(uname, "memory@0") != 0)
return 0;
- } else if (strcmp(type, "memory") != 0)
+#else
+ return 0;
+#endif
+ } else if (strcmp(type, "memory") != 0) {
return 0;
+ }
reg = of_get_flat_dt_prop(node, "linux,usable-memory", &l);
if (reg == NULL)
--
1.7.10.4
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Re: [PATCH 0/3] of: dts: enable memory@0 quirk for PPC32 only
On Thu, Apr 17, 2014 at 07:43:13PM -0500, Rob Herring wrote: > On Thu, Apr 17, 2014 at 12:41 PM, Leif Lindholm > wrote: > > drivers/of/fdt.c contains a workaround for a missing memory type > > entry on longtrail firmware. Make that quirk PPC32 only, and while > > at it - fix up the .dts files in the tree currently working only > > because of that quirk. > > But why do you need this? Apart from the current code permitting recreating a 15+ year old firmware bug into completely new platform ports? Because the UEFI stub for arm/arm64 needs to delete all of the "memory" nodes from the DT. And it would be nice to at least not have to compile the "and also delete anything called memory@0" into the arm64 image. Or any image not including support for affected platforms. > > arch/arm/boot/dts/ste-ccu8540.dts |1 + > > arch/mips/lantiq/dts/easy50712.dts|1 + > > arch/mips/ralink/dts/mt7620a_eval.dts |1 + > > arch/mips/ralink/dts/rt2880_eval.dts |1 + > > arch/mips/ralink/dts/rt3052_eval.dts |1 + > > arch/mips/ralink/dts/rt3883_eval.dts |1 + > > I'm not worried about these MIPS dts files because they are all > built-in, but you are breaking compatibility with old dtbs for this > ARM board. Yeah, sorry. Sending out a v2 of part 3 shortly. / Leif ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 5/6] powerpc/corenet: Add DPAA FMan support to the SoC device tree(s)
FMan 1 Gb/s MACs (dTSEC and mEMAC) have support for SGMII PHYs.
Add support for the internal SerDes TBI PHYs
Based on prior work by Andy Fleming
Signed-off-by: Shruti Kanetkar
---
arch/powerpc/boot/dts/fsl/b4860si-post.dtsi | 28 +
arch/powerpc/boot/dts/fsl/b4si-post.dtsi| 51 +
arch/powerpc/boot/dts/fsl/p1023si-post.dtsi | 14 +++
arch/powerpc/boot/dts/fsl/p2041si-post.dtsi | 64
arch/powerpc/boot/dts/fsl/p3041si-post.dtsi | 64
arch/powerpc/boot/dts/fsl/p4080si-post.dtsi | 104 +++
arch/powerpc/boot/dts/fsl/p5020si-post.dtsi | 64
arch/powerpc/boot/dts/fsl/p5040si-post.dtsi | 128 +++
arch/powerpc/boot/dts/fsl/t4240si-post.dtsi | 154
9 files changed, 671 insertions(+)
diff --git a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
index cbc354b..45b0ff5 100644
--- a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
@@ -172,6 +172,34 @@
compatible = "fsl,b4860-rcpm", "fsl,qoriq-rcpm-2.0";
};
+/include/ "qoriq-fman3-0-1g-4.dtsi"
+/include/ "qoriq-fman3-0-1g-5.dtsi"
+/include/ "qoriq-fman3-0-10g-0.dtsi"
+/include/ "qoriq-fman3-0-10g-1.dtsi"
+ fman@40 {
+ ethernet@e8000 {
+ tbi-handle = <&tbi4>;
+ };
+
+ mdio@e9000 {
+ tbi4: tbi-phy@8 {
+ reg = <0x8>;
+ device_type = "tbi-phy";
+ };
+ };
+
+ ethernet@ea000 {
+ tbi-handle = <&tbi5>;
+ };
+
+ mdio@eb000 {
+ tbi5: tbi-phy@8 {
+ reg = <0x8>;
+ device_type = "tbi-phy";
+ };
+ };
+ };
+
L2: l2-cache-controller@c2 {
compatible = "fsl,b4860-l2-cache-controller";
};
diff --git a/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
b/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
index 4f6e482..e59d6ae 100644
--- a/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
@@ -260,6 +260,57 @@
/include/ "qoriq-duart-1.dtsi"
/include/ "qoriq-sec5.3-0.dtsi"
+/include/ "qoriq-fman3-0.dtsi"
+/include/ "qoriq-fman3-0-1g-0.dtsi"
+/include/ "qoriq-fman3-0-1g-1.dtsi"
+/include/ "qoriq-fman3-0-1g-2.dtsi"
+/include/ "qoriq-fman3-0-1g-3.dtsi"
+ fman@40 {
+ ethernet@e {
+ tbi-handle = <&tbi0>;
+ };
+
+ mdio@e1000 {
+ tbi0: tbi-phy@8 {
+ reg = <0x8>;
+ device_type = "tbi-phy";
+ };
+ };
+
+ ethernet@e2000 {
+ tbi-handle = <&tbi1>;
+ };
+
+ mdio@e3000 {
+ tbi1: tbi-phy@8 {
+ reg = <0x8>;
+ device_type = "tbi-phy";
+ };
+ };
+
+ ethernet@e4000 {
+ tbi-handle = <&tbi2>;
+ };
+
+ mdio@e5000 {
+ tbi2: tbi-phy@8 {
+ reg = <0x8>;
+ device_type = "tbi-phy";
+ };
+ };
+
+ ethernet@e6000 {
+ tbi-handle = <&tbi3>;
+ };
+
+ mdio@e7000 {
+ tbi3: tbi-phy@8 {
+ reg = <0x8>;
+ device_type = "tbi-phy";
+ };
+ };
+ };
+
L2: l2-cache-controller@c2 {
compatible = "fsl,b4-l2-cache-controller";
reg = <0xc2 0x1000>;
diff --git a/arch/powerpc/boot/dts/fsl/p1023si-post.dtsi
b/arch/powerpc/boot/dts/fsl/p1023si-post.dtsi
index 81437fd..01fd153 100644
--- a/arch/powerpc/boot/dts/fsl/p1023si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p1023si-post.dtsi
@@ -226,4 +226,18 @@
reg = <0xe 0x1000>;
fsl,has-rstcr;
};
+
+ fman@10 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x10 0x10>;
+ compatible = "simple-bus";
+
+ mdio@e1120 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,fman-mdio";
+ reg = <0xe1120 0xee0>;
+ };
+ };
};
diff --git a/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
b/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
index e2987a3..6f3836e 100644
--- a/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
[PATCH 3/3] of: Handle memory@0 node on PPC32 only
In order to deal with an firmware bug on a specific ppc32 platform
(longtrail), early_init_dt_scan_memory() looks for a node called
memory@0 on all platforms. Restrict this quirk to ppc32 kernels only.
Signed-off-by: Leif Lindholm
Cc: linuxppc-dev@lists.ozlabs.org
Cc: Grant Likely
Cc: Mark Rutland
Cc: devicet...@vger.kernel.org
Cc: linux-ker...@vger.kernel.org
---
drivers/of/fdt.c |7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/of/fdt.c b/drivers/of/fdt.c
index fa16a91..7368472 100644
--- a/drivers/of/fdt.c
+++ b/drivers/of/fdt.c
@@ -887,14 +887,19 @@ int __init early_init_dt_scan_memory(unsigned long node,
const char *uname,
/* We are scanning "memory" nodes only */
if (type == NULL) {
+#ifdef CONFIG_PPC32
/*
* The longtrail doesn't have a device_type on the
* /memory node, so look for the node called /memory@0.
*/
if (depth != 1 || strcmp(uname, "memory@0") != 0)
return 0;
- } else if (strcmp(type, "memory") != 0)
+#else
+ return 0;
+#endif
+ } else if (strcmp(type, "memory") != 0) {
return 0;
+ }
reg = of_get_flat_dt_prop(node, "linux,usable-memory", &l);
if (reg == NULL)
--
1.7.10.4
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[PATCH 0/3] of: dts: enable memory@0 quirk for PPC32 only
drivers/of/fdt.c contains a workaround for a missing memory type entry on longtrail firmware. Make that quirk PPC32 only, and while at it - fix up the .dts files in the tree currently working only because of that quirk. Cc: devicet...@vger.kernel.org Cc: linuxppc-dev@lists.ozlabs.org Cc: linux-ker...@vger.kernel.org Cc: Mark Rutland Leif Lindholm (3): arm: dts: add device_type="memory" for ste-ccu8540 mips: dts: add device_type="memory" where missing of: Handle memory@0 node on PPC32 only arch/arm/boot/dts/ste-ccu8540.dts |1 + arch/mips/lantiq/dts/easy50712.dts|1 + arch/mips/ralink/dts/mt7620a_eval.dts |1 + arch/mips/ralink/dts/rt2880_eval.dts |1 + arch/mips/ralink/dts/rt3052_eval.dts |1 + arch/mips/ralink/dts/rt3883_eval.dts |1 + drivers/of/fdt.c |7 ++- 7 files changed, 12 insertions(+), 1 deletion(-) -- 1.7.10.4 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 6/6] powerpc/corenet: Add MDIO bus muxing support to the board device tree(s)
Based on prior work by Andy Fleming
Signed-off-by: Shruti Kanetkar
---
arch/powerpc/boot/dts/b4860qds.dts | 56 +++
arch/powerpc/boot/dts/b4qds.dtsi | 45 ++
arch/powerpc/boot/dts/p1023rdb.dts | 19 +++
arch/powerpc/boot/dts/p2041rdb.dts | 87 +++
arch/powerpc/boot/dts/p3041ds.dts | 138 +
arch/powerpc/boot/dts/p4080ds.dts | 178 ++
arch/powerpc/boot/dts/p5020ds.dts | 138 +
arch/powerpc/boot/dts/p5040ds.dts | 232
arch/powerpc/boot/dts/t4240qds.dts | 305 +
9 files changed, 1198 insertions(+)
diff --git a/arch/powerpc/boot/dts/b4860qds.dts
b/arch/powerpc/boot/dts/b4860qds.dts
index 6bb3707..d7daf44 100644
--- a/arch/powerpc/boot/dts/b4860qds.dts
+++ b/arch/powerpc/boot/dts/b4860qds.dts
@@ -39,12 +39,68 @@
model = "fsl,B4860QDS";
compatible = "fsl,B4860QDS";
+ aliases {
+ phy_sgmii_1e = &phy_sgmii_1e;
+ phy_sgmii_1f = &phy_sgmii_1f;
+ phy_xaui_slot1 = &phy_xaui_slot1;
+ phy_xaui_slot2 = &phy_xaui_slot2;
+ };
+
ifc: localbus@ffe124000 {
board-control@3,0 {
compatible = "fsl,b4860qds-fpga", "fsl,fpga-qixis";
};
};
+ soc@ffe00 {
+ fman@40 {
+ ethernet@e8000 {
+ phy-handle = <&phy_sgmii_1e>;
+ phy-connection-type = "sgmii";
+ };
+
+ ethernet@ea000 {
+ phy-handle = <&phy_sgmii_1f>;
+ phy-connection-type = "sgmii";
+ };
+
+ ethernet@f { /* FM1@TGEC2 */
+ phy-handle = <&phy_xaui_slot1>;
+ phy-connection-type = "xgmii";
+ };
+
+ ethernet@f2000 { /* FM1@TGEC1 */
+ phy-handle = <&phy_xaui_slot2>;
+ phy-connection-type = "xgmii";
+ };
+
+ mdio@fc000 {
+ phy_sgmii_1e: ethernet-phy@1e {
+ status = "disabled";
+ reg = <0x1e>;
+ };
+ phy_sgmii_1f: ethernet-phy@1f {
+ status = "disabled";
+ reg = <0x1f>;
+ };
+ };
+
+ mdio@fd000 {
+ /* For 10g interfaces */
+ phy_xaui_slot1: xaui-phy@slot1 {
+ status = "disabled";
+ compatible =
"ethernet-phy-ieee802.3-c45";
+ reg = <0x7>; /* default switch setting
on slot1 of AMC2PEX */
+ };
+ phy_xaui_slot2: xaui-phy@slot2 {
+ status = "disabled";
+ compatible =
"ethernet-phy-ieee802.3-c45";
+ reg = <0x6>; /* default switch setting
on slot1 of AMC2PEX */
+ };
+ };
+ };
+ };
+
rio: rapidio@ffe0c {
reg = <0xf 0xfe0c 0 0x11000>;
diff --git a/arch/powerpc/boot/dts/b4qds.dtsi b/arch/powerpc/boot/dts/b4qds.dtsi
index 8b47edc..6188583 100644
--- a/arch/powerpc/boot/dts/b4qds.dtsi
+++ b/arch/powerpc/boot/dts/b4qds.dtsi
@@ -39,6 +39,13 @@
#size-cells = <2>;
interrupt-parent = <&mpic>;
+ aliases {
+ phy_sgmii_10 = &phy_sgmii_10;
+ phy_sgmii_11 = &phy_sgmii_11;
+ phy_sgmii_1c = &phy_sgmii_1c;
+ phy_sgmii_1d = &phy_sgmii_1d;
+ };
+
ifc: localbus@ffe124000 {
reg = <0xf 0xfe124000 0 0x2000>;
ranges = <0 0 0xf 0xe800 0x0800
@@ -160,6 +167,44 @@
phy_type = "ulpi";
};
+ fman@40 {
+ ethernet@e {
+ phy-handle = <&phy_sgmii_10>;
+ phy-connection-type = "sgmii";
+ };
+
+ ethernet@e2000 {
+ phy-handle = <&phy_sgmii_11>;
+ phy-connection-type = "sgmii";
+ };
+
+ ethernet@e4000 {
+ phy-handle = <&phy_sgmii_1c>;
+ phy-connection-type = "sgmii";
+ };
+
+
[PATCH 2/6] powerpc/corenet: Enable muxing MDIO buses via FPGA
Signed-off-by: Andy Fleming
Signed-off-by: Shaohui Xie
Signed-off-by: Shruti Kanetkar
---
arch/powerpc/configs/corenet32_smp_defconfig | 1 +
arch/powerpc/configs/corenet64_smp_defconfig | 1 +
arch/powerpc/platforms/85xx/corenet_generic.c | 3 +++
3 files changed, 5 insertions(+)
diff --git a/arch/powerpc/configs/corenet32_smp_defconfig
b/arch/powerpc/configs/corenet32_smp_defconfig
index 548b21c..132d9f6 100644
--- a/arch/powerpc/configs/corenet32_smp_defconfig
+++ b/arch/powerpc/configs/corenet32_smp_defconfig
@@ -104,6 +104,7 @@ CONFIG_AT803X_PHY=y
CONFIG_FIXED_PHY=y
CONFIG_MDIO_BUS_MUX=y
CONFIG_MDIO_BUS_MUX_GPIO=y
+CONFIG_MDIO_BUS_MUX_MMIOREG=y
# CONFIG_INPUT_MOUSEDEV is not set
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
diff --git a/arch/powerpc/configs/corenet64_smp_defconfig
b/arch/powerpc/configs/corenet64_smp_defconfig
index cbe7afb..b32 100644
--- a/arch/powerpc/configs/corenet64_smp_defconfig
+++ b/arch/powerpc/configs/corenet64_smp_defconfig
@@ -99,6 +99,7 @@ CONFIG_E1000E=y
CONFIG_MDIO_BUS_MUX=y
CONFIG_MDIO_BUS_MUX_GPIO=y
CONFIG_INPUT_FF_MEMLESS=m
+CONFIG_MDIO_BUS_MUX_MMIOREG=y
# CONFIG_INPUT_MOUSEDEV is not set
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
diff --git a/arch/powerpc/platforms/85xx/corenet_generic.c
b/arch/powerpc/platforms/85xx/corenet_generic.c
index dc9e24e..814faae 100644
--- a/arch/powerpc/platforms/85xx/corenet_generic.c
+++ b/arch/powerpc/platforms/85xx/corenet_generic.c
@@ -80,6 +80,9 @@ static const struct of_device_id of_device_ids[] = {
.compatible = "mdio-mux-gpio"
},
{
+ .compatible = "fsl,fpga-ngpixis"
+ },
+ {
.compatible = "fsl,srio",
},
{
--
1.8.3.1
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[PATCH 3/6] net/fsl_pq_mdio: Document supported compatibles
The device tree binding(s) document has fallen out of sync with the driver code. Update the list of supported devices to reflect current driver capabilities Signed-off-by: Shruti Kanetkar --- Documentation/devicetree/bindings/net/fsl-tsec-phy.txt | 11 ++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt b/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt index d2ea460..14b72fc 100644 --- a/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt +++ b/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt @@ -8,7 +8,16 @@ of how to define a PHY. Required properties: - reg : Offset and length of the register set for the device - compatible : Should define the compatible device type for the -mdio. Currently, this is most likely to be "fsl,gianfar-mdio" +mdio. Currently supported strings/devices are: + - "fsl,gianfar-tbi" + - "fsl,gianfar-mdio" + - "fsl,etsec2-tbi" + - "fsl,etsec2-mdio" + - "fsl,ucc-mdio" + - "fsl,fman-mdio" +When device_type is "mdio", the following strings are also considered: + - "gianfar" + - "ucc_geth_phy" Example: -- 1.8.3.1 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 1/6] powerpc/corenet: Enable muxing MDIO buses via GPIO
From: Andy Fleming
Signed-off-by: Andy Fleming
Signed-off-by: Shaohui Xie
Signed-off-by: Shruti Kanetkar
---
arch/powerpc/configs/corenet32_smp_defconfig | 2 ++
arch/powerpc/configs/corenet64_smp_defconfig | 2 ++
arch/powerpc/platforms/85xx/corenet_generic.c | 3 +++
3 files changed, 7 insertions(+)
diff --git a/arch/powerpc/configs/corenet32_smp_defconfig
b/arch/powerpc/configs/corenet32_smp_defconfig
index bbd794d..548b21c 100644
--- a/arch/powerpc/configs/corenet32_smp_defconfig
+++ b/arch/powerpc/configs/corenet32_smp_defconfig
@@ -102,6 +102,8 @@ CONFIG_E1000E=y
CONFIG_VITESSE_PHY=y
CONFIG_AT803X_PHY=y
CONFIG_FIXED_PHY=y
+CONFIG_MDIO_BUS_MUX=y
+CONFIG_MDIO_BUS_MUX_GPIO=y
# CONFIG_INPUT_MOUSEDEV is not set
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
diff --git a/arch/powerpc/configs/corenet64_smp_defconfig
b/arch/powerpc/configs/corenet64_smp_defconfig
index 5c7fa19..cbe7afb 100644
--- a/arch/powerpc/configs/corenet64_smp_defconfig
+++ b/arch/powerpc/configs/corenet64_smp_defconfig
@@ -96,6 +96,8 @@ CONFIG_SATA_SIL24=y
CONFIG_NETDEVICES=y
CONFIG_DUMMY=y
CONFIG_E1000E=y
+CONFIG_MDIO_BUS_MUX=y
+CONFIG_MDIO_BUS_MUX_GPIO=y
CONFIG_INPUT_FF_MEMLESS=m
# CONFIG_INPUT_MOUSEDEV is not set
# CONFIG_INPUT_KEYBOARD is not set
diff --git a/arch/powerpc/platforms/85xx/corenet_generic.c
b/arch/powerpc/platforms/85xx/corenet_generic.c
index 8e4b1e1..dc9e24e 100644
--- a/arch/powerpc/platforms/85xx/corenet_generic.c
+++ b/arch/powerpc/platforms/85xx/corenet_generic.c
@@ -77,6 +77,9 @@ static const struct of_device_id of_device_ids[] = {
.compatible = "simple-bus"
},
{
+ .compatible = "mdio-mux-gpio"
+ },
+ {
.compatible = "fsl,srio",
},
{
--
1.8.3.1
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Re: [PATCH 3/3] of: Handle memory@0 node on PPC32 only
Hei Leif,
On Fri, Apr 18, 2014 at 2:59 PM, Leif Lindholm wrote:
> On Fri, Apr 18, 2014 at 10:04:15AM +0200, Geert Uytterhoeven wrote:
>> On Thu, Apr 17, 2014 at 7:42 PM, Leif Lindholm
>> wrote:
>> > In order to deal with an firmware bug on a specific ppc32 platform
>> > (longtrail), early_init_dt_scan_memory() looks for a node called
>> > memory@0 on all platforms. Restrict this quirk to ppc32 kernels only.
>>
>> This breaks backwards compatibilty with old DTSes (at least on ARM/MIPS,
>> where you added the missing property in patches 1 and 2 of the series)?
>
> As Rob said in response to 0/3, the MIPSs would likely not be affected,
> since they embed the DT.
>
> How about the below v2 3/3 to address the ARM platform?
Looks fine to me, thanks!
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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Re: [PATCH RFC v11 5/6] dma: mpc512x: add device tree binding document
Thanks for your reply, Gerhard
2014-04-17 0:44 GMT+04:00 Gerhard Sittig :
> On Tue, 2014-04-15 at 14:54 +0400, Alexander Popov wrote:
>>
>> Introduce a device tree binding document for the MPC512x DMA controller
>>
>> Signed-off-by: Gerhard Sittig
>> Signed-off-by: Alexander Popov
>
> I'm not certain whether the attribution is right. Is the S-o-b
> appropriate when the patch is not "from" me? As I've stated
> before, it's OK if you pick up and extend what I provide, but
> please don't pretend that I wrote what you did,
Thanks. I've read the corresponding part of
Documentation/SubmittingPatches once again and now I see
my mistake.
> and don't pretend
> that I ACKed or passed along your submission when I didn't.
I didn't have any malicious intent.
> This binding certainly needs further improvement to become a good
> one. As I've communicated in the past, I was rather ignorant
> "back then" when I wrote v1 and v2 of the RFC. We have learned
> something in the meantime. Though I admit having gone silent
> after several review iterations. Assumed you would pick up
> information that showed up several times on public lists.
>
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/dma/mpc512x-dma.txt
>> @@ -0,0 +1,51 @@
>> +* Freescale MPC512x and MPC8308 DMA Controller
>> +
>> +The DMA controller in the Freescale MPC512x and MPC8308 SoCs can move
>> +blocks of memory contents between memory and peripherals or
>> +from memory to memory.
>> +
>> +Refer to the "Generic DMA Controller and DMA request bindings" in
>> +the dma/dma.txt file for a more detailed description of binding.
>> +
>> +* DMA controller
>> +
>> +Required properties:
>> +- compatible: Should be one of
>> + "fsl,mpc5121-dma"
>> + "fsl,mpc8308-dma", "fsl,mpc5121-dma"
>
> is this a duplicate? looks funny, needs a fix
>
> or is it a requirement that for MPC8308 you need to provide both
> compatible strings? that would be wrong, as MPC8308 certainly is
> not an MPC5121
>
> a quick search reveals: the drivers/dma/mpc512x_dma.c Linux
> driver implementation is wrong, it should match on both strings;
> expecting the MPC8308 to disguise as an MPC5121 when it's not is
> inappropriate (and only went unnoticed because of missing
> bindings, I guess)
I can try to fix that and add a new patch to the series.
>> +- reg: Address and size of the DMA controller's register set
>> +- interrupts: Interrupt for the DMA controller. Generic interrupt client
>> node
>> + is described in interrupt-controller/interrupts.txt
>
> 'interrupts' only works in combinations with 'interrupt-parent',
> that actual .dts files don't have the latter in the nodes is an
> implementation detail but not a binding's requirement
Excuse me, I didn't understand your point.
> and an alternative method of specifying interrupts was introduced
> recently, a reference to the common binding without naming one
> specific property name could be most appropriate
Excuse me, I haven't found such an example.
>> +
>> +Optional properties:
>> +- #dma-cells: The length of the DMA specifier, must be <1> since
>> + the DMA controller uses a fixed assignment of request lines
>> + per channel. Refer to dma/dma.txt for the detailed description
>> + of this property
>
> I'm afraid that a generic/common document does not and cannot
> describe the specific semantics of this provider's cells
Ok, I see.
> this binding should explicitly mention that the number of cells
> needs to be one, and that this one cell is the DMA channel (which
> translates to "peripheral request line"), because these
> assigments are fixed in hardware
Ok.
>> +
>> +Example:
>> +
>> + dma0: dma@14000 {
>> + compatible = "fsl,mpc5121-dma";
>> + reg = <0x14000 0x1800>;
>> + interrupts = <65 0x8>;
>> + #dma-cells = <1>;
>> + };
>> +
>> +* DMA client
>
> the DMA provider's binding probably need not discuss client
> specs, a reference to the common binding should suffice if it's
> appropriate at all
Ok.
Best regards,
Alexander
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[PATCH] powerpc/diu: adjust DIU initialization entry
From: Wang Dongsheng
Move fsl_diu_init into diu probe function, because it should be
initialized when system get diu device tree node, not always do
initialization.
Signed-off-by: Wang Dongsheng
diff --git a/drivers/video/fsl-diu-fb.c b/drivers/video/fsl-diu-fb.c
index e8758b9..75ab20e 100644
--- a/drivers/video/fsl-diu-fb.c
+++ b/drivers/video/fsl-diu-fb.c
@@ -1680,6 +1680,99 @@ static ssize_t show_monitor(struct device *device,
return 0;
}
+#ifndef MODULE
+static int __init fsl_diu_setup(char *options)
+{
+ char *opt;
+ unsigned long val;
+
+ if (!options || !*options)
+ return 0;
+
+ while ((opt = strsep(&options, ",")) != NULL) {
+ if (!*opt)
+ continue;
+ if (!strncmp(opt, "monitor=", 8)) {
+ monitor_port = fsl_diu_name_to_port(opt + 8);
+ } else if (!strncmp(opt, "bpp=", 4)) {
+ if (!kstrtoul(opt + 4, 10, &val))
+ default_bpp = val;
+ } else
+ fb_mode = opt;
+ }
+
+ return 0;
+}
+#endif
+
+static int fsl_diu_perpare(void)
+{
+#ifdef CONFIG_NOT_COHERENT_CACHE
+ struct device_node *np;
+ const u32 *prop;
+#endif
+ int ret;
+#ifndef MODULE
+ char *option;
+
+ /*
+* For kernel boot options (in 'video=xxxfb:' format)
+*/
+ if (fb_get_options("fslfb", &option))
+ return -ENODEV;
+ fsl_diu_setup(option);
+#else
+ monitor_port = fsl_diu_name_to_port(monitor_string);
+#endif
+ pr_info("Freescale Display Interface Unit (DIU) framebuffer driver\n");
+
+#ifdef CONFIG_NOT_COHERENT_CACHE
+ np = of_find_node_by_type(NULL, "cpu");
+ if (!np) {
+ pr_err("fsl-diu-fb: can't find 'cpu' device node\n");
+ return -ENODEV;
+ }
+
+ prop = of_get_property(np, "d-cache-size", NULL);
+ if (prop == NULL) {
+ pr_err("fsl-diu-fb: missing 'd-cache-size'\n");
+ of_node_put(np);
+ return -ENODEV;
+ }
+
+ /*
+* Freescale PLRU requires 13/8 times the cache size to do a proper
+* displacement flush
+*/
+ coherence_data_size = be32_to_cpup(prop) * 13;
+ coherence_data_size /= 8;
+
+ pr_debug("fsl-diu-fb: coherence data size is %zu bytes\n",
+coherence_data_size);
+
+ prop = of_get_property(np, "d-cache-line-size", NULL);
+ if (prop == NULL) {
+ pr_err("fsl-diu-fb: missing 'd-cache-line-size'\n");
+ of_node_put(np);
+ return -ENODEV;
+ }
+ d_cache_line_size = be32_to_cpup(prop);
+
+ pr_debug("fsl-diu-fb: cache lines size is %u bytes\n",
+d_cache_line_size);
+
+ of_node_put(np);
+ coherence_data = vmalloc(coherence_data_size);
+ if (!coherence_data) {
+ pr_err("fsl-diu-fb: could not allocate coherence data\n");
+ pr_err("coherence_data_size=%zu)\n", coherence_data_size);
+ return -ENOMEM;
+ }
+
+#endif
+ return ret;
+}
+
static int fsl_diu_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
@@ -1690,10 +1783,14 @@ static int fsl_diu_probe(struct platform_device *pdev)
unsigned int i;
int ret;
+ fsl_diu_perpare();
+
data = dmam_alloc_coherent(&pdev->dev, sizeof(struct fsl_diu_data),
&dma_addr, GFP_DMA | __GFP_ZERO);
- if (!data)
- return -ENOMEM;
+ if (!data) {
+ ret = -ENOMEM;
+ goto out_perpare;
+ }
data->dma_addr = dma_addr;
/*
@@ -1819,6 +1916,11 @@ error:
iounmap(data->diu_reg);
+out_perpare:
+#if defined(CONFIG_NOT_COHERENT_CACHE)
+ if (coherence_data)
+ vfree(coherence_data);
+#endif
return ret;
}
@@ -1837,34 +1939,12 @@ static int fsl_diu_remove(struct platform_device *pdev)
iounmap(data->diu_reg);
+#if defined(CONFIG_NOT_COHERENT_CACHE)
+ vfree(coherence_data);
+#endif
return 0;
}
-#ifndef MODULE
-static int __init fsl_diu_setup(char *options)
-{
- char *opt;
- unsigned long val;
-
- if (!options || !*options)
- return 0;
-
- while ((opt = strsep(&options, ",")) != NULL) {
- if (!*opt)
- continue;
- if (!strncmp(opt, "monitor=", 8)) {
- monitor_port = fsl_diu_name_to_port(opt + 8);
- } else if (!strncmp(opt, "bpp=", 4)) {
- if (!kstrtoul(opt + 4, 10, &val))
- default_bpp = val;
- } else
- fb_mode = opt;
- }
-
- return 0;
-}
-#endif
-
static struct of_device_id fsl_diu_match[] = {
#ifdef CONFIG_PPC_MPC512x
{
[PATCH v4 8/8] DMA: Freescale: add suspend resume functions for DMA driver
From: Hongbo Zhang
This patch adds suspend resume functions for Freescale DMA driver.
.prepare callback is used to stop further descriptors from being added into the
pending queue, and also issue pending queues into execution if there is any.
.suspend callback makes sure all the pending jobs are cleaned up and all the
channels are idle, and save the mode registers.
.resume callback re-initializes the channels by restore the mode registers.
Signed-off-by: Hongbo Zhang
---
drivers/dma/fsldma.c | 100 ++
drivers/dma/fsldma.h | 16
2 files changed, 116 insertions(+)
diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c
index 6e1c9b3..836fc27 100644
--- a/drivers/dma/fsldma.c
+++ b/drivers/dma/fsldma.c
@@ -400,6 +400,14 @@ static dma_cookie_t fsl_dma_tx_submit(struct
dma_async_tx_descriptor *tx)
spin_lock_bh(&chan->desc_lock);
+#ifdef CONFIG_PM
+ if (unlikely(chan->pm_state != RUNNING)) {
+ chan_dbg(chan, "cannot submit due to suspend\n");
+ spin_unlock_bh(&chan->desc_lock);
+ return -1;
+ }
+#endif
+
/*
* assign cookies to all of the software descriptors
* that make up this transaction
@@ -1312,6 +1320,9 @@ static int fsl_dma_chan_probe(struct fsldma_device *fdev,
INIT_LIST_HEAD(&chan->ld_running);
INIT_LIST_HEAD(&chan->ld_completed);
chan->idle = true;
+#ifdef CONFIG_PM
+ chan->pm_state = RUNNING;
+#endif
chan->common.device = &fdev->common;
dma_cookie_init(&chan->common);
@@ -1451,6 +1462,92 @@ static int fsldma_of_remove(struct platform_device *op)
return 0;
}
+#ifdef CONFIG_PM
+static int fsldma_prepare(struct device *dev)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct fsldma_device *fdev = platform_get_drvdata(pdev);
+ struct fsldma_chan *chan;
+ int i;
+
+ for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
+ chan = fdev->chan[i];
+ if (!chan)
+ continue;
+
+ spin_lock_bh(&chan->desc_lock);
+ chan->pm_state = SUSPENDING;
+ if (!list_empty(&chan->ld_pending))
+ fsl_chan_xfer_ld_queue(chan);
+ spin_unlock_bh(&chan->desc_lock);
+ }
+
+ return 0;
+}
+
+static int fsldma_suspend(struct device *dev)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct fsldma_device *fdev = platform_get_drvdata(pdev);
+ struct fsldma_chan *chan;
+ int i;
+
+ for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
+ chan = fdev->chan[i];
+ if (!chan)
+ continue;
+
+ spin_lock_bh(&chan->desc_lock);
+ if (!chan->idle)
+ goto out;
+ chan->regs_save.mr = get_mr(chan);
+ chan->pm_state = SUSPENDED;
+ spin_unlock_bh(&chan->desc_lock);
+ }
+ return 0;
+
+out:
+ for (; i >= 0; i--) {
+ chan = fdev->chan[i];
+ if (!chan)
+ continue;
+ chan->pm_state = RUNNING;
+ spin_unlock_bh(&chan->desc_lock);
+ }
+ return -EBUSY;
+}
+
+static int fsldma_resume(struct device *dev)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct fsldma_device *fdev = platform_get_drvdata(pdev);
+ struct fsldma_chan *chan;
+ u32 mode;
+ int i;
+
+ for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
+ chan = fdev->chan[i];
+ if (!chan)
+ continue;
+
+ spin_lock_bh(&chan->desc_lock);
+ mode = chan->regs_save.mr
+ & ~FSL_DMA_MR_CS & ~FSL_DMA_MR_CC & ~FSL_DMA_MR_CA;
+ set_mr(chan, mode);
+ chan->pm_state = RUNNING;
+ spin_unlock_bh(&chan->desc_lock);
+ }
+
+ return 0;
+}
+
+static const struct dev_pm_ops fsldma_pm_ops = {
+ .prepare= fsldma_prepare,
+ .suspend= fsldma_suspend,
+ .resume = fsldma_resume,
+};
+#endif
+
static const struct of_device_id fsldma_of_ids[] = {
{ .compatible = "fsl,elo3-dma", },
{ .compatible = "fsl,eloplus-dma", },
@@ -1463,6 +1560,9 @@ static struct platform_driver fsldma_of_driver = {
.name = "fsl-elo-dma",
.owner = THIS_MODULE,
.of_match_table = fsldma_of_ids,
+#ifdef CONFIG_PM
+ .pm = &fsldma_pm_ops,
+#endif
},
.probe = fsldma_of_probe,
.remove = fsldma_of_remove,
diff --git a/drivers/dma/fsldma.h b/drivers/dma/fsldma.h
index ec19517..eecaf9e 100644
--- a/drivers/dma/fsldma.h
+++ b/drivers/dma/fsldma.h
@@ -134,6 +134,18 @@ struct fsldma_device {
#define FSL_DMA_CHAN_PAUSE_EXT 0x1000
#define FS
[PATCH v4 7/8] DMA: Freescale: use spin_lock_bh instead of spin_lock_irqsave
From: Hongbo Zhang
The usage of spin_lock_irqsave() is a stronger locking mechanism than is
required throughout the driver. The minimum locking required should be used
instead. Interrupts will be turned off and context will be saved, it is
unnecessary to use irqsave.
This patch changes all instances of spin_lock_irqsave() to spin_lock_bh(). All
manipulation of protected fields is done using tasklet context or weaker, which
makes spin_lock_bh() the correct choice.
Signed-off-by: Hongbo Zhang
Signed-off-by: Qiang Liu
---
drivers/dma/fsldma.c | 25 ++---
1 file changed, 10 insertions(+), 15 deletions(-)
diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c
index 374ca97..6e1c9b3 100644
--- a/drivers/dma/fsldma.c
+++ b/drivers/dma/fsldma.c
@@ -396,10 +396,9 @@ static dma_cookie_t fsl_dma_tx_submit(struct
dma_async_tx_descriptor *tx)
struct fsldma_chan *chan = to_fsl_chan(tx->chan);
struct fsl_desc_sw *desc = tx_to_fsl_desc(tx);
struct fsl_desc_sw *child;
- unsigned long flags;
dma_cookie_t cookie = -EINVAL;
- spin_lock_irqsave(&chan->desc_lock, flags);
+ spin_lock_bh(&chan->desc_lock);
/*
* assign cookies to all of the software descriptors
@@ -412,7 +411,7 @@ static dma_cookie_t fsl_dma_tx_submit(struct
dma_async_tx_descriptor *tx)
/* put this transaction onto the tail of the pending queue */
append_ld_queue(chan, desc);
- spin_unlock_irqrestore(&chan->desc_lock, flags);
+ spin_unlock_bh(&chan->desc_lock);
return cookie;
}
@@ -726,15 +725,14 @@ static void fsldma_free_desc_list_reverse(struct
fsldma_chan *chan,
static void fsl_dma_free_chan_resources(struct dma_chan *dchan)
{
struct fsldma_chan *chan = to_fsl_chan(dchan);
- unsigned long flags;
chan_dbg(chan, "free all channel resources\n");
- spin_lock_irqsave(&chan->desc_lock, flags);
+ spin_lock_bh(&chan->desc_lock);
fsldma_cleanup_descriptors(chan);
fsldma_free_desc_list(chan, &chan->ld_pending);
fsldma_free_desc_list(chan, &chan->ld_running);
fsldma_free_desc_list(chan, &chan->ld_completed);
- spin_unlock_irqrestore(&chan->desc_lock, flags);
+ spin_unlock_bh(&chan->desc_lock);
dma_pool_destroy(chan->desc_pool);
chan->desc_pool = NULL;
@@ -953,7 +951,6 @@ static int fsl_dma_device_control(struct dma_chan *dchan,
{
struct dma_slave_config *config;
struct fsldma_chan *chan;
- unsigned long flags;
int size;
if (!dchan)
@@ -963,7 +960,7 @@ static int fsl_dma_device_control(struct dma_chan *dchan,
switch (cmd) {
case DMA_TERMINATE_ALL:
- spin_lock_irqsave(&chan->desc_lock, flags);
+ spin_lock_bh(&chan->desc_lock);
/* Halt the DMA engine */
dma_halt(chan);
@@ -974,7 +971,7 @@ static int fsl_dma_device_control(struct dma_chan *dchan,
fsldma_free_desc_list(chan, &chan->ld_completed);
chan->idle = true;
- spin_unlock_irqrestore(&chan->desc_lock, flags);
+ spin_unlock_bh(&chan->desc_lock);
return 0;
case DMA_SLAVE_CONFIG:
@@ -1016,11 +1013,10 @@ static int fsl_dma_device_control(struct dma_chan
*dchan,
static void fsl_dma_memcpy_issue_pending(struct dma_chan *dchan)
{
struct fsldma_chan *chan = to_fsl_chan(dchan);
- unsigned long flags;
- spin_lock_irqsave(&chan->desc_lock, flags);
+ spin_lock_bh(&chan->desc_lock);
fsl_chan_xfer_ld_queue(chan);
- spin_unlock_irqrestore(&chan->desc_lock, flags);
+ spin_unlock_bh(&chan->desc_lock);
}
/**
@@ -1119,11 +1115,10 @@ static irqreturn_t fsldma_chan_irq(int irq, void *data)
static void dma_do_tasklet(unsigned long data)
{
struct fsldma_chan *chan = (struct fsldma_chan *)data;
- unsigned long flags;
chan_dbg(chan, "tasklet entry\n");
- spin_lock_irqsave(&chan->desc_lock, flags);
+ spin_lock_bh(&chan->desc_lock);
/* the hardware is now idle and ready for more */
chan->idle = true;
@@ -1131,7 +1126,7 @@ static void dma_do_tasklet(unsigned long data)
/* Run all cleanup for descriptors which have been completed */
fsldma_cleanup_descriptors(chan);
- spin_unlock_irqrestore(&chan->desc_lock, flags);
+ spin_unlock_bh(&chan->desc_lock);
chan_dbg(chan, "tasklet exit\n");
}
--
1.7.9.5
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[PATCH v4 6/8] DMA: Freescale: change descriptor release process for supporting async_tx
From: Hongbo Zhang
Fix the potential risk when enable config NET_DMA and ASYNC_TX. Async_tx is
lack of support in current release process of dma descriptor, all descriptors
will be released whatever is acked or no-acked by async_tx, so there is a
potential race condition when dma engine is uesd by others clients (e.g. when
enable NET_DMA to offload TCP).
In our case, a race condition which is raised when use both of talitos and
dmaengine to offload xor is because napi scheduler will sync all pending
requests in dma channels, it affects the process of raid operations due to
ack_tx is not checked in fsl dma. The no-acked descriptor is freed which is
submitted just now, as a dependent tx, this freed descriptor trigger
BUG_ON(async_tx_test_ack(depend_tx)) in async_tx_submit().
TASK = ee1a94a0[1390] 'md0_raid5' THREAD: ecf4 CPU: 0
GPR00: 0001 ecf41ca0 ee44/921a94a0 003f 0001 c00593e4
0001
GPR08: a7a7a7a7 0001 045/92002 42028042 100a38d4 ed576d98
GPR16: ed5a11b0 2b162000 0200 046/92000 2d555000 ed3015e8
c15a7aa0
GPR24: c155fc40 ecb63220 ecf41d28 e47/92f640bb0 ef640c30
ecf41ca0
NIP [c02b048c] async_tx_submit+0x6c/0x2b4
LR [c02b068c] async_tx_submit+0x26c/0x2b4
Call Trace:
[ecf41ca0] [c02b068c] async_tx_submit+0x26c/0x2b448/92 (unreliable)
[ecf41cd0] [c02b0a4c] async_memcpy+0x240/0x25c
[ecf41d20] [c0421064] async_copy_data+0xa0/0x17c
[ecf41d70] [c0421cf4] __raid_run_ops+0x874/0xe10
[ecf41df0] [c0426ee4] handle_stripe+0x820/0x25e8
[ecf41e90] [c0429080] raid5d+0x3d4/0x5b4
[ecf41f40] [c04329b8] md_thread+0x138/0x16c
[ecf41f90] [c008277c] kthread+0x8c/0x90
[ecf41ff0] [c0011630] kernel_thread+0x4c/0x68
Another modification in this patch is the change of completed descriptors,
there is a potential risk which caused by exception interrupt, all descriptors
in ld_running list are seemed completed when an interrupt raised, it works fine
under normal condition, but if there is an exception occured, it cannot work as
our excepted. Hardware should not be depend on s/w list, the right way is to
read current descriptor address register to find the last completed descriptor.
If an interrupt is raised by an error, all descriptors in ld_running should not
be seemed finished, or these unfinished descriptors in ld_running will be
released wrongly.
A simple way to reproduce:
Enable dmatest first, then insert some bad descriptors which can trigger
Programming Error interrupts before the good descriptors. Last, the good
descriptors will be freed before they are processsed because of the exception
intrerrupt.
Note: the bad descriptors are only for simulating an exception interrupt. This
case can illustrate the potential risk in current fsl-dma very well.
Signed-off-by: Hongbo Zhang
Signed-off-by: Qiang Liu
Signed-off-by: Ira W. Snyder
---
drivers/dma/fsldma.c | 197 --
drivers/dma/fsldma.h | 17 -
2 files changed, 159 insertions(+), 55 deletions(-)
diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c
index e0fec68..374ca97 100644
--- a/drivers/dma/fsldma.c
+++ b/drivers/dma/fsldma.c
@@ -459,6 +459,88 @@ static struct fsl_desc_sw *fsl_dma_alloc_descriptor(struct
fsldma_chan *chan)
}
/**
+ * fsldma_clean_completed_descriptor - free all descriptors which
+ * has been completed and acked
+ * @chan: Freescale DMA channel
+ *
+ * This function is used on all completed and acked descriptors.
+ * All descriptors should only be freed in this function.
+ */
+static void fsldma_clean_completed_descriptor(struct fsldma_chan *chan)
+{
+ struct fsl_desc_sw *desc, *_desc;
+
+ /* Run the callback for each descriptor, in order */
+ list_for_each_entry_safe(desc, _desc, &chan->ld_completed, node)
+ if (async_tx_test_ack(&desc->async_tx))
+ fsl_dma_free_descriptor(chan, desc);
+}
+
+/**
+ * fsldma_run_tx_complete_actions - cleanup a single link descriptor
+ * @chan: Freescale DMA channel
+ * @desc: descriptor to cleanup and free
+ * @cookie: Freescale DMA transaction identifier
+ *
+ * This function is used on a descriptor which has been executed by the DMA
+ * controller. It will run any callbacks, submit any dependencies.
+ */
+static dma_cookie_t fsldma_run_tx_complete_actions(struct fsldma_chan *chan,
+ struct fsl_desc_sw *desc, dma_cookie_t cookie)
+{
+ struct dma_async_tx_descriptor *txd = &desc->async_tx;
+ dma_cookie_t ret = cookie;
+
+ BUG_ON(txd->cookie < 0);
+
+ if (txd->cookie > 0) {
+ ret = txd->cookie;
+
+ /* Run the link descriptor callback function */
+ if (txd->callback) {
+ chan_dbg(chan, "LD %p callback\n", desc);
+ txd->callback(txd->callback_param);
+ }
+ }
+
+ /* Run any dependencies */
+ dma_run_dependencies(txd);
+
+ return ret;
+}
+
+/**
+ * fsldma_cl
[PATCH v4 3/8] DMA: Freescale: remove attribute DMA_INTERRUPT of dmaengine
From: Hongbo Zhang
Delete attribute DMA_INTERRUPT because fsldma doesn't support this function,
exception will be thrown if talitos is used to offload xor at the same time.
Signed-off-by: Hongbo Zhang
Signed-off-by: Qiang Liu
---
drivers/dma/fsldma.c | 31 ---
1 file changed, 31 deletions(-)
diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c
index 5f32cb8..b71cc04 100644
--- a/drivers/dma/fsldma.c
+++ b/drivers/dma/fsldma.c
@@ -528,35 +528,6 @@ static void fsl_dma_free_chan_resources(struct dma_chan
*dchan)
}
static struct dma_async_tx_descriptor *
-fsl_dma_prep_interrupt(struct dma_chan *dchan, unsigned long flags)
-{
- struct fsldma_chan *chan;
- struct fsl_desc_sw *new;
-
- if (!dchan)
- return NULL;
-
- chan = to_fsl_chan(dchan);
-
- new = fsl_dma_alloc_descriptor(chan);
- if (!new) {
- chan_err(chan, "%s\n", msg_ld_oom);
- return NULL;
- }
-
- new->async_tx.cookie = -EBUSY;
- new->async_tx.flags = flags;
-
- /* Insert the link descriptor to the LD ring */
- list_add_tail(&new->node, &new->tx_list);
-
- /* Set End-of-link to the last link descriptor of new list */
- set_ld_eol(chan, new);
-
- return &new->async_tx;
-}
-
-static struct dma_async_tx_descriptor *
fsl_dma_prep_memcpy(struct dma_chan *dchan,
dma_addr_t dma_dst, dma_addr_t dma_src,
size_t len, unsigned long flags)
@@ -1308,12 +1279,10 @@ static int fsldma_of_probe(struct platform_device *op)
fdev->irq = irq_of_parse_and_map(op->dev.of_node, 0);
dma_cap_set(DMA_MEMCPY, fdev->common.cap_mask);
- dma_cap_set(DMA_INTERRUPT, fdev->common.cap_mask);
dma_cap_set(DMA_SG, fdev->common.cap_mask);
dma_cap_set(DMA_SLAVE, fdev->common.cap_mask);
fdev->common.device_alloc_chan_resources = fsl_dma_alloc_chan_resources;
fdev->common.device_free_chan_resources = fsl_dma_free_chan_resources;
- fdev->common.device_prep_dma_interrupt = fsl_dma_prep_interrupt;
fdev->common.device_prep_dma_memcpy = fsl_dma_prep_memcpy;
fdev->common.device_prep_dma_sg = fsl_dma_prep_sg;
fdev->common.device_tx_status = fsl_tx_status;
--
1.7.9.5
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[PATCH v4 5/8] DMA: Freescale: move functions to avoid forward declarations
From: Hongbo Zhang
These functions will be modified in the next patch in the series. By moving the
function in a patch separate from the changes, it will make review easier.
Signed-off-by: Hongbo Zhang
Signed-off-by: Qiang Liu
---
drivers/dma/fsldma.c | 190 +-
1 file changed, 95 insertions(+), 95 deletions(-)
diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c
index adc266e..e0fec68 100644
--- a/drivers/dma/fsldma.c
+++ b/drivers/dma/fsldma.c
@@ -459,6 +459,101 @@ static struct fsl_desc_sw
*fsl_dma_alloc_descriptor(struct fsldma_chan *chan)
}
/**
+ * fsl_chan_xfer_ld_queue - transfer any pending transactions
+ * @chan : Freescale DMA channel
+ *
+ * HARDWARE STATE: idle
+ * LOCKING: must hold chan->desc_lock
+ */
+static void fsl_chan_xfer_ld_queue(struct fsldma_chan *chan)
+{
+ struct fsl_desc_sw *desc;
+
+ /*
+* If the list of pending descriptors is empty, then we
+* don't need to do any work at all
+*/
+ if (list_empty(&chan->ld_pending)) {
+ chan_dbg(chan, "no pending LDs\n");
+ return;
+ }
+
+ /*
+* The DMA controller is not idle, which means that the interrupt
+* handler will start any queued transactions when it runs after
+* this transaction finishes
+*/
+ if (!chan->idle) {
+ chan_dbg(chan, "DMA controller still busy\n");
+ return;
+ }
+
+ /*
+* If there are some link descriptors which have not been
+* transferred, we need to start the controller
+*/
+
+ /*
+* Move all elements from the queue of pending transactions
+* onto the list of running transactions
+*/
+ chan_dbg(chan, "idle, starting controller\n");
+ desc = list_first_entry(&chan->ld_pending, struct fsl_desc_sw, node);
+ list_splice_tail_init(&chan->ld_pending, &chan->ld_running);
+
+ /*
+* The 85xx DMA controller doesn't clear the channel start bit
+* automatically at the end of a transfer. Therefore we must clear
+* it in software before starting the transfer.
+*/
+ if ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) {
+ u32 mode;
+
+ mode = get_mr(chan);
+ mode &= ~FSL_DMA_MR_CS;
+ set_mr(chan, mode);
+ }
+
+ /*
+* Program the descriptor's address into the DMA controller,
+* then start the DMA transaction
+*/
+ set_cdar(chan, desc->async_tx.phys);
+ get_cdar(chan);
+
+ dma_start(chan);
+ chan->idle = false;
+}
+
+/**
+ * fsldma_cleanup_descriptor - cleanup and free a single link descriptor
+ * @chan: Freescale DMA channel
+ * @desc: descriptor to cleanup and free
+ *
+ * This function is used on a descriptor which has been executed by the DMA
+ * controller. It will run any callbacks, submit any dependencies, and then
+ * free the descriptor.
+ */
+static void fsldma_cleanup_descriptor(struct fsldma_chan *chan,
+ struct fsl_desc_sw *desc)
+{
+ struct dma_async_tx_descriptor *txd = &desc->async_tx;
+
+ /* Run the link descriptor callback function */
+ if (txd->callback) {
+ chan_dbg(chan, "LD %p callback\n", desc);
+ txd->callback(txd->callback_param);
+ }
+
+ /* Run any dependencies */
+ dma_run_dependencies(txd);
+
+ dma_descriptor_unmap(txd);
+ chan_dbg(chan, "LD %p free\n", desc);
+ dma_pool_free(chan->desc_pool, desc, txd->phys);
+}
+
+/**
* fsl_dma_alloc_chan_resources - Allocate resources for DMA channel.
* @chan : Freescale DMA channel
*
@@ -803,101 +898,6 @@ static int fsl_dma_device_control(struct dma_chan *dchan,
}
/**
- * fsldma_cleanup_descriptor - cleanup and free a single link descriptor
- * @chan: Freescale DMA channel
- * @desc: descriptor to cleanup and free
- *
- * This function is used on a descriptor which has been executed by the DMA
- * controller. It will run any callbacks, submit any dependencies, and then
- * free the descriptor.
- */
-static void fsldma_cleanup_descriptor(struct fsldma_chan *chan,
- struct fsl_desc_sw *desc)
-{
- struct dma_async_tx_descriptor *txd = &desc->async_tx;
-
- /* Run the link descriptor callback function */
- if (txd->callback) {
- chan_dbg(chan, "LD %p callback\n", desc);
- txd->callback(txd->callback_param);
- }
-
- /* Run any dependencies */
- dma_run_dependencies(txd);
-
- dma_descriptor_unmap(txd);
- chan_dbg(chan, "LD %p free\n", desc);
- dma_pool_free(chan->desc_pool, desc, txd->phys);
-}
-
-/**
- * fsl_chan_xfer_ld_queue - transfer any pending transactions
- * @chan : Freescale DMA channel
- *
- * HARDWARE STATE: idle
- * LOCKING: must hold chan->desc_lock
- */
-static void fs
[PATCH v4 4/8] DMA: Freescale: add fsl_dma_free_descriptor() to reduce code duplication
From: Hongbo Zhang
There are several places where descriptors are freed using identical code.
This patch puts this code into a function to reduce code duplication.
Signed-off-by: Hongbo Zhang
Signed-off-by: Qiang Liu
---
drivers/dma/fsldma.c | 27 +--
1 file changed, 17 insertions(+), 10 deletions(-)
diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c
index b71cc04..adc266e 100644
--- a/drivers/dma/fsldma.c
+++ b/drivers/dma/fsldma.c
@@ -418,6 +418,19 @@ static dma_cookie_t fsl_dma_tx_submit(struct
dma_async_tx_descriptor *tx)
}
/**
+ * fsl_dma_free_descriptor - Free descriptor from channel's DMA pool.
+ * @chan : Freescale DMA channel
+ * @desc: descriptor to be freed
+ */
+static void fsl_dma_free_descriptor(struct fsldma_chan *chan,
+ struct fsl_desc_sw *desc)
+{
+ list_del(&desc->node);
+ chan_dbg(chan, "LD %p free\n", desc);
+ dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
+}
+
+/**
* fsl_dma_alloc_descriptor - Allocate descriptor from channel's DMA pool.
* @chan : Freescale DMA channel
*
@@ -489,11 +502,8 @@ static void fsldma_free_desc_list(struct fsldma_chan *chan,
{
struct fsl_desc_sw *desc, *_desc;
- list_for_each_entry_safe(desc, _desc, list, node) {
- list_del(&desc->node);
- chan_dbg(chan, "LD %p free\n", desc);
- dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
- }
+ list_for_each_entry_safe(desc, _desc, list, node)
+ fsl_dma_free_descriptor(chan, desc);
}
static void fsldma_free_desc_list_reverse(struct fsldma_chan *chan,
@@ -501,11 +511,8 @@ static void fsldma_free_desc_list_reverse(struct
fsldma_chan *chan,
{
struct fsl_desc_sw *desc, *_desc;
- list_for_each_entry_safe_reverse(desc, _desc, list, node) {
- list_del(&desc->node);
- chan_dbg(chan, "LD %p free\n", desc);
- dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
- }
+ list_for_each_entry_safe_reverse(desc, _desc, list, node)
+ fsl_dma_free_descriptor(chan, desc);
}
/**
--
1.7.9.5
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[PATCH v4 2/8] DMA: Freescale: unify register access methods
From: Hongbo Zhang
Methods of accessing DMA controller registers are inconsistent, some registers
are accessed by DMA_IN/OUT directly, while others are accessed by functions
get/set_* which are wrappers of DMA_IN/OUT, and even for the BCR register, it
is read by get_bcr but written by DMA_OUT.
This patch unifies the inconsistent methods, all registers are accessed by
get/set_* now.
Signed-off-by: Hongbo Zhang
---
drivers/dma/fsldma.c | 52 --
1 file changed, 33 insertions(+), 19 deletions(-)
diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c
index ec50420..5f32cb8 100644
--- a/drivers/dma/fsldma.c
+++ b/drivers/dma/fsldma.c
@@ -61,6 +61,16 @@ static u32 get_sr(struct fsldma_chan *chan)
return DMA_IN(chan, &chan->regs->sr, 32);
}
+static void set_mr(struct fsldma_chan *chan, u32 val)
+{
+ DMA_OUT(chan, &chan->regs->mr, val, 32);
+}
+
+static u32 get_mr(struct fsldma_chan *chan)
+{
+ return DMA_IN(chan, &chan->regs->mr, 32);
+}
+
static void set_cdar(struct fsldma_chan *chan, dma_addr_t addr)
{
DMA_OUT(chan, &chan->regs->cdar, addr | FSL_DMA_SNEN, 64);
@@ -71,6 +81,11 @@ static dma_addr_t get_cdar(struct fsldma_chan *chan)
return DMA_IN(chan, &chan->regs->cdar, 64) & ~FSL_DMA_SNEN;
}
+static void set_bcr(struct fsldma_chan *chan, u32 val)
+{
+ DMA_OUT(chan, &chan->regs->bcr, val, 32);
+}
+
static u32 get_bcr(struct fsldma_chan *chan)
{
return DMA_IN(chan, &chan->regs->bcr, 32);
@@ -135,7 +150,7 @@ static void set_ld_eol(struct fsldma_chan *chan, struct
fsl_desc_sw *desc)
static void dma_init(struct fsldma_chan *chan)
{
/* Reset the channel */
- DMA_OUT(chan, &chan->regs->mr, 0, 32);
+ set_mr(chan, 0);
switch (chan->feature & FSL_DMA_IP_MASK) {
case FSL_DMA_IP_85XX:
@@ -144,16 +159,15 @@ static void dma_init(struct fsldma_chan *chan)
* EOLNIE - End of links interrupt enable
* BWC - Bandwidth sharing among channels
*/
- DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_BWC
- | FSL_DMA_MR_EIE | FSL_DMA_MR_EOLNIE, 32);
+ set_mr(chan, FSL_DMA_MR_BWC | FSL_DMA_MR_EIE
+ | FSL_DMA_MR_EOLNIE);
break;
case FSL_DMA_IP_83XX:
/* Set the channel to below modes:
* EOTIE - End-of-transfer interrupt enable
* PRC_RM - PCI read multiple
*/
- DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_EOTIE
- | FSL_DMA_MR_PRC_RM, 32);
+ set_mr(chan, FSL_DMA_MR_EOTIE | FSL_DMA_MR_PRC_RM);
break;
}
}
@@ -175,10 +189,10 @@ static void dma_start(struct fsldma_chan *chan)
{
u32 mode;
- mode = DMA_IN(chan, &chan->regs->mr, 32);
+ mode = get_mr(chan);
if (chan->feature & FSL_DMA_CHAN_PAUSE_EXT) {
- DMA_OUT(chan, &chan->regs->bcr, 0, 32);
+ set_bcr(chan, 0);
mode |= FSL_DMA_MR_EMP_EN;
} else {
mode &= ~FSL_DMA_MR_EMP_EN;
@@ -191,7 +205,7 @@ static void dma_start(struct fsldma_chan *chan)
mode |= FSL_DMA_MR_CS;
}
- DMA_OUT(chan, &chan->regs->mr, mode, 32);
+ set_mr(chan, mode);
}
static void dma_halt(struct fsldma_chan *chan)
@@ -200,7 +214,7 @@ static void dma_halt(struct fsldma_chan *chan)
int i;
/* read the mode register */
- mode = DMA_IN(chan, &chan->regs->mr, 32);
+ mode = get_mr(chan);
/*
* The 85xx controller supports channel abort, which will stop
@@ -209,14 +223,14 @@ static void dma_halt(struct fsldma_chan *chan)
*/
if ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) {
mode |= FSL_DMA_MR_CA;
- DMA_OUT(chan, &chan->regs->mr, mode, 32);
+ set_mr(chan, mode);
mode &= ~FSL_DMA_MR_CA;
}
/* stop the DMA controller */
mode &= ~(FSL_DMA_MR_CS | FSL_DMA_MR_EMS_EN);
- DMA_OUT(chan, &chan->regs->mr, mode, 32);
+ set_mr(chan, mode);
/* wait for the DMA controller to become idle */
for (i = 0; i < 100; i++) {
@@ -245,7 +259,7 @@ static void fsl_chan_set_src_loop_size(struct fsldma_chan
*chan, int size)
{
u32 mode;
- mode = DMA_IN(chan, &chan->regs->mr, 32);
+ mode = get_mr(chan);
switch (size) {
case 0:
@@ -259,7 +273,7 @@ static void fsl_chan_set_src_loop_size(struct fsldma_chan
*chan, int size)
break;
}
- DMA_OUT(chan, &chan->regs->mr, mode, 32);
+ set_mr(chan, mode);
}
/**
@@ -277,7 +291,7 @@ static void fsl_chan_set_dst_loop_size(struct fsldma_chan
*chan, int size)
{
u32 mode;
- mode = DMA_IN(chan, &chan->regs->mr, 32);
+ mode = get_mr(chan);
switch (size) {
[PATCH v4 1/8] DMA: Freescale: remove the unnecessary FSL_DMA_LD_DEBUG
From: Hongbo Zhang
Some codes are calling chan_dbg with FSL_DMA_LD_DEBUG surrounded, it is really
unnecessary to use such a macro because chan_dbg is a wrapper of dev_dbg, we do
have corresponding DEBUG macro to switch on/off dev_dbg, and most of the other
codes are also calling chan_dbg directly without using FSL_DMA_LD_DEBUG.
Signed-off-by: Hongbo Zhang
---
drivers/dma/fsldma.c | 10 --
1 file changed, 10 deletions(-)
diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c
index f157c6f..ec50420 100644
--- a/drivers/dma/fsldma.c
+++ b/drivers/dma/fsldma.c
@@ -426,9 +426,7 @@ static struct fsl_desc_sw *fsl_dma_alloc_descriptor(struct
fsldma_chan *chan)
desc->async_tx.tx_submit = fsl_dma_tx_submit;
desc->async_tx.phys = pdesc;
-#ifdef FSL_DMA_LD_DEBUG
chan_dbg(chan, "LD %p allocated\n", desc);
-#endif
return desc;
}
@@ -479,9 +477,7 @@ static void fsldma_free_desc_list(struct fsldma_chan *chan,
list_for_each_entry_safe(desc, _desc, list, node) {
list_del(&desc->node);
-#ifdef FSL_DMA_LD_DEBUG
chan_dbg(chan, "LD %p free\n", desc);
-#endif
dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
}
}
@@ -493,9 +489,7 @@ static void fsldma_free_desc_list_reverse(struct
fsldma_chan *chan,
list_for_each_entry_safe_reverse(desc, _desc, list, node) {
list_del(&desc->node);
-#ifdef FSL_DMA_LD_DEBUG
chan_dbg(chan, "LD %p free\n", desc);
-#endif
dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
}
}
@@ -832,9 +826,7 @@ static void fsldma_cleanup_descriptor(struct fsldma_chan
*chan,
/* Run the link descriptor callback function */
if (txd->callback) {
-#ifdef FSL_DMA_LD_DEBUG
chan_dbg(chan, "LD %p callback\n", desc);
-#endif
txd->callback(txd->callback_param);
}
@@ -842,9 +834,7 @@ static void fsldma_cleanup_descriptor(struct fsldma_chan
*chan,
dma_run_dependencies(txd);
dma_descriptor_unmap(txd);
-#ifdef FSL_DMA_LD_DEBUG
chan_dbg(chan, "LD %p free\n", desc);
-#endif
dma_pool_free(chan->desc_pool, desc, txd->phys);
}
--
1.7.9.5
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[PATCH v4 0/8] DMA: Freescale: driver cleanups and enhancements
From: Hongbo Zhang Hi Vinod Koul, Please have a look at the v4 patch set. v3 -> v4 changes: - Fixed a typo in [2/8] commit message. - There was a potential double call of list_del() when apply [4/8] only, although this defect is removed again in later [6/8]. This version eliminates this problem by updating [4/8] and [6/8] slightly. - Updated [8/8] to use register access method introduced by [2/8] v2 -> v3 change: Only add "chan->pm_state = RUNNING" for patch[8/8]. v1 -> v2 change: The only one change is introducing a new patch[1/7] to remove the unnecessary macro FSL_DMA_LD_DEBUG, thus the total patches number is 8 now (was 7) v1 notes: Note that patch 2~6 had beed sent out for upstream before, but were together with other storage patches at that time, that was not easy for being reviewed and merged, so I send them separately this time. Hongbo Zhang (8): DMA: Freescale: remove the unnecessary FSL_DMA_LD_DEBUG DMA: Freescale: unify register access methods DMA: Freescale: remove attribute DMA_INTERRUPT of dmaengine DMA: Freescale: add fsl_dma_free_descriptor() to reduce code duplication DMA: Freescale: move functions to avoid forward declarations DMA: Freescale: change descriptor release process for supporting async_tx DMA: Freescale: use spin_lock_bh instead of spin_lock_irqsave DMA: Freescale: add suspend resume functions for DMA driver drivers/dma/fsldma.c | 592 -- drivers/dma/fsldma.h | 33 ++- 2 files changed, 410 insertions(+), 215 deletions(-) -- 1.7.9.5 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 3/3] of: Handle memory@0 node on PPC32 only
Hi Leif,
On Thu, Apr 17, 2014 at 7:42 PM, Leif Lindholm wrote:
> In order to deal with an firmware bug on a specific ppc32 platform
> (longtrail), early_init_dt_scan_memory() looks for a node called
> memory@0 on all platforms. Restrict this quirk to ppc32 kernels only.
This breaks backwards compatibilty with old DTSes (at least on ARM/MIPS,
where you added the missing property in patches 1 and 2 of the series)?
For the Longtrail, I don't care much anymore, as mine died in 2004.
AFAIK, there have never been many users anyway.
> Signed-off-by: Leif Lindholm
> Cc: linuxppc-dev@lists.ozlabs.org
> Cc: Grant Likely
> Cc: Mark Rutland
> Cc: devicet...@vger.kernel.org
> Cc: linux-ker...@vger.kernel.org
> ---
> drivers/of/fdt.c |7 ++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/of/fdt.c b/drivers/of/fdt.c
> index fa16a91..7368472 100644
> --- a/drivers/of/fdt.c
> +++ b/drivers/of/fdt.c
> @@ -887,14 +887,19 @@ int __init early_init_dt_scan_memory(unsigned long
> node, const char *uname,
>
> /* We are scanning "memory" nodes only */
> if (type == NULL) {
> +#ifdef CONFIG_PPC32
> /*
> * The longtrail doesn't have a device_type on the
> * /memory node, so look for the node called /memory@0.
> */
> if (depth != 1 || strcmp(uname, "memory@0") != 0)
> return 0;
> - } else if (strcmp(type, "memory") != 0)
> +#else
> + return 0;
> +#endif
> + } else if (strcmp(type, "memory") != 0) {
> return 0;
> + }
>
> reg = of_get_flat_dt_prop(node, "linux,usable-memory", &l);
> if (reg == NULL)
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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