Re: [RFC PATCH] powerpc: Make SPU_FS depend on SPARSEMEM
Hi Pranith,
On Tue, Aug 19, 2014 at 11:16 PM, Pranith Kumar bobby.pr...@gmail.com wrote:
SPU_FS unconditionally enables MEMORY_HOTPLUG, which will fail to build if
SPARSEMEM=n.
Make SPU_FS depend on SPARSEMEM so that hotplug-memory.c does not fail to
compile.
Signed-off-by: Pranith Kumar bobby.pr...@gmail.com
---
arch/powerpc/platforms/cell/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/platforms/cell/Kconfig
b/arch/powerpc/platforms/cell/Kconfig
index 9978f59..832872e 100644
--- a/arch/powerpc/platforms/cell/Kconfig
+++ b/arch/powerpc/platforms/cell/Kconfig
@@ -60,7 +60,7 @@ menu Cell Broadband Engine options
config SPU_FS
tristate SPU file system
default m
- depends on PPC_CELL
+ depends on PPC_CELL SPARSEMEM
select SPU_BASE
select MEMORY_HOTPLUG
help
--
1.9.1
Is this a randconfig kernel?
config ARCH_SPARSEMEM_DEFAULT
def_bool y
depends on (SMP PPC_PSERIES) || PPC_PS3
Why is this not enabled? !SMP? !PPC_PSERIES? !PPC_PS3?
If PPC_CELL is enabled, this issue was introduced by
commit 78bde53e351bc89cff85d1c2c7e6d7c2ffdf120d
Author: Benjamin Herrenschmidt b...@kernel.crashing.org
Date: Tue Feb 13 11:46:06 2007 +1100
[POWERPC] spufs: remove need for struct page for SPEs
This patch removes the need for struct page for SPE local store
and registers from spufs. It also makes the locking much more
obvious and no longer relying on the truncate logic black magic
for protecting against races between unmap_mapping_range() and
new pages faulted in. It does so by switching to a nopfn() handler
and using the new vm_insert_pfn() to setup the PTEs itself while
holding a lock on the SPE.
The nice thing is that this patch actually removes a lot more code
than it adds :-)
Signed-off-by: Benjamin Herrenschmidt b...@kernel.crashing.org
Signed-off-by: Paul Mackerras pau...@samba.org
Another question: why does SPU_FS select MEMORY_HOTPLUG?
commit 4da30d15b6d5036b0d96422d6946ca758111fae3
Author: Geoff Levand geoffrey.lev...@am.sony.com
Date: Fri Jun 23 20:57:49 2006 +0200
[POWERPC] spufs: fix memory hotplug dependency
spufs_base.c calls __add_pages, which depends on CONFIG_MEMORY_HOTPLUG.
Moved the selection of CONFIG_MEMORY_HOTPLUG from CONFIG_SPUFS_MMAP
to CONFIG_SPU_FS.
Signed-off-by: Geoff Levand geoffrey.lev...@am.sony.com
Signed-off-by: Arnd Bergmann arnd.bergm...@de.ibm.com
Signed-off-by: Paul Mackerras pau...@samba.org
However, the call to __add_pages() has been moved a few times afterwards,
to be finally removed in the aforementioned commit
78bde53e351bc89cff85d1c2c7e6d7c2ffdf120d.
Does it still build/work if you just drop the select MEMORY_HOTPLUG?
Gr{oetje,eeting}s,
Geert
--
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when I'm talking to journalists I just say programmer or something like that.
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Re: [PATCH] powerpc: Fix build failure when MEMORY_HOTPLUG=y
On Tue, Aug 19, 2014 at 11:01 PM, Pranith Kumar bobby.pr...@gmail.com wrote:
ARCH_ENABLE_MEMORY_HOTPLUG is enabled by default for powerpc. This causes
build
failures when SPARSEMEM=n as memory hotplug needs definition which are defined
only when SPARSEMEM=y. The error is as follows:
arch/powerpc/platforms/pseries/hotplug-memory.c:27:31: error:
'SECTION_SIZE_BITS' undeclared (first use in this function)
arch/powerpc/platforms/pseries/hotplug-memory.c:27:31: note: each undeclared
identifier is reported only once for each function it appears in
arch/powerpc/platforms/pseries/hotplug-memory.c: In function
'pseries_remove_memblock':
arch/powerpc/platforms/pseries/hotplug-memory.c:98:34: error:
'SECTION_SIZE_BITS' undeclared (first use in this function)
make[2]: *** [arch/powerpc/platforms/pseries/hotplug-memory.o] Error 1
Signed-off-by: Pranith Kumar bobby.pr...@gmail.com
CC: Andew Morton a...@linux-foundation.org
---
arch/powerpc/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 9c1aa77..da16ffe 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -383,6 +383,7 @@ config ARCH_CPU_PROBE_RELEASE
config ARCH_ENABLE_MEMORY_HOTPLUG
def_bool y
+ depends on SPARSEMEM
config ARCH_HAS_WALK_MEMORY
def_bool y
--
1.9.1
In light of my investigation for your spufs patch, I guess this is a non-SMP
PSERIES config?
Gr{oetje,eeting}s,
Geert
--
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In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say programmer or something like that.
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[RFC PATCH 6/6] rtc: rtc-isl12057: Change vendor prefix for Intersil Corporation to isil
Currently there is a wild mixture of isl, isil, and intersil
compatibles in the kernel. At this point, changing the vendor
symbol to the most often used variant, which is equal to the
NASDAQ symbol, isil, should not hurt, since the isl1208 driver
doesn't care either way.
Patch 70e123373c05 added this driver with device tree support
using the then documented isl vendor prefix, so we keep that
around for backwards compatibility.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
drivers/rtc/rtc-isl12057.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/rtc/rtc-isl12057.c b/drivers/rtc/rtc-isl12057.c
index 455b601..8276bd6 100644
--- a/drivers/rtc/rtc-isl12057.c
+++ b/drivers/rtc/rtc-isl12057.c
@@ -279,7 +279,8 @@ static int isl12057_probe(struct i2c_client *client,
#ifdef CONFIG_OF
static const struct of_device_id isl12057_dt_match[] = {
- { .compatible = isl,isl12057 },
+ { .compatible = isil,isl12057 },
+ { .compatible = isl,isl12057 }, /* for backwards compatibility */
{ },
};
#endif
--
2.1.0.rc1
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[RFC PATCH 4/6] powerpc/85xx: Change vendor prefix for Intersil Corporation to isil
Currently there is a wild mixture of isl, isil, and intersil
compatibles in the kernel. At this point, changing the vendor
symbol to the most often used variant, which is equal to the
NASDAQ symbol, isil, should not hurt, since the isl1208 driver
doesn't care either way.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
arch/powerpc/boot/dts/ppa8548.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/boot/dts/ppa8548.dts
b/arch/powerpc/boot/dts/ppa8548.dts
index 27b0699..000262b 100644
--- a/arch/powerpc/boot/dts/ppa8548.dts
+++ b/arch/powerpc/boot/dts/ppa8548.dts
@@ -89,7 +89,7 @@
soc {
i2c@3000 {
rtc@6f {
- compatible = intersil,isl1208;
+ compatible = isil,isl1208;
reg = 0x6f;
};
};
--
2.1.0.rc1
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[RFC PATCH 2/6] Documentation: Add isl1208 and isl12022 to trivial-devices list
This patch adds the Intersil ISL1208 and ISL12022 I2C RTCs to the trivial-devices list. Signed-off-by: Philipp Zabel p.za...@pengutronix.de --- Documentation/devicetree/bindings/i2c/trivial-devices.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/i2c/trivial-devices.txt b/Documentation/devicetree/bindings/i2c/trivial-devices.txt index 6504297..ec4c6b2 100644 --- a/Documentation/devicetree/bindings/i2c/trivial-devices.txt +++ b/Documentation/devicetree/bindings/i2c/trivial-devices.txt @@ -56,6 +56,8 @@ fsl,sgtl5000 SGTL5000: Ultra Low-Power Audio Codec gmt,g751 G751: Digital Temperature Sensor and Thermal Watchdog with Two-Wire Interface infineon,slb9635tt Infineon SLB9635 (Soft-) I2C TPM (old protocol, max 100khz) infineon,slb9645tt Infineon SLB9645 I2C TPM (new protocol, max 400khz) +isil,isl1208 Intersil ISL1208 I2C RTC Chip +isil,isl12022 Intersil ISL12022 I2C RTC Chip isil,isl12057 Intersil ISL12057 I2C RTC Chip maxim,ds1050 5 Bit Programmable, Pulse-Width Modulator maxim,max1237 Low-Power, 4-/12-Channel, 2-Wire Serial, 12-Bit ADCs -- 2.1.0.rc1 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[RFC PATCH 1/6] of: Change vendor prefix for Intersil Corporation to isil
Currently there is a wild mixture of isl, isil, and intersil compatibles in the kernel. At this point, changing the vendor symbol to the most often used variant, which is equal to the NASDAQ symbol, isil, should not hurt. Signed-off-by: Philipp Zabel p.za...@pengutronix.de --- Documentation/devicetree/bindings/i2c/trivial-devices.txt | 2 +- Documentation/devicetree/bindings/vendor-prefixes.txt | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/i2c/trivial-devices.txt b/Documentation/devicetree/bindings/i2c/trivial-devices.txt index 6af570e..6504297 100644 --- a/Documentation/devicetree/bindings/i2c/trivial-devices.txt +++ b/Documentation/devicetree/bindings/i2c/trivial-devices.txt @@ -56,7 +56,7 @@ fsl,sgtl5000 SGTL5000: Ultra Low-Power Audio Codec gmt,g751 G751: Digital Temperature Sensor and Thermal Watchdog with Two-Wire Interface infineon,slb9635tt Infineon SLB9635 (Soft-) I2C TPM (old protocol, max 100khz) infineon,slb9645tt Infineon SLB9645 I2C TPM (new protocol, max 400khz) -isl,isl12057 Intersil ISL12057 I2C RTC Chip +isil,isl12057 Intersil ISL12057 I2C RTC Chip maxim,ds1050 5 Bit Programmable, Pulse-Width Modulator maxim,max1237 Low-Power, 4-/12-Channel, 2-Wire Serial, 12-Bit ADCs maxim,max6625 9-Bit/12-Bit Temperature Sensors with I²C-Compatible Serial Interface diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index ac7269f..938e0ce 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -68,7 +68,7 @@ img Imagination Technologies Ltd. intel Intel Corporation intercontrol Inter Control Group isee ISEE 2007 S.L. -islIntersil +isil Intersil Corporation karo Ka-Ro electronics GmbH keymileKeymile GmbH lacie LaCie -- 2.1.0.rc1 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[RFC PATCH 3/6] ARM: mvebu: Change vendor prefix for Intersil Corporation to isil
Currently there is a wild mixture of isl, isil, and intersil
compatibles in the kernel. At this point, changing the vendor
symbol to the most often used variant, which is equal to the
NASDAQ symbol, isil, should not hurt.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
arch/arm/boot/dts/armada-370-netgear-rn102.dts | 2 +-
arch/arm/boot/dts/armada-370-netgear-rn104.dts | 2 +-
arch/arm/boot/dts/armada-xp-netgear-rn2120.dts | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/armada-370-netgear-rn102.dts
b/arch/arm/boot/dts/armada-370-netgear-rn102.dts
index d6d572e..edc381c 100644
--- a/arch/arm/boot/dts/armada-370-netgear-rn102.dts
+++ b/arch/arm/boot/dts/armada-370-netgear-rn102.dts
@@ -122,7 +122,7 @@
status = okay;
isl12057: isl12057@68 {
- compatible = isl,isl12057;
+ compatible = isil,isl12057;
reg = 0x68;
};
diff --git a/arch/arm/boot/dts/armada-370-netgear-rn104.dts
b/arch/arm/boot/dts/armada-370-netgear-rn104.dts
index c5fe8b5..7367b4c 100644
--- a/arch/arm/boot/dts/armada-370-netgear-rn104.dts
+++ b/arch/arm/boot/dts/armada-370-netgear-rn104.dts
@@ -117,7 +117,7 @@
status = okay;
isl12057: isl12057@68 {
- compatible = isl,isl12057;
+ compatible = isil,isl12057;
reg = 0x68;
};
diff --git a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
index 0cf999a..252def8 100644
--- a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
+++ b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
@@ -174,7 +174,7 @@
status = okay;
isl12057: isl12057@68 {
- compatible = isl,isl12057;
+ compatible = isil,isl12057;
reg = 0x68;
};
--
2.1.0.rc1
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[RFC PATCH 5/6] rtc: rtc-isl12022: Change vendor prefix for Intersil Corporation to isil
Currently there is a wild mixture of isl, isil, and intersil
compatibles in the kernel. At this point, changing the vendor
symbol to the most often used variant, which is equal to the
NASDAQ symbol, isil, should not hurt, since the isl1208 driver
doesn't care either way.
Patch db04d6284e2a added device tree support using the then
documented isl vendor prefix, so we keep that around for
backwards compatibility.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
drivers/rtc/rtc-isl12022.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/rtc/rtc-isl12022.c b/drivers/rtc/rtc-isl12022.c
index aa55f08..df20f18 100644
--- a/drivers/rtc/rtc-isl12022.c
+++ b/drivers/rtc/rtc-isl12022.c
@@ -275,7 +275,8 @@ static int isl12022_probe(struct i2c_client *client,
#ifdef CONFIG_OF
static struct of_device_id isl12022_dt_match[] = {
- { .compatible = isl,isl12022 },
+ { .compatible = isil,isl12022 },
+ { .compatible = isl,isl12022 }, /* for backwards compatibility */
{ },
};
#endif
--
2.1.0.rc1
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[RFC PATCH 0/6] Change vendor prefix for Intersil Corporation
Hi, currently there is a wild mixture of isl, isil, and intersil compatibles in the kernel. I figure at this point it is still possible to change this to use isil everywhere without too much pain, but it might be preferred to keep the already documented isl prefix, even though it doesn't follow the convention to use the NASDAQ symbol where available. The current users of the isil prefix are the following drivers and device trees, so we could just as well change those instead: arch/arm/boot/dts/tegra20-seaboard.dts arch/arm/boot/dts/tegra20-ventana.dts arch/arm/boot/dts/tegra30-cardhu.dtsi arch/powerpc/boot/dts/p1022rdk.dts drivers/staging/iio/light/isl29018.c drivers/staging/iio/light/isl29028.c regards Philipp Philipp Zabel (6): of: Change vendor prefix for Intersil Corporation to isil Documentation: Add isl1208 and isl12022 to trivial-devices list ARM: mvebu: Change vendor prefix for Intersil Corporation to isil powerpc/85xx: Change vendor prefix for Intersil Corporation to isil rtc: rtc-isl12022: Change vendor prefix for Intersil Corporation to isil rtc: rtc-isl12057: Change vendor prefix for Intersil Corporation to isil Documentation/devicetree/bindings/i2c/trivial-devices.txt | 4 +++- Documentation/devicetree/bindings/vendor-prefixes.txt | 2 +- arch/arm/boot/dts/armada-370-netgear-rn102.dts| 2 +- arch/arm/boot/dts/armada-370-netgear-rn104.dts| 2 +- arch/arm/boot/dts/armada-xp-netgear-rn2120.dts| 2 +- arch/powerpc/boot/dts/ppa8548.dts | 2 +- drivers/rtc/rtc-isl12022.c| 3 ++- drivers/rtc/rtc-isl12057.c| 3 ++- 8 files changed, 12 insertions(+), 8 deletions(-) -- 2.1.0.rc1 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [RFC PATCH 6/6] rtc: rtc-isl12057: Change vendor prefix for Intersil Corporation to isil
Hello. On 8/20/2014 12:43 PM, Philipp Zabel wrote: Currently there is a wild mixture of isl, isil, and intersil compatibles in the kernel. At this point, changing the vendor symbol to the most often used variant, which is equal to the NASDAQ symbol, isil, should not hurt, since the isl1208 driver doesn't care either way. Patch 70e123373c05 added this driver with device tree support Please also specify that commit's summary line in parens. using the then documented isl vendor prefix, so we keep that around for backwards compatibility. Signed-off-by: Philipp Zabel p.za...@pengutronix.de WBR, Sergei ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 1/2] fsl_ifc: Fix csor_ext position in fsl_ifc_regs
On 8/16/2014 2:37 AM, Aaron Sierra wrote: According to Freescale manuals, the IFC_CSORn_EXT register is located immediately _after_ the bank's IFC_CSORn register. This patch adjusts the csor_ext member of and reserved register arrays immediately surrounding the csor_cs structure to provide proper access to this register. Signed-off-by: Aaron Sierra asie...@xes-inc.com --- Thanks for fixing it. Acked-by: Prabhakar Kushwaha prabha...@freescale.com Thanks, Prabhakar ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v2 2/2] powerpc/booke: Revert SPE/AltiVec common defines for interrupt numbers
Book3E specification defines shared interrupt numbers for SPE and AltiVec units. Still SPE is present in e200/e500v2 cores while AltiVec is present in e6500 core. So we can currently decide at compile-time which unit to support exclusively. As Alexander Graf suggested, this will improve code readability especially in KVM. Use distinct defines to identify SPE/AltiVec interrupt numbers, reverting c58ce397 and 6b310fc5 patches that added common defines. Signed-off-by: Mihai Caraman mihai.cara...@freescale.com Cc: Scott Wood scottw...@freescale.com Cc: Alexander Graf ag...@suse.de --- arch/powerpc/kernel/exceptions-64e.S | 4 ++-- arch/powerpc/kernel/head_fsl_booke.S | 8 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/powerpc/kernel/exceptions-64e.S b/arch/powerpc/kernel/exceptions-64e.S index bb9cac6..3e68d1c 100644 --- a/arch/powerpc/kernel/exceptions-64e.S +++ b/arch/powerpc/kernel/exceptions-64e.S @@ -635,7 +635,7 @@ interrupt_end_book3e: /* Altivec Unavailable Interrupt */ START_EXCEPTION(altivec_unavailable); - NORMAL_EXCEPTION_PROLOG(0x200, BOOKE_INTERRUPT_SPE_ALTIVEC_UNAVAIL, + NORMAL_EXCEPTION_PROLOG(0x200, BOOKE_INTERRUPT_ALTIVEC_UNAVAIL, PROLOG_ADDITION_NONE) /* we can probably do a shorter exception entry for that one... */ EXCEPTION_COMMON(0x200) @@ -658,7 +658,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) /* AltiVec Assist */ START_EXCEPTION(altivec_assist); NORMAL_EXCEPTION_PROLOG(0x220, - BOOKE_INTERRUPT_SPE_FP_DATA_ALTIVEC_ASSIST, + BOOKE_INTERRUPT_ALTIVEC_ASSIST, PROLOG_ADDITION_NONE) EXCEPTION_COMMON(0x220) INTS_DISABLE diff --git a/arch/powerpc/kernel/head_fsl_booke.S b/arch/powerpc/kernel/head_fsl_booke.S index 90f487f..fffd1f9 100644 --- a/arch/powerpc/kernel/head_fsl_booke.S +++ b/arch/powerpc/kernel/head_fsl_booke.S @@ -617,27 +617,27 @@ END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV) #ifdef CONFIG_SPE /* SPE Unavailable */ START_EXCEPTION(SPEUnavailable) - NORMAL_EXCEPTION_PROLOG(SPE_ALTIVEC_UNAVAIL) + NORMAL_EXCEPTION_PROLOG(SPE_UNAVAIL) beq 1f bl load_up_spe b fast_exception_return 1: addir3,r1,STACK_FRAME_OVERHEAD EXC_XFER_EE_LITE(0x2010, KernelSPE) #elif defined(CONFIG_SPE_POSSIBLE) - EXCEPTION(0x2020, SPE_ALTIVEC_UNAVAIL, SPEUnavailable, \ + EXCEPTION(0x2020, SPE_UNAVAIL, SPEUnavailable, \ unknown_exception, EXC_XFER_EE) #endif /* CONFIG_SPE_POSSIBLE */ /* SPE Floating Point Data */ #ifdef CONFIG_SPE - EXCEPTION(0x2030, SPE_FP_DATA_ALTIVEC_ASSIST, SPEFloatingPointData, + EXCEPTION(0x2030, SPE_FP_DATA, SPEFloatingPointData, SPEFloatingPointException, EXC_XFER_EE) /* SPE Floating Point Round */ EXCEPTION(0x2050, SPE_FP_ROUND, SPEFloatingPointRound, \ SPEFloatingPointRoundException, EXC_XFER_EE) #elif defined(CONFIG_SPE_POSSIBLE) - EXCEPTION(0x2040, SPE_FP_DATA_ALTIVEC_ASSIST, SPEFloatingPointData, + EXCEPTION(0x2040, SPE_FP_DATA, SPEFloatingPointData, unknown_exception, EXC_XFER_EE) EXCEPTION(0x2050, SPE_FP_ROUND, SPEFloatingPointRound, \ unknown_exception, EXC_XFER_EE) -- 1.7.11.7 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v2 1/2] powerpc/booke: Restrict SPE exception handlers to e200/e500 cores
SPE exception handlers are now defined for 32-bit e500mc cores even though
SPE unit is not present and CONFIG_SPE is undefined.
Restrict SPE exception handlers to e200/e500 cores adding CONFIG_SPE_POSSIBLE
and consequently guard __stup_ivors and __setup_cpu functions.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
Cc: Scott Wood scottw...@freescale.com
Cc: Alexander Graf ag...@suse.de
---
v2:
- use CONFIG_PPC_E500MC without CONFIG_E500
- use elif defined()
arch/powerpc/kernel/cpu_setup_fsl_booke.S | 12 +++-
arch/powerpc/kernel/cputable.c| 5 +
arch/powerpc/kernel/head_fsl_booke.S | 18 +-
arch/powerpc/platforms/Kconfig.cputype| 6 +-
4 files changed, 34 insertions(+), 7 deletions(-)
diff --git a/arch/powerpc/kernel/cpu_setup_fsl_booke.S
b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
index 4f1393d..dddba3e 100644
--- a/arch/powerpc/kernel/cpu_setup_fsl_booke.S
+++ b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
@@ -91,6 +91,7 @@ _GLOBAL(setup_altivec_idle)
blr
+#ifdef CONFIG_PPC_E500MC
_GLOBAL(__setup_cpu_e6500)
mflrr6
#ifdef CONFIG_PPC64
@@ -107,14 +108,20 @@ _GLOBAL(__setup_cpu_e6500)
bl __setup_cpu_e5500
mtlrr6
blr
+#endif /* CONFIG_PPC_E500MC */
#ifdef CONFIG_PPC32
+#ifdef CONFIG_E200
_GLOBAL(__setup_cpu_e200)
/* enable dedicated debug exception handling resources (Debug APU) */
mfspr r3,SPRN_HID0
ori r3,r3,HID0_DAPUEN@l
mtspr SPRN_HID0,r3
b __setup_e200_ivors
+#endif /* CONFIG_E200 */
+
+#ifdef CONFIG_E500
+#ifndef CONFIG_PPC_E500MC
_GLOBAL(__setup_cpu_e500v1)
_GLOBAL(__setup_cpu_e500v2)
mflrr4
@@ -129,6 +136,7 @@ _GLOBAL(__setup_cpu_e500v2)
#endif
mtlrr4
blr
+#else /* CONFIG_PPC_E500MC */
_GLOBAL(__setup_cpu_e500mc)
_GLOBAL(__setup_cpu_e5500)
mflrr5
@@ -159,7 +167,9 @@ _GLOBAL(__setup_cpu_e5500)
2:
mtlrr5
blr
-#endif
+#endif /* CONFIG_PPC_E500MC */
+#endif /* CONFIG_E500 */
+#endif /* CONFIG_PPC32 */
#ifdef CONFIG_PPC_BOOK3E_64
_GLOBAL(__restore_cpu_e6500)
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index 0c15764..df979c5f 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -2051,6 +2051,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
#endif /* CONFIG_PPC32 */
#ifdef CONFIG_E500
#ifdef CONFIG_PPC32
+#ifndef CONFIG_PPC_E500MC
{ /* e500 */
.pvr_mask = 0x,
.pvr_value = 0x8020,
@@ -2090,6 +2091,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
.machine_check = machine_check_e500,
.platform = ppc8548,
},
+#else
{ /* e500mc */
.pvr_mask = 0x,
.pvr_value = 0x8023,
@@ -2108,7 +2110,9 @@ static struct cpu_spec __initdata cpu_specs[] = {
.machine_check = machine_check_e500mc,
.platform = ppce500mc,
},
+#endif /* CONFIG_PPC_E500MC */
#endif /* CONFIG_PPC32 */
+#ifdef CONFIG_PPC_E500MC
{ /* e5500 */
.pvr_mask = 0x,
.pvr_value = 0x8024,
@@ -2152,6 +2156,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
.machine_check = machine_check_e500mc,
.platform = ppce6500,
},
+#endif /* CONFIG_PPC_E500MC */
#ifdef CONFIG_PPC32
{ /* default match */
.pvr_mask = 0x,
diff --git a/arch/powerpc/kernel/head_fsl_booke.S
b/arch/powerpc/kernel/head_fsl_booke.S
index b497188..90f487f 100644
--- a/arch/powerpc/kernel/head_fsl_booke.S
+++ b/arch/powerpc/kernel/head_fsl_booke.S
@@ -613,6 +613,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
mfspr r10, SPRN_SPRG_RSCRATCH0
b InstructionStorage
+/* Define SPE handlers for e200 and e500v2 */
#ifdef CONFIG_SPE
/* SPE Unavailable */
START_EXCEPTION(SPEUnavailable)
@@ -622,10 +623,10 @@ END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
b fast_exception_return
1: addir3,r1,STACK_FRAME_OVERHEAD
EXC_XFER_EE_LITE(0x2010, KernelSPE)
-#else
+#elif defined(CONFIG_SPE_POSSIBLE)
EXCEPTION(0x2020, SPE_ALTIVEC_UNAVAIL, SPEUnavailable, \
unknown_exception, EXC_XFER_EE)
-#endif /* CONFIG_SPE */
+#endif /* CONFIG_SPE_POSSIBLE */
/* SPE Floating Point Data */
#ifdef CONFIG_SPE
@@ -635,12 +636,13 @@ END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
/* SPE Floating Point Round */
EXCEPTION(0x2050, SPE_FP_ROUND, SPEFloatingPointRound, \
SPEFloatingPointRoundException, EXC_XFER_EE)
-#else
+#elif defined(CONFIG_SPE_POSSIBLE)
EXCEPTION(0x2040,
Re: [RFC PATCH] powerpc: Make SPU_FS depend on SPARSEMEM
On Wed, Aug 20, 2014 at 3:49 AM, Geert Uytterhoeven ge...@linux-m68k.org wrote: Is this a randconfig kernel? Yes, randconfig with ARCH=powerpc. config ARCH_SPARSEMEM_DEFAULT def_bool y depends on (SMP PPC_PSERIES) || PPC_PS3 Why is this not enabled? !SMP? !PPC_PSERIES? !PPC_PS3? This was indeed enabled, but that does not do much. We will need CONFIG_SPARSEMEM which depends on CONFIG_SPARSEMEM_MANUAL which was not enabled. If PPC_CELL is enabled, this issue was introduced by commit 78bde53e351bc89cff85d1c2c7e6d7c2ffdf120d Author: Benjamin Herrenschmidt b...@kernel.crashing.org Date: Tue Feb 13 11:46:06 2007 +1100 [POWERPC] spufs: remove need for struct page for SPEs This patch removes the need for struct page for SPE local store and registers from spufs. It also makes the locking much more obvious and no longer relying on the truncate logic black magic for protecting against races between unmap_mapping_range() and new pages faulted in. It does so by switching to a nopfn() handler and using the new vm_insert_pfn() to setup the PTEs itself while holding a lock on the SPE. The nice thing is that this patch actually removes a lot more code than it adds :-) Signed-off-by: Benjamin Herrenschmidt b...@kernel.crashing.org Signed-off-by: Paul Mackerras pau...@samba.org Another question: why does SPU_FS select MEMORY_HOTPLUG? Not really sure :( commit 4da30d15b6d5036b0d96422d6946ca758111fae3 Author: Geoff Levand geoffrey.lev...@am.sony.com Date: Fri Jun 23 20:57:49 2006 +0200 [POWERPC] spufs: fix memory hotplug dependency spufs_base.c calls __add_pages, which depends on CONFIG_MEMORY_HOTPLUG. Moved the selection of CONFIG_MEMORY_HOTPLUG from CONFIG_SPUFS_MMAP to CONFIG_SPU_FS. Signed-off-by: Geoff Levand geoffrey.lev...@am.sony.com Signed-off-by: Arnd Bergmann arnd.bergm...@de.ibm.com Signed-off-by: Paul Mackerras pau...@samba.org However, the call to __add_pages() has been moved a few times afterwards, to be finally removed in the aforementioned commit 78bde53e351bc89cff85d1c2c7e6d7c2ffdf120d. Does it still build/work if you just drop the select MEMORY_HOTPLUG? I should have saved the config file :(. I think it will build since the problem was that hotplug-memory.o needs CONFIG_SPARSEMEM. -- Pranith ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] powerpc: Fix build failure when MEMORY_HOTPLUG=y
On Wed, Aug 20, 2014 at 4:00 AM, Geert Uytterhoeven ge...@linux-m68k.org wrote: 1.9.1 In light of my investigation for your spufs patch, I guess this is a non-SMP PSERIES config? So what happens is SELECT_MEMORY_MODEL choses FLATMEM_MANUAL because of which SPARSEMEM is not enabled despite having ARCH_SPARSEMEM_ENABLE=y. -- Pranith ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [RFC PATCH 0/6] Change vendor prefix for Intersil Corporation
Philipp, On Wed, Aug 20, 2014 at 10:42:58AM +0200, Philipp Zabel wrote: Hi, currently there is a wild mixture of isl, isil, and intersil compatibles in the kernel. I figure at this point it is still possible to change this to use isil everywhere without too much pain, but it might be preferred to keep the already documented isl prefix, even though it doesn't follow the convention to use the NASDAQ symbol where available. The current users of the isil prefix are the following drivers and device trees, so we could just as well change those instead: arch/arm/boot/dts/tegra20-seaboard.dts arch/arm/boot/dts/tegra20-ventana.dts arch/arm/boot/dts/tegra30-cardhu.dtsi arch/powerpc/boot/dts/p1022rdk.dts drivers/staging/iio/light/isl29018.c drivers/staging/iio/light/isl29028.c regards Philipp Philipp Zabel (6): of: Change vendor prefix for Intersil Corporation to isil Documentation: Add isl1208 and isl12022 to trivial-devices list ARM: mvebu: Change vendor prefix for Intersil Corporation to isil powerpc/85xx: Change vendor prefix for Intersil Corporation to isil rtc: rtc-isl12022: Change vendor prefix for Intersil Corporation to isil rtc: rtc-isl12057: Change vendor prefix for Intersil Corporation to isil Documentation/devicetree/bindings/i2c/trivial-devices.txt | 4 +++- Documentation/devicetree/bindings/vendor-prefixes.txt | 2 +- arch/arm/boot/dts/armada-370-netgear-rn102.dts| 2 +- arch/arm/boot/dts/armada-370-netgear-rn104.dts| 2 +- arch/arm/boot/dts/armada-xp-netgear-rn2120.dts| 2 +- arch/powerpc/boot/dts/ppa8548.dts | 2 +- drivers/rtc/rtc-isl12022.c| 3 ++- drivers/rtc/rtc-isl12057.c| 3 ++- 8 files changed, 12 insertions(+), 8 deletions(-) This looks good overall. My only nit is that I'd like to see the legacy name(s) captured in the binding docs. I'll take the Armada dts changes through mvebu/arm-soc after a few days. thx, Jason. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v4 1/6] KVM: PPC: Book3E: Increase FPU laziness
Increase FPU laziness by loading the guest state into the unit before entering
the guest instead of doing it on each vcpu schedule. Without this improvement
an interrupt may claim floating point corrupting guest state.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
v4:
- update commit message
v3:
- no changes
v2:
- remove fpu_active
- add descriptive comments
arch/powerpc/kvm/booke.c | 43 ---
arch/powerpc/kvm/booke.h | 34 --
arch/powerpc/kvm/e500mc.c | 2 --
3 files changed, 36 insertions(+), 43 deletions(-)
diff --git a/arch/powerpc/kvm/booke.c b/arch/powerpc/kvm/booke.c
index 074b7fc..91e7217 100644
--- a/arch/powerpc/kvm/booke.c
+++ b/arch/powerpc/kvm/booke.c
@@ -124,6 +124,40 @@ static void kvmppc_vcpu_sync_spe(struct kvm_vcpu *vcpu)
}
#endif
+/*
+ * Load up guest vcpu FP state if it's needed.
+ * It also set the MSR_FP in thread so that host know
+ * we're holding FPU, and then host can help to save
+ * guest vcpu FP state if other threads require to use FPU.
+ * This simulates an FP unavailable fault.
+ *
+ * It requires to be called with preemption disabled.
+ */
+static inline void kvmppc_load_guest_fp(struct kvm_vcpu *vcpu)
+{
+#ifdef CONFIG_PPC_FPU
+ if (!(current-thread.regs-msr MSR_FP)) {
+ enable_kernel_fp();
+ load_fp_state(vcpu-arch.fp);
+ current-thread.fp_save_area = vcpu-arch.fp;
+ current-thread.regs-msr |= MSR_FP;
+ }
+#endif
+}
+
+/*
+ * Save guest vcpu FP state into thread.
+ * It requires to be called with preemption disabled.
+ */
+static inline void kvmppc_save_guest_fp(struct kvm_vcpu *vcpu)
+{
+#ifdef CONFIG_PPC_FPU
+ if (current-thread.regs-msr MSR_FP)
+ giveup_fpu(current);
+ current-thread.fp_save_area = NULL;
+#endif
+}
+
static void kvmppc_vcpu_sync_fpu(struct kvm_vcpu *vcpu)
{
#if defined(CONFIG_PPC_FPU) !defined(CONFIG_KVM_BOOKE_HV)
@@ -658,12 +692,8 @@ int kvmppc_vcpu_run(struct kvm_run *kvm_run, struct
kvm_vcpu *vcpu)
/*
* Since we can't trap on MSR_FP in GS-mode, we consider the guest
-* as always using the FPU. Kernel usage of FP (via
-* enable_kernel_fp()) in this thread must not occur while
-* vcpu-fpu_active is set.
+* as always using the FPU.
*/
- vcpu-fpu_active = 1;
-
kvmppc_load_guest_fp(vcpu);
#endif
@@ -687,8 +717,6 @@ int kvmppc_vcpu_run(struct kvm_run *kvm_run, struct
kvm_vcpu *vcpu)
#ifdef CONFIG_PPC_FPU
kvmppc_save_guest_fp(vcpu);
-
- vcpu-fpu_active = 0;
#endif
out:
@@ -1194,6 +1222,7 @@ out:
else {
/* interrupts now hard-disabled */
kvmppc_fix_ee_before_entry();
+ kvmppc_load_guest_fp(vcpu);
}
}
diff --git a/arch/powerpc/kvm/booke.h b/arch/powerpc/kvm/booke.h
index f753543..e73d513 100644
--- a/arch/powerpc/kvm/booke.h
+++ b/arch/powerpc/kvm/booke.h
@@ -116,40 +116,6 @@ extern int kvmppc_core_emulate_mtspr_e500(struct kvm_vcpu
*vcpu, int sprn,
extern int kvmppc_core_emulate_mfspr_e500(struct kvm_vcpu *vcpu, int sprn,
ulong *spr_val);
-/*
- * Load up guest vcpu FP state if it's needed.
- * It also set the MSR_FP in thread so that host know
- * we're holding FPU, and then host can help to save
- * guest vcpu FP state if other threads require to use FPU.
- * This simulates an FP unavailable fault.
- *
- * It requires to be called with preemption disabled.
- */
-static inline void kvmppc_load_guest_fp(struct kvm_vcpu *vcpu)
-{
-#ifdef CONFIG_PPC_FPU
- if (vcpu-fpu_active !(current-thread.regs-msr MSR_FP)) {
- enable_kernel_fp();
- load_fp_state(vcpu-arch.fp);
- current-thread.fp_save_area = vcpu-arch.fp;
- current-thread.regs-msr |= MSR_FP;
- }
-#endif
-}
-
-/*
- * Save guest vcpu FP state into thread.
- * It requires to be called with preemption disabled.
- */
-static inline void kvmppc_save_guest_fp(struct kvm_vcpu *vcpu)
-{
-#ifdef CONFIG_PPC_FPU
- if (vcpu-fpu_active (current-thread.regs-msr MSR_FP))
- giveup_fpu(current);
- current-thread.fp_save_area = NULL;
-#endif
-}
-
static inline void kvmppc_clear_dbsr(void)
{
mtspr(SPRN_DBSR, mfspr(SPRN_DBSR));
diff --git a/arch/powerpc/kvm/e500mc.c b/arch/powerpc/kvm/e500mc.c
index 000cf82..4549349 100644
--- a/arch/powerpc/kvm/e500mc.c
+++ b/arch/powerpc/kvm/e500mc.c
@@ -145,8 +145,6 @@ static void kvmppc_core_vcpu_load_e500mc(struct kvm_vcpu
*vcpu, int cpu)
kvmppc_e500_tlbil_all(vcpu_e500);
__get_cpu_var(last_vcpu_of_lpid)[vcpu-kvm-arch.lpid] = vcpu;
}
-
- kvmppc_load_guest_fp(vcpu);
}
static void kvmppc_core_vcpu_put_e500mc(struct kvm_vcpu *vcpu)
--
1.7.11.7
[PATCH v4 0/6] KVM: PPC: Book3e: AltiVec support
Add KVM Book3e AltiVec support. Changes: v4: - use CONFIG_SPE_POSSIBLE and a new ifdef for CONFIG_ALTIVEC - remove SPE handlers from bookehv - split ONE_REG powerpc generic and ONE_REG AltiVec - add setters for IVPR, IVOR2 and IVOR8 - add api documentation for ONE_REG IVPR and IVORs - don't enable e6500 core since hardware threads are not yet supported v3: - use distinct SPE/AltiVec exception handlers - make ONE_REG AltiVec support powerpc generic - add ONE_REG IVORs support v2: - integrate Paul's FP/VMX/VSX changes that landed in kvm-ppc-queue in January and take into account feedback Mihai Caraman (6): KVM: PPC: Book3E: Increase FPU laziness KVM: PPC: Book3e: Add AltiVec support KVM: PPC: Make ONE_REG powerpc generic KVM: PPC: Move ONE_REG AltiVec support to powerpc KVM: PPC: Booke: Add setter functions for IVPR, IVOR2 and IVOR8 emulation KVM: PPC: Booke: Add ONE_REG support for IVPR and IVORs Documentation/virtual/kvm/api.txt | 7 + arch/powerpc/include/uapi/asm/kvm.h | 30 +++ arch/powerpc/kvm/book3s.c | 151 -- arch/powerpc/kvm/booke.c | 371 -- arch/powerpc/kvm/booke.h | 43 +--- arch/powerpc/kvm/booke_emulate.c | 15 +- arch/powerpc/kvm/bookehv_interrupts.S | 9 +- arch/powerpc/kvm/e500.c | 42 +++- arch/powerpc/kvm/e500_emulate.c | 20 ++ arch/powerpc/kvm/e500mc.c | 18 +- arch/powerpc/kvm/powerpc.c| 97 + 11 files changed, 576 insertions(+), 227 deletions(-) -- 1.7.11.7 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v4 2/6] KVM: PPC: Book3e: Add AltiVec support
Add AltiVec support in KVM for Book3e. FPU support gracefully reuse host
infrastructure so follow the same approach for AltiVec.
Book3e specification defines shared interrupt numbers for SPE and AltiVec
units. Still SPE is present in e200/e500v2 cores while AltiVec is present in
e6500 core. So we can currently decide at compile-time which of the SPE or
AltiVec units to support exclusively by using CONFIG_SPE_POSSIBLE and
CONFIG_PPC_E500MC defines. As Alexander Graf suggested, keep SPE and AltiVec
exception handlers distinct to improve code readability.
Guests have the privilege to enable AltiVec, so we always need to support
AltiVec in KVM and implicitly in host to reflect interrupts and to save/restore
the unit context. KVM will be loaded on cores with AltiVec unit only if
CONFIG_ALTIVEC is defined. Use this define to guard KVM AltiVec logic.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
v4:
- use CONFIG_SPE_POSSIBLE and a new ifdef for CONFIG_ALTIVEC
- remove SPE handlers from bookehv
- update commit message
v3:
- use distinct SPE/AltiVec exception handlers
v2:
- integrate Paul's FP/VMX/VSX changes
arch/powerpc/kvm/booke.c | 74 ++-
arch/powerpc/kvm/booke.h | 6 +++
arch/powerpc/kvm/bookehv_interrupts.S | 9 +
arch/powerpc/kvm/e500_emulate.c | 20 ++
4 files changed, 101 insertions(+), 8 deletions(-)
diff --git a/arch/powerpc/kvm/booke.c b/arch/powerpc/kvm/booke.c
index 91e7217..8ace612 100644
--- a/arch/powerpc/kvm/booke.c
+++ b/arch/powerpc/kvm/booke.c
@@ -168,6 +168,40 @@ static void kvmppc_vcpu_sync_fpu(struct kvm_vcpu *vcpu)
#endif
}
+/*
+ * Simulate AltiVec unavailable fault to load guest state
+ * from thread to AltiVec unit.
+ * It requires to be called with preemption disabled.
+ */
+static inline void kvmppc_load_guest_altivec(struct kvm_vcpu *vcpu)
+{
+#ifdef CONFIG_ALTIVEC
+ if (cpu_has_feature(CPU_FTR_ALTIVEC)) {
+ if (!(current-thread.regs-msr MSR_VEC)) {
+ enable_kernel_altivec();
+ load_vr_state(vcpu-arch.vr);
+ current-thread.vr_save_area = vcpu-arch.vr;
+ current-thread.regs-msr |= MSR_VEC;
+ }
+ }
+#endif
+}
+
+/*
+ * Save guest vcpu AltiVec state into thread.
+ * It requires to be called with preemption disabled.
+ */
+static inline void kvmppc_save_guest_altivec(struct kvm_vcpu *vcpu)
+{
+#ifdef CONFIG_ALTIVEC
+ if (cpu_has_feature(CPU_FTR_ALTIVEC)) {
+ if (current-thread.regs-msr MSR_VEC)
+ giveup_altivec(current);
+ current-thread.vr_save_area = NULL;
+ }
+#endif
+}
+
static void kvmppc_vcpu_sync_debug(struct kvm_vcpu *vcpu)
{
/* Synchronize guest's desire to get debug interrupts into shadow MSR */
@@ -375,9 +409,15 @@ static int kvmppc_booke_irqprio_deliver(struct kvm_vcpu
*vcpu,
case BOOKE_IRQPRIO_ITLB_MISS:
case BOOKE_IRQPRIO_SYSCALL:
case BOOKE_IRQPRIO_FP_UNAVAIL:
+#ifdef CONFIG_SPE_POSSIBLE
case BOOKE_IRQPRIO_SPE_UNAVAIL:
case BOOKE_IRQPRIO_SPE_FP_DATA:
case BOOKE_IRQPRIO_SPE_FP_ROUND:
+#endif
+#ifdef CONFIG_ALTIVEC
+ case BOOKE_IRQPRIO_ALTIVEC_UNAVAIL:
+ case BOOKE_IRQPRIO_ALTIVEC_ASSIST:
+#endif
case BOOKE_IRQPRIO_AP_UNAVAIL:
allowed = 1;
msr_mask = MSR_CE | MSR_ME | MSR_DE;
@@ -697,6 +737,17 @@ int kvmppc_vcpu_run(struct kvm_run *kvm_run, struct
kvm_vcpu *vcpu)
kvmppc_load_guest_fp(vcpu);
#endif
+#ifdef CONFIG_ALTIVEC
+ /* Save userspace AltiVec state in stack */
+ if (cpu_has_feature(CPU_FTR_ALTIVEC))
+ enable_kernel_altivec();
+ /*
+* Since we can't trap on MSR_VEC in GS-mode, we consider the guest
+* as always using the AltiVec.
+*/
+ kvmppc_load_guest_altivec(vcpu);
+#endif
+
/* Switch to guest debug context */
debug = vcpu-arch.dbg_reg;
switch_booke_debug_regs(debug);
@@ -719,6 +770,10 @@ int kvmppc_vcpu_run(struct kvm_run *kvm_run, struct
kvm_vcpu *vcpu)
kvmppc_save_guest_fp(vcpu);
#endif
+#ifdef CONFIG_ALTIVEC
+ kvmppc_save_guest_altivec(vcpu);
+#endif
+
out:
vcpu-mode = OUTSIDE_GUEST_MODE;
return ret;
@@ -1025,7 +1080,7 @@ int kvmppc_handle_exit(struct kvm_run *run, struct
kvm_vcpu *vcpu,
kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_SPE_FP_ROUND);
r = RESUME_GUEST;
break;
-#else
+#elif defined(CONFIG_SPE_POSSIBLE)
case BOOKE_INTERRUPT_SPE_UNAVAIL:
/*
* Guest wants SPE, but host kernel doesn't support it. Send
@@ -1046,6 +1101,22 @@ int kvmppc_handle_exit(struct kvm_run *run, struct
kvm_vcpu *vcpu,
run-hw.hardware_exit_reason = exit_nr;
r = RESUME_HOST;
break;
+#endif /* CONFIG_SPE_POSSIBLE
[PATCH v4 4/6] KVM: PPC: Move ONE_REG AltiVec support to powerpc
Move ONE_REG AltiVec support to powerpc generic layer.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
v4:
- split ONE_REG powerpc generic and ONE_REG AltiVec
v3:
- make ONE_REG AltiVec support powerpc generic
v2:
- add comment describing VCSR register representation in KVM vs kernel
arch/powerpc/include/uapi/asm/kvm.h | 5 +
arch/powerpc/kvm/book3s.c | 42 -
arch/powerpc/kvm/powerpc.c | 42 +
3 files changed, 47 insertions(+), 42 deletions(-)
diff --git a/arch/powerpc/include/uapi/asm/kvm.h
b/arch/powerpc/include/uapi/asm/kvm.h
index 3ca357a..ab4d473 100644
--- a/arch/powerpc/include/uapi/asm/kvm.h
+++ b/arch/powerpc/include/uapi/asm/kvm.h
@@ -476,6 +476,11 @@ struct kvm_get_htab_header {
/* FP and vector status/control registers */
#define KVM_REG_PPC_FPSCR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x80)
+/*
+ * VSCR register is documented as a 32-bit register in the ISA, but it can
+ * only be accesses via a vector register. Expose VSCR as a 32-bit register
+ * even though the kernel represents it as a 128-bit vector.
+ */
#define KVM_REG_PPC_VSCR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x81)
/* Virtual processor areas */
diff --git a/arch/powerpc/kvm/book3s.c b/arch/powerpc/kvm/book3s.c
index 26868e2..1b5adda 100644
--- a/arch/powerpc/kvm/book3s.c
+++ b/arch/powerpc/kvm/book3s.c
@@ -558,25 +558,6 @@ int kvmppc_get_one_reg(struct kvm_vcpu *vcpu, u64 id,
case KVM_REG_PPC_FPSCR:
*val = get_reg_val(id, vcpu-arch.fp.fpscr);
break;
-#ifdef CONFIG_ALTIVEC
- case KVM_REG_PPC_VR0 ... KVM_REG_PPC_VR31:
- if (!cpu_has_feature(CPU_FTR_ALTIVEC)) {
- r = -ENXIO;
- break;
- }
- val-vval = vcpu-arch.vr.vr[id - KVM_REG_PPC_VR0];
- break;
- case KVM_REG_PPC_VSCR:
- if (!cpu_has_feature(CPU_FTR_ALTIVEC)) {
- r = -ENXIO;
- break;
- }
- *val = get_reg_val(id, vcpu-arch.vr.vscr.u[3]);
- break;
- case KVM_REG_PPC_VRSAVE:
- *val = get_reg_val(id, vcpu-arch.vrsave);
- break;
-#endif /* CONFIG_ALTIVEC */
#ifdef CONFIG_VSX
case KVM_REG_PPC_VSR0 ... KVM_REG_PPC_VSR31:
if (cpu_has_feature(CPU_FTR_VSX)) {
@@ -653,29 +634,6 @@ int kvmppc_set_one_reg(struct kvm_vcpu *vcpu, u64 id,
case KVM_REG_PPC_FPSCR:
vcpu-arch.fp.fpscr = set_reg_val(id, *val);
break;
-#ifdef CONFIG_ALTIVEC
- case KVM_REG_PPC_VR0 ... KVM_REG_PPC_VR31:
- if (!cpu_has_feature(CPU_FTR_ALTIVEC)) {
- r = -ENXIO;
- break;
- }
- vcpu-arch.vr.vr[id - KVM_REG_PPC_VR0] = val-vval;
- break;
- case KVM_REG_PPC_VSCR:
- if (!cpu_has_feature(CPU_FTR_ALTIVEC)) {
- r = -ENXIO;
- break;
- }
- vcpu-arch.vr.vscr.u[3] = set_reg_val(id, *val);
- break;
- case KVM_REG_PPC_VRSAVE:
- if (!cpu_has_feature(CPU_FTR_ALTIVEC)) {
- r = -ENXIO;
- break;
- }
- vcpu-arch.vrsave = set_reg_val(id, *val);
- break;
-#endif /* CONFIG_ALTIVEC */
#ifdef CONFIG_VSX
case KVM_REG_PPC_VSR0 ... KVM_REG_PPC_VSR31:
if (cpu_has_feature(CPU_FTR_VSX)) {
diff --git a/arch/powerpc/kvm/powerpc.c b/arch/powerpc/kvm/powerpc.c
index 1326116..19d4755 100644
--- a/arch/powerpc/kvm/powerpc.c
+++ b/arch/powerpc/kvm/powerpc.c
@@ -941,6 +941,25 @@ int kvm_vcpu_ioctl_get_one_reg(struct kvm_vcpu *vcpu,
struct kvm_one_reg *reg)
if (r == -EINVAL) {
r = 0;
switch (reg-id) {
+#ifdef CONFIG_ALTIVEC
+ case KVM_REG_PPC_VR0 ... KVM_REG_PPC_VR31:
+ if (!cpu_has_feature(CPU_FTR_ALTIVEC)) {
+ r = -ENXIO;
+ break;
+ }
+ val.vval = vcpu-arch.vr.vr[reg-id - KVM_REG_PPC_VR0];
+ break;
+ case KVM_REG_PPC_VSCR:
+ if (!cpu_has_feature(CPU_FTR_ALTIVEC)) {
+ r = -ENXIO;
+ break;
+ }
+ val = get_reg_val(reg-id,
[PATCH v4 5/6] KVM: PPC: Booke: Add setter functions for IVPR, IVOR2 and IVOR8 emulation
Add setter functions for IVPR, IVOR2 and IVOR8 emulation in preparation
for ONE_REG support.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
v4:
- new patch
- add api documentation for ONE_REG IVPR and IVORs
arch/powerpc/kvm/booke.c | 24
arch/powerpc/kvm/booke.h | 3 +++
arch/powerpc/kvm/booke_emulate.c | 15 +++
3 files changed, 30 insertions(+), 12 deletions(-)
diff --git a/arch/powerpc/kvm/booke.c b/arch/powerpc/kvm/booke.c
index 831c1b4..d4df648 100644
--- a/arch/powerpc/kvm/booke.c
+++ b/arch/powerpc/kvm/booke.c
@@ -1782,6 +1782,30 @@ void kvmppc_clr_tsr_bits(struct kvm_vcpu *vcpu, u32
tsr_bits)
update_timer_ints(vcpu);
}
+void kvmppc_set_ivpr(struct kvm_vcpu *vcpu, ulong new_ivpr)
+{
+ vcpu-arch.ivpr = new_ivpr;
+#ifdef CONFIG_KVM_BOOKE_HV
+ mtspr(SPRN_GIVPR, new_ivpr);
+#endif
+}
+
+void kvmppc_set_ivor2(struct kvm_vcpu *vcpu, u32 new_ivor)
+{
+ vcpu-arch.ivor[BOOKE_IRQPRIO_DATA_STORAGE] = new_ivor;
+#ifdef CONFIG_KVM_BOOKE_HV
+ mtspr(SPRN_GIVOR2, new_ivor);
+#endif
+}
+
+void kvmppc_set_ivor8(struct kvm_vcpu *vcpu, u32 new_ivor)
+{
+ vcpu-arch.ivor[BOOKE_IRQPRIO_SYSCALL] = new_ivor;
+#ifdef CONFIG_KVM_BOOKE_HV
+ mtspr(SPRN_GIVOR8, new_ivor);
+#endif
+}
+
void kvmppc_decrementer_func(unsigned long data)
{
struct kvm_vcpu *vcpu = (struct kvm_vcpu *)data;
diff --git a/arch/powerpc/kvm/booke.h b/arch/powerpc/kvm/booke.h
index 22ba08e..0242530 100644
--- a/arch/powerpc/kvm/booke.h
+++ b/arch/powerpc/kvm/booke.h
@@ -80,6 +80,9 @@ void kvmppc_set_epcr(struct kvm_vcpu *vcpu, u32 new_epcr);
void kvmppc_set_tcr(struct kvm_vcpu *vcpu, u32 new_tcr);
void kvmppc_set_tsr_bits(struct kvm_vcpu *vcpu, u32 tsr_bits);
void kvmppc_clr_tsr_bits(struct kvm_vcpu *vcpu, u32 tsr_bits);
+void kvmppc_set_ivpr(struct kvm_vcpu *vcpu, ulong new_ivpr);
+void kvmppc_set_ivor2(struct kvm_vcpu *vcpu, u32 new_ivor);
+void kvmppc_set_ivor8(struct kvm_vcpu *vcpu, u32 new_ivor);
int kvmppc_booke_emulate_op(struct kvm_run *run, struct kvm_vcpu *vcpu,
unsigned int inst, int *advance);
diff --git a/arch/powerpc/kvm/booke_emulate.c b/arch/powerpc/kvm/booke_emulate.c
index 92bc668..94c64e3 100644
--- a/arch/powerpc/kvm/booke_emulate.c
+++ b/arch/powerpc/kvm/booke_emulate.c
@@ -191,10 +191,7 @@ int kvmppc_booke_emulate_mtspr(struct kvm_vcpu *vcpu, int
sprn, ulong spr_val)
break;
case SPRN_IVPR:
- vcpu-arch.ivpr = spr_val;
-#ifdef CONFIG_KVM_BOOKE_HV
- mtspr(SPRN_GIVPR, spr_val);
-#endif
+ kvmppc_set_ivpr(vcpu, spr_val);
break;
case SPRN_IVOR0:
vcpu-arch.ivor[BOOKE_IRQPRIO_CRITICAL] = spr_val;
@@ -203,10 +200,7 @@ int kvmppc_booke_emulate_mtspr(struct kvm_vcpu *vcpu, int
sprn, ulong spr_val)
vcpu-arch.ivor[BOOKE_IRQPRIO_MACHINE_CHECK] = spr_val;
break;
case SPRN_IVOR2:
- vcpu-arch.ivor[BOOKE_IRQPRIO_DATA_STORAGE] = spr_val;
-#ifdef CONFIG_KVM_BOOKE_HV
- mtspr(SPRN_GIVOR2, spr_val);
-#endif
+ kvmppc_set_ivor2(vcpu, spr_val);
break;
case SPRN_IVOR3:
vcpu-arch.ivor[BOOKE_IRQPRIO_INST_STORAGE] = spr_val;
@@ -224,10 +218,7 @@ int kvmppc_booke_emulate_mtspr(struct kvm_vcpu *vcpu, int
sprn, ulong spr_val)
vcpu-arch.ivor[BOOKE_IRQPRIO_FP_UNAVAIL] = spr_val;
break;
case SPRN_IVOR8:
- vcpu-arch.ivor[BOOKE_IRQPRIO_SYSCALL] = spr_val;
-#ifdef CONFIG_KVM_BOOKE_HV
- mtspr(SPRN_GIVOR8, spr_val);
-#endif
+ kvmppc_set_ivor8(vcpu, spr_val);
break;
case SPRN_IVOR9:
vcpu-arch.ivor[BOOKE_IRQPRIO_AP_UNAVAIL] = spr_val;
--
1.7.11.7
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v4 6/6] KVM: PPC: Booke: Add ONE_REG support for IVPR and IVORs
Add ONE_REG support for IVPR and IVORs registers. Implement IVPR, IVORs 0-15
and 35 in booke common layer.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
v4:
- add ONE_REG IVPR
- use IVPR, IVOR2 and IVOR8 setters
- add api documentation for ONE_REG IVPR and IVORs
v3:
- new patch
Documentation/virtual/kvm/api.txt | 7 ++
arch/powerpc/include/uapi/asm/kvm.h | 25 +++
arch/powerpc/kvm/booke.c| 145
arch/powerpc/kvm/e500.c | 42 ++-
arch/powerpc/kvm/e500mc.c | 16
5 files changed, 233 insertions(+), 2 deletions(-)
diff --git a/Documentation/virtual/kvm/api.txt
b/Documentation/virtual/kvm/api.txt
index beae3fd..cd7b171 100644
--- a/Documentation/virtual/kvm/api.txt
+++ b/Documentation/virtual/kvm/api.txt
@@ -1917,6 +1917,13 @@ registers, find a list below:
PPC | KVM_REG_PPC_TM_VSCR | 32
PPC | KVM_REG_PPC_TM_DSCR | 64
PPC | KVM_REG_PPC_TM_TAR| 64
+ PPC | KVM_REG_PPC_IVPR | 64
+ PPC | KVM_REG_PPC_IVOR0 | 32
+ ...
+ PPC | KVM_REG_PPC_IVOR15| 32
+ PPC | KVM_REG_PPC_IVOR32| 32
+ ...
+ PPC | KVM_REG_PPC_IVOR37| 32
| |
MIPS | KVM_REG_MIPS_R0 | 64
...
diff --git a/arch/powerpc/include/uapi/asm/kvm.h
b/arch/powerpc/include/uapi/asm/kvm.h
index ab4d473..c97f119 100644
--- a/arch/powerpc/include/uapi/asm/kvm.h
+++ b/arch/powerpc/include/uapi/asm/kvm.h
@@ -564,6 +564,31 @@ struct kvm_get_htab_header {
#define KVM_REG_PPC_SPRG9 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xba)
#define KVM_REG_PPC_DBSR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xbb)
+/* Booke IVPR IVOR registers */
+#define KVM_REG_PPC_IVPR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xbc)
+#define KVM_REG_PPC_IVOR0 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xbd)
+#define KVM_REG_PPC_IVOR1 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xbe)
+#define KVM_REG_PPC_IVOR2 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xbf)
+#define KVM_REG_PPC_IVOR3 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xc0)
+#define KVM_REG_PPC_IVOR4 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xc1)
+#define KVM_REG_PPC_IVOR5 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xc2)
+#define KVM_REG_PPC_IVOR6 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xc3)
+#define KVM_REG_PPC_IVOR7 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xc4)
+#define KVM_REG_PPC_IVOR8 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xc5)
+#define KVM_REG_PPC_IVOR9 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xc6)
+#define KVM_REG_PPC_IVOR10 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xc7)
+#define KVM_REG_PPC_IVOR11 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xc8)
+#define KVM_REG_PPC_IVOR12 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xc9)
+#define KVM_REG_PPC_IVOR13 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xca)
+#define KVM_REG_PPC_IVOR14 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xcb)
+#define KVM_REG_PPC_IVOR15 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xcc)
+#define KVM_REG_PPC_IVOR32 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xcd)
+#define KVM_REG_PPC_IVOR33 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xce)
+#define KVM_REG_PPC_IVOR34 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xcf)
+#define KVM_REG_PPC_IVOR35 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xd0)
+#define KVM_REG_PPC_IVOR36 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xd1)
+#define KVM_REG_PPC_IVOR37 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xd2)
+
/* Transactional Memory checkpointed state:
* This is all GPRs, all VSX regs and a subset of SPRs
*/
diff --git a/arch/powerpc/kvm/booke.c b/arch/powerpc/kvm/booke.c
index d4df648..1cb2a2a 100644
--- a/arch/powerpc/kvm/booke.c
+++ b/arch/powerpc/kvm/booke.c
@@ -1570,6 +1570,75 @@ int kvmppc_get_one_reg(struct kvm_vcpu *vcpu, u64 id,
int r = 0;
switch (id) {
+ case KVM_REG_PPC_IVPR:
+ *val = get_reg_val(id, vcpu-arch.ivpr);
+ break;
+ case KVM_REG_PPC_IVOR0:
+ *val = get_reg_val(id,
+ vcpu-arch.ivor[BOOKE_IRQPRIO_CRITICAL]);
+ break;
+ case KVM_REG_PPC_IVOR1:
+ *val = get_reg_val(id,
+ vcpu-arch.ivor[BOOKE_IRQPRIO_MACHINE_CHECK]);
+ break;
+ case KVM_REG_PPC_IVOR2:
+ *val = get_reg_val(id,
+ vcpu-arch.ivor[BOOKE_IRQPRIO_DATA_STORAGE]);
+ break;
+ case KVM_REG_PPC_IVOR3:
+ *val = get_reg_val(id,
+ vcpu-arch.ivor[BOOKE_IRQPRIO_INST_STORAGE]);
+ break;
+ case KVM_REG_PPC_IVOR4:
+ *val = get_reg_val(id,
+ vcpu-arch.ivor[BOOKE_IRQPRIO_EXTERNAL]);
+ break;
+ case KVM_REG_PPC_IVOR5:
+ *val = get_reg_val(id,
+ vcpu-arch.ivor[BOOKE_IRQPRIO_ALIGNMENT]);
+ break;
+ case
[PATCH v4 3/6] KVM: PPC: Make ONE_REG powerpc generic
Make ONE_REG generic for server and embedded architectures by moving
kvm_vcpu_ioctl_get_one_reg() and kvm_vcpu_ioctl_set_one_reg() functions
to powerpc layer.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
v4:
- split ONE_REG powerpc generic and ONE_REG AltiVec
v3:
- make ONE_REG AltiVec support powerpc generic
v2:
- add comment describing VCSR register representation in KVM vs kernel
arch/powerpc/kvm/book3s.c | 121 +++--
arch/powerpc/kvm/booke.c | 91 +-
arch/powerpc/kvm/powerpc.c | 55 +
3 files changed, 138 insertions(+), 129 deletions(-)
diff --git a/arch/powerpc/kvm/book3s.c b/arch/powerpc/kvm/book3s.c
index dd03f6b..26868e2 100644
--- a/arch/powerpc/kvm/book3s.c
+++ b/arch/powerpc/kvm/book3s.c
@@ -535,33 +535,28 @@ int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu,
struct kvm_fpu *fpu)
return -ENOTSUPP;
}
-int kvm_vcpu_ioctl_get_one_reg(struct kvm_vcpu *vcpu, struct kvm_one_reg *reg)
+int kvmppc_get_one_reg(struct kvm_vcpu *vcpu, u64 id,
+ union kvmppc_one_reg *val)
{
- int r;
- union kvmppc_one_reg val;
- int size;
+ int r = 0;
long int i;
- size = one_reg_size(reg-id);
- if (size sizeof(val))
- return -EINVAL;
-
- r = vcpu-kvm-arch.kvm_ops-get_one_reg(vcpu, reg-id, val);
+ r = vcpu-kvm-arch.kvm_ops-get_one_reg(vcpu, id, val);
if (r == -EINVAL) {
r = 0;
- switch (reg-id) {
+ switch (id) {
case KVM_REG_PPC_DAR:
- val = get_reg_val(reg-id, kvmppc_get_dar(vcpu));
+ *val = get_reg_val(id, kvmppc_get_dar(vcpu));
break;
case KVM_REG_PPC_DSISR:
- val = get_reg_val(reg-id, kvmppc_get_dsisr(vcpu));
+ *val = get_reg_val(id, kvmppc_get_dsisr(vcpu));
break;
case KVM_REG_PPC_FPR0 ... KVM_REG_PPC_FPR31:
- i = reg-id - KVM_REG_PPC_FPR0;
- val = get_reg_val(reg-id, VCPU_FPR(vcpu, i));
+ i = id - KVM_REG_PPC_FPR0;
+ *val = get_reg_val(id, VCPU_FPR(vcpu, i));
break;
case KVM_REG_PPC_FPSCR:
- val = get_reg_val(reg-id, vcpu-arch.fp.fpscr);
+ *val = get_reg_val(id, vcpu-arch.fp.fpscr);
break;
#ifdef CONFIG_ALTIVEC
case KVM_REG_PPC_VR0 ... KVM_REG_PPC_VR31:
@@ -569,110 +564,94 @@ int kvm_vcpu_ioctl_get_one_reg(struct kvm_vcpu *vcpu,
struct kvm_one_reg *reg)
r = -ENXIO;
break;
}
- val.vval = vcpu-arch.vr.vr[reg-id - KVM_REG_PPC_VR0];
+ val-vval = vcpu-arch.vr.vr[id - KVM_REG_PPC_VR0];
break;
case KVM_REG_PPC_VSCR:
if (!cpu_has_feature(CPU_FTR_ALTIVEC)) {
r = -ENXIO;
break;
}
- val = get_reg_val(reg-id, vcpu-arch.vr.vscr.u[3]);
+ *val = get_reg_val(id, vcpu-arch.vr.vscr.u[3]);
break;
case KVM_REG_PPC_VRSAVE:
- val = get_reg_val(reg-id, vcpu-arch.vrsave);
+ *val = get_reg_val(id, vcpu-arch.vrsave);
break;
#endif /* CONFIG_ALTIVEC */
#ifdef CONFIG_VSX
case KVM_REG_PPC_VSR0 ... KVM_REG_PPC_VSR31:
if (cpu_has_feature(CPU_FTR_VSX)) {
- long int i = reg-id - KVM_REG_PPC_VSR0;
- val.vsxval[0] = vcpu-arch.fp.fpr[i][0];
- val.vsxval[1] = vcpu-arch.fp.fpr[i][1];
+ i = id - KVM_REG_PPC_VSR0;
+ val-vsxval[0] = vcpu-arch.fp.fpr[i][0];
+ val-vsxval[1] = vcpu-arch.fp.fpr[i][1];
} else {
r = -ENXIO;
}
break;
#endif /* CONFIG_VSX */
- case KVM_REG_PPC_DEBUG_INST: {
- u32 opcode = INS_TW;
- r = copy_to_user((u32 __user *)(long)reg-addr,
-opcode, sizeof(u32));
+ case KVM_REG_PPC_DEBUG_INST:
+ *val = get_reg_val(id, INS_TW);
break;
- }
#ifdef CONFIG_KVM_XICS
case KVM_REG_PPC_ICP_STATE:
if (!vcpu-arch.icp) {
r = -ENXIO;
break;
}
Re: [PATCH v2 00/14] Add support for parameterized events from sysfs
On Fri, Aug 15, 2014 at 12:26:09AM -0700, Sukadev Bhattiprolu wrote: From: Cody P Schafer d...@codyps.com What this patchset does: - the first patch (override sysfs in tools/perf via SYSFS_PATH) was sent out previously, but needed a resend anyhow. Having it is useful for testing the later changes to tools/perf. - the second patch is a bugfix to the powerpc hv-24x7 code which was previously sent out, which is a good idea to have when testing these patches on POWER8 hardware. - document perf sysfs and the changes to add parameterized events - semi-notably: removes the growing list of specific POWER cpu events and begins documenting them generically, much like the docs for /sys/modules/MODULENAME do for modules. - tools/perf changes to support parameterized events - export some parameterized events from the powerpc pmus hv_24x7 and hv_gpci Description of event parameters from the documentation patch: Event parameters are a basic way for partial events to be specified in sysfs with per-event names given to the fields that need to be filled in when using a particular event. It is intended for supporting cases where the single 'cpu' parameter is insufficient. For example, POWER 8 has events for physical sockets/cores/cpus that are accessible from with virtual machines. To keep using the single 'cpu' parameter we'd need to perform a mapping between Linux's cpus and the physical machine's cpus (in this case Linux is running under a hypervisor). This isn't possible because bindings between our cpus and physical cpus may not be fixed, and we probably won't have a cpu on each physical cpu. Description of the sysfs contents when events are parameterized (copied from an included patch): Examples: domain=0x1,offset=0x8,starting_index=phys_cpu In the case of the last example, a value replacing phys_cpu would need to be provided by the user selecting the particular event. This is refered to as event parameterization. All non-numerical values indicate an event parameter. Notes on how perf-list displays parameterized events (and how to use them, again culled from an included patch): PARAMETERIZED EVENTS Some pmu events listed by 'perf-list' will be displayed with '?' in them. For example: hv_gpci/dtbp_ptitc,phys_processor_idx=?/ This means that when provided as an event, a value for phys_processor_idx must also be supplied. For example: perf stat -e 'hv_gpci/dtbp_ptitc,phys_processor_idx=0x2/' ... hi, is the reason for this to document this field for event in events/event file? Because once you have the field (phys_processor_idx) defined in formats/phys_processor_idx you should be able to use it as in your example: perf stat -e 'hv_gpci/dtbp_ptitc,phys_processor_idx=0x2/' without any changes thanks, jirka ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 2/2] fsl_ifc: Support all 8 IFC chip selects
-#define FSL_IFC_BANK_COUNT 4 +#define FSL_IFC_BANK_COUNT 8 First please modify fsl_ifc_nand.c to limit itself to the number of banks it dynamically determines are present based on the IFC version. Number of available bank/chip select are defined by SoC and it is independent of SoC. You mean that there is no way to tell from an IFC-specific register how many chip selects are valid for a given SoC, correct? It should be fix in following way Option 1: u-boot: fix device tree with number of available chip select. It may require IFC binding change Linux: Read device tree and determine the Chip Selects or Option 2: Make it static because any way IFC NAND driver polls to FSL_IFC_BANK_COUNT to know NAND flash chip select. This patch is doing same. My patch is based on the assumption that it is safe to access the addresses of the four nonexistent (unconnected?) chip selects in devices with fewer than eight chip selects. Also, the full FSL_IFC_BANK_COUNT range of chip selects should only be probed when no match is not found for a chip select's DTS-defined address base within any IFC bank. The typical case would be for the device tree to properly define the address space prepared by the bootloader, which would result in only banks present in the SoC being probed. I have tested this patch on P1010 and T1042 processors, which feature four and eight chip selects respectively with no apparent ill effects. Our P1010 product has NAND attached to chip selects 0 and 1: ranges = 0x0 0x0 0x0 0xef80 0x001 0x1 0x0 0x0 0xef84 0x001; I mangled chip-select 0 so that the DTS-defined base would not match the address programmed by firmware, so that all eight chip selects would be scanned on this four chip-select part: ranges = 0x0 0x0 0x0 0xefc0 0x001 0x1 0x0 0x0 0xef84 0x001; This resulted in the following kernel message: fsl,ifc-nand efc0.nand0: fsl_ifc_nand_probe: address did not match any chip selects The NAND device at chip select 1 was properly detected. Regards, Prabhakar ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: PCIe driver not working properly after upgrading to linux 3.8.13
- Original Message - From: Gokul C G goku...@kalkitech.in Sent: Tuesday, August 19, 2014 9:43:38 AM HI, I am facing problem with PCIE driver in new Linux kernel compiled for powerpc architecture (Big endian) ,freescales P2040 processor.I was using old kernel Linux version 3.0.48 previously and now updated to Linux version 3.8.13-rt9.After updating to the new kernel, PCIe device drivers not working properly and i am getting some error messages in the boot-up .My intention is to use EXAR PCIe Multiport serial driver and add 8 serial ports in addition to 4 built in serial ports provided by P2040 processor. The PCIe driver form EXAR is compiled and loaded as kernel module . The same was working with linux kernel 3.0.48 and following prints observed while loading kernel module. Have you attempted to use the XR17V35x support present in the updated version of the kernel that you're using (I assume it's Freescale SDK 1.4.x)? 8250 core support for Exar parts: http://git.freescale.com/git/cgit.cgi/ppc/sdk/linux.git/tree/drivers/tty/serial/8250/8250.c?h=sdk-v.1.4.x#n296 PCI vendor and device IDs for 2, 4 and 8 port Exar parts: http://git.freescale.com/git/cgit.cgi/ppc/sdk/linux.git/tree/drivers/tty/serial/8250/8250_pci.c?h=sdk-v.1.4.x#n1722 -Aaron ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 2/2] fsl_ifc: Support all 8 IFC chip selects
On Wed, 2014-08-20 at 09:05 +0530, Prabhakar Kushwaha wrote: On 8/20/2014 5:38 AM, Scott Wood wrote: On Fri, 2014-08-15 at 16:07 -0500, Aaron Sierra wrote: Freescale's QorIQ T Series processors support 8 IFC chip selects within a memory map backward compatible with previous P Series processors which supported only 4 chip selects. Signed-off-by: Aaron Sierra asie...@xes-inc.com --- include/linux/fsl_ifc.h | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/include/linux/fsl_ifc.h b/include/linux/fsl_ifc.h index 84d60cb..62762ff 100644 --- a/include/linux/fsl_ifc.h +++ b/include/linux/fsl_ifc.h @@ -29,7 +29,7 @@ #include linux/of_platform.h #include linux/interrupt.h -#define FSL_IFC_BANK_COUNT 4 +#define FSL_IFC_BANK_COUNT 8 First please modify fsl_ifc_nand.c to limit itself to the number of banks it dynamically determines are present based on the IFC version. Number of available bank/chip select are defined by SoC and it is independent of SoC. Do you mean defined by the SoC and independent of the IFC version? It should be fix in following way Option 1: u-boot: fix device tree with number of available chip select. It may require IFC binding change Linux: Read device tree and determine the Chip Selects If we do this then it will need to be an optional property that defaults to the current assumption being made (4). In the future we really ought to check whether there are integration parameters when coming up with the initial binding for a hardware block... Option 2: Make it static because any way IFC NAND driver polls to FSL_IFC_BANK_COUNT to know NAND flash chip select. This patch is doing same. I don't understand what you're saying here. The driver does not know at compile time how many there are. What this patch does is assume it's OK to access non-existent registers in the rare case that there's no match in the registers that exist. Aaron tested this on P1010 and it seemed to work, though I'm not generally fond of relying on such things. -Scott ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH] PCI: Increase BAR size quirk for IBM ipr SAS Crocodile adapters
From: Douglas Lehr dll...@us.ibm.com
The Crocodile chip occasionally comes up with 4k and 8k BAR sizes.
Due to an errata, setting the SR-IOV page size causes the physical
function BARs to expand to the system page size. Since ppc64 uses
64k pages, when Linux tries to assign the smaller resource sizes
to the now 64k BARs the address will be truncated and the BARs will
overlap.
This quirk will force Linux to allocate the resource as a full page,
which will avoid the overlap.
Cc: sta...@vger.kernel.org
Signed-off-by: Douglas Lehr dll...@us.ibm.com
Signed-off-by: Anton Blanchard an...@samba.org
Acked-by: Milton Miller milt...@us.ibm.com
---
drivers/pci/quirks.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 80c2d01..45b946d 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -24,6 +24,7 @@
#include linux/ioport.h
#include linux/sched.h
#include linux/ktime.h
+#include linux/mm.h
#include asm/dma.h /* isa_dma_bridge_buggy */
#include pci.h
@@ -287,6 +288,24 @@ static void quirk_citrine(struct pci_dev *dev)
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM,PCI_DEVICE_ID_IBM_CITRINE,
quirk_citrine);
+/* On IBM Crocodile ipr SAS adapters, expand bar size to system page size. */
+static void quirk_extend_bar_to_page(struct pci_dev *dev)
+{
+ int i;
+
+ for (i = 0; i PCI_STD_RESOURCE_END; i++) {
+ struct resource *r = dev-resource[i];
+
+ if (r-flags IORESOURCE_MEM resource_size(r) PAGE_SIZE) {
+ dev_info(dev-dev, Setting Bar size to Page size);
+ r-end = PAGE_SIZE-1;
+ r-start = 0;
+ r-flags |= IORESOURCE_UNSET;
+ }
+ }
+}
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, 0x034a, quirk_extend_bar_to_page);
+
/*
* S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
* If it's needed, re-allocate the region.
--
1.7.9.5
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[PATCH] powerpc: fsl_pci: Fix PCI/PCI-X regression
The following commit prevents the MPC8548E on the XPedite5200 PrPMC
module from enumerating its PCI/PCI-X bus, though it was previously
able to:
powerpc/fsl-pci: use 'Header Type' to identify PCIE mode
The previous patch prevents any Freescale PCI-X bridge from enumerating
the bus, if it is hardware strapped into Agent mode.
In PCI-X, the Host is responsible for driving the PCI-X initialization
pattern to devices on the bus, so that they know whether to operate in
conventional PCI or PCI-X mode as well as what the bus timing will be.
For a PCI-X PrPMC, the pattern is driven by the mezzanine carrier it is
installed onto. Therefore, PrPMCs are PCI-X Agents, but they may still
enumerate the bus.
This patch depends on firmware to determine if the bridge should
perform enumeration based on factors other than the Host/Agent mode,
such as the state of the VITA 32-defined MONARCH# signal. If firmware
has determined that enumeration should be allowed, then it will set the
bridge's Bus Master bit in the Command register.
Without firmware intervention, the Bus Master bit defaults to 1 in Host
mode and 0 in Agent mode.
Cc: Minghuan Lian minghuan.l...@freescale.com
Signed-off-by: Aaron Sierra asie...@xes-inc.com
---
arch/powerpc/sysdev/fsl_pci.c | 21 +
1 file changed, 17 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 4bd091a..88d8844 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -463,7 +463,7 @@ int fsl_add_bridge(struct platform_device *pdev, int
is_primary)
struct pci_controller *hose;
struct resource rsrc;
const int *bus_range;
- u8 hdr_type, progif;
+ u8 hdr_type;
struct device_node *dev;
struct ccsr_pci __iomem *pci;
@@ -520,9 +520,22 @@ int fsl_add_bridge(struct platform_device *pdev, int
is_primary)
goto no_bridge;
} else {
- /* For PCI read PROG to identify controller mode */
- early_read_config_byte(hose, 0, 0, PCI_CLASS_PROG, progif);
- if ((progif 1) == 1)
+ u16 master;
+
+ /*
+* If the controller is PCI-X, then Host mode refers to a
+* bridge that drives the PCI-X initialization pattern to
+* indicate bus operating mode/frequency to devices on the bus.
+* Some hardware (specifically PrPMC modules) are Agents, since
+* the mezzanine carrier is responsible for driving the
+* pattern, but they still may perform bus enumeration.
+*
+* Allow the bridge to be used for enumeration, if hardware
+* strapping (Host mode) or firmware (Agent mode) has enabled
+* bus mastering.
+*/
+ early_read_config_word(hose, 0, 0, PCI_COMMAND, master);
+ if (!(master PCI_COMMAND_MASTER))
goto no_bridge;
}
--
1.9.1
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Re: [PATCH v2 1/2] powerpc/booke: Restrict SPE exception handlers to e200/e500 cores
On Wed, 2014-08-20 at 16:09 +0300, Mihai Caraman wrote: SPE exception handlers are now defined for 32-bit e500mc cores even though SPE unit is not present and CONFIG_SPE is undefined. Restrict SPE exception handlers to e200/e500 cores adding CONFIG_SPE_POSSIBLE and consequently guard __stup_ivors and __setup_cpu functions. Signed-off-by: Mihai Caraman mihai.cara...@freescale.com Cc: Scott Wood scottw...@freescale.com Cc: Alexander Graf ag...@suse.de --- v2: - use CONFIG_PPC_E500MC without CONFIG_E500 - use elif defined() arch/powerpc/kernel/cpu_setup_fsl_booke.S | 12 +++- arch/powerpc/kernel/cputable.c| 5 + arch/powerpc/kernel/head_fsl_booke.S | 18 +- arch/powerpc/platforms/Kconfig.cputype| 6 +- 4 files changed, 34 insertions(+), 7 deletions(-) Acked-by: Scott Wood scottw...@freescale.com -Scott ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH v2 2/2] powerpc/booke: Revert SPE/AltiVec common defines for interrupt numbers
On Wed, 2014-08-20 at 16:09 +0300, Mihai Caraman wrote: Book3E specification defines shared interrupt numbers for SPE and AltiVec units. Still SPE is present in e200/e500v2 cores while AltiVec is present in e6500 core. So we can currently decide at compile-time which unit to support exclusively. As Alexander Graf suggested, this will improve code readability especially in KVM. Use distinct defines to identify SPE/AltiVec interrupt numbers, reverting c58ce397 and 6b310fc5 patches that added common defines. Signed-off-by: Mihai Caraman mihai.cara...@freescale.com Cc: Scott Wood scottw...@freescale.com Cc: Alexander Graf ag...@suse.de --- arch/powerpc/kernel/exceptions-64e.S | 4 ++-- arch/powerpc/kernel/head_fsl_booke.S | 8 2 files changed, 6 insertions(+), 6 deletions(-) Acked-by: Scott Wood scottw...@freescale.com -Scott ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 1/1] powerpc/jump_label: use HAVE_JUMP_LABEL?
CONFIG_JUMP_LABEL doesn't ensure HAVE_JUMP_LABEL, if it is not the case use maintainers's own mutex to guard the modification of global values. Signed-off-by: Zhouyi Zhou yizhouz...@ict.ac.cn --- arch/powerpc/platforms/powernv/opal-tracepoints.c |2 +- arch/powerpc/platforms/pseries/lpar.c |2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/platforms/powernv/opal-tracepoints.c b/arch/powerpc/platforms/powernv/opal-tracepoints.c index d8a000a..ae14c40 100644 --- a/arch/powerpc/platforms/powernv/opal-tracepoints.c +++ b/arch/powerpc/platforms/powernv/opal-tracepoints.c @@ -2,7 +2,7 @@ #include linux/jump_label.h #include asm/trace.h -#ifdef CONFIG_JUMP_LABEL +#ifdef HAVE_JUMP_LABEL struct static_key opal_tracepoint_key = STATIC_KEY_INIT; void opal_tracepoint_regfunc(void) diff --git a/arch/powerpc/platforms/pseries/lpar.c b/arch/powerpc/platforms/pseries/lpar.c index 34e6423..059cfe0 100644 --- a/arch/powerpc/platforms/pseries/lpar.c +++ b/arch/powerpc/platforms/pseries/lpar.c @@ -642,7 +642,7 @@ EXPORT_SYMBOL(arch_free_page); #endif #ifdef CONFIG_TRACEPOINTS -#ifdef CONFIG_JUMP_LABEL +#ifdef HAVE_JUMP_LABEL struct static_key hcall_tracepoint_key = STATIC_KEY_INIT; void hcall_tracepoint_regfunc(void) -- 1.7.10.4 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] powerpc/pseries: Drop unnecessary continue
On Wed, 2014-08-13 at 14:48 +0530, Himangi Saraogi wrote: Continue is not needed at the bottom of a loop. True. I wonder though, is the code trying to continue to the outer loop? I stared at it for a minute but it wasn't obvious. I wonder if Robert still remembers? cheers diff --git a/arch/powerpc/platforms/pseries/cmm.c b/arch/powerpc/platforms/pseries/cmm.c index 2d8bf15..fc44ad0 100644 --- a/arch/powerpc/platforms/pseries/cmm.c +++ b/arch/powerpc/platforms/pseries/cmm.c @@ -555,7 +555,6 @@ static int cmm_mem_going_offline(void *arg) pa_last = pa_last-next; free_page((unsigned long)cmm_page_list); cmm_page_list = pa_last; - continue; } } pa_curr = pa_curr-next; ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] cpufreq: powernv: Register the driver with reboot notifier
On 08/18/2014 01:16 PM, Viresh Kumar wrote:
On 14 August 2014 16:49, Shilpasri G Bhat
shilpa.b...@linux.vnet.ibm.com wrote:
This patch ensures the cpus to kexec/reboot at nominal frequency.
Nominal frequency is the highest cpu frequency on PowerPC at
which the cores can run without getting throttled.
If the host kernel had set the cpus to a low pstate and then it
kexecs/reboots to a cpufreq disabled kernel it would cause the target
kernel to perform poorly. It will also increase the boot up time of
the target kernel. So set the cpus to high pstate, in this case to
nominal frequency before rebooting to avoid such scenarios.
The reboot notifier will suspend the cpufreq governor and enable
nominal frequency to be set during a reboot/kexec similar to the
suspend operartion.
Signed-off-by: Shilpasri G Bhat shilpa.b...@linux.vnet.ibm.com
Reviewed-by: Preeti U Murthy pre...@linux.vnet.ibm.com
---
drivers/cpufreq/powernv-cpufreq.c | 16
1 file changed, 16 insertions(+)
diff --git a/drivers/cpufreq/powernv-cpufreq.c
b/drivers/cpufreq/powernv-cpufreq.c
index 379c083..e9f3d3a 100644
--- a/drivers/cpufreq/powernv-cpufreq.c
+++ b/drivers/cpufreq/powernv-cpufreq.c
@@ -26,6 +26,7 @@
#include linux/cpufreq.h
#include linux/smp.h
#include linux/of.h
+#include linux/reboot.h
#include asm/cputhreads.h
#include asm/firmware.h
@@ -314,9 +315,21 @@ static int powernv_cpufreq_cpu_init(struct cpufreq_policy
*policy)
for (i = 0; i threads_per_core; i++)
cpumask_set_cpu(base + i, policy-cpus);
+ policy-suspend_freq = pstate_id_to_freq(powernv_pstate_info.nominal);
return cpufreq_table_validate_and_show(policy, powernv_freqs);
}
+static int powernv_cpufreq_reboot_notifier(struct notifier_block *nb,
+ unsigned long action, void *unused)
+{
+ cpufreq_suspend();
+ return NOTIFY_DONE;
+}
+
+static struct notifier_block powernv_cpufreq_reboot_nb = {
+ .notifier_call = powernv_cpufreq_reboot_notifier,
+};
+
static struct cpufreq_driver powernv_cpufreq_driver = {
.name = powernv-cpufreq,
.flags = CPUFREQ_CONST_LOOPS,
@@ -325,6 +338,7 @@ static struct cpufreq_driver powernv_cpufreq_driver = {
.target_index = powernv_cpufreq_target_index,
.get= powernv_cpufreq_get,
.attr = powernv_cpu_freq_attr,
+ .suspend= cpufreq_generic_suspend,
I couldn't understand why you have added a notifier here. This callback
by itself should be enough. Isn't it?
And then you have called cpufreq_suspend(), which is absolutely wrong,
from that notifier..
Hi Viresh,
The intention here is stop the cpufreq governor and then to set the cpus to
nominal frequency so as to ensure that the frequency won't be changed later.
The .suspend callback of the driver is not called during reboot/kexec.
So we need an explicit reboot notifier to call cpufreq-suspend() to
suffice the requirement.
Thanks and Regards,
Shilpa
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