[PATCH v3 4/4] powernv: powerpc: Add winkle support for offline cpus

[Shreyas B. Prabhu]

Winkle is a deep idle state supported in power8 chips. A core enters
winkle when all the threads of the core enter winkle. In this state
power supply to the entire chiplet i.e core, private L2 and private L3
is turned off. As a result it gives higher powersavings compared to
sleep.

But entering winkle results in a total hypervisor state loss. Hence the
hypervisor context has to be preserved before entering winkle and
restored upon wake up.

Power-on Reset Engine (PORE) is a dedicated engine which is responsible
for powering on the chiplet during wake up. It can be programmed to
restore the register contests of a few specific registers. This patch
uses PORE to restore register state wherever possible and uses stack to
save and restore rest of the necessary registers.

With hypervisor state restore things fall under three categories-
per-core state, per-subcore state and per-thread state. To manage this,
extend the infrastructure introduced for sleep. Mainly we add a paca
variable subcore_sibling_mask. Using this and the core_idle_state we can
distingush first thread in core and subcore.

Signed-off-by: Shreyas B. Prabhu 
Cc: Benjamin Herrenschmidt 
Cc: Paul Mackerras 
Cc: Michael Ellerman 
Cc: linuxppc-dev@lists.ozlabs.org
---
 arch/powerpc/include/asm/opal.h|   3 +
 arch/powerpc/include/asm/paca.h|   2 +
 arch/powerpc/include/asm/ppc-opcode.h  |   2 +
 arch/powerpc/include/asm/processor.h   |   1 +
 arch/powerpc/include/asm/reg.h |   2 +
 arch/powerpc/kernel/asm-offsets.c  |   2 +
 arch/powerpc/kernel/exceptions-64s.S   |  16 ++-
 arch/powerpc/kernel/idle_power7.S  | 151 +++--
 arch/powerpc/platforms/powernv/opal-wrappers.S |   1 +
 arch/powerpc/platforms/powernv/setup.c |  73 
 arch/powerpc/platforms/powernv/smp.c   |   4 +-
 arch/powerpc/platforms/powernv/subcore.c   |  34 ++
 arch/powerpc/platforms/powernv/subcore.h   |   1 +
 13 files changed, 280 insertions(+), 12 deletions(-)

diff --git a/arch/powerpc/include/asm/opal.h b/arch/powerpc/include/asm/opal.h
index bef7fbc..f0ca2d9 100644
--- a/arch/powerpc/include/asm/opal.h
+++ b/arch/powerpc/include/asm/opal.h
@@ -153,6 +153,7 @@ struct opal_sg_list {
 #define OPAL_PCI_EEH_FREEZE_SET97
 #define OPAL_HANDLE_HMI98
 #define OPAL_CONFIG_CPU_IDLE_STATE 99
+#define OPAL_SLW_SET_REG   100
 #define OPAL_REGISTER_DUMP_REGION  101
 #define OPAL_UNREGISTER_DUMP_REGION102
 
@@ -163,6 +164,7 @@ struct opal_sg_list {
  */
 #define OPAL_PM_NAP_ENABLED0x0001
 #define OPAL_PM_SLEEP_ENABLED  0x0002
+#define OPAL_PM_WINKLE_ENABLED 0x0004
 #define OPAL_PM_SLEEP_ENABLED_ER1  0x0008
 
 #ifndef __ASSEMBLY__
@@ -972,6 +974,7 @@ int64_t opal_sensor_read(uint32_t sensor_hndl, int token, 
__be32 *sensor_data);
 int64_t opal_handle_hmi(void);
 int64_t opal_register_dump_region(uint32_t id, uint64_t start, uint64_t end);
 int64_t opal_unregister_dump_region(uint32_t id);
+int64_t opal_slw_set_reg(uint64_t cpu_pir, uint64_t sprn, uint64_t val);
 int64_t opal_pci_set_phb_cxl_mode(uint64_t phb_id, uint64_t mode, uint64_t 
pe_number);
 
 /* Internal functions */
diff --git a/arch/powerpc/include/asm/paca.h b/arch/powerpc/include/asm/paca.h
index e4578c3..e89f4a4 100644
--- a/arch/powerpc/include/asm/paca.h
+++ b/arch/powerpc/include/asm/paca.h
@@ -164,6 +164,8 @@ struct paca_struct {
u8 thread_idle_state;   /* ~Idle[0]/Nap[1]/Sleep[2]/Winkle[3] */
/* Mask to indicate thread id in core */
u8 thread_mask;
+   /* Mask to denote subcore sibling threads */
+   u8 subcore_sibling_mask;
 #endif
 #ifdef CONFIG_PPC_BOOK3S_64
/* Exclusive emergency stack pointer for machine check exception. */
diff --git a/arch/powerpc/include/asm/ppc-opcode.h 
b/arch/powerpc/include/asm/ppc-opcode.h
index 6f85362..5155be7 100644
--- a/arch/powerpc/include/asm/ppc-opcode.h
+++ b/arch/powerpc/include/asm/ppc-opcode.h
@@ -194,6 +194,7 @@
 
 #define PPC_INST_NAP   0x4c000364
 #define PPC_INST_SLEEP 0x4c0003a4
+#define PPC_INST_WINKLE0x4c0003e4
 
 /* A2 specific instructions */
 #define PPC_INST_ERATWE0x7c0001a6
@@ -374,6 +375,7 @@
 
 #define PPC_NAPstringify_in_c(.long PPC_INST_NAP)
 #define PPC_SLEEP  stringify_in_c(.long PPC_INST_SLEEP)
+#define PPC_WINKLE stringify_in_c(.long PPC_INST_WINKLE)
 
 /* BHRB instructions */
 #define PPC_CLRBHRBstringify_in_c(.long PPC_INST_CLRBHRB)
diff --git a/arch/powerpc/include/asm/processor.h 
b/arch/powerpc/include/asm/processor.h
index dda7ac4..c076842 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -453,6 +453,7 @@ enum idle_boot_override {IDLE_NO_OVERRIDE

[PATCH v3 3/4] powernv: cpuidle: Redesign idle states management

[Shreyas B. Prabhu]

Deep idle states like sleep and winkle are per core idle states. A core
enters these states only when all the threads enter either the
particular idle state or a deeper one. There are tasks like fastsleep
hardware bug workaround and hypervisor core state save which have to be
done only by the last thread of the core entering deep idle state and
similarly tasks like timebase resync, hypervisor core register restore
that have to be done only by the first thread waking up from these
state.

The current idle state management does not have a way to distinguish the
first/last thread of the core waking/entering idle states. Tasks like
timebase resync are done for all the threads. This is not only is
suboptimal, but can cause functionality issues when subcores and kvm is
involved.

This patch adds the necessary infrastructure to track idle states of
threads in a per-core structure. It uses this info to perform tasks like
fastsleep workaround and timebase resync only once per core.

Signed-off-by: Shreyas B. Prabhu 
Originally-by: Preeti U. Murthy 
Cc: Benjamin Herrenschmidt 
Cc: Paul Mackerras 
Cc: Michael Ellerman 
Cc: Rafael J. Wysocki 
Cc: linux...@vger.kernel.org
Cc: linuxppc-dev@lists.ozlabs.org
---
 arch/powerpc/include/asm/cpuidle.h |  20 +++
 arch/powerpc/include/asm/opal.h|   2 +
 arch/powerpc/include/asm/paca.h|   6 +
 arch/powerpc/kernel/asm-offsets.c  |   6 +
 arch/powerpc/kernel/exceptions-64s.S   |  24 ++--
 arch/powerpc/kernel/idle_power7.S  | 188 +++--
 arch/powerpc/platforms/powernv/opal-wrappers.S |  37 +
 arch/powerpc/platforms/powernv/setup.c |  47 ++-
 arch/powerpc/platforms/powernv/smp.c   |   3 +-
 drivers/cpuidle/cpuidle-powernv.c  |   3 +-
 10 files changed, 277 insertions(+), 59 deletions(-)
 create mode 100644 arch/powerpc/include/asm/cpuidle.h

diff --git a/arch/powerpc/include/asm/cpuidle.h 
b/arch/powerpc/include/asm/cpuidle.h
new file mode 100644
index 000..d2f99ca
--- /dev/null
+++ b/arch/powerpc/include/asm/cpuidle.h
@@ -0,0 +1,20 @@
+#ifndef _ASM_POWERPC_CPUIDLE_H
+#define _ASM_POWERPC_CPUIDLE_H
+
+#ifdef CONFIG_PPC_POWERNV
+/* Used in powernv idle state management */
+#define PNV_THREAD_RUNNING  0
+#define PNV_THREAD_NAP  1
+#define PNV_THREAD_SLEEP2
+#define PNV_THREAD_WINKLE   3
+#define PNV_CORE_IDLE_LOCK_BIT  0x100
+#define PNV_CORE_IDLE_THREAD_BITS   0x0FF
+
+#ifndef __ASSEMBLY__
+extern u32 pnv_fastsleep_workaround_at_entry[];
+extern u32 pnv_fastsleep_workaround_at_exit[];
+#endif
+
+#endif
+
+#endif
diff --git a/arch/powerpc/include/asm/opal.h b/arch/powerpc/include/asm/opal.h
index f8b95c0..bef7fbc 100644
--- a/arch/powerpc/include/asm/opal.h
+++ b/arch/powerpc/include/asm/opal.h
@@ -152,6 +152,7 @@ struct opal_sg_list {
 #define OPAL_PCI_ERR_INJECT96
 #define OPAL_PCI_EEH_FREEZE_SET97
 #define OPAL_HANDLE_HMI98
+#define OPAL_CONFIG_CPU_IDLE_STATE 99
 #define OPAL_REGISTER_DUMP_REGION  101
 #define OPAL_UNREGISTER_DUMP_REGION102
 
@@ -162,6 +163,7 @@ struct opal_sg_list {
  */
 #define OPAL_PM_NAP_ENABLED0x0001
 #define OPAL_PM_SLEEP_ENABLED  0x0002
+#define OPAL_PM_SLEEP_ENABLED_ER1  0x0008
 
 #ifndef __ASSEMBLY__
 
diff --git a/arch/powerpc/include/asm/paca.h b/arch/powerpc/include/asm/paca.h
index a5139ea..e4578c3 100644
--- a/arch/powerpc/include/asm/paca.h
+++ b/arch/powerpc/include/asm/paca.h
@@ -158,6 +158,12 @@ struct paca_struct {
 * early exception handler for use by high level C handler
 */
struct opal_machine_check_event *opal_mc_evt;
+
+   /* Per-core mask tracking idle threads and a lock bit-[L][] */
+   u32 *core_idle_state_ptr;
+   u8 thread_idle_state;   /* ~Idle[0]/Nap[1]/Sleep[2]/Winkle[3] */
+   /* Mask to indicate thread id in core */
+   u8 thread_mask;
 #endif
 #ifdef CONFIG_PPC_BOOK3S_64
/* Exclusive emergency stack pointer for machine check exception. */
diff --git a/arch/powerpc/kernel/asm-offsets.c 
b/arch/powerpc/kernel/asm-offsets.c
index 9d7dede..3bc0352 100644
--- a/arch/powerpc/kernel/asm-offsets.c
+++ b/arch/powerpc/kernel/asm-offsets.c
@@ -731,6 +731,12 @@ int main(void)
DEFINE(OPAL_MC_SRR0, offsetof(struct opal_machine_check_event, srr0));
DEFINE(OPAL_MC_SRR1, offsetof(struct opal_machine_check_event, srr1));
DEFINE(PACA_OPAL_MC_EVT, offsetof(struct paca_struct, opal_mc_evt));
+   DEFINE(PACA_CORE_IDLE_STATE_PTR,
+   offsetof(struct paca_struct, core_idle_state_ptr));
+   DEFINE(PACA_THREAD_IDLE_STATE,
+   offsetof(struct paca_struct, thread_idle_state));
+   DEFINE(PACA_THREAD_MASK,
+   offsetof(struct paca_struct, thread_mask));
 #endif
 
 

[PATCH v3 2/4] powerpc/powernv: Enable Offline CPUs to enter deep idle states

[Shreyas B. Prabhu]

From: "Preeti U. Murthy" 

The secondary threads should enter deep idle states so as to gain maximum
powersavings when the entire core is offline. To do so the offline path
must be made aware of the available deepest idle state. Hence probe the
device tree for the possible idle states in powernv core code and
expose the deepest idle state through flags.

Since the  device tree is probed by the cpuidle driver as well, move
the parameters required to discover the idle states into an appropriate
common place to both the driver and the powernv core code.

Another point is that fastsleep idle state may require workarounds in
the kernel to function properly. This workaround is introduced in the
subsequent patches. However neither the cpuidle driver or the hotplug
path need be bothered about this workaround.

They will be taken care of by the core powernv code.

Originally-by: Srivatsa S. Bhat 
Signed-off-by: Preeti U. Murthy 
Signed-off-by: Shreyas B. Prabhu 
Cc: Benjamin Herrenschmidt 
Cc: Paul Mackerras 
Cc: Michael Ellerman 
Cc: Rafael J. Wysocki 
Cc: linux...@vger.kernel.org
Cc: linuxppc-dev@lists.ozlabs.org
---
 arch/powerpc/include/asm/opal.h  |  8 ++
 arch/powerpc/platforms/powernv/powernv.h |  2 ++
 arch/powerpc/platforms/powernv/setup.c   | 49 
 arch/powerpc/platforms/powernv/smp.c |  7 -
 drivers/cpuidle/cpuidle-powernv.c|  9 ++
 5 files changed, 68 insertions(+), 7 deletions(-)

diff --git a/arch/powerpc/include/asm/opal.h b/arch/powerpc/include/asm/opal.h
index 9124b0e..f8b95c0 100644
--- a/arch/powerpc/include/asm/opal.h
+++ b/arch/powerpc/include/asm/opal.h
@@ -155,6 +155,14 @@ struct opal_sg_list {
 #define OPAL_REGISTER_DUMP_REGION  101
 #define OPAL_UNREGISTER_DUMP_REGION102
 
+/* Device tree flags */
+
+/* Flags set in power-mgmt nodes in device tree if
+ * respective idle states are supported in the platform.
+ */
+#define OPAL_PM_NAP_ENABLED0x0001
+#define OPAL_PM_SLEEP_ENABLED  0x0002
+
 #ifndef __ASSEMBLY__
 
 #include 
diff --git a/arch/powerpc/platforms/powernv/powernv.h 
b/arch/powerpc/platforms/powernv/powernv.h
index 6c8e2d1..604c48e 100644
--- a/arch/powerpc/platforms/powernv/powernv.h
+++ b/arch/powerpc/platforms/powernv/powernv.h
@@ -29,6 +29,8 @@ static inline u64 pnv_pci_dma_get_required_mask(struct 
pci_dev *pdev)
 }
 #endif
 
+extern u32 pnv_get_supported_cpuidle_states(void);
+
 extern void pnv_lpc_init(void);
 
 bool cpu_core_split_required(void);
diff --git a/arch/powerpc/platforms/powernv/setup.c 
b/arch/powerpc/platforms/powernv/setup.c
index 3f9546d..34c6665 100644
--- a/arch/powerpc/platforms/powernv/setup.c
+++ b/arch/powerpc/platforms/powernv/setup.c
@@ -290,6 +290,55 @@ static void __init pnv_setup_machdep_rtas(void)
 }
 #endif /* CONFIG_PPC_POWERNV_RTAS */
 
+static u32 supported_cpuidle_states;
+
+u32 pnv_get_supported_cpuidle_states(void)
+{
+   return supported_cpuidle_states;
+}
+
+static int __init pnv_init_idle_states(void)
+{
+   struct device_node *power_mgt;
+   int dt_idle_states;
+   const __be32 *idle_state_flags;
+   u32 len_flags, flags;
+   int i;
+
+   supported_cpuidle_states = 0;
+
+   if (cpuidle_disable != IDLE_NO_OVERRIDE)
+   return 0;
+
+   if (!firmware_has_feature(FW_FEATURE_OPALv3))
+   return 0;
+
+   power_mgt = of_find_node_by_path("/ibm,opal/power-mgt");
+   if (!power_mgt) {
+   pr_warn("opal: PowerMgmt Node not found\n");
+   return 0;
+   }
+
+   idle_state_flags = of_get_property(power_mgt,
+   "ibm,cpu-idle-state-flags", &len_flags);
+   if (!idle_state_flags) {
+   pr_warn("DT-PowerMgmt: missing ibm,cpu-idle-state-flags\n");
+   return 0;
+   }
+
+   dt_idle_states = len_flags / sizeof(u32);
+
+   for (i = 0; i < dt_idle_states; i++) {
+   flags = be32_to_cpu(idle_state_flags[i]);
+   supported_cpuidle_states |= flags;
+   }
+
+   return 0;
+}
+
+subsys_initcall(pnv_init_idle_states);
+
+
 static int __init pnv_probe(void)
 {
unsigned long root = of_get_flat_dt_root();
diff --git a/arch/powerpc/platforms/powernv/smp.c 
b/arch/powerpc/platforms/powernv/smp.c
index 4753958..3dc4cec 100644
--- a/arch/powerpc/platforms/powernv/smp.c
+++ b/arch/powerpc/platforms/powernv/smp.c
@@ -149,6 +149,7 @@ static int pnv_smp_cpu_disable(void)
 static void pnv_smp_cpu_kill_self(void)
 {
unsigned int cpu;
+   u32 idle_states;
 
/* Standard hot unplug procedure */
local_irq_disable();
@@ -159,13 +160,17 @@ static void pnv_smp_cpu_kill_self(void)
generic_set_cpu_dead(cpu);
smp_wmb();
 
+   idle_states = pnv_get_supported_cpuidle_states();
/* We don't want to take decrementer interrupts while we are offline,
 * so clear LPCR:PECE1. We keep PECE2 enabled.
 */
mtspr(SPRN_LPCR, mfspr

[PATCH v3 1/4] powerpc: powernv: Switch off MMU before entering nap/sleep/rvwinkle mode

[Shreyas B. Prabhu]

From: Paul Mackerras 

Currently, when going idle, we set the flag indicating that we are in
nap mode (paca->kvm_hstate.hwthread_state) and then execute the nap
(or sleep or rvwinkle) instruction, all with the MMU on.  This is bad
for two reasons: (a) the architecture specifies that those instructions
must be executed with the MMU off, and in fact with only the SF, HV, ME
and possibly RI bits set, and (b) this introduces a race, because as
soon as we set the flag, another thread can switch the MMU to a guest
context.  If the race is lost, this thread will typically start looping
on relocation-on ISIs at 0xc...4400.

This fixes it by setting the MSR as required by the architecture before
setting the flag or executing the nap/sleep/rvwinkle instruction.

[ shre...@linux.vnet.ibm.com: Edited to handle LE ]
Signed-off-by: Paul Mackerras 
Signed-off-by: Shreyas B. Prabhu 
Cc: Benjamin Herrenschmidt 
Cc: Michael Ellerman 
Cc: linuxppc-dev@lists.ozlabs.org
---
 arch/powerpc/include/asm/reg.h|  2 ++
 arch/powerpc/kernel/idle_power7.S | 18 +-
 2 files changed, 19 insertions(+), 1 deletion(-)

diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index c998279..a68ee15 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -118,8 +118,10 @@
 #define __MSR  (MSR_ME | MSR_RI | MSR_IR | MSR_DR | MSR_ISF |MSR_HV)
 #ifdef __BIG_ENDIAN__
 #define MSR_   __MSR
+#define MSR_IDLE   (MSR_ME | MSR_SF | MSR_HV)
 #else
 #define MSR_   (__MSR | MSR_LE)
+#define MSR_IDLE   (MSR_ME | MSR_SF | MSR_HV | MSR_LE)
 #endif
 #define MSR_KERNEL (MSR_ | MSR_64BIT)
 #define MSR_USER32 (MSR_ | MSR_PR | MSR_EE)
diff --git a/arch/powerpc/kernel/idle_power7.S 
b/arch/powerpc/kernel/idle_power7.S
index c0754bb..283c603 100644
--- a/arch/powerpc/kernel/idle_power7.S
+++ b/arch/powerpc/kernel/idle_power7.S
@@ -101,7 +101,23 @@ _GLOBAL(power7_powersave_common)
std r9,_MSR(r1)
std r1,PACAR1(r13)
 
-_GLOBAL(power7_enter_nap_mode)
+   /*
+* Go to real mode to do the nap, as required by the architecture.
+* Also, we need to be in real mode before setting hwthread_state,
+* because as soon as we do that, another thread can switch
+* the MMU context to the guest.
+*/
+   LOAD_REG_IMMEDIATE(r5, MSR_IDLE)
+   li  r6, MSR_RI
+   andcr6, r9, r6
+   LOAD_REG_ADDR(r7, power7_enter_nap_mode)
+   mtmsrd  r6, 1   /* clear RI before setting SRR0/1 */
+   mtspr   SPRN_SRR0, r7
+   mtspr   SPRN_SRR1, r5
+   rfid
+
+   .globl  power7_enter_nap_mode
+power7_enter_nap_mode:
 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
/* Tell KVM we're napping */
li  r4,KVM_HWTHREAD_IN_NAP
-- 
1.9.3

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[PATCH v3 0/4] powernv: cpuidle: Redesign idle states management

[Shreyas B. Prabhu]

Deep idle states like sleep and winkle are per core idle states. A core
enters these states only when all the threads enter either the particular
idle state or a deeper one. There are tasks like fastsleep hardware bug
workaround and hypervisor core state save which have to be done only by
the last thread of the core entering deep idle state and similarly tasks
like timebase resync, hypervisor core register restore that have to be
done only by the first thread waking up from these states. 

The current idle state management does not have a way to distinguish the
first/last thread of the core waking/entering idle states. Tasks like
timebase resync are done for all the threads. This is not only is suboptimal,
but can cause functionality issues when subcores are involved.

Winkle is deeper idle state compared to fastsleep. In this state the power
supply to the chiplet, i.e core, private L2 and private L3 is turned off.
This results in a total hypervisor state loss. This patch set adds support
for winkle and provides a way to track the idle states of the threads of the
core and use it for idle state management of idle states sleep and winkle.

TBD:

- Remove duplication of branching to kvm code. 

Changes in v3:
-
- Added barriers after lock
- Added a paca field to that stores thread mask. 
- Changed code structure around fastsleep workaround, to allow for manual
  patching out if the platform does not require it. 
- Threads waiting on core_idle_state lock now loop in HMT_LOW
- Using NV CRs to avoid save/restore of CR while making OPAL calls.
- Fixed couple of flow issues in path where fastsleep workaround was not needed
- Using PPC_LR_STKOFF instead of _LINK in opal_call_realmode
- Restoring WORT and WORC

Changes in v2:
--
-Using PNV_THREAD_NAP/SLEEP defines while calling power7_powersave_common
-Comment changes based on review
-Rebased on top of 3.18-rc6


Cc: Benjamin Herrenschmidt 
Cc: Paul Mackerras 
Cc: Michael Ellerman 
Cc: Rafael J. Wysocki 
Cc: linux...@vger.kernel.org
Cc: linuxppc-dev@lists.ozlabs.org
Cc: Vaidyanathan Srinivasan 
Cc: Preeti U Murthy 

Paul Mackerras (1):
  powerpc: powernv: Switch off MMU before entering nap/sleep/rvwinkle
mode

Preeti U. Murthy (1):
  powerpc/powernv: Enable Offline CPUs to enter deep idle states

Shreyas B. Prabhu (2):
  powernv: cpuidle: Redesign idle states management
  powernv: powerpc: Add winkle support for offline cpus

 arch/powerpc/include/asm/cpuidle.h |  14 ++
 arch/powerpc/include/asm/opal.h|  13 +
 arch/powerpc/include/asm/paca.h|   6 +
 arch/powerpc/include/asm/ppc-opcode.h  |   2 +
 arch/powerpc/include/asm/processor.h   |   1 +
 arch/powerpc/include/asm/reg.h |   4 +
 arch/powerpc/kernel/asm-offsets.c  |   6 +
 arch/powerpc/kernel/cpu_setup_power.S  |   4 +
 arch/powerpc/kernel/exceptions-64s.S   |  30 ++-
 arch/powerpc/kernel/idle_power7.S  | 332 +
 arch/powerpc/platforms/powernv/opal-wrappers.S |  39 +++
 arch/powerpc/platforms/powernv/powernv.h   |   2 +
 arch/powerpc/platforms/powernv/setup.c | 160 
 arch/powerpc/platforms/powernv/smp.c   |  10 +-
 arch/powerpc/platforms/powernv/subcore.c   |  34 +++
 arch/powerpc/platforms/powernv/subcore.h   |   1 +
 drivers/cpuidle/cpuidle-powernv.c  |  10 +-
 17 files changed, 608 insertions(+), 60 deletions(-)
 create mode 100644 arch/powerpc/include/asm/cpuidle.h

-- 
1.9.3

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Re: powerpc/pci: remove pci device on a bus in reverse order

[Wei Yang]

On Thu, Dec 04, 2014 at 04:40:35PM +1100, Michael Ellerman wrote:
>On Thu, 2014-04-12 at 03:24:37 UTC, Wei Yang wrote:
>> As in commit ac205b7b (PCI: make sriov work with hotplug remove) indicates,
>> when removing pci devices on a bus which has VFs, we need to remove them in
>> the reverse order.
>> 
>> This patch applies this pattern on the hotplug remove path on powerpc arch.
>
>So is this is a bug fix?

It hasn't trigger a bug yet. I found this issue during the code reading. When
VFs are enabled and try to remove a bus with VFs, it will face a problem. So I
port the change in commit ac205b7b here.

>
>Where/how have you tested this?

I have tested after change on Power8, the EEH hotplug path works fine for PFs
now. Will test this when EEH for VFs are ready.

Suggest me to keep it untill EEH for VFs are ready?

>
>cheers

-- 
Richard Yang
Help you, Help me

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Re: [PATCH v3 1/3] Revert "clk: ppc-corenet: Fix Section mismatch warning"

[Kevin Hao]

On Wed, Dec 03, 2014 at 10:46:24PM -0600, Scott Wood wrote:
> Since only this first patch is a critical bugfix, and there's no
> arch/powerpc content in that patch, I think it should go via Mike's tree
> if it's to go in for 3.18 (if it's not already too late).  Or, to keep
> things simple given the dependency of the following patches, we could
> batch them all together for -next and add a # 3.18 stable request.

We don't need to explicitly add a #3.18 stable request in this case. As I know,
we only need to indicate the first version which is affected by the bug fixed by
this commit in the cc tag. This would imply that the applicable stable kernel
version rang should be from 3.17 to the previous version of the kernel which
finally merge this commit.

Thanks,
Kevin


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Re: powerpc: remove the smt-enabled kernel parameter

[Michael Ellerman]

On Wed, 2014-03-12 at 13:58:13 UTC, Greg Kurz wrote:
> This parameter basically leaves unwanted cpus executing in firmware or
> wherever they happen to be. This is a hack that shoudn't be used in a
> production environment.
> 
> It also has an evil side effect on the split-core feature for powernv. The
> code needs all the cpus to participate to the split mode update: it relies
> on smp_send_reschedule() to get offline ones to do so. This doesn't work with
> cpus that haven't come up... The consequence is a kernel hang at boot time
> on powernv when smt-enabled is used to limit the number of threads.
> 
> This patch simply removes the smt-enabled kernel parameter for all platforms.
> >From now on, SMT mode should be set by userspace.
> 
> I see there also is a ibm,smt-enabled property but I could not find any
> piece of information about it. Since it does the very same thing as the
> kernel parameter, it is tempting to drop it alike... This would possibly
> allow more simplification like killing the cpu_bootable hook.
> 
> Please give advice anyone.

Hi Greg,

Thanks for doing this.

I discussed this on irc and Benh & Anton both agree we should drop it.

Please send a v2 which also drops the support for ibm,smt-enabled.

Our reasoning is 1) it doesn't work correctly in the same way as the command
line option, 2) no one is aware of anything that still uses it, 3) there are
better ways for firmware to disable SMT.

Can you then send a 2nd patch which removes the cpu_bootable hook.

cheers
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[PATCH 4/5] powerpc/powernv: Functions to retrieve PCI slot status

[Gavin Shan]

The patch exports two functions, which base on corresponding OPAL
APIs to retrieve PCI slot status. Those functions are going to be
used by PCI hotplug module in subsequent patches:

   pnv_pci_get_power_status() opal_pci_get_power_status()
   pnv_pci_get_presence_status()  opal_pci_get_presence_status()

Signed-off-by: Gavin Shan 
---
 arch/powerpc/include/asm/opal.h|  4 
 arch/powerpc/include/asm/pnv-pci.h |  3 +++
 arch/powerpc/platforms/powernv/opal-wrappers.S |  2 ++
 arch/powerpc/platforms/powernv/pci.c   | 24 
 4 files changed, 33 insertions(+)

diff --git a/arch/powerpc/include/asm/opal.h b/arch/powerpc/include/asm/opal.h
index edd1993..c17fe80 100644
--- a/arch/powerpc/include/asm/opal.h
+++ b/arch/powerpc/include/asm/opal.h
@@ -154,6 +154,8 @@ struct opal_sg_list {
 #define OPAL_HANDLE_HMI98
 #define OPAL_REGISTER_DUMP_REGION  101
 #define OPAL_UNREGISTER_DUMP_REGION102
+#define OPAL_PCI_GET_POWER_STATUS  110
+#define OPAL_PCI_GET_PRESENCE_STATUS   111
 
 #ifndef __ASSEMBLY__
 
@@ -958,6 +960,8 @@ int64_t opal_handle_hmi(void);
 int64_t opal_register_dump_region(uint32_t id, uint64_t start, uint64_t end);
 int64_t opal_unregister_dump_region(uint32_t id);
 int64_t opal_pci_set_phb_cxl_mode(uint64_t phb_id, uint64_t mode, uint64_t 
pe_number);
+int64_t opal_pci_get_power_status(uint64_t id, uint8_t *status);
+int64_t opal_pci_get_presence_status(uint64_t id, uint8_t *status);
 
 /* Internal functions */
 extern int early_init_dt_scan_opal(unsigned long node, const char *uname,
diff --git a/arch/powerpc/include/asm/pnv-pci.h 
b/arch/powerpc/include/asm/pnv-pci.h
index f09a22f..fc73f72 100644
--- a/arch/powerpc/include/asm/pnv-pci.h
+++ b/arch/powerpc/include/asm/pnv-pci.h
@@ -13,6 +13,9 @@
 #include 
 #include 
 
+extern int pnv_pci_get_power_status(uint64_t id, uint8_t *status);
+extern int pnv_pci_get_presence_status(uint64_t id, uint8_t *status);
+
 int pnv_phb_to_cxl(struct pci_dev *dev);
 int pnv_cxl_ioda_msi_setup(struct pci_dev *dev, unsigned int hwirq,
   unsigned int virq);
diff --git a/arch/powerpc/platforms/powernv/opal-wrappers.S 
b/arch/powerpc/platforms/powernv/opal-wrappers.S
index feb549a..bc5be98 100644
--- a/arch/powerpc/platforms/powernv/opal-wrappers.S
+++ b/arch/powerpc/platforms/powernv/opal-wrappers.S
@@ -250,3 +250,5 @@ OPAL_CALL(opal_handle_hmi,  
OPAL_HANDLE_HMI);
 OPAL_CALL(opal_register_dump_region,   OPAL_REGISTER_DUMP_REGION);
 OPAL_CALL(opal_unregister_dump_region, OPAL_UNREGISTER_DUMP_REGION);
 OPAL_CALL(opal_pci_set_phb_cxl_mode,   OPAL_PCI_SET_PHB_CXL_MODE);
+OPAL_CALL(opal_pci_get_power_status,   OPAL_PCI_GET_POWER_STATUS);
+OPAL_CALL(opal_pci_get_presence_status,
OPAL_PCI_GET_PRESENCE_STATUS);
diff --git a/arch/powerpc/platforms/powernv/pci.c 
b/arch/powerpc/platforms/powernv/pci.c
index 6dc8ea9..d3af9e5 100644
--- a/arch/powerpc/platforms/powernv/pci.c
+++ b/arch/powerpc/platforms/powernv/pci.c
@@ -64,6 +64,30 @@ int pnv_pci_poll(uint64_t id, int64_t rval, uint8_t *pval)
return rval ? -EIO : 0;
 }
 
+int pnv_pci_get_power_status(uint64_t id, uint8_t *status)
+{
+   long rc;
+
+   if (!opal_check_token(OPAL_PCI_GET_POWER_STATUS))
+   return -ENXIO;
+
+   rc = opal_pci_get_power_status(id, status);
+   return pnv_pci_poll(id, rc, status);
+}
+EXPORT_SYMBOL_GPL(pnv_pci_get_power_status);
+
+int pnv_pci_get_presence_status(uint64_t id, uint8_t *status)
+{
+   long rc;
+
+   if (!opal_check_token(OPAL_PCI_GET_PRESENCE_STATUS))
+   return -ENXIO;
+
+   rc = opal_pci_get_presence_status(id, status);
+   return pnv_pci_poll(id, rc, status);
+}
+EXPORT_SYMBOL_GPL(pnv_pci_get_presence_status);
+
 #ifdef CONFIG_PCI_MSI
 static int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
 {
-- 
1.8.3.2

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[PATCH v2 0/5] PCI Hotplug Driver for PowerPC PowerNV

[Gavin Shan]

The series of patches depends on the OPAL firmware changes. If the firmware
doesn't have the changes, PCI hotplug slots won't be populated properly.
Other than that, no more problems found.

A new driver "powernv-php.ko" is introduced by the patchset to support
PCI hotplug for PowerNV platform. The device tree is scanned when the
driver is loaded. If any PCI device node is equipped with property "ibm,
slot-pluggable" and "ibm,reset-by-firmware", it's regarded as hotpluggable
slot and the driver creates/registers slot for it. After that, the sysfs
entries can be used to operate the slot.

PATCH[1-4]: Necessary code changes to PPC PCI subsystem in order to
support PCI slots for PPC PowerNV platform.
PATCH[5]  : powernv-php driver to support PCI hotplug for PowerNV
platform.

Testing
===
# cat /proc/cpuinfo | grep -i powernv
platform: PowerNV
machine : PowerNV 8286-41A

# pwd
/sys/bus/pci/slots
# ls
C10  C11  C12  C14  C15  C6  C7  C8  C9

# lspci -s 0003::.
0003:00:00.0 PCI bridge: IBM Device 03dc
0003:01:00.0 PCI bridge: PLX Technology, Inc. Device 8748 (rev ca)
0003:02:01.0 PCI bridge: PLX Technology, Inc. Device 8748 (rev ca)
0003:02:08.0 PCI bridge: PLX Technology, Inc. Device 8748 (rev ca)
0003:02:09.0 PCI bridge: PLX Technology, Inc. Device 8748 (rev ca)
0003:02:10.0 PCI bridge: PLX Technology, Inc. Device 8748 (rev ca)
0003:02:11.0 PCI bridge: PLX Technology, Inc. Device 8748 (rev ca)
0003:03:00.0 USB controller: Texas Instruments TUSB73x0 SuperSpeed USB 3.0 xHCI 
Host Controller (rev 02)
0003:09:00.0 Ethernet controller: Broadcom Corporation NetXtreme BCM5719 
Gigabit Ethernet PCIe (rev 01)
0003:09:00.1 Ethernet controller: Broadcom Corporation NetXtreme BCM5719 
Gigabit Ethernet PCIe (rev 01)
0003:09:00.2 Ethernet controller: Broadcom Corporation NetXtreme BCM5719 
Gigabit Ethernet PCIe (rev 01)
0003:09:00.3 Ethernet controller: Broadcom Corporation NetXtreme BCM5719 
Gigabit Ethernet PCIe (rev 01)
0003:0f:00.0 Network controller: Mellanox Technologies MT27500 Family 
[ConnectX-3]
# pwd
/sys/bus/pci/slots/C10
# cat address
0003:09:00
# cat cur_bus_speed
5.0 GT/s PCIe
# cat max_bus_speed
8.0 GT/s PCIe
# cat power
1
# echo 0 > power
# lspci -s 0003::.
0003:00:00.0 PCI bridge: IBM Device 03dc
0003:01:00.0 PCI bridge: PLX Technology, Inc. Device 8748 (rev ca)
0003:02:01.0 PCI bridge: PLX Technology, Inc. Device 8748 (rev ca)
0003:02:08.0 PCI bridge: PLX Technology, Inc. Device 8748 (rev ca)
0003:02:09.0 PCI bridge: PLX Technology, Inc. Device 8748 (rev ca)
0003:02:10.0 PCI bridge: PLX Technology, Inc. Device 8748 (rev ca)
0003:02:11.0 PCI bridge: PLX Technology, Inc. Device 8748 (rev ca)
0003:03:00.0 USB controller: Texas Instruments TUSB73x0 SuperSpeed USB 3.0 xHCI 
Host Controller (rev 02)
0003:0f:00.0 Network controller: Mellanox Technologies MT27500 Family 
[ConnectX-3]
# echo 1 > power
# lspci -s 0003::.
0003:00:00.0 PCI bridge: IBM Device 03dc
0003:01:00.0 PCI bridge: PLX Technology, Inc. Device 8748 (rev ca)
0003:02:01.0 PCI bridge: PLX Technology, Inc. Device 8748 (rev ca)
0003:02:08.0 PCI bridge: PLX Technology, Inc. Device 8748 (rev ca)
0003:02:09.0 PCI bridge: PLX Technology, Inc. Device 8748 (rev ca)
0003:02:10.0 PCI bridge: PLX Technology, Inc. Device 8748 (rev ca)
0003:02:11.0 PCI bridge: PLX Technology, Inc. Device 8748 (rev ca)
0003:03:00.0 USB controller: Texas Instruments TUSB73x0 SuperSpeed USB 3.0 xHCI 
Host Controller (rev 02)
0003:09:00.0 Ethernet controller: Broadcom Corporation NetXtreme BCM5719 
Gigabit Ethernet PCIe (rev 01)
0003:09:00.1 Ethernet controller: Broadcom Corporation NetXtreme BCM5719 
Gigabit Ethernet PCIe (rev 01)
0003:09:00.2 Ethernet controller: Broadcom Corporation NetXtreme BCM5719 
Gigabit Ethernet PCIe (rev 01)
0003:09:00.3 Ethernet controller: Broadcom Corporation NetXtreme BCM5719 
Gigabit Ethernet PCIe (rev 01)
0003:0f:00.0 Network controller: Mellanox Technologies MT27500 Family 
[ConnectX-3]

Changelog
=
v1 -> v2:
* Separate powernv-php driver to support PCI hotplug for
  PowerNV platform.
* Check if the OPAL API supported by firmware before calling
  into it, which is necessary for back-compability.
* Separate patch for factoring pnv_pci_poll().

Gavin Shan (5):
  powerpc/pci: Move pcibios_find_pci_bus() around
  powerpc/pci: Don't scan empty slot
  powerpc/powernv: Introduce pnv_pci_poll()
  powerpc/powernv: Functions to retrieve PCI slot status
  PCI/hotplug: PowerPC PowerNV PCI hotplug driver

 arch/powerpc/include/asm/opal.h|   4 +
 arch/powerpc/include/asm/pnv-pci.h |   3 +
 arch/powerpc/kernel/pci-hotplug.c  |  39 ++-
 arch/powerpc/platforms/powernv/eeh-ioda.c  |  28 +-
 arch/powerpc/platforms/powernv/opal-wrappers.S |   2 +
 arch/powerpc/platforms/powernv/pci.c   |  43 +++
 arch/powerpc/platforms/powernv/pci.h   |   1 +
 arch/powerpc/platforms/pseries/pci_dlpar.c |  32 ---
 drivers/pci/hotplu

[PATCH 2/5] powerpc/pci: Don't scan empty slot

[Gavin Shan]

In hotplug case, function pcibios_add_pci_devices() is called to
rescan the specified PCI bus, which possibly doesn't have any child
devices. Access to the PCI bus's child device node will cause kernel
crash without exception. The patch adds conditions to skip scanning
the PCI bus, which doesn't have any child devices, to avoid the kernel
crash.

Signed-off-by: Gavin Shan 
---
 arch/powerpc/kernel/pci-hotplug.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/powerpc/kernel/pci-hotplug.c 
b/arch/powerpc/kernel/pci-hotplug.c
index 6e2b4e3..270a26d 100644
--- a/arch/powerpc/kernel/pci-hotplug.c
+++ b/arch/powerpc/kernel/pci-hotplug.c
@@ -120,7 +120,8 @@ void pcibios_add_pci_devices(struct pci_bus * bus)
if (mode == PCI_PROBE_DEVTREE) {
/* use ofdt-based probe */
of_rescan_bus(dn, bus);
-   } else if (mode == PCI_PROBE_NORMAL) {
+   } else if (mode == PCI_PROBE_NORMAL &&
+  dn->child && PCI_DN(dn->child)) {
/*
 * Use legacy probe. In the partial hotplug case, we
 * probably have grandchildren devices unplugged. So
-- 
1.8.3.2

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[PATCH 3/5] powerpc/powernv: Introduce pnv_pci_poll()

[Gavin Shan]

We might not get some PCI slot information (e.g. power status)
immediately by OPAL API. Instead, opal_pci_poll() need to be called
for the required information.

The patch introduces pnv_pci_poll(), which bases on original
ioda_eeh_poll(), to cover the above case

Signed-off-by: Gavin Shan 
---
 arch/powerpc/platforms/powernv/eeh-ioda.c | 28 ++--
 arch/powerpc/platforms/powernv/pci.c  | 19 +++
 arch/powerpc/platforms/powernv/pci.h  |  1 +
 3 files changed, 22 insertions(+), 26 deletions(-)

diff --git a/arch/powerpc/platforms/powernv/eeh-ioda.c 
b/arch/powerpc/platforms/powernv/eeh-ioda.c
index cf38781..21fa033 100644
--- a/arch/powerpc/platforms/powernv/eeh-ioda.c
+++ b/arch/powerpc/platforms/powernv/eeh-ioda.c
@@ -490,24 +490,6 @@ static int ioda_eeh_get_state(struct eeh_pe *pe)
return ioda_eeh_get_pe_state(pe);
 }
 
-static s64 ioda_eeh_poll(uint64_t id)
-{
-   s64 rc = OPAL_HARDWARE;
-
-   while (1) {
-   rc = opal_pci_poll(id, NULL);
-   if (rc <= 0)
-   break;
-
-   if (system_state < SYSTEM_RUNNING)
-   udelay(1000 * rc);
-   else
-   msleep(rc);
-   }
-
-   return rc;
-}
-
 int ioda_eeh_phb_reset(struct pci_controller *hose, int option)
 {
struct pnv_phb *phb = hose->private_data;
@@ -536,10 +518,7 @@ int ioda_eeh_phb_reset(struct pci_controller *hose, int 
option)
 
/* Issue reset and poll until it's completed */
rc = opal_pci_reset(phb->opal_id, scope, OPAL_ASSERT_RESET);
-   if (rc > 0)
-   rc = ioda_eeh_poll(phb->opal_id);
-
-   return (rc == OPAL_SUCCESS) ? 0 : -EIO;
+   return pnv_pci_poll(phb->opal_id, rc, NULL);
 }
 
 static int __ioda_eeh_bridge_reset(struct pci_dev *dev, int option)
@@ -630,10 +609,7 @@ static int ioda_eeh_bridge_reset(struct pci_dev *dev, int 
option)
phb = hose->private_data;
id |= (dev->bus->number << 24) | (dev->devfn << 16) | phb->opal_id;
rc = opal_pci_reset(id, scope, OPAL_ASSERT_RESET);
-   if (rc > 0)
-   ioda_eeh_poll(id);
-
-   return (rc == OPAL_SUCCESS) ? 0 : -EIO;
+   return pnv_pci_poll(id, rc, NULL);
 }
 
 static int pnv_pci_dev_reset_type(struct pci_dev *pdev, void *data)
diff --git a/arch/powerpc/platforms/powernv/pci.c 
b/arch/powerpc/platforms/powernv/pci.c
index 4b20f2c..6dc8ea9 100644
--- a/arch/powerpc/platforms/powernv/pci.c
+++ b/arch/powerpc/platforms/powernv/pci.c
@@ -45,6 +45,25 @@
 #define cfg_dbg(fmt...)do { } while(0)
 //#define cfg_dbg(fmt...)  printk(fmt)
 
+int pnv_pci_poll(uint64_t id, int64_t rval, uint8_t *pval)
+{
+   while (rval > 0) {
+   rval = opal_pci_poll(id, pval);
+   if (rval == OPAL_SUCCESS && pval)
+   rval = opal_pci_poll(id, pval);
+
+   if (rval <= 0)
+   break;
+
+   if (system_state < SYSTEM_RUNNING)
+   udelay(1000 * rval);
+   else
+   msleep(rval);
+   }
+
+   return rval ? -EIO : 0;
+}
+
 #ifdef CONFIG_PCI_MSI
 static int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
 {
diff --git a/arch/powerpc/platforms/powernv/pci.h 
b/arch/powerpc/platforms/powernv/pci.h
index 6c02ff8..396fe02 100644
--- a/arch/powerpc/platforms/powernv/pci.h
+++ b/arch/powerpc/platforms/powernv/pci.h
@@ -217,6 +217,7 @@ extern struct pci_ops pnv_pci_ops;
 extern struct pnv_eeh_ops ioda_eeh_ops;
 #endif
 
+int pnv_pci_poll(uint64_t id, int64_t rval, uint8_t *pval);
 void pnv_pci_dump_phb_diag_data(struct pci_controller *hose,
unsigned char *log_buff);
 int pnv_pci_cfg_read(struct device_node *dn,
-- 
1.8.3.2

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[PATCH 1/5] powerpc/pci: Move pcibios_find_pci_bus() around

[Gavin Shan]

The patch moves pcibios_find_pci_bus() to PPC kerenl directory so
that it can be reused by hotplug code for pSeries and PowerNV
platform at the same time.

Signed-off-by: Gavin Shan 
Acked-by: Benjamin Herrenschmidt 
---
 arch/powerpc/kernel/pci-hotplug.c  | 36 ++
 arch/powerpc/platforms/pseries/pci_dlpar.c | 32 --
 2 files changed, 36 insertions(+), 32 deletions(-)

diff --git a/arch/powerpc/kernel/pci-hotplug.c 
b/arch/powerpc/kernel/pci-hotplug.c
index 5b78917..6e2b4e3 100644
--- a/arch/powerpc/kernel/pci-hotplug.c
+++ b/arch/powerpc/kernel/pci-hotplug.c
@@ -21,6 +21,42 @@
 #include 
 #include 
 
+static struct pci_bus *find_pci_bus(struct pci_bus *bus,
+   struct device_node *dn)
+{
+   struct pci_bus *tmp, *child = NULL;
+   struct device_node *busdn;
+
+   busdn = pci_bus_to_OF_node(bus);
+   if (busdn == dn)
+   return bus;
+
+   list_for_each_entry(tmp, &bus->children, node) {
+   child = find_pci_bus(tmp, dn);
+   if (child)
+   break;
+   }
+
+   return child;
+}
+
+/**
+ * pcibios_find_pci_bus - find PCI bus according to the given device node
+ * @dn: Device node
+ *
+ * Find the corresponding PCI bus according to the given device node.
+ */
+struct pci_bus *pcibios_find_pci_bus(struct device_node *dn)
+{
+   struct pci_dn *pdn = PCI_DN(dn);
+
+   if (!pdn  || !pdn->phb || !pdn->phb->bus)
+   return NULL;
+
+   return find_pci_bus(pdn->phb->bus, dn);
+}
+EXPORT_SYMBOL_GPL(pcibios_find_pci_bus);
+
 /**
  * pcibios_release_device - release PCI device
  * @dev: PCI device
diff --git a/arch/powerpc/platforms/pseries/pci_dlpar.c 
b/arch/powerpc/platforms/pseries/pci_dlpar.c
index 89e2381..98c50bc 100644
--- a/arch/powerpc/platforms/pseries/pci_dlpar.c
+++ b/arch/powerpc/platforms/pseries/pci_dlpar.c
@@ -32,38 +32,6 @@
 #include 
 #include 
 
-static struct pci_bus *
-find_bus_among_children(struct pci_bus *bus,
-struct device_node *dn)
-{
-   struct pci_bus *child = NULL;
-   struct pci_bus *tmp;
-   struct device_node *busdn;
-
-   busdn = pci_bus_to_OF_node(bus);
-   if (busdn == dn)
-   return bus;
-
-   list_for_each_entry(tmp, &bus->children, node) {
-   child = find_bus_among_children(tmp, dn);
-   if (child)
-   break;
-   };
-   return child;
-}
-
-struct pci_bus *
-pcibios_find_pci_bus(struct device_node *dn)
-{
-   struct pci_dn *pdn = dn->data;
-
-   if (!pdn  || !pdn->phb || !pdn->phb->bus)
-   return NULL;
-
-   return find_bus_among_children(pdn->phb->bus, dn);
-}
-EXPORT_SYMBOL_GPL(pcibios_find_pci_bus);
-
 struct pci_controller *init_phb_dynamic(struct device_node *dn)
 {
struct pci_controller *phb;
-- 
1.8.3.2

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[PATCH 5/5] PCI/hotplug: PowerPC PowerNV PCI hotplug driver

[Gavin Shan]

The patch intends to add standalone driver to support PCI hotplug
for PowerPC PowerNV platform, which runs on top of skiboot firmware.
The firmware identified hotpluggable slots and marked their device
tree node with proper "ibm,slot-pluggable" and "ibm,reset-by-firmware".
The driver simply scans device-tree to create/register PCI hotplug slot
accordingly.

If the skiboot firmware doesn't support slot status retrieval, the PCI
slot device node shouldn't have property "ibm,reset-by-firmware". In
that case, none of valid PCI slots will be detected from device tree.
The skiboot firmware doesn't export the capability to access attention
LEDs yet and it's something for TBD.

Signed-off-by: Gavin Shan 
---
 drivers/pci/hotplug/Kconfig|  12 ++
 drivers/pci/hotplug/Makefile   |   4 +
 drivers/pci/hotplug/powernv_php.c  | 126 +++
 drivers/pci/hotplug/powernv_php.h  |  70 ++
 drivers/pci/hotplug/powernv_php_slot.c | 382 +
 5 files changed, 594 insertions(+)
 create mode 100644 drivers/pci/hotplug/powernv_php.c
 create mode 100644 drivers/pci/hotplug/powernv_php.h
 create mode 100644 drivers/pci/hotplug/powernv_php_slot.c

diff --git a/drivers/pci/hotplug/Kconfig b/drivers/pci/hotplug/Kconfig
index df8caec..ef55dae 100644
--- a/drivers/pci/hotplug/Kconfig
+++ b/drivers/pci/hotplug/Kconfig
@@ -113,6 +113,18 @@ config HOTPLUG_PCI_SHPC
 
  When in doubt, say N.
 
+config HOTPLUG_PCI_POWERNV
+   tristate "PowerPC PowerNV PCI Hotplug driver"
+   depends on PPC_POWERNV && EEH
+   help
+ Say Y here if you run PowerPC PowerNV platform that supports
+  PCI Hotplug
+
+ To compile this driver as a module, choose M here: the
+ module will be called powernv-php.
+
+ When in doubt, say N.
+
 config HOTPLUG_PCI_RPA
tristate "RPA PCI Hotplug driver"
depends on PPC_PSERIES && EEH
diff --git a/drivers/pci/hotplug/Makefile b/drivers/pci/hotplug/Makefile
index 4a9aa08..a69665e 100644
--- a/drivers/pci/hotplug/Makefile
+++ b/drivers/pci/hotplug/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_HOTPLUG_PCI_PCIE)+= pciehp.o
 obj-$(CONFIG_HOTPLUG_PCI_CPCI_ZT5550)  += cpcihp_zt5550.o
 obj-$(CONFIG_HOTPLUG_PCI_CPCI_GENERIC) += cpcihp_generic.o
 obj-$(CONFIG_HOTPLUG_PCI_SHPC) += shpchp.o
+obj-$(CONFIG_HOTPLUG_PCI_POWERNV)  += powernv-php.o
 obj-$(CONFIG_HOTPLUG_PCI_RPA)  += rpaphp.o
 obj-$(CONFIG_HOTPLUG_PCI_RPA_DLPAR)+= rpadlpar_io.o
 obj-$(CONFIG_HOTPLUG_PCI_SGI)  += sgi_hotplug.o
@@ -50,6 +51,9 @@ ibmphp-objs   :=  ibmphp_core.o   \
 acpiphp-objs   :=  acpiphp_core.o  \
acpiphp_glue.o
 
+powernv-php-objs   :=  powernv_php.o   \
+   powernv_php_slot.o
+
 rpaphp-objs:=  rpaphp_core.o   \
rpaphp_pci.o\
rpaphp_slot.o
diff --git a/drivers/pci/hotplug/powernv_php.c 
b/drivers/pci/hotplug/powernv_php.c
new file mode 100644
index 000..e36eaf1
--- /dev/null
+++ b/drivers/pci/hotplug/powernv_php.c
@@ -0,0 +1,126 @@
+/*
+ * PCI Hotplug Driver for PowerPC PowerNV platform.
+ *
+ * Copyright Gavin Shan, IBM Corporation 2015.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "powernv_php.h"
+
+#define DRIVER_VERSION "0.1"
+#define DRIVER_AUTHOR  "Gavin Shan, IBM Corporation"
+#define DRIVER_DESC"PowerPC PowerNV PCI Hotplug Driver"
+
+static int powernv_php_register_one(struct device_node *dn)
+{
+   struct powernv_php_slot *slot;
+   const __be32 *prop32;
+   int ret;
+
+   /* Check if it's hotpluggable slot */
+   prop32 = of_get_property(dn, "ibm,slot-pluggable", NULL);
+   if (!prop32 || !of_read_number(prop32, 1))
+   return 0;
+
+   prop32 = of_get_property(dn, "ibm,reset-by-firmware", NULL);
+   if (!prop32 || !of_read_number(prop32, 1))
+   return 0;
+
+   /* Allocate slot */
+   slot = powernv_php_slot_alloc(dn);
+   if (!slot)
+   return -ENODEV;
+
+   /* Register it */
+   ret = powernv_php_slot_register(slot);
+   if (ret) {
+   powernv_php_slot_put(slot);
+   return ret;
+   }
+
+   return powernv_php_slot_enable(slot->php_slot, false);
+}
+
+int powernv_php_register(struct device_node *dn)
+{
+   struct device_node *child;
+   int ret = 0;
+
+   for_each_child_of_node(dn, child) {
+   ret = powernv_php_register_one(child);
+   if (ret)
+   break;
+
+   powernv_php_regi

[PATCH 1/3] powerpc/powernv: Use PCI slot reset infrastructure

[Gavin Shan]

For PowerPC PowerNV platform, running on top of skiboot, all PE
level reset should be routed to firmware, which exported PCI slot
reset capability with device-node property "ibm,reset-by-firmware".
Otherwise, the kernel still has to simulate hot reset on PCI bridge's
secondary bus. So the code doesn't depend on if the firmware has
corresponding feature supported.

Signed-off-by: Gavin Shan 
---
 arch/powerpc/include/asm/eeh.h|   1 +
 arch/powerpc/include/asm/opal.h   |   9 +-
 arch/powerpc/platforms/powernv/eeh-ioda.c | 163 --
 3 files changed, 89 insertions(+), 84 deletions(-)

diff --git a/arch/powerpc/include/asm/eeh.h b/arch/powerpc/include/asm/eeh.h
index 9c11d1e..5847721 100644
--- a/arch/powerpc/include/asm/eeh.h
+++ b/arch/powerpc/include/asm/eeh.h
@@ -192,6 +192,7 @@ enum {
 #define EEH_RESET_DEACTIVATE   0   /* Deactivate the PE reset  */
 #define EEH_RESET_HOT  1   /* Hot reset*/
 #define EEH_RESET_FUNDAMENTAL  3   /* Fundamental reset*/
+#define EEH_RESET_COMPLETE 4   /* PHB complete reset   */
 #define EEH_LOG_TEMP   1   /* EEH temporary error log  */
 #define EEH_LOG_PERM   2   /* EEH permanent error log  */
 
diff --git a/arch/powerpc/include/asm/opal.h b/arch/powerpc/include/asm/opal.h
index 9124b0e..edd1993 100644
--- a/arch/powerpc/include/asm/opal.h
+++ b/arch/powerpc/include/asm/opal.h
@@ -405,11 +405,6 @@ enum OpalPciResetState {
OPAL_ASSERT_RESET = 1
 };
 
-enum OpalPciMaskAction {
-   OPAL_UNMASK_ERROR_TYPE = 0,
-   OPAL_MASK_ERROR_TYPE = 1
-};
-
 enum OpalSlotLedType {
OPAL_SLOT_LED_ID_TYPE = 0,
OPAL_SLOT_LED_FAULT_TYPE = 1
@@ -906,7 +901,7 @@ int64_t opal_pci_map_pe_dma_window(uint64_t phb_id, 
uint16_t pe_number, uint16_t
 int64_t opal_pci_map_pe_dma_window_real(uint64_t phb_id, uint16_t pe_number,
uint16_t dma_window_number, uint64_t 
pci_start_addr,
uint64_t pci_mem_size);
-int64_t opal_pci_reset(uint64_t phb_id, uint8_t reset_scope, uint8_t 
assert_state);
+int64_t opal_pci_reset(uint64_t id, uint8_t reset_scope, uint8_t assert_state);
 
 int64_t opal_pci_get_hub_diag_data(uint64_t hub_id, void *diag_buffer,
   uint64_t diag_buffer_len);
@@ -922,7 +917,7 @@ int64_t opal_get_epow_status(__be64 *status);
 int64_t opal_set_system_attention_led(uint8_t led_action);
 int64_t opal_pci_next_error(uint64_t phb_id, __be64 *first_frozen_pe,
__be16 *pci_error_type, __be16 *severity);
-int64_t opal_pci_poll(uint64_t phb_id);
+int64_t opal_pci_poll(uint64_t id, uint8_t *val);
 int64_t opal_return_cpu(void);
 int64_t opal_check_token(uint64_t token);
 int64_t opal_reinit_cpus(uint64_t flags);
diff --git a/arch/powerpc/platforms/powernv/eeh-ioda.c 
b/arch/powerpc/platforms/powernv/eeh-ioda.c
index 43aba2d..825da60 100644
--- a/arch/powerpc/platforms/powernv/eeh-ioda.c
+++ b/arch/powerpc/platforms/powernv/eeh-ioda.c
@@ -490,12 +490,12 @@ static int ioda_eeh_get_state(struct eeh_pe *pe)
return ioda_eeh_get_pe_state(pe);
 }
 
-static s64 ioda_eeh_phb_poll(struct pnv_phb *phb)
+static s64 ioda_eeh_poll(uint64_t id)
 {
s64 rc = OPAL_HARDWARE;
 
while (1) {
-   rc = opal_pci_poll(phb->opal_id);
+   rc = opal_pci_poll(id, NULL);
if (rc <= 0)
break;
 
@@ -511,84 +511,38 @@ static s64 ioda_eeh_phb_poll(struct pnv_phb *phb)
 int ioda_eeh_phb_reset(struct pci_controller *hose, int option)
 {
struct pnv_phb *phb = hose->private_data;
+   uint8_t scope;
s64 rc = OPAL_HARDWARE;
 
pr_debug("%s: Reset PHB#%x, option=%d\n",
 __func__, hose->global_number, option);
-
-   /* Issue PHB complete reset request */
-   if (option == EEH_RESET_FUNDAMENTAL ||
-   option == EEH_RESET_HOT)
-   rc = opal_pci_reset(phb->opal_id,
-   OPAL_RESET_PHB_COMPLETE,
-   OPAL_ASSERT_RESET);
-   else if (option == EEH_RESET_DEACTIVATE)
-   rc = opal_pci_reset(phb->opal_id,
-   OPAL_RESET_PHB_COMPLETE,
-   OPAL_DEASSERT_RESET);
-   if (rc < 0)
-   goto out;
-
-   /*
-* Poll state of the PHB until the request is done
-* successfully. The PHB reset is usually PHB complete
-* reset followed by hot reset on root bus. So we also
-* need the PCI bus settlement delay.
-*/
-   rc = ioda_eeh_phb_poll(phb);
-   if (option == EEH_RESET_DEACTIVATE) {
-   if (system_state < SYSTEM_RUNNING)
-   udelay(1000 * EEH_PE_RST_SETTLE_TIME);
-   else
-   msleep(EEH_PE_RST_SETTLE_TIME);
+   switch (option) {
+   case EE

[PATCH 2/3] powerpc/powernv: Refactor ioda_eeh_reset()

[Gavin Shan]

The patch refactors ioda_eeh_reset() to eliminate unnecessary
nested if statements to improve code readability. Except printing
the PHB index in the error message when failing to clear PHB error
injection registers, no logic changed.

Signed-off-by: Gavin Shan 
---
 arch/powerpc/platforms/powernv/eeh-ioda.c | 65 ++-
 1 file changed, 29 insertions(+), 36 deletions(-)

diff --git a/arch/powerpc/platforms/powernv/eeh-ioda.c 
b/arch/powerpc/platforms/powernv/eeh-ioda.c
index 825da60..78d94df 100644
--- a/arch/powerpc/platforms/powernv/eeh-ioda.c
+++ b/arch/powerpc/platforms/powernv/eeh-ioda.c
@@ -665,8 +665,8 @@ void pnv_pci_reset_secondary_bus(struct pci_dev *dev)
 static int ioda_eeh_reset(struct eeh_pe *pe, int option)
 {
struct pci_controller *hose = pe->phb;
+   struct pnv_phb *phb = hose->private_data;
struct pci_bus *bus;
-   int ret;
 
/*
 * For PHB reset, we always have complete reset. For those PEs whose
@@ -687,50 +687,43 @@ static int ioda_eeh_reset(struct eeh_pe *pe, int option)
case EEH_RESET_HOT:
case EEH_RESET_FUNDAMENTAL:
case EEH_RESET_COMPLETE:
-   ret = ioda_eeh_phb_reset(hose, EEH_RESET_COMPLETE);
-   break;
+   return ioda_eeh_phb_reset(hose, EEH_RESET_COMPLETE);
case EEH_RESET_DEACTIVATE:
-   ret = 0;
-   break;
+   return 0;
default:
-   ret = -EINVAL;
+   return -EINVAL;
}
+   }
 
-   return ret;
-   } else {
-   struct pnv_phb *phb;
+   /*
+* The frozen PE might be caused by PAPR error injection
+* registers, which are expected to be cleared after hitting
+* frozen PE as stated in the hardware spec. Unfortunately,
+* that's not true on P7IOC. So we have to clear it manually
+* to avoid recursive EEH errors during recovery.
+*/
+   if (phb->model == PNV_PHB_MODEL_P7IOC &&
+   (option == EEH_RESET_HOT ||
+option == EEH_RESET_FUNDAMENTAL)) {
s64 rc;
 
-   /*
-* The frozen PE might be caused by PAPR error injection
-* registers, which are expected to be cleared after hitting
-* frozen PE as stated in the hardware spec. Unfortunately,
-* that's not true on P7IOC. So we have to clear it manually
-* to avoid recursive EEH errors during recovery.
-*/
-   phb = hose->private_data;
-   if (phb->model == PNV_PHB_MODEL_P7IOC &&
-   (option == EEH_RESET_HOT ||
-   option == EEH_RESET_FUNDAMENTAL)) {
-   rc = opal_pci_reset(phb->opal_id,
-   OPAL_RESET_PHB_ERROR,
-   OPAL_ASSERT_RESET);
-   if (rc != OPAL_SUCCESS) {
-   pr_warn("%s: Failure %lld clearing "
-   "error injection registers\n",
-   __func__, rc);
-   return -EIO;
-   }
+   rc = opal_pci_reset(phb->opal_id,
+   OPAL_RESET_PHB_ERROR,
+   OPAL_ASSERT_RESET);
+   if (rc != OPAL_SUCCESS) {
+   pr_warn("%s: Failure %lld clearing PHB#%x "
+   "error injection registers\n",
+   __func__, rc, hose->global_number);
+   return -EIO;
}
-
-   bus = eeh_pe_bus_get(pe);
-   if (pci_is_root_bus(bus))
-   ret = ioda_eeh_phb_reset(hose, option);
-   else
-   ret = ioda_eeh_bridge_reset(bus->self, option);
}
 
-   return ret;
+   /* Route PE reset request */
+   bus = eeh_pe_bus_get(pe);
+   if (pci_is_root_bus(bus))
+   return ioda_eeh_phb_reset(hose, option);
+
+   return ioda_eeh_bridge_reset(bus->self, option);
 }
 
 /**
-- 
1.8.3.2

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[PATCH v2 0/3] powerpc/pci: PCI slot unified reset

[Gavin Shan]

The patchset corresponds to skiboot changes, which manages PCI slots
in a unified way: OPAL APIs used to do slot reset, power management,
presence status retrival. The patchset shouldn't be merged before
the OPAL firmware counterpart is merged.

The kernel changes have been split into 2 parts: (A) Use the unified
PCI slot reset OPAL API - this patchset; (B) powernv-php driver to
support PCI hotplug for PowerNV platform, which will be sent separately.

This patchset affects EEH, PCI reset logics, which is used mainly by
VFIO. A couple of cases have been tested out on P7/P8 boxes and looks
good: EEH on PowerNV, EEH support for guest, PCI passthrou.

Changelog
=
v1 -> v2
* Keep opal_pci_reinit(). In case the slot is resetted by kernel,
  instead of skiboot, this API should be called to restore states
  for those affected devices.
* Reworked slot ID scheme so that old/new kernel can work with
  skiboot with or without unified PCI slot management support.
* Code cleanup here and there.

Gavin Shan (3):
  powerpc/powernv: Use PCI slot reset infrastructure
  powerpc/powernv: Refactor ioda_eeh_reset()
  powerpc/powernv: Issue fundamental reset if required

 arch/powerpc/include/asm/eeh.h|   1 +
 arch/powerpc/include/asm/opal.h   |   9 +-
 arch/powerpc/platforms/powernv/eeh-ioda.c | 240 --
 3 files changed, 132 insertions(+), 118 deletions(-)

Thanks,
Gavin

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[PATCH 3/3] powerpc/powernv: Issue fundamental reset if required

[Gavin Shan]

Function pnv_pci_reset_secondary_bus() is used to reset specified
PCI bus, which is leaded by root complex or PCI bridge. That means
the function shouldn't be called on PCI root bus and the patch
removes the logic for the case.

Also, some adapters may require fundamental reset to reload their
firmwares. Otherwise, they will fail to load their firmwares and
those adapters can't work properly after reset, as being reported
in VFIO pass-through scenario. The patch checks the reset type
required by the child adapters of the PCI bus and issue fundamental
reset if necessary.

Signed-off-by: Gavin Shan 
---
 arch/powerpc/platforms/powernv/eeh-ioda.c | 34 +++
 1 file changed, 25 insertions(+), 9 deletions(-)

diff --git a/arch/powerpc/platforms/powernv/eeh-ioda.c 
b/arch/powerpc/platforms/powernv/eeh-ioda.c
index 78d94df..cf38781 100644
--- a/arch/powerpc/platforms/powernv/eeh-ioda.c
+++ b/arch/powerpc/platforms/powernv/eeh-ioda.c
@@ -636,18 +636,34 @@ static int ioda_eeh_bridge_reset(struct pci_dev *dev, int 
option)
return (rc == OPAL_SUCCESS) ? 0 : -EIO;
 }
 
-void pnv_pci_reset_secondary_bus(struct pci_dev *dev)
+static int pnv_pci_dev_reset_type(struct pci_dev *pdev, void *data)
 {
-   struct pci_controller *hose;
+   int *freset = data;
 
-   if (pci_is_root_bus(dev->bus)) {
-   hose = pci_bus_to_host(dev->bus);
-   ioda_eeh_phb_reset(hose, EEH_RESET_HOT);
-   ioda_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE);
-   } else {
-   ioda_eeh_bridge_reset(dev, EEH_RESET_HOT);
-   ioda_eeh_bridge_reset(dev, EEH_RESET_DEACTIVATE);
+   /*
+* Stop the iteration immediately if any one PCI
+* device requires fundamental reset
+*/
+   *freset |= pdev->needs_freset;
+   return *freset;
+}
+
+void pnv_pci_reset_secondary_bus(struct pci_dev *pdev)
+{
+   int option = EEH_RESET_HOT;
+   int freset = 0;
+
+   /* Check if we need issue fundamental reset */
+   if (pdev->subordinate) {
+   pci_walk_bus(pdev->subordinate,
+pnv_pci_dev_reset_type, &freset);
+   if (freset)
+   option = EEH_RESET_FUNDAMENTAL;
}
+
+   /* Issue required reset type */
+   ioda_eeh_bridge_reset(pdev, option);
+   ioda_eeh_bridge_reset(pdev, EEH_RESET_DEACTIVATE);
 }
 
 /**
-- 
1.8.3.2

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Re: powerpc/pci: remove pci device on a bus in reverse order

[Michael Ellerman]

On Thu, 2014-04-12 at 03:24:37 UTC, Wei Yang wrote:
> As in commit ac205b7b (PCI: make sriov work with hotplug remove) indicates,
> when removing pci devices on a bus which has VFs, we need to remove them in
> the reverse order.
> 
> This patch applies this pattern on the hotplug remove path on powerpc arch.

So is this is a bug fix?

Where/how have you tested this?

cheers
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[PATCH V3] powerpc/mm: don't do tlbie for updatepp request with NO HPTE fault

[Aneesh Kumar K.V]

upatepp can get called for a nohpte fault when we find from the linux
page table that the translation was hashed before. In that case
we are sure that there is no existing translation, hence we could
avoid doing tlbie.

We could possibly race with a parallel fault filling the TLB. But
that should be ok because updatepp is only ever relaxing permissions.
We also look at linux pte permission bits when filling hash pte
permission bits. We also hold the linux pte busy bits while
inserting/updating a hashpte entry, hence a paralle update of
linux pte is not possible. On the other hand mprotect involves
ptep_modify_prot_start which cause a hpte invalidate and not updatepp.

Performance number:
We use randbox_access_bench written by Anton.

Kernel with THP disabled and smaller hash page table size.

86.60%  random_access_b  [kernel.kallsyms][k] 
.native_hpte_updatepp
 2.10%  random_access_b  random_access_bench  [.] doit
 1.99%  random_access_b  [kernel.kallsyms][k] 
.do_raw_spin_lock
 1.85%  random_access_b  [kernel.kallsyms][k] 
.native_hpte_insert
 1.26%  random_access_b  [kernel.kallsyms][k] 
.native_flush_hash_range
 1.18%  random_access_b  [kernel.kallsyms][k] .__delay
 0.69%  random_access_b  [kernel.kallsyms][k] 
.native_hpte_remove
 0.37%  random_access_b  [kernel.kallsyms][k] 
.clear_user_page
 0.34%  random_access_b  [kernel.kallsyms][k] 
.__hash_page_64K
 0.32%  random_access_b  [kernel.kallsyms][k] 
fast_exception_return
 0.30%  random_access_b  [kernel.kallsyms][k] .hash_page_mm

With Fix:

27.54%  random_access_b  random_access_bench  [.] doit
22.90%  random_access_b  [kernel.kallsyms][k] 
.native_hpte_insert
 5.76%  random_access_b  [kernel.kallsyms][k] 
.native_hpte_remove
 5.20%  random_access_b  [kernel.kallsyms][k] 
fast_exception_return
 5.12%  random_access_b  [kernel.kallsyms][k] 
.__hash_page_64K
 4.80%  random_access_b  [kernel.kallsyms][k] .hash_page_mm
 3.31%  random_access_b  [kernel.kallsyms][k] 
data_access_common
 1.84%  random_access_b  [kernel.kallsyms][k] 
.trace_hardirqs_on_caller

Signed-off-by: Aneesh Kumar K.V 
---
Changes from V2:
* update commit message.

 arch/powerpc/include/asm/machdep.h|  2 +-
 arch/powerpc/include/asm/mmu-hash64.h | 22 ++--
 arch/powerpc/include/asm/tlbflush.h   |  4 +--
 arch/powerpc/kernel/exceptions-64s.S  |  2 ++
 arch/powerpc/mm/hash_low_64.S | 15 ++-
 arch/powerpc/mm/hash_native_64.c  | 15 ---
 arch/powerpc/mm/hash_utils_64.c   | 44 ---
 arch/powerpc/mm/hugepage-hash64.c |  8 +++---
 arch/powerpc/mm/hugetlbpage-hash64.c  |  6 ++---
 arch/powerpc/mm/pgtable_64.c  |  7 ++---
 arch/powerpc/platforms/cell/beat_htab.c   |  4 +--
 arch/powerpc/platforms/cell/spu_base.c|  5 ++--
 arch/powerpc/platforms/cell/spufs/fault.c |  2 +-
 arch/powerpc/platforms/ps3/htab.c |  2 +-
 arch/powerpc/platforms/pseries/lpar.c |  2 +-
 drivers/misc/cxl/fault.c  |  8 --
 16 files changed, 91 insertions(+), 57 deletions(-)

diff --git a/arch/powerpc/include/asm/machdep.h 
b/arch/powerpc/include/asm/machdep.h
index e5c0919acca4..c8175a3fe560 100644
--- a/arch/powerpc/include/asm/machdep.h
+++ b/arch/powerpc/include/asm/machdep.h
@@ -42,7 +42,7 @@ struct machdep_calls {
 unsigned long newpp, 
 unsigned long vpn,
 int bpsize, int apsize,
-int ssize, int local);
+int ssize, unsigned long flags);
void(*hpte_updateboltedpp)(unsigned long newpp, 
   unsigned long ea,
   int psize, int ssize);
diff --git a/arch/powerpc/include/asm/mmu-hash64.h 
b/arch/powerpc/include/asm/mmu-hash64.h
index aeebc94b2bce..4f13c3ed7acf 100644
--- a/arch/powerpc/include/asm/mmu-hash64.h
+++ b/arch/powerpc/include/asm/mmu-hash64.h
@@ -316,27 +316,33 @@ static inline unsigned long hpt_hash(unsigned long vpn,
return hash & 0x7fUL;
 }
 
+#define HPTE_LOCAL_UPDATE  0x1
+#define HPTE_NOHPTE_UPDATE 0x2
+
 extern int __hash_page_4K(unsigned long ea, unsigned long access,
  unsigned long vsid, pte_t *ptep, unsigned long trap,
- unsigned int local, int ssize, int subpage_prot);
+ unsigned long flags, int ssize, int subpage_prot);
 extern int __hash_page_64K(unsigned long ea, unsigned long 

Re: [2/2] pstore: add pstore support on powernv

[Michael Ellerman]

On Wed, 2014-03-12 at 11:03:15 UTC, Hari Bathini wrote:
> This patch extends pstore, a generic interface to platform dependent
> persistent storage, support for powernv  platform to capture certain
> useful information, during dying moments. Such support is already in
> place for  pseries platform.  This patch while adding pstore support
> for  powernv platform,  moves common code for pseries and powernv to
> arch/powerpc/kernel/nvram_64.c file.

Please move the common code first in a separate patch. Unless there's some
reason you absolutely can't do that.

cheers
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Re: [PATCH v5 6/6] powerpc/perf/hv-24x7: Document sysfs event description entries

[Cody P Schafer]

> diff --git a/Documentation/ABI/testing/sysfs-bus-event_source-devices-hv_24x7 
> b/Documentation/ABI/testing/sysfs-bus-event_source-devices-hv_24x7
> index 32f3f5f..cf70084 100644
> --- a/Documentation/ABI/testing/sysfs-bus-event_source-devices-hv_24x7
> +++ b/Documentation/ABI/testing/sysfs-bus-event_source-devices-hv_24x7
> @@ -21,3 +21,25 @@ Contact: Linux on PowerPC Developer List 
> 
> +Contact:   Cody P Schafer 

Probably want someone else to be the contact here.
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Re: [PATCH v1 0/5] powerpc/pci: PCI slot unified reset

[Gavin Shan]

On Tue, Nov 25, 2014 at 09:38:42AM +1100, Gavin Shan wrote:

Please ignore this revision. v2 is on the way...

Thanks,
Gavin

>The patchset corresponds to skiboot changes, which manages PCI slots
>in a unified way: OPAL APIs used to do slot reset, power management,
>presence status retrival. The patchset shouldn't be merged before
>the OPAL firmware counterpart is merged.
>
>The kernel changes have been split into 2 parts: (A) Use the unified
>PCI slot reset OPAL API - this patchset; (B) Changes to rpaphp.ko to
>support PCI slot hotplug via sysfs entries for PowerPC PowerNV platform.
>
>This patchset affects EEH, PCI reset logics, which is used mainly by
>VFIO. A couple of cases have been tested out on P7/P8 boxes and looks
>good: EEH on PowerNV, EEH support for guest, PCI passthrou.
>
>Gavin Shan (5):
>  powerpc/powernv: Use PCI slot reset infrastructure
>  powerpc/powernv: Refactor ioda_eeh_reset()
>  powerpc/powernv: Avoid do complete reset for twice
>  powerpc/powernv: Issue fundamental reset if required
>  powerpc/powernv: Drop opal_pci_reinit()
>
> arch/powerpc/include/asm/eeh.h |   2 +-
> arch/powerpc/include/asm/opal.h|  31 +---
> arch/powerpc/kernel/eeh_pe.c   |   3 -
> arch/powerpc/platforms/powernv/eeh-ioda.c  | 230 ++---
> arch/powerpc/platforms/powernv/eeh-powernv.c   |  24 +--
> arch/powerpc/platforms/powernv/opal-wrappers.S |   1 -
> arch/powerpc/platforms/powernv/pci-ioda.c  |   5 +-
> arch/powerpc/platforms/pseries/eeh_pseries.c   |   3 +-
> 8 files changed, 139 insertions(+), 160 deletions(-)
>
>Thanks,
>Gavin

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Re: [PATCH 5/8] PCI/hotplug/rpa: Create PCI slot properly

[Gavin Shan]

On Wed, Nov 26, 2014 at 10:04:57AM +1100, Benjamin Herrenschmidt wrote:
>On Tue, 2014-11-25 at 09:49 +1100, Gavin Shan wrote:
>> When loading rpaphp.ko on a P7 box, I didn't see any PCI slots
>> created under /sys/bus/pci/slots as expected. It seems that the
>> RPA PCI slot stuff has been broken for long time. The driver
>> doesn't use the properties of PCI device-tree nodes properly to
>> populate PCI slots: device-tree node property "ibm,my-drc-index"
>> is the identifier of hotpluggable PCI slot. The (direct or indirect)
>> parent device-tree node should have properties associated with the
>> "ibm,my-drc-index", which are "ibm,drc-indexes","ibm,drc-names",
>> "ibm,drc-types", "ibm,drc-power-domains".
>> 
>> The patch parses above device-tree node properties to create PCI
>> slots properly. One PCI slot is created for PCI device-tree node,
>> which has meaningful "ibm,my-drc-index".
>
>Nathan, can you review this ?
>

Ben had the suggestion to have separate drivers for pSeries and PowerNV.
So this patch isn't related to PowerNV PCI hotplug any more. I'll send
reworked patch (including the cleanup one) separately and put Nathan to
the cc list.

Thanks,
Gavin

>Cheers,
>Ben.
>
>> Signed-off-by: Gavin Shan 
>> ---
>>  drivers/pci/hotplug/rpaphp.h  |   2 +-
>>  drivers/pci/hotplug/rpaphp_core.c | 205 
>> ++
>>  2 files changed, 74 insertions(+), 133 deletions(-)
>> 
>> diff --git a/drivers/pci/hotplug/rpaphp.h b/drivers/pci/hotplug/rpaphp.h
>> index b2593e8..39ddbdf 100644
>> --- a/drivers/pci/hotplug/rpaphp.h
>> +++ b/drivers/pci/hotplug/rpaphp.h
>> @@ -92,7 +92,7 @@ int rpaphp_get_sensor_state(struct slot *slot, int *state);
>>  /* rpaphp_core.c */
>>  int rpaphp_add_slot(struct device_node *dn);
>>  int rpaphp_get_drc_props(struct device_node *dn, int *drc_index,
>> -char **drc_name, char **drc_type, int *drc_power_domain);
>> +char **drc_name, char **drc_type, int *drc_power);
>>  
>>  /* rpaphp_slot.c */
>>  void dealloc_slot_struct(struct slot *slot);
>> diff --git a/drivers/pci/hotplug/rpaphp_core.c 
>> b/drivers/pci/hotplug/rpaphp_core.c
>> index ff800df..a639c5c 100644
>> --- a/drivers/pci/hotplug/rpaphp_core.c
>> +++ b/drivers/pci/hotplug/rpaphp_core.c
>> @@ -165,119 +165,76 @@ static enum pci_bus_speed get_max_bus_speed(struct 
>> slot *slot)
>>  return speed;
>>  }
>>  
>> -static int get_children_props(struct device_node *dn, const int 
>> **drc_indexes,
>> -const int **drc_names, const int **drc_types,
>> -const int **drc_power_domains)
>> +static int parse_drc_props(struct device_node *dn, u32 drc_index,
>> +   char **drc_name, char **drc_type, u32 *drc_power)
>>  {
>> -const int *indexes, *names, *types, *domains;
>> +const u32 *indexes, *names, *types, *domains;
>> +char *name, *type;
>> +struct device_node *parent = dn;
>> +u32 i;
>> +
>> +while ((parent = of_get_parent(parent))) {
>> +indexes = of_get_property(parent, "ibm,drc-indexes", NULL);
>> +names   = of_get_property(parent, "ibm,drc-names", NULL);
>> +types   = of_get_property(parent, "ibm,drc-types", NULL);
>> +domains = of_get_property(parent, "ibm,drc-power-domains", 
>> NULL);
>> +
>> +if (!indexes || !names || !types || !domains) {
>> +of_node_put(parent);
>> +continue;
>> +}
>>  
>> -indexes = of_get_property(dn, "ibm,drc-indexes", NULL);
>> -names = of_get_property(dn, "ibm,drc-names", NULL);
>> -types = of_get_property(dn, "ibm,drc-types", NULL);
>> -domains = of_get_property(dn, "ibm,drc-power-domains", NULL);
>> +name = (char *)&names[1];
>> +type = (char *)&types[1];
>> +for (i = 0; i < be32_to_cpu(indexes[0]); i++) {
>> +if (be32_to_cpu(indexes[i + 1]) != drc_index) {
>> +name += (strlen(name) + 1);
>> +type += (strlen(type) + 1);
>> +continue;
>> +}
>>  
>> -/* Slot does not have dynamically-removable children */
>> -if (!indexes || !names || !types || !domains)
>> -return -EINVAL;
>> +/* Matched index */
>> +if (drc_name)
>> +*drc_name = name;
>> +if (drc_type)
>> +*drc_type = type;
>> +if (drc_power)
>> +*drc_power = be32_to_cpu(domains[i + 1]);
>> +
>> +of_node_put(parent);
>> +return 0;
>> +}
>>  
>> -if (drc_indexes)
>> -*drc_indexes = indexes;
>> -/* &drc_names[1] contains NULL terminated slot names */
>> -if (drc_names)
>> -*drc_names = names;
>> -/* &drc_types[1] contains NULL terminated slot types */
>> -if (drc_types)
>

Re: [PATCH v4 1/6] dt/bindings: bman: Add phandle to the portals

[Scott Wood]

On Wed, 2014-12-03 at 04:02 -0600, Emil Medve wrote:
> This supports SoC(s) with multiple BMan instances
> 
> Signed-off-by: Emil Medve 
> ---
>  Documentation/devicetree/bindings/soc/fsl/bman.txt | 10 ++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/soc/fsl/bman.txt 
> b/Documentation/devicetree/bindings/soc/fsl/bman.txt
> index 9f80bf8..4fc4a6e 100644
> --- a/Documentation/devicetree/bindings/soc/fsl/bman.txt
> +++ b/Documentation/devicetree/bindings/soc/fsl/bman.txt
> @@ -36,6 +36,11 @@ are located at offsets 0xbf8 and 0xbfc
>   Value type: 
>   Definition: Standard property. The error interrupt
>  
> +- fsl,bman-portals
> + Usage:  Required
> + Value type: 
> + Definition: Phandle to this BMan's instance portals

s/BMan's instance/BMan instance's/

Likewise for QMan

-Scott


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Re: [PATCH v3 1/3] Revert "clk: ppc-corenet: Fix Section mismatch warning"

[Scott Wood]

On Thu, 2014-12-04 at 12:38 +0800, Kevin Hao wrote:
> On Wed, Dec 03, 2014 at 10:04:51PM -0600, Scott Wood wrote:
> > On Wed, 2014-12-03 at 16:53 +0800, Kevin Hao wrote:
> > > This reverts commit da788acb28386aa896224e784954bb73c99ff26c.
> > > 
> > > That commit tried to fix the section mismatch warning by moving the
> > > ppc_corenet_clk_driver struct to init section. This is definitely wrong
> > > because the kernel would free the memories occupied by this struct
> > > after boot while this driver is still registered in the driver core.
> > > The kernel would panic when accessing this driver struct.
> > > 
> > > Cc: sta...@vger.kernel.org # 3.17
> > 
> > I don't see sta...@vger.kernel.org in the actual CC list.
> 
> With the above cc tag, Won't this get automatically included in the stable
> tree once it is merged into mainline? As I know, we only need to explicitly
> send the patch to sta...@vger.kernel.org only when that patch was already
> merged into mainline without the corresponding cc stable tag and we also want
> the stable tree include it. Did I miss something?

I reread stable_kernel_rules.txt and it looks like you're right, though
usually it ends up on the real CC list anyway due to how git send-email
works.

Since only this first patch is a critical bugfix, and there's no
arch/powerpc content in that patch, I think it should go via Mike's tree
if it's to go in for 3.18 (if it's not already too late).  Or, to keep
things simple given the dependency of the following patches, we could
batch them all together for -next and add a # 3.18 stable request.

-Scott


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Re: [PATCH v3 1/3] Revert "clk: ppc-corenet: Fix Section mismatch warning"

[Kevin Hao]

On Wed, Dec 03, 2014 at 10:04:51PM -0600, Scott Wood wrote:
> On Wed, 2014-12-03 at 16:53 +0800, Kevin Hao wrote:
> > This reverts commit da788acb28386aa896224e784954bb73c99ff26c.
> > 
> > That commit tried to fix the section mismatch warning by moving the
> > ppc_corenet_clk_driver struct to init section. This is definitely wrong
> > because the kernel would free the memories occupied by this struct
> > after boot while this driver is still registered in the driver core.
> > The kernel would panic when accessing this driver struct.
> > 
> > Cc: sta...@vger.kernel.org # 3.17
> 
> I don't see sta...@vger.kernel.org in the actual CC list.

With the above cc tag, Won't this get automatically included in the stable
tree once it is merged into mainline? As I know, we only need to explicitly
send the patch to sta...@vger.kernel.org only when that patch was already
merged into mainline without the corresponding cc stable tag and we also want
the stable tree include it. Did I miss something?

Thanks,
Kevin


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Re: Right location in sysfs for dlpar file

[Greg KH]

On Wed, Dec 03, 2014 at 09:07:27PM -0600, Nathan Fontenot wrote:
> On 12/01/2014 10:26 PM, Greg KH wrote:
> > On Mon, Dec 01, 2014 at 09:41:03AM -0600, Nathan Fontenot wrote:
> >> On 11/26/2014 09:12 PM, Benjamin Herrenschmidt wrote:
> >>> Hi Greg,
> >>>
> >>> So Nathan is working on a patch series to cleanup and improve our
> >>> "DLPAR" infrastructure which is basically our hotplug mechanism when
> >>> running under the PowerVM (aka pHyp) and KVM hypervisors.
> >>
> >> The cleanup to the dlpar infrastructure will move the entire operation
> >> of hotplugging a device to the kernel instead of doing it partially in
> >> userspace and partially in the kernel as is currently done.
> >>
> >>>
> >>> I'll let Nathan give you a bit more details/background and answer
> >>> subsequent question you might have as this is really his area of
> >>> expertise.
> >>>
> >>> To cut a long story short, we need a sysfs file that allows our
> >>> userspace tools to notify the kernel of hotplug events coming from
> >>> the management console (which talks to userspace daemons using a
> >>> proprietary protocol) to "initiate" the hotplug operations, which in
> >>> turn get dispatched internally in the kernel to the right subsystem
> >>> (memory, cpu, pci, ...) based on the resource type.
> >>>
> >>> On IRC, Greg suggested /sys/firmware and /sys/hypervisor which both
> >>> look like a reasonable option to me, probably better than dlpar...
> >>
> >> For PowerVM systems we need this sysfs file to deliver what is
> >> essentially a binary blob (specifically a rtas error log) to the
> >> kernel. The current patch set is creating /sys/kernel/dlpar. As Ben
> >> mentioned we would like your input on what would be the proper place
> >> to create this file.
> > 
> > And what is the kernel supposed to do with such a binary blob?  Parse
> > it?  Or pass it to something else?
> 
> The kernel will parse it and perform the requested hotplug operation.

Oh I was hoping you would not say that :(

Seriously?  Parsing binary blobs from userspace?  Don't do that, you
know better.

greg k-h
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Re: [PATCH v3 1/3] Revert "clk: ppc-corenet: Fix Section mismatch warning"

[Scott Wood]

On Wed, 2014-12-03 at 16:53 +0800, Kevin Hao wrote:
> This reverts commit da788acb28386aa896224e784954bb73c99ff26c.
> 
> That commit tried to fix the section mismatch warning by moving the
> ppc_corenet_clk_driver struct to init section. This is definitely wrong
> because the kernel would free the memories occupied by this struct
> after boot while this driver is still registered in the driver core.
> The kernel would panic when accessing this driver struct.
> 
> Cc: sta...@vger.kernel.org # 3.17

I don't see sta...@vger.kernel.org in the actual CC list.

-Scott


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Re: [PATCH v3 3/4] powerpc/mpc85xx: Add FSL QorIQ DPAA BMan support to device tree(s)

[Scott Wood]

On Wed, 2014-12-03 at 20:42 +0100, Arnd Bergmann wrote:
> On Wednesday 03 December 2014 01:53:39 Emil Medve wrote:
> > On 12/02/2014 06:32 PM, Scott Wood wrote:
> > > On Mon, 2014-12-01 at 04:02 -0600, Emil Medve wrote:
> > >> diff --git a/arch/powerpc/boot/dts/t4240rdb.dts 
> > >> b/arch/powerpc/boot/dts/t4240rdb.dts
> > >> index 53761d4..431bf4e 100644
> > >> --- a/arch/powerpc/boot/dts/t4240rdb.dts
> > >> +++ b/arch/powerpc/boot/dts/t4240rdb.dts
> > >> @@ -69,10 +69,27 @@
> > >>  device_type = "memory";
> > >>  };
> > >>  
> > >> +reserved-memory {
> > >> +#address-cells = <2>;
> > >> +#size-cells = <2>;
> > >> +ranges;
> > >> +
> > >> +bman_fbpr: bman-fbpr {
> > >> +compatible = "fsl,bman-fbpr";
> > >> +alloc-ranges = <0 0 0x 0x>;
> > >> +size = <0 0x100>;
> > >> +alignment = <0 0x100>;
> > >> +};
> > >> +};
> > > 
> > > Can't this be done at the SoC level rather than board level?
> > 
> > The size of the memory is not SoC specific. Among other things is
> > determined by the number of MACs that are pinned-out on the board
> > 

Oh, right.

> Is this really a hardware property then, or some setting?

It's sort of a gray area (as is the reserved-memory mechanism itself)...
The hardware technically allows software to choose the size of the
memory, but the size required to perform optimally is primarily
determined by the ethernet ports that are pinned out on a given board --
except for any extra memory required by accelerators.

I previously suggested an extension to the reserved-memory binding to
convey the fact that the region can potentially be sized differently:
https://lists.ozlabs.org/pipermail/linuxppc-dev/2014-October/122300.html

In most cases the size calculated from the board's ethernet ports is
what is desired, so I think providing a sane default counts as hardware
description.

-Scott


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Re: [PATCH] powerpc/pci: remove pci device on a bus in reverse order

[Wei Yang]

Please ignore this one, I create an old version of the patch.

The new one is sent.

On Thu, Dec 04, 2014 at 11:04:32AM +0800, Wei Yang wrote:
>As in commit ac205b7b (PCI: make sriov work with hotplug remove) indicates,
>when removing pci devices on a bus which has VFs, we need to remove them in
>the reverse order.
>
>This patch applies this patten on the hotplug remove patch on powerpc arch.
>
>Signed-off-by: Wei Yang 
>---
> arch/powerpc/kernel/pci-hotplug.c |2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
>diff --git a/arch/powerpc/kernel/pci-hotplug.c 
>b/arch/powerpc/kernel/pci-hotplug.c
>index 5b78917..f0f00d9 100644
>--- a/arch/powerpc/kernel/pci-hotplug.c
>+++ b/arch/powerpc/kernel/pci-hotplug.c
>@@ -50,7 +50,7 @@ void pcibios_remove_pci_devices(struct pci_bus *bus)
>
>   pr_debug("PCI: Removing devices on bus %04x:%02x\n",
>pci_domain_nr(bus),  bus->number);
>-  list_for_each_entry_safe(dev, tmp, &bus->devices, bus_list) {
>+  list_for_each_entry_safe_reverse(dev, tmp, &bus->devices, bus_list) {
>   pr_debug("   Removing %s...\n", pci_name(dev));
>   pci_stop_and_remove_bus_device(dev);
>   }
>-- 
>1.7.9.5

-- 
Richard Yang
Help you, Help me

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[PATCH] powerpc/pci: remove pci device on a bus in reverse order

[Wei Yang]

As in commit ac205b7b (PCI: make sriov work with hotplug remove) indicates,
when removing pci devices on a bus which has VFs, we need to remove them in
the reverse order.

This patch applies this pattern on the hotplug remove path on powerpc arch.

Signed-off-by: Wei Yang 
Acked-by: Gavin Shan 
---
 arch/powerpc/kernel/pci-hotplug.c |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/powerpc/kernel/pci-hotplug.c 
b/arch/powerpc/kernel/pci-hotplug.c
index 5b78917..f0f00d9 100644
--- a/arch/powerpc/kernel/pci-hotplug.c
+++ b/arch/powerpc/kernel/pci-hotplug.c
@@ -50,7 +50,7 @@ void pcibios_remove_pci_devices(struct pci_bus *bus)
 
pr_debug("PCI: Removing devices on bus %04x:%02x\n",
 pci_domain_nr(bus),  bus->number);
-   list_for_each_entry_safe(dev, tmp, &bus->devices, bus_list) {
+   list_for_each_entry_safe_reverse(dev, tmp, &bus->devices, bus_list) {
pr_debug("   Removing %s...\n", pci_name(dev));
pci_stop_and_remove_bus_device(dev);
}
-- 
1.7.9.5

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Re: Right location in sysfs for dlpar file

[Nathan Fontenot]

On 12/01/2014 10:26 PM, Greg KH wrote:
> On Mon, Dec 01, 2014 at 09:41:03AM -0600, Nathan Fontenot wrote:
>> On 11/26/2014 09:12 PM, Benjamin Herrenschmidt wrote:
>>> Hi Greg,
>>>
>>> So Nathan is working on a patch series to cleanup and improve our
>>> "DLPAR" infrastructure which is basically our hotplug mechanism when
>>> running under the PowerVM (aka pHyp) and KVM hypervisors.
>>
>> The cleanup to the dlpar infrastructure will move the entire operation
>> of hotplugging a device to the kernel instead of doing it partially in
>> userspace and partially in the kernel as is currently done.
>>
>>>
>>> I'll let Nathan give you a bit more details/background and answer
>>> subsequent question you might have as this is really his area of
>>> expertise.
>>>
>>> To cut a long story short, we need a sysfs file that allows our
>>> userspace tools to notify the kernel of hotplug events coming from
>>> the management console (which talks to userspace daemons using a
>>> proprietary protocol) to "initiate" the hotplug operations, which in
>>> turn get dispatched internally in the kernel to the right subsystem
>>> (memory, cpu, pci, ...) based on the resource type.
>>>
>>> On IRC, Greg suggested /sys/firmware and /sys/hypervisor which both
>>> look like a reasonable option to me, probably better than dlpar...
>>
>> For PowerVM systems we need this sysfs file to deliver what is
>> essentially a binary blob (specifically a rtas error log) to the
>> kernel. The current patch set is creating /sys/kernel/dlpar. As Ben
>> mentioned we would like your input on what would be the proper place
>> to create this file.
> 
> And what is the kernel supposed to do with such a binary blob?  Parse
> it?  Or pass it to something else?

The kernel will parse it and perform the requested hotplug operation.

> 
> Anyway, let's see the patches before I guess anything else, that will
> determine how things work out best.

I'll cc you on the next version of the patch set.

-Nathan

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Re: Right location in sysfs for dlpar file

[Nathan Fontenot]

On 12/01/2014 11:09 PM, Michael Ellerman wrote:
> On Mon, 2014-12-01 at 09:41 -0600, Nathan Fontenot wrote:
>> On 11/26/2014 09:12 PM, Benjamin Herrenschmidt wrote:
>>> Hi Greg,
>>>
>>> So Nathan is working on a patch series to cleanup and improve our
>>> "DLPAR" infrastructure which is basically our hotplug mechanism when
>>> running under the PowerVM (aka pHyp) and KVM hypervisors.
>>
>> The cleanup to the dlpar infrastructure will move the entire operation
>> of hotplugging a device to the kernel instead of doing it partially in
>> userspace and partially in the kernel as is currently done.
>>
> ...
>>
>> For PowerVM systems we need this sysfs file to deliver what is
>> essentially a binary blob (specifically a rtas error log) to the
>> kernel.
> 
> Those two statements don't really agree with each other. ie. "move the entire
> operation .. to the kernel", but then we need a sysfs file so userspace can
> deliver us a blob?
> 
> I think what you mean is that all the actual logic will move into the kernel,
> and the only thing userspace will do (on PowerVM) is write the blog to kick 
> off
> the process.
> 
> On PowerKVM the entire process will be handled in the kernel (after some
> additional patches to hook up the rtas event to the hotplug).
> 

This is correct. I should have explained it better.

> 
> As ugly as it is, we already have /proc/rtas, which includes a bunch of files,
> including error_log, which is where you can *read* the RTAS error logs from.
>

I have no problem making this a writeable file. I think keeping all of the rtas
error log communication between the kernel userspace in one place would be a 
good
idea.
 
> So maybe we just extend that, either a new file, or just by making error_log
> writable?
> 
> It'd be nice to drop all that rtas gunk and move to something cleaner in /sys,
> but I don't think we can realistically do that any time soon anyway?
> 

Perhaps doing this at a later time would be worthwhile.

-Nathan

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[PATCH] powerpc/pci: remove pci device on a bus in reverse order

[Wei Yang]

As in commit ac205b7b (PCI: make sriov work with hotplug remove) indicates,
when removing pci devices on a bus which has VFs, we need to remove them in
the reverse order.

This patch applies this patten on the hotplug remove patch on powerpc arch.

Signed-off-by: Wei Yang 
---
 arch/powerpc/kernel/pci-hotplug.c |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/powerpc/kernel/pci-hotplug.c 
b/arch/powerpc/kernel/pci-hotplug.c
index 5b78917..f0f00d9 100644
--- a/arch/powerpc/kernel/pci-hotplug.c
+++ b/arch/powerpc/kernel/pci-hotplug.c
@@ -50,7 +50,7 @@ void pcibios_remove_pci_devices(struct pci_bus *bus)
 
pr_debug("PCI: Removing devices on bus %04x:%02x\n",
 pci_domain_nr(bus),  bus->number);
-   list_for_each_entry_safe(dev, tmp, &bus->devices, bus_list) {
+   list_for_each_entry_safe_reverse(dev, tmp, &bus->devices, bus_list) {
pr_debug("   Removing %s...\n", pci_name(dev));
pci_stop_and_remove_bus_device(dev);
}
-- 
1.7.9.5

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Re: [PATCH] powerpc: drop useless warning in eeh_init()

[Michael Ellerman]

On Thu, 2014-12-04 at 09:14 +1100, Gavin Shan wrote:
> On Wed, Dec 03, 2014 at 03:20:46PM +0100, Greg Kurz wrote:
> >On Wed, 26 Nov 2014 09:28:47 +1100
> >Gavin Shan  wrote:
> >> On Tue, Nov 25, 2014 at 05:10:06PM +0100, Greg Kurz wrote:
> >> >This is what we get in dmesg when booting a pseries guest and
> >> >the hypervisor doesn't provide EEH support.
> >
> >Ping ?
> 
> It's already in Michael's git tree.

Indeed.

It's also marked as "Under Review" in patchwork, which basically means I've
seen it and it's on its way into my tree unless you hear otherwise.

http://patchwork.ozlabs.org/patch/414753/

cheers


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Re: [PATCH] powerpc: add little endian flag to syscall_get_arch()

[Paul Moore]

On Tuesday, December 02, 2014 01:54:16 PM Tony Jones wrote:
> On 12/02/2014 01:27 PM, Richard Guy Briggs wrote:
> > Since both ppc and ppc64 have LE variants which are now reported by uname,
> > add that flag (__AUDIT_ARCH_LE) to syscall_get_arch() and add
> > AUDIT_ARCH_PPC*LE variants.
> > 
> > Without this,  perf trace and auditctl fail.
> > 
> > Mainline kernel reports ppc64le (per a058801) but there is no matching
> > AUDIT_ARCH_PPC64LE.
> > 
> > See:
> > https://www.redhat.com/archives/linux-audit/2014-August/msg00082.html
> > https://www.redhat.com/archives/linux-audit/2014-December/msg4.html
> > 
> > Signed-off-by: Richard Guy Briggs 
> > ---
> > 
> >  arch/powerpc/include/asm/syscall.h |6 +-
> >  include/uapi/linux/audit.h |2 ++
> >  2 files changed, 7 insertions(+), 1 deletions(-)
> > 
> > diff --git a/arch/powerpc/include/asm/syscall.h
> > b/arch/powerpc/include/asm/syscall.h index 6fa2708..a58acab 100644
> > --- a/arch/powerpc/include/asm/syscall.h
> > +++ b/arch/powerpc/include/asm/syscall.h
> > @@ -90,6 +90,10 @@ static inline void syscall_set_arguments(struct
> > task_struct *task,> 
> >  static inline int syscall_get_arch(void)
> >  {
> > 
> > -   return is_32bit_task() ? AUDIT_ARCH_PPC : AUDIT_ARCH_PPC64;
> > +   int arch = is_32bit_task() ? AUDIT_ARCH_PPC : AUDIT_ARCH_PPC64;
> > +#ifdef __LITTLE_ENDIAN__
> > +   arch |= __AUDIT_ARCH_LE
> > +#endif
> > +   return arch;
> > 
> >  }
> >  #endif /* _ASM_SYSCALL_H */
> > 
> > diff --git a/include/uapi/linux/audit.h b/include/uapi/linux/audit.h
> > index 4d100c8..fe29a99 100644
> > --- a/include/uapi/linux/audit.h
> > +++ b/include/uapi/linux/audit.h
> > @@ -364,7 +364,9 @@ enum {
> > 
> >  #define AUDIT_ARCH_PARISC  (EM_PARISC)
> >  #define AUDIT_ARCH_PARISC64(EM_PARISC|__AUDIT_ARCH_64BIT)
> >  #define AUDIT_ARCH_PPC (EM_PPC)
> > 
> > +#define AUDIT_ARCH_PPCLE   (EM_PPC|__AUDIT_ARCH_LE)
> > 
> >  #define AUDIT_ARCH_PPC64   (EM_PPC64|__AUDIT_ARCH_64BIT)
> > 
> > +#define AUDIT_ARCH_PPC64LE (EM_PPC64|__AUDIT_ARCH_64BIT|__AUDIT_ARCH_LE)
> > 
> >  #define AUDIT_ARCH_S390(EM_S390)
> >  #define AUDIT_ARCH_S390X   (EM_S390|__AUDIT_ARCH_64BIT)
> >  #define AUDIT_ARCH_SH  (EM_SH)
> 
> IBM would know for certain but I wasn't aware there was a PPCLE (32bit
> compat).

FWIW, I've heard the same thing from IBM folks off-list.

-- 
paul moore
security and virtualization @ redhat

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Re: [PATCH] powerpc: drop useless warning in eeh_init()

[Gavin Shan]

On Wed, Dec 03, 2014 at 03:20:46PM +0100, Greg Kurz wrote:
>On Wed, 26 Nov 2014 09:28:47 +1100
>Gavin Shan  wrote:
>> On Tue, Nov 25, 2014 at 05:10:06PM +0100, Greg Kurz wrote:
>> >This is what we get in dmesg when booting a pseries guest and
>> >the hypervisor doesn't provide EEH support.
>> >
>> >[0.166655] EEH functionality not supported
>> >[0.166778] eeh_init: Failed to call platform init function (-22)
>> >
>> >Since both powernv_eeh_init() and pseries_eeh_init() already complain when
>> >hitting an error, it is not needed to print more (especially such an
>> >uninformative message).
>> >
>> >Signed-off-by: Greg Kurz 
>> 
>> Acked-by: Gavin Shan 
>> 
>> Thanks,
>> Gavin
>> 
>
>Ping ?
>

It's already in Michael's git tree.

shangw@shangw:~/sandbox/linux.ppc$ git remote -v
origin  git://git.kernel.org/pub/scm/linux/kernel/git/mpe/linux.git (fetch)
origin  git://git.kernel.org/pub/scm/linux/kernel/git/mpe/linux.git (push)
shangw@shangw:~/sandbox/linux.ppc$ git branch 
  master
* next
shangw@shangw:~/sandbox/linux.ppc$ git log --author="Greg Kurz" --oneline
  1 221195f powerpc: Drop useless warning in eeh_init()

Thanks,
Gavin

>> >---
>> > arch/powerpc/kernel/eeh.c |5 +
>> > 1 file changed, 1 insertion(+), 4 deletions(-)
>> >
>> >diff --git a/arch/powerpc/kernel/eeh.c b/arch/powerpc/kernel/eeh.c
>> >index 2248a19..7d62018 100644
>> >--- a/arch/powerpc/kernel/eeh.c
>> >+++ b/arch/powerpc/kernel/eeh.c
>> >@@ -920,11 +920,8 @@ int eeh_init(void)
>> >pr_warn("%s: Platform EEH operation not found\n",
>> >__func__);
>> >return -EEXIST;
>> >-   } else if ((ret = eeh_ops->init())) {
>> >-   pr_warn("%s: Failed to call platform init function (%d)\n",
>> >-   __func__, ret);
>> >+   } else if ((ret = eeh_ops->init()))
>> >return ret;
>> >-   }
>> > 
>> >/* Initialize EEH event */
>> >ret = eeh_event_init();
>> >
>> >___
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>> >https://lists.ozlabs.org/listinfo/linuxppc-dev
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Re: [PATCH] Documentation: bindings: net: DPAA corenet binding document

[Scott Wood]

On Tue, 2014-12-02 at 17:03 -0600, Scott Wood wrote:
> On Tue, 2014-12-02 at 06:12 -0600, Bucur Madalin-Cristian-B32716 wrote:
> > > -Original Message-
> > > From: Wood Scott-B07421
> > > Sent: Tuesday, December 02, 2014 6:40 AM
> > >
> > > No need for the  part.  As we previously discussed, the only
> > > purpose of this node is backwards compatibility with the U-Boot MAC
> > > address fixup -- if U-Boot doesn't look for the  version, then
> > > don't complicate things.
> > > 
> > > Though, I can't find where U-Boot references this node.  Are you sure
> > > it's not using the ethernet%d aliases like everything else, in which
> > > case why do we need this node at all?
> > > 
> > > -Scott
> > > 
> > 
> > The initial (Freescale SDK) binding document contained those compatibles,
> > not sure what the initial intent was for the  variants.
> > 
> > The "fsl,dpaa" node is of interest to the DPAA Ethernet because it is
> > the parent of the "fsl,dpa-ethernet" nodes.
> 
> I'm not interested in what the SDK binding says, or what the SDK kernel
> does.  I'm interested in whether there's a U-Boot compatibility issue,
> as was previously alleged.  If there isn't, then there's no need for
> fsl,dpaa *or* fsl,dpa-ethernet.

OK, I found the U-Boot fixup in question.  It's not for MAC addresses,
but for marking disabled ports as disabled.  It marks the dpa-ethernet
node as disabled, based on it having an fsl,fman-mac property that
points to the MAC node.

U-Boot also disables the MAC node itself, so it doesn't matter if it
doesn't find fsl,fman-mac -- except for the special case of fm1-dtsec1,
which is always kept enabled because it's used for MDIO for all ports.

Based on http://patchwork.ozlabs.org/patch/410770/ there's a separate
node for mdio, so why can't we mark the MAC disabled?  Assuming that
there's no real problem in marking the fm1-dtsec1 MAC node disabled, we
can consider this to be a bug in U-Boot which can be worked around by
having the fm1-dtsec1 mac node have an fsl,fman-mac property that points
to itself.  This property would only go on the fm1-dtsec1 mac node and
would only be in device trees for SoCs that are supported by U-Boots old
enough to not have had the bug be fixed.

-Scott


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Re: [PATCH 03/10] mm: Convert p[te|md]_numa users to p[te|md]_protnone_numa

[Benjamin Herrenschmidt]

On Wed, 2014-12-03 at 15:52 +, Mel Gorman wrote:
> 
> It's implied but can I assume it passed? If so, Ben and Paul, can I
> consider the series to be acked by you other than the minor comment
> updates?

Yes. Assuming it passed :-)

Acked-by: Benjamin Herrenschmidt 

Cheers,
Ben.


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Re: [PATCH v3 3/4] powerpc/mpc85xx: Add FSL QorIQ DPAA BMan support to device tree(s)

[Emil Medve]

Hello Arnd,


Thanks for taking the time to review this

On 12/03/2014 01:42 PM, Arnd Bergmann wrote:
> On Wednesday 03 December 2014 01:53:39 Emil Medve wrote:
>> On 12/02/2014 06:32 PM, Scott Wood wrote:
>>> On Mon, 2014-12-01 at 04:02 -0600, Emil Medve wrote:
 diff --git a/arch/powerpc/boot/dts/t4240rdb.dts 
 b/arch/powerpc/boot/dts/t4240rdb.dts
 index 53761d4..431bf4e 100644
 --- a/arch/powerpc/boot/dts/t4240rdb.dts
 +++ b/arch/powerpc/boot/dts/t4240rdb.dts
 @@ -69,10 +69,27 @@
  device_type = "memory";
  };
  
 +reserved-memory {
 +#address-cells = <2>;
 +#size-cells = <2>;
 +ranges;
 +
 +bman_fbpr: bman-fbpr {
 +compatible = "fsl,bman-fbpr";
 +alloc-ranges = <0 0 0x 0x>;
 +size = <0 0x100>;
 +alignment = <0 0x100>;
 +};
 +};
>>>
>>> Can't this be done at the SoC level rather than board level?
>>
>> The size of the memory is not SoC specific. Among other things is
>> determined by the number of MACs that are pinned-out on the board
> 
> Is this really a hardware property then, or some setting?

I'm unsure how to answer this. It is my opinion it's a hardware property
and that we're not stretching the intent of the reserved-memory binding

> Also, if you use the name 'ranges', I would assume that the second
> set of two cells is a length and should be <0 0 0x1 0>.

Uh... Right. I'll fix it

> Finally, you add a label here, so anything that is not board
> specific could just stay in the per-soc file, with the board
> specific properties added at teh board level.

I will do that


Cheers,
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Re: [PATCH v3 3/4] powerpc/mpc85xx: Add FSL QorIQ DPAA BMan support to device tree(s)

[Arnd Bergmann]

On Wednesday 03 December 2014 01:53:39 Emil Medve wrote:
> On 12/02/2014 06:32 PM, Scott Wood wrote:
> > On Mon, 2014-12-01 at 04:02 -0600, Emil Medve wrote:
> >> diff --git a/arch/powerpc/boot/dts/t4240rdb.dts 
> >> b/arch/powerpc/boot/dts/t4240rdb.dts
> >> index 53761d4..431bf4e 100644
> >> --- a/arch/powerpc/boot/dts/t4240rdb.dts
> >> +++ b/arch/powerpc/boot/dts/t4240rdb.dts
> >> @@ -69,10 +69,27 @@
> >>  device_type = "memory";
> >>  };
> >>  
> >> +reserved-memory {
> >> +#address-cells = <2>;
> >> +#size-cells = <2>;
> >> +ranges;
> >> +
> >> +bman_fbpr: bman-fbpr {
> >> +compatible = "fsl,bman-fbpr";
> >> +alloc-ranges = <0 0 0x 0x>;
> >> +size = <0 0x100>;
> >> +alignment = <0 0x100>;
> >> +};
> >> +};
> > 
> > Can't this be done at the SoC level rather than board level?
> 
> The size of the memory is not SoC specific. Among other things is
> determined by the number of MACs that are pinned-out on the board
> 

Is this really a hardware property then, or some setting?

Also, if you use the name 'ranges', I would assume that the second
set of two cells is a length and should be <0 0 0x1 0>.

Finally, you add a label here, so anything that is not board
specific could just stay in the per-soc file, with the board
specific properties added at teh board level.

Arnd
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Re: [PATCH 03/10] mm: Convert p[te|md]_numa users to p[te|md]_protnone_numa

[Aneesh Kumar K.V]

Mel Gorman  writes:

> On Wed, Dec 03, 2014 at 08:53:37PM +0530, Aneesh Kumar K.V wrote:
>> Benjamin Herrenschmidt  writes:
>> 
>> > On Tue, 2014-12-02 at 12:57 +0530, Aneesh Kumar K.V wrote:
>> >> Now, hash_preload can possibly insert an hpte in hash page table even if
>> >> the access is not allowed by the pte permissions. But i guess even that
>> >> is ok. because we will fault again, end-up calling hash_page_mm where we
>> >> handle that part correctly.
>> >
>> > I think we need a test case...
>> >
>> 
>> I ran the subpageprot test that Paul had written. I modified it to ran
>> with selftest. 
>> 
>
> It's implied but can I assume it passed? 

Yes.

-bash-4.2# ./subpage_prot 
test: subpage_prot
tags: git_version:v3.17-rc3-13511-g0cd3756
allocated malloc block of 0x400 bytes at 0x0x3fffb0d1
testing malloc block...
OK
success: subpage_prot
-bash-4.2# 

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Re: [RFC PATCH 1/2]powerpc: foundation code to handle CR5 for local_t

[Gabriel Paubert]

On Wed, Dec 03, 2014 at 08:29:37PM +0530, Madhavan Srinivasan wrote:
> On Tuesday 02 December 2014 03:05 AM, Gabriel Paubert wrote:
> > On Thu, Nov 27, 2014 at 05:48:40PM +0530, Madhavan Srinivasan wrote:
> >> diff --git a/arch/powerpc/include/asm/exception-64s.h 
> >> b/arch/powerpc/include/asm/exception-64s.h
> >> index 77f52b2..c42919a 100644
> >> --- a/arch/powerpc/include/asm/exception-64s.h
> >> +++ b/arch/powerpc/include/asm/exception-64s.h
> >> @@ -306,7 +306,26 @@ do_kvm_##n:   
> >> \
> >>std r10,0(r1);  /* make stack chain pointer */ \
> >>std r0,GPR0(r1);/* save r0 in stackframe*/ \
> >>std r10,GPR1(r1);   /* save r1 in stackframe*/ \
> >> -  beq 4f; /* if from kernel mode  */ \
> >> +BEGIN_FTR_SECTION;
> >>\
> >> +  lis r9,4096;/* Create a mask with HV and PR */ \
> >> +  rldicr  r9,r9,32,31;/* bits, AND with the MSR   */ \
> >> +  mr  r10,r9; /* to check for Hyp state   */ \
> >> +  ori r9,r9,16384;   \
> >> +  and r9,r12,r9; \
> >> +  cmpdcr3,r10,r9; 
> >>\
> >> +  beq cr3,66f;/* Jump if we come from Hyp mode*/ \
> >> +  mtcrf   0x04,r10;   /* Clear CR5 if coming from usr */ \
> > 
> > I think you can do better than this, powerpc has a fantastic set
> > of rotate and mask instructions. If I understand correctly your
> > code you can replace it with the following:
> > 
> > rldicl  r10,r12,4,63   /* Extract HV bit to LSB of r10*/
> > rlwinm  r9,r12,19,0x02 /* Extract PR bit to 2nd to last bit of r9 */
> > or  r9,r9,10
> > cmplwi  cr3,r9,1   /* Check for HV=1 and PR=0 */
> > beq cr3,66f
> > mtcrf   0x04,r10   /* Bits going to cr5 bits are 0 in r10 */
> > 
> 
> >From previous comment, at this point, CR0 already has MSR[PR], and only
> HV need to be checked. So I guess there still room for optimization.
> But good to learn this seq.

Actually the sequence I suggested can even be shortened again since the or
is not necessary and you can use an rlwimi instead.

rldicl r9,r12,5,62  /*  r9 = 62 zeroes | HV | ?  */
rlwimi r9,r12,18,0x01   /*  r9 = 62 zeroes | HV | PR */
cmplwi cr3,r9,2 /* Check for HV=1 and PR=0 */

For 32 bit operands, rlwimi is a generic bit field to bit field move, but
GCC is (was, maybe GCC5 is better?) quite bad at recognizing opportunities
to use it.

I'm not sure that it is better to have two separate branches, one for
testing PR and the other for testing HV. Through how many branches can
the hardware speculate? 

Unless I'm mistaken, this is code which is likely not to be in the
cache so I would optimize it first towards minimal code size.

Regards,
Gabriel
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Re: [PATCH 03/10] mm: Convert p[te|md]_numa users to p[te|md]_protnone_numa

[Mel Gorman]

On Wed, Dec 03, 2014 at 08:53:37PM +0530, Aneesh Kumar K.V wrote:
> Benjamin Herrenschmidt  writes:
> 
> > On Tue, 2014-12-02 at 12:57 +0530, Aneesh Kumar K.V wrote:
> >> Now, hash_preload can possibly insert an hpte in hash page table even if
> >> the access is not allowed by the pte permissions. But i guess even that
> >> is ok. because we will fault again, end-up calling hash_page_mm where we
> >> handle that part correctly.
> >
> > I think we need a test case...
> >
> 
> I ran the subpageprot test that Paul had written. I modified it to ran
> with selftest. 
> 

It's implied but can I assume it passed? If so, Ben and Paul, can I
consider the series to be acked by you other than the minor comment
updates?

Thanks.

-- 
Mel Gorman
SUSE Labs
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Re: [PATCH 03/10] mm: Convert p[te|md]_numa users to p[te|md]_protnone_numa

[Aneesh Kumar K.V]

Benjamin Herrenschmidt  writes:

> On Tue, 2014-12-02 at 12:57 +0530, Aneesh Kumar K.V wrote:
>> Now, hash_preload can possibly insert an hpte in hash page table even if
>> the access is not allowed by the pte permissions. But i guess even that
>> is ok. because we will fault again, end-up calling hash_page_mm where we
>> handle that part correctly.
>
> I think we need a test case...
>

I ran the subpageprot test that Paul had written. I modified it to ran
with selftest. 

commit 0cd3756bce6880a13de49406ce5c8537712c9bf8
Author: Aneesh Kumar K.V 
Date:   Wed Dec 3 20:40:06 2014 +0530

selftest/ppc: Add subpage protection self test.

Originally written by  Paul Mackerras 

Signed-off-by: Aneesh Kumar K.V 

diff --git a/tools/testing/selftests/powerpc/mm/Makefile 
b/tools/testing/selftests/powerpc/mm/Makefile
index 357ccbd6bad9..fb00c6f7d675 100644
--- a/tools/testing/selftests/powerpc/mm/Makefile
+++ b/tools/testing/selftests/powerpc/mm/Makefile
@@ -1,7 +1,7 @@
 noarg:
$(MAKE) -C ../
 
-PROGS := hugetlb_vs_thp_test
+PROGS := hugetlb_vs_thp_test subpage_prot
 
 all: $(PROGS)
 
diff --git a/tools/testing/selftests/powerpc/mm/subpage_prot.c 
b/tools/testing/selftests/powerpc/mm/subpage_prot.c
new file mode 100644
index ..1efeafc2e175
--- /dev/null
+++ b/tools/testing/selftests/powerpc/mm/subpage_prot.c
@@ -0,0 +1,150 @@
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "utils.h"
+
+void *mallocblock;
+unsigned long mallocsize;
+void *fileblock;
+off_t filesize;
+
+int in_test;
+volatile int faulted;
+volatile void *dar;
+int errors;
+
+static void segv(int signum, siginfo_t *info, void *ctxt_v)
+{
+   ucontext_t *ctxt = (ucontext_t *)ctxt_v;
+   struct pt_regs *regs = ctxt->uc_mcontext.regs;
+
+   if (!in_test) {
+   fprintf(stderr, "Segfault outside of test !\n");
+   exit(1);
+   }
+   faulted = 1;
+   dar = (void *)regs->dar;
+   regs->nip += 4;
+}
+
+static inline void do_read(const volatile void *addr)
+{
+   int ret;
+   asm volatile("lwz %0,0(%1); twi 0,%0,0; isync;\n"
+: "=r" (ret) : "r" (addr) : "memory");
+}
+
+static inline void do_write(const volatile void *addr)
+{
+   int val = 0x1234567;
+   asm volatile("stw %0,0(%1); sync; \n"
+: : "r" (val), "r" (addr) : "memory");
+}
+
+static inline void check_faulted(void *addr, long page, long subpage, int 
write)
+{
+   int want_fault = (subpage == ((page + 3) % 16));
+
+   if (write)
+   want_fault |= (subpage == ((page + 1) % 16));
+
+   if (faulted != want_fault) {
+   printf("Failed at 0x%p (p=%ld,sp=%ld,w=%d), want=%s, got=%s 
!\n",
+  addr, page, subpage, write,
+  want_fault ? "fault" : "pass",
+  faulted ? "fault" : "pass");
+   ++errors;
+   }
+   if (faulted) {
+   if (dar != addr) {
+   printf("Fault expected at 0x%p and happened at 0x%p 
!\n",
+  addr, dar);
+   }
+   faulted = 0;
+   asm volatile("sync" : : : "memory");
+   }
+}
+
+static int run_test(void *addr, unsigned long size)
+{
+   unsigned int *map;
+   long i, j, pages, err;
+
+   pages = size / 0x1;
+   map = malloc(pages * 4);
+   assert(map);
+
+   /* for each page, mark subpage i % 16 read only and subpage
+* (i + 3) % 16 inaccessible
+*/
+   for (i = 0; i < pages; i++)
+   map[i] = (0x4000 >> (((i + 1) * 2) % 32)) |
+   (0xc000 >> (((i + 3) * 2) % 32));
+   err = syscall(310, addr, size, map);
+   if (err) {
+   perror("subpage_perm");
+   return 1;
+   }
+   free(map);
+
+   in_test = 1;
+   errors = 0;
+   for (i = 0; i < pages; i++)
+   for (j = 0; j < 16; j++, addr += 0x1000) {
+   do_read(addr);
+   check_faulted(addr, i, j, 0);
+   do_write(addr);
+   check_faulted(addr, i, j, 1);
+   }
+   in_test = 0;
+   if (errors) {
+   printf("%d errors detected\n", errors);
+   return 1;
+   }
+   printf("OK\n");
+   return 0;
+}
+
+int test_main(void)
+{
+   unsigned long align;
+
+   if (getpagesize() != 0x1) {
+   fprintf(stderr, "Kernel page size must be 64K!\n");
+   return 1;
+   }
+
+   struct sigaction act = {
+   .sa_sigaction = segv,
+   .sa_flags = SA_SIGINFO
+   };
+   sigaction(SIGSEGV, &act, NULL);
+
+   mallocsize = 4*16*1024*1024;
+   posix_memalign(&mallocblock, 64*1024, mallocsize);
+   assert(mallocblock);
+   align = (unsigned long)mallocblock;
+ 

Re: [RFC PATCH 2/2]powerpc: rewrite local_* to use CR5 flag

[Madhavan Srinivasan]

On Monday 01 December 2014 11:31 PM, Gabriel Paubert wrote:
> On Thu, Nov 27, 2014 at 05:48:41PM +0530, Madhavan Srinivasan wrote:
>> This patch re-write the current local_* functions to CR5 based one.
>> Base flow for each function is 
>>
>> {
>>  set cr5(eq)
>>  load
>>  ..
>>  store
>>  clear cr5(eq)
>> }
>>
>> Above set of instructions are followed by a fixup section which points
>> to the entry of the function incase of interrupt in the flow. If the 
>> interrupt happens to be after the store, we just continue to last 
>> instruction in that block. 
>>
>> Currently only asm/local.h has been rewrite, and local64 is TODO.
>> Also the entire change is only for PPC64.
>>
>> Signed-off-by: Madhavan Srinivasan 
>> ---
>>  arch/powerpc/include/asm/local.h | 306 
>> +++
>>  1 file changed, 306 insertions(+)
>>
>> diff --git a/arch/powerpc/include/asm/local.h 
>> b/arch/powerpc/include/asm/local.h
>> index b8da913..a26e5d3 100644
>> --- a/arch/powerpc/include/asm/local.h
>> +++ b/arch/powerpc/include/asm/local.h
>> @@ -11,6 +11,310 @@ typedef struct
>>  
>>  #define LOCAL_INIT(i)   { ATOMIC_LONG_INIT(i) }
>>  
>> +#ifdef  CONFIG_PPC64
>> +
>> +static __inline__ long local_read(local_t *l)
>> +{
>> +long t;
>> +
>> +__asm__ __volatile__(
>> +"1: crset   22\n"
>> +"2:"PPC_LL" %0,0(%1)\n"
>> +"3: crclr   22\n"
>> +"4:\n"
>> +"   .section __ex_table,\"a\"\n"
>> +PPC_LONG_ALIGN "\n"
>> +PPC_LONG "2b,1b\n"
>> +PPC_LONG "3b,3b\n"
>> +"   .previous\n"
>> +: "=&r" (t)
>> +: "r" (&(l->a.counter)));
>> +
>> +return t;
>> +}
>> +
>> +static __inline__ void local_set(local_t *l, long i)
>> +{
>> +long t;
>> +
>> +__asm__ __volatile__(
>> +"1: crset   22\n"
>> +"2:"PPC_LL" %0,0(%1)\n"
>> +"3:"PPC405_ERR77(0,%2)
>> +"4:"PPC_STL" %0,0(%2)\n"
>> +"5: crclr   22\n"
>> +"6:\n"
>> +"   .section __ex_table,\"a\"\n"
>> +PPC_LONG_ALIGN "\n"
>> +PPC_LONG "2b,1b\n"
>> +PPC_LONG "3b,1b\n"
>> +PPC_LONG "4b,1b\n"
>> +PPC_LONG "5b,5b\n"
>> +"   .previous\n"
>> +: "=&r" (t)
>> +: "r" (&(i)), "r" (&(l->a.counter)));
>> +}
>> +
> 
> Apart from the other comments on bloat which can very likely
> be removed by tracing backwards for a few instructions, removing
> the exception table entries which are 2 or 4 (64 bit?) times as 
> large as the instruction sequence, I don't understand at all why
> you need these sequences for the local_read and local_set functions.
>
> After all these are single instructions (why do you perform a read before
> the write in set when the result of the read is never used?).
>
Agreed. But the benchmark I used, also did check for local_read timing.
So for consistency I re-wrote the these functions. But will drop the
changes for these function in the next version.

> I believe read and set are better mapped to access_once (or assign_once
> or whatever it's called after the recent discussion on linux-kernel).
> You don't even need a memory barrier if it's for a single thread,
> so you could get away with a single volatile access to the variables.
> 

OK.

> For the other ones, I think that what you do is correct, except that
> the workaround for PPC405 erratum 77 is not needed since this erratum
> only affects the stwcx. instruction and the whole point of the patch
> is to avoid the use of an l?arx/st?cx. pair.

Yes. Will remove it.

With regards
Maddy

> 
>   Regards,
>   Gabriel
> 
>> +static __inline__ void local_add(long i, local_t *l)
>> +{
>> +long t;
>> +
>> +__asm__ __volatile__(
>> +"1: crset   22\n"
>> +"2:"PPC_LL" %0,0(%2)\n"
>> +"3: add %0,%1,%0\n"
>> +"4:"PPC405_ERR77(0,%2)
>> +"5:"PPC_STL" %0,0(%2)\n"
>> +"6: crclr   22\n"
>> +"7:\n"
>> +"   .section __ex_table,\"a\"\n"
>> +PPC_LONG_ALIGN "\n"
>> +PPC_LONG "2b,1b\n"
>> +PPC_LONG "3b,1b\n"
>> +PPC_LONG "4b,1b\n"
>> +PPC_LONG "5b,1b\n"
>> +PPC_LONG "6b,6b\n"
>> +"   .previous\n"
>> +: "=&r" (t)
>> +: "r" (i), "r" (&(l->a.counter)));
>> +}
>> +
>> +static __inline__ void local_sub(long i, local_t *l)
>> +{
>> +long t;
>> +
>> +__asm__ __volatile__(
>> +"1: crset   22\n"
>> +"2:"PPC_LL" %0,0(%2)\n"
>> +"3: subf%0,%1,%0\n"
>> +"4:"PPC405_ERR77(0,%2)
>> +"5:"PPC_STL" %0,0(%2)\n"
>> +"6: crclr   22\n"
>> +"7:\n"
>> +"   .section __ex_table,\"a\"\n"
>> +PPC_LONG_ALIGN "\n"
>> +PPC_LONG "2b,1b\n"
>> +PPC_LONG "3b,1b\n"
>> +PPC_LONG "4b,1b\n"
>> +PPC_LONG "5b,1b\n"
>> +PPC_LONG "6b,6b\n"
>> +"   .previous\n"
>> +: "=&r" (t)
>> +: "r" (i), "r" (&(l->a.counter)));
>> +}
>> +
>> +static __inline__ long local_add_return(long a, local_t *l)
>> +{
>> +long t;
>> +
>> +__asm__ __volatile__(
>> +"1: crset   22\n"
>> +"2:"PPC_LL" %0,0(%2)\n"
>> +"3: add %0,%1,%0\n"
>> +"4:"PPC405_ERR77(0,%2)
>> +"5:"PPC_STL "%0,0(%2)\n"
>> +"6: crclr   22

Re: [RFC PATCH 1/2]powerpc: foundation code to handle CR5 for local_t

[Madhavan Srinivasan]

On Tuesday 02 December 2014 03:05 AM, Gabriel Paubert wrote:
> On Thu, Nov 27, 2014 at 05:48:40PM +0530, Madhavan Srinivasan wrote:
>> This patch create the infrastructure to handle the CR based 
>> local_* atomic operations. Local atomic operations are fast 
>> and highly reentrant per CPU counters.  Used for percpu 
>> variable updates. Local atomic operations only guarantee 
>> variable modification atomicity wrt the CPU which owns the
>> data and these needs to be executed in a preemption safe way. 
>>
>> Here is the design of this patch. Since local_* operations 
>> are only need to be atomic to interrupts (IIUC), patch uses 
>> one of the Condition Register (CR) fields as a flag variable. When 
>> entering the local_*, specific bit in the CR5 field is set
>> and on exit, bit is cleared. CR bit checking is done in the
>> interrupt return path. If CR5[EQ] bit set and if we return 
>> to kernel, we reset to start of local_* operation.
>>
>> Reason for this approach is that, currently l[w/d]arx/st[w/d]cx.
>> instruction pair is used for local_* operations, which are heavy 
>> on cycle count and they dont support a local variant. So to 
>> see whether the new implementation helps, used a modified 
>> version of Rusty's benchmark code on local_t.   
>>
>> https://lkml.org/lkml/2008/12/16/450
>>
>> Modifications: 
>>  - increated the working set size from 1MB to 8MB,
>>  - removed cpu_local_inc test.
>>
>> Test ran 
>> - on POWER8 1S Scale out System 2.0GHz
>> - on OPAL v3 with v3.18-rc4 patch kernel as Host
>>
>> Here are the values with the patch.
>>
>> Time in ns per iteration
>>
>>  inc add readadd_return
>> atomic_long  67  67  18  69
>> irqsave/rest 39  39  23  39
>> trivalue 39  39  29  49
>> local_t  26  26  24  26
>>
>> Since CR5 is used as a flag, have added CFLAGS to avoid CR5 
>> for the kernel compilation and CR5 is zeroed at the kernel
>> entry.  
>>
>> Tested the patch in a 
>>  - pSeries LPAR, 
>>  - Host with patched/unmodified guest kernel 
>>
>> To check whether userspace see any CR5 corruption, ran a simple
>> test which does,
>>  - set CR5 field,
>>  - while(1)
>>- sleep or gettimeofday
>>- chk bit set
>>
>> Signed-off-by: Madhavan Srinivasan 
>> ---
>> - I really appreciate feedback on the patchset.
>> - Kindly comment if I should try with any other benchmark or
>> workload to check the numbers.
>> - Also, kindly recommand any know stress test for CR
>>
>>  Makefile |   6 ++
>>  arch/powerpc/include/asm/exception-64s.h |  21 +-
>>  arch/powerpc/kernel/entry_64.S   | 106 
>> ++-
>>  arch/powerpc/kernel/exceptions-64s.S |   2 +-
>>  arch/powerpc/kernel/head_64.S|   8 +++
>>  5 files changed, 138 insertions(+), 5 deletions(-)
>>
>> diff --git a/Makefile b/Makefile
>> index 00d618b..2e271ad 100644
>> --- a/Makefile
>> +++ b/Makefile
>> @@ -706,6 +706,12 @@ endif
>>  
>>  KBUILD_CFLAGS   += $(call cc-option, -fno-var-tracking-assignments)
>>  
>> +ifdef   CONFIG_PPC64
>> +# We need this flag to force compiler not to use CR5, since
>> +# local_t type code is based on this.
>> +KBUILD_CFLAGS   += -ffixed-cr5
>> +endif
>> +
>>  ifdef CONFIG_DEBUG_INFO
>>  ifdef CONFIG_DEBUG_INFO_SPLIT
>>  KBUILD_CFLAGS   += $(call cc-option, -gsplit-dwarf, -g)
>> diff --git a/arch/powerpc/include/asm/exception-64s.h 
>> b/arch/powerpc/include/asm/exception-64s.h
>> index 77f52b2..c42919a 100644
>> --- a/arch/powerpc/include/asm/exception-64s.h
>> +++ b/arch/powerpc/include/asm/exception-64s.h
>> @@ -306,7 +306,26 @@ do_kvm_##n: 
>> \
>>  std r10,0(r1);  /* make stack chain pointer */ \
>>  std r0,GPR0(r1);/* save r0 in stackframe*/ \
>>  std r10,GPR1(r1);   /* save r1 in stackframe*/ \
>> -beq 4f; /* if from kernel mode  */ \
>> +BEGIN_FTR_SECTION; \
>> +lis r9,4096;/* Create a mask with HV and PR */ \
>> +rldicr  r9,r9,32,31;/* bits, AND with the MSR   */ \
>> +mr  r10,r9; /* to check for Hyp state   */ \
>> +ori r9,r9,16384;   \
>> +and r9,r12,r9; \
>> +cmpdcr3,r10,r9; 
>>\
>> +beq cr3,66f;/* Jump if we come from Hyp mode*/ \
>> +mtcrf   0x04,r10;   /* Clear CR5 if coming from usr */ \
> 
> I think you can do better than this, powerpc has a fantastic set
> of rotate and mask instructions. If I understand correctly your
> code you can replace it with the following:
> 
>   rldicl  r10,r12,4,63   /* Extract H

Re: [RFC PATCH 1/2]powerpc: foundation code to handle CR5 for local_t

[Madhavan Srinivasan]

On Tuesday 02 December 2014 07:34 AM, Scott Wood wrote:
> On Thu, 2014-11-27 at 17:48 +0530, Madhavan Srinivasan wrote:
>> - I really appreciate feedback on the patchset.
>> - Kindly comment if I should try with any other benchmark or
>> workload to check the numbers.
>> - Also, kindly recommand any know stress test for CR
>>
>>  Makefile |   6 ++
>>  arch/powerpc/include/asm/exception-64s.h |  21 +-
>>  arch/powerpc/kernel/entry_64.S   | 106 
>> ++-
>>  arch/powerpc/kernel/exceptions-64s.S |   2 +-
>>  arch/powerpc/kernel/head_64.S|   8 +++
>>  5 files changed, 138 insertions(+), 5 deletions(-)
> 
> Patch 2/2 enables this for all PPC64, not just book3s -- so please don't
> forget about the book3e exception paths (also MSR[GS] for KVM, but
> aren't most if not all the places you're checking for HV mode after KVM
> would have taken control?  Or am I missing something about how book3s
> KVM works?).
> 
> Or, if you don't want to do that, change patch 2/2 to be book3s only and
> ifdef-protect the changes to common exception code.
> 

Still learning the interrupt path and various configs. Was assuming
PPC64 is for server side. My bad. Will change the it to book3s and also
to common code.

>> @@ -224,8 +243,26 @@ syscall_exit:
>>  BEGIN_FTR_SECTION
>>  stdcx.  r0,0,r1 /* to clear the reservation */
>>  END_FTR_SECTION_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
>> +BEGIN_FTR_SECTION
>> +lis r4,4096
>> +rldicr  r4,r4,32,31
>> +mr  r6,r4
>> +ori r4,r4,16384
>> +and r4,r8,r4
>> +cmpdcr3,r6,r4
>> +beq cr3,65f
>> +mtcrr5
>> +FTR_SECTION_ELSE
>>  andi.   r6,r8,MSR_PR
>> -ld  r4,_LINK(r1)
>> +beq 65f
>> +mtcrr5
>> +nop
>> +nop
>> +nop
>> +nop
>> +nop
>> +ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)
>> +65: ld  r4,_LINK(r1)
>>  
>>  beq-1f
>>  ACCOUNT_CPU_USER_EXIT(r11, r12)
>> @@ -234,7 +271,11 @@ END_FTR_SECTION_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
>>  1:  ld  r2,GPR2(r1)
>>  ld  r1,GPR1(r1)
>>  mtlrr4
>> +#ifdef  CONFIG_PPC64
>> +mtcrf   0xFB,r5
>> +#else
>>  mtcrr5
>> +#endif
> 
> mtcrf with more than one CRn being updated is expensive on Freescale
> chips (and this isn't a book3s-only code path).  Why do you need to do
> it twice?  I don't see where either r5 or cr5 are messed with between
> the two places...
> 
Incase of returning to userspace, will be updating it twice. Which can
be avoid. Will redo this.

Regards
Maddy

> -Scott
> 
> 

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Re: [PATCH V2] powerpc/mm: don't do tlbie for updatepp request with NO HPTE fault

[Aneesh Kumar K.V]

Michael Ellerman  writes:

> On Tue, 2014-12-02 at 12:20 +0530, Aneesh Kumar K.V wrote:
>> upatepp get called for a nohpte fault, when we find from the linux
>> page table that the translation was hashed before. In that case
>> we are sure that there is no existing translation, hence we could
>> avoid doing tlbie.
>
> Same comments as last time.
>
> http://patchwork.ozlabs.org/patch/406219/

I replied to that review feedback right ? 

   > We are sure there *was* no existing translation. It's possible that since 
the
   > nohpte fault occurred the translation has been loaded into the tlb.
   >
   > Ben says that's OK, because updatepp is only ever relaxing permissions. But
   > please add some explanation of that to the changelog - it's not obvious.

I am not sure what we need to document. We look at pte bits to determine
the access bits in hpte, so even if we race and miss the tlbie, we
should have the right permissions. Or are you suggesting that we capture
in commit message that, even if we have parrallel fault, we should be
ok if we skip the tlbie ? Or do you want to capture the fact that
mprotect won't call updatepp, because that involve a
ptep_modify_prot_start which cause a hpte invalidate and not updatepp ?


   > The context preceeding this hunk includes this comment:
   >
   >/*
   > * We need to invalidate the TLB always because hpte_remove doesn't do
   > * a tlb invalidate. If a hash bucket gets full, we "evict" a more/less
   > * random entry from it. When we do that we don't invalidate the TLB
   > * (hpte_remove) because we assume the old translation is still
   > * technically "valid".
   > */
   >
   > Which seems out of sync with the code now.

The comment is still valid. What it explain is the part that, even if we
didn't find hash pte matching we still need to do a tlbie. We don't look
at the nohpte fault details in the comment.

-aneesh


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Re: [PATCH] powerpc: drop useless warning in eeh_init()

[Greg Kurz]

On Wed, 26 Nov 2014 09:28:47 +1100
Gavin Shan  wrote:
> On Tue, Nov 25, 2014 at 05:10:06PM +0100, Greg Kurz wrote:
> >This is what we get in dmesg when booting a pseries guest and
> >the hypervisor doesn't provide EEH support.
> >
> >[0.166655] EEH functionality not supported
> >[0.166778] eeh_init: Failed to call platform init function (-22)
> >
> >Since both powernv_eeh_init() and pseries_eeh_init() already complain when
> >hitting an error, it is not needed to print more (especially such an
> >uninformative message).
> >
> >Signed-off-by: Greg Kurz 
> 
> Acked-by: Gavin Shan 
> 
> Thanks,
> Gavin
> 

Ping ?

> >---
> > arch/powerpc/kernel/eeh.c |5 +
> > 1 file changed, 1 insertion(+), 4 deletions(-)
> >
> >diff --git a/arch/powerpc/kernel/eeh.c b/arch/powerpc/kernel/eeh.c
> >index 2248a19..7d62018 100644
> >--- a/arch/powerpc/kernel/eeh.c
> >+++ b/arch/powerpc/kernel/eeh.c
> >@@ -920,11 +920,8 @@ int eeh_init(void)
> > pr_warn("%s: Platform EEH operation not found\n",
> > __func__);
> > return -EEXIST;
> >-} else if ((ret = eeh_ops->init())) {
> >-pr_warn("%s: Failed to call platform init function (%d)\n",
> >-__func__, ret);
> >+} else if ((ret = eeh_ops->init()))
> > return ret;
> >-}
> > 
> > /* Initialize EEH event */
> > ret = eeh_event_init();
> >
> >___
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> >Linuxppc-dev@lists.ozlabs.org
> >https://lists.ozlabs.org/listinfo/linuxppc-dev
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[PATCH] powerpc: remove the smt-enabled kernel parameter

[Greg Kurz]

This parameter basically leaves unwanted cpus executing in firmware or
wherever they happen to be. This is a hack that shoudn't be used in a
production environment.

It also has an evil side effect on the split-core feature for powernv. The
code needs all the cpus to participate to the split mode update: it relies
on smp_send_reschedule() to get offline ones to do so. This doesn't work with
cpus that haven't come up... The consequence is a kernel hang at boot time
on powernv when smt-enabled is used to limit the number of threads.

This patch simply removes the smt-enabled kernel parameter for all platforms.
>From now on, SMT mode should be set by userspace.

I see there also is a ibm,smt-enabled property but I could not find any
piece of information about it. Since it does the very same thing as the
kernel parameter, it is tempting to drop it alike... This would possibly
allow more simplification like killing the cpu_bootable hook.

Please give advice anyone.

Signed-off-by: Greg Kurz 
---
 arch/powerpc/kernel/setup_64.c |   51 +---
 1 file changed, 12 insertions(+), 39 deletions(-)

diff --git a/arch/powerpc/kernel/setup_64.c b/arch/powerpc/kernel/setup_64.c
index 4f3cfe1..62c7602 100644
--- a/arch/powerpc/kernel/setup_64.c
+++ b/arch/powerpc/kernel/setup_64.c
@@ -131,8 +131,6 @@ static void setup_tlb_core_data(void)
 
 #ifdef CONFIG_SMP
 
-static char *smt_enabled_cmdline;
-
 /* Look for ibm,smt-enabled OF option */
 static void check_smt_enabled(void)
 {
@@ -142,46 +140,21 @@ static void check_smt_enabled(void)
/* Default to enabling all threads */
smt_enabled_at_boot = threads_per_core;
 
-   /* Allow the command line to overrule the OF option */
-   if (smt_enabled_cmdline) {
-   if (!strcmp(smt_enabled_cmdline, "on"))
-   smt_enabled_at_boot = threads_per_core;
-   else if (!strcmp(smt_enabled_cmdline, "off"))
-   smt_enabled_at_boot = 0;
-   else {
-   int smt;
-   int rc;
-
-   rc = kstrtoint(smt_enabled_cmdline, 10, &smt);
-   if (!rc)
-   smt_enabled_at_boot =
-   min(threads_per_core, smt);
-   }
-   } else {
-   dn = of_find_node_by_path("/options");
-   if (dn) {
-   smt_option = of_get_property(dn, "ibm,smt-enabled",
-NULL);
-
-   if (smt_option) {
-   if (!strcmp(smt_option, "on"))
-   smt_enabled_at_boot = threads_per_core;
-   else if (!strcmp(smt_option, "off"))
-   smt_enabled_at_boot = 0;
-   }
-
-   of_node_put(dn);
+   dn = of_find_node_by_path("/options");
+   if (dn) {
+   smt_option = of_get_property(dn, "ibm,smt-enabled",
+NULL);
+
+   if (smt_option) {
+   if (!strcmp(smt_option, "on"))
+   smt_enabled_at_boot = threads_per_core;
+   else if (!strcmp(smt_option, "off"))
+   smt_enabled_at_boot = 0;
}
-   }
-}
 
-/* Look for smt-enabled= cmdline option */
-static int __init early_smt_enabled(char *p)
-{
-   smt_enabled_cmdline = p;
-   return 0;
+   of_node_put(dn);
+   }
 }
-early_param("smt-enabled", early_smt_enabled);
 
 #else
 #define check_smt_enabled()

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[PATCH 2/2] pstore: add pstore support on powernv

[Hari Bathini]

This patch extends pstore, a generic interface to platform dependent
persistent storage, support for powernv  platform to capture certain
useful information, during dying moments. Such support is already in
place for  pseries platform.  This patch while adding pstore support
for  powernv platform,  moves common code for pseries and powernv to
arch/powerpc/kernel/nvram_64.c file.

Signed-off-by: Hari Bathini 
---
 arch/powerpc/include/asm/nvram.h|   50 ++
 arch/powerpc/include/asm/rtas.h |2 
 arch/powerpc/kernel/nvram_64.c  |  679 +++
 arch/powerpc/platforms/powernv/opal-nvram.c |   10 
 arch/powerpc/platforms/pseries/nvram.c  |  663 --
 5 files changed, 745 insertions(+), 659 deletions(-)

diff --git a/arch/powerpc/include/asm/nvram.h b/arch/powerpc/include/asm/nvram.h
index b0fe0fe..09a518b 100644
--- a/arch/powerpc/include/asm/nvram.h
+++ b/arch/powerpc/include/asm/nvram.h
@@ -9,12 +9,43 @@
 #ifndef _ASM_POWERPC_NVRAM_H
 #define _ASM_POWERPC_NVRAM_H
 
-
+#include 
 #include 
 #include 
 #include 
 
+/*
+ * Set oops header version to distinguish between old and new format header.
+ * lnx,oops-log partition max size is 4000, header version > 4000 will
+ * help in identifying new header.
+ */
+#define OOPS_HDR_VERSION 5000
+
+struct err_log_info {
+   __be32 error_type;
+   __be32 seq_num;
+};
+
+struct nvram_os_partition {
+   const char *name;
+   int req_size;   /* desired size, in bytes */
+   int min_size;   /* minimum acceptable size (0 means req_size) */
+   long size;  /* size of data portion (excluding err_log_info) */
+   long index; /* offset of data portion of partition */
+   bool os_partition; /* partition initialized by OS, not FW */
+};
+
+struct oops_log_info {
+   __be16 version;
+   __be16 report_length;
+   __be64 timestamp;
+} __attribute__((packed));
+
+extern struct nvram_os_partition oops_log_partition;
+
 #ifdef CONFIG_PPC_PSERIES
+extern struct nvram_os_partition rtas_log_partition;
+
 extern int nvram_write_error_log(char * buff, int length,
 unsigned int err_type, unsigned int 
err_seq);
 extern int nvram_read_error_log(char * buff, int length,
@@ -50,6 +81,23 @@ extern void  pmac_xpram_write(int xpaddr, u8 data);
 /* Synchronize NVRAM */
 extern voidnvram_sync(void);
 
+/* Initialize NVRAM OS partition */
+extern int __init nvram_init_os_partition(struct nvram_os_partition *part);
+
+/* Initialize NVRAM oops partition */
+extern void __init nvram_init_oops_partition(int rtas_partition_exists);
+
+/* Read a NVRAM partition */
+extern int nvram_read_partition(struct nvram_os_partition *part, char *buff,
+   int length, unsigned int *err_type,
+   unsigned int *error_log_cnt);
+
+/* Write to NVRAM OS partition */
+extern int nvram_write_os_partition(struct nvram_os_partition *part,
+   char *buff, int length,
+   unsigned int err_type,
+   unsigned int error_log_cnt);
+
 /* Determine NVRAM size */
 extern ssize_t nvram_get_size(void);
 
diff --git a/arch/powerpc/include/asm/rtas.h b/arch/powerpc/include/asm/rtas.h
index b390f55..a033fe9 100644
--- a/arch/powerpc/include/asm/rtas.h
+++ b/arch/powerpc/include/asm/rtas.h
@@ -343,6 +343,8 @@ extern int early_init_dt_scan_rtas(unsigned long node,
 extern void pSeries_log_error(char *buf, unsigned int err_type, int fatal);
 
 #ifdef CONFIG_PPC_PSERIES
+extern unsigned long last_rtas_event;
+extern int clobbering_unread_rtas_event(void);
 extern int pseries_devicetree_update(s32 scope);
 extern void post_mobility_fixup(void);
 #endif
diff --git a/arch/powerpc/kernel/nvram_64.c b/arch/powerpc/kernel/nvram_64.c
index 34f7c9b..8c439a3 100644
--- a/arch/powerpc/kernel/nvram_64.c
+++ b/arch/powerpc/kernel/nvram_64.c
@@ -26,6 +26,9 @@
 #include 
 #include 
 #include 
+#include 
+#include 
+#include 
 #include 
 #include 
 #include 
@@ -54,6 +57,682 @@ struct nvram_partition {
 
 static LIST_HEAD(nvram_partitions);
 
+#ifdef CONFIG_PPC_PSERIES
+struct nvram_os_partition rtas_log_partition = {
+   .name = "ibm,rtas-log",
+   .req_size = 2079,
+   .min_size = 1055,
+   .index = -1,
+   .os_partition = true
+};
+#endif
+
+struct nvram_os_partition oops_log_partition = {
+   .name = "lnx,oops-log",
+   .req_size = 4000,
+   .min_size = 2000,
+   .index = -1,
+   .os_partition = true
+};
+
+static const char *nvram_os_partitions[] = {
+#ifdef CONFIG_PPC_PSERIES
+   "ibm,rtas-log",
+#endif
+   "lnx,oops-log",
+   NULL
+};
+
+static void oops_to_nvram(struct kmsg_dumper *dumper,
+ enum kmsg_dump_reason reason);
+
+static struct kmsg_dumper nvram_kmsg_dumper = {
+   .dump = oops_to_nvram
+};
+
+/*
+ * For capturing and compressing an oops or

[PATCH 1/2] pstore: Add pstore type id for firmware partition

[Hari Bathini]

This patch adds a pstore type id to be used for opal specific
nvram partitions.

Signed-off-by: Hari Bathini 
---
 fs/pstore/inode.c  |3 +++
 include/linux/pstore.h |1 +
 2 files changed, 4 insertions(+)

diff --git a/fs/pstore/inode.c b/fs/pstore/inode.c
index fafb7a0..e83bb93 100644
--- a/fs/pstore/inode.c
+++ b/fs/pstore/inode.c
@@ -337,6 +337,9 @@ int pstore_mkfile(enum pstore_type_id type, char *psname, 
u64 id, int count,
case PSTORE_TYPE_PPC_COMMON:
sprintf(name, "powerpc-common-%s-%lld", psname, id);
break;
+   case PSTORE_TYPE_PPC_OPAL:
+   sprintf(name, "powerpc-opal-%s-%lld", psname, id);
+   break;
case PSTORE_TYPE_UNKNOWN:
sprintf(name, "unknown-%s-%lld", psname, id);
break;
diff --git a/include/linux/pstore.h b/include/linux/pstore.h
index ece0c6b..af44980 100644
--- a/include/linux/pstore.h
+++ b/include/linux/pstore.h
@@ -39,6 +39,7 @@ enum pstore_type_id {
PSTORE_TYPE_PPC_RTAS= 4,
PSTORE_TYPE_PPC_OF  = 5,
PSTORE_TYPE_PPC_COMMON  = 6,
+   PSTORE_TYPE_PPC_OPAL= 7,
PSTORE_TYPE_UNKNOWN = 255
 };
 

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[PATCH 0/2] powerpc/pstore: Add pstore support for nvram partitions

[Hari Bathini]

This patch series adds pstore support on powernv platform to
read different nvram partitions and write compressed data to
oops-log nvram partition. As pseries platform already has
pstore support, this series moves most of the common code
for pseries and powernv platforms to a common file. Tested
the patches successfully on both pseries and powernv
platforms.

---

Hari Bathini (2):
  pstore: Add pstore type id for firmware partition
  pstore: add pstore support on powernv


 arch/powerpc/include/asm/nvram.h|   50 ++
 arch/powerpc/include/asm/rtas.h |2 
 arch/powerpc/kernel/nvram_64.c  |  679 +++
 arch/powerpc/platforms/powernv/opal-nvram.c |   10 
 arch/powerpc/platforms/pseries/nvram.c  |  663 --
 fs/pstore/inode.c   |3 
 include/linux/pstore.h  |1 
 7 files changed, 749 insertions(+), 659 deletions(-)

--
- Hari

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[PATCH v4 6/6] powerpc/mpc85xx: Add FSL QorIQ DPAA QMan support to device tree(s)

[Emil Medve]

From: Kumar Gala 

Change-Id: If643fa5ba0a903aef8f5056a2c90ebecc995b760
Signed-off-by: Kumar Gala 
Signed-off-by: Geoff Thorpe 
Signed-off-by: Hai-Ying Wang 
Signed-off-by: Chunhe Lan 
Signed-off-by: Poonam Aggrwal 
[Emil Medve: Sync with the upstream binding]
Signed-off-by: Emil Medve 
---
 arch/powerpc/boot/dts/b4qds.dtsi|  16 ++
 arch/powerpc/boot/dts/fsl/b4860si-post.dtsi |  69 +++
 arch/powerpc/boot/dts/fsl/b4si-post.dtsi|  96 +
 arch/powerpc/boot/dts/fsl/p1023si-post.dtsi |  31 +++
 arch/powerpc/boot/dts/fsl/p2041si-post.dtsi |   3 +
 arch/powerpc/boot/dts/fsl/p3041si-post.dtsi |   3 +
 arch/powerpc/boot/dts/fsl/p4080si-post.dtsi |   3 +
 arch/powerpc/boot/dts/fsl/p5020si-post.dtsi |   3 +
 arch/powerpc/boot/dts/fsl/p5040si-post.dtsi |   3 +
 arch/powerpc/boot/dts/fsl/t1040si-post.dtsi |  68 ++
 arch/powerpc/boot/dts/fsl/t2081si-post.dtsi | 116 +++
 arch/powerpc/boot/dts/fsl/t4240si-post.dtsi | 308 
 arch/powerpc/boot/dts/kmcoge4.dts   |  16 ++
 arch/powerpc/boot/dts/oca4080.dts   |  16 ++
 arch/powerpc/boot/dts/p1023rdb.dts  |  16 ++
 arch/powerpc/boot/dts/p2041rdb.dts  |  16 ++
 arch/powerpc/boot/dts/p3041ds.dts   |  16 ++
 arch/powerpc/boot/dts/p4080ds.dts   |  16 ++
 arch/powerpc/boot/dts/p5020ds.dts   |  16 ++
 arch/powerpc/boot/dts/p5040ds.dts   |  16 ++
 arch/powerpc/boot/dts/t104xqds.dtsi |  16 ++
 arch/powerpc/boot/dts/t104xrdb.dtsi |  16 ++
 arch/powerpc/boot/dts/t208xqds.dtsi |  16 ++
 arch/powerpc/boot/dts/t208xrdb.dtsi |  16 ++
 arch/powerpc/boot/dts/t4240qds.dts  |  16 ++
 arch/powerpc/boot/dts/t4240rdb.dts  |  16 ++
 26 files changed, 943 insertions(+)

diff --git a/arch/powerpc/boot/dts/b4qds.dtsi b/arch/powerpc/boot/dts/b4qds.dtsi
index b30fa5d..542ec19 100644
--- a/arch/powerpc/boot/dts/b4qds.dtsi
+++ b/arch/powerpc/boot/dts/b4qds.dtsi
@@ -115,6 +115,18 @@
size = <0 0x100>;
alignment = <0 0x100>;
};
+   qman_fqd: qman-fqd {
+   compatible = "fsl,qman-fqd";
+   alloc-ranges = <0 0 0x 0x>;
+   size = <0 0x40>;
+   alignment = <0 0x40>;
+   };
+   qman_pfdr: qman-pfdr {
+   compatible = "fsl,qman-pfdr";
+   alloc-ranges = <0 0 0x 0x>;
+   size = <0 0x200>;
+   alignment = <0 0x200>;
+   };
};
 
dcsr: dcsr@f {
@@ -125,6 +137,10 @@
ranges = <0x0 0xf 0xf400 0x200>;
};
 
+   qportals: qman-portals@ff600 {
+   ranges = <0x0 0xf 0xf600 0x200>;
+   };
+
soc: soc@ffe00 {
ranges = <0x 0xf 0xfe00 0x100>;
reg = <0xf 0xfe00 0 0x1000>;
diff --git a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi 
b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
index 2dd61fa..38e297b 100644
--- a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
@@ -167,6 +167,75 @@
};
 };
 
+&qportals {
+   qportal14: qman-portal@38000 {
+   compatible = "fsl,qman-portal";
+   reg = <0x38000 0x4000>, <0x100e000 0x1000>;
+   interrupts = <132 0x2 0 0>;
+   fsl,qman-channel-id = <0xe>;
+   };
+   qportal15: qman-portal@3c000 {
+   compatible = "fsl,qman-portal";
+   reg = <0x3c000 0x4000>, <0x100f000 0x1000>;
+   interrupts = <134 0x2 0 0>;
+   fsl,qman-channel-id = <0xf>;
+   };
+   qportal16: qman-portal@4 {
+   compatible = "fsl,qman-portal";
+   reg = <0x4 0x4000>, <0x101 0x1000>;
+   interrupts = <136 0x2 0 0>;
+   fsl,qman-channel-id = <0x10>;
+   };
+   qportal17: qman-portal@44000 {
+   compatible = "fsl,qman-portal";
+   reg = <0x44000 0x4000>, <0x1011000 0x1000>;
+   interrupts = <138 0x2 0 0>;
+   fsl,qman-channel-id = <0x11>;
+   };
+   qportal18: qman-portal@48000 {
+   compatible = "fsl,qman-portal";
+   reg = <0x48000 0x4000>, <0x1012000 0x1000>;
+   interrupts = <140 0x2 0 0>;
+   fsl,qman-channel-id = <0x12>;
+   };
+   qportal19: qman-portal@4c000 {
+   compatible = "fsl,qman-portal";
+   reg = <0x4c000 0x4000>, <0x1013000 0x1000>;
+   interrupts = <142 0x2 0 0>;
+   fsl,qman-channel-id = <0x13>;
+   };
+   qportal20: qman-portal@5 {
+   compatible = "fsl,qman-portal";
+   reg = <0x5 0x4000>, <0x1014000 0x1000>;
+   interrupts = <144 0x2 0

[PATCH v4 5/6] powerpc/mpc85xx: Add FSL QorIQ DPAA BMan support to device tree(s)

[Emil Medve]

From: Kumar Gala 

Change-Id: If643fa5ba0a903aef8f5056a2c90ebecc995b760
Signed-off-by: Kumar Gala 
Signed-off-by: Geoff Thorpe 
Signed-off-by: Hai-Ying Wang 
Signed-off-by: Chunhe Lan 
Signed-off-by: Poonam Aggrwal 
[Emil Medve: Sync with the upstream binding]
Signed-off-by: Emil Medve 
---
 arch/powerpc/boot/dts/b4qds.dtsi|  19 +-
 arch/powerpc/boot/dts/fsl/b4860si-post.dtsi |  60 ++-
 arch/powerpc/boot/dts/fsl/b4si-post.dtsi|  84 -
 arch/powerpc/boot/dts/fsl/p1023si-post.dtsi |  30 +++-
 arch/powerpc/boot/dts/fsl/p2041si-post.dtsi |   6 +-
 arch/powerpc/boot/dts/fsl/p3041si-post.dtsi |   6 +-
 arch/powerpc/boot/dts/fsl/p4080si-post.dtsi |   6 +-
 arch/powerpc/boot/dts/fsl/p5020si-post.dtsi |   6 +-
 arch/powerpc/boot/dts/fsl/p5040si-post.dtsi |   6 +-
 arch/powerpc/boot/dts/fsl/t1040si-post.dtsi |  60 ++-
 arch/powerpc/boot/dts/fsl/t2081si-post.dtsi | 100 ++-
 arch/powerpc/boot/dts/fsl/t4240si-post.dtsi | 260 +++-
 arch/powerpc/boot/dts/kmcoge4.dts   |  17 ++
 arch/powerpc/boot/dts/oca4080.dts   |  17 ++
 arch/powerpc/boot/dts/p1023rdb.dts  |  20 ++-
 arch/powerpc/boot/dts/p2041rdb.dts  |  19 +-
 arch/powerpc/boot/dts/p3041ds.dts   |  19 +-
 arch/powerpc/boot/dts/p4080ds.dts   |  19 +-
 arch/powerpc/boot/dts/p5020ds.dts   |  19 +-
 arch/powerpc/boot/dts/p5040ds.dts   |  19 +-
 arch/powerpc/boot/dts/t104xqds.dtsi |  19 +-
 arch/powerpc/boot/dts/t104xrdb.dtsi |  16 ++
 arch/powerpc/boot/dts/t208xqds.dtsi |  19 +-
 arch/powerpc/boot/dts/t208xrdb.dtsi |  17 ++
 arch/powerpc/boot/dts/t4240qds.dts  |  19 +-
 arch/powerpc/boot/dts/t4240rdb.dts  |  17 ++
 26 files changed, 877 insertions(+), 22 deletions(-)

diff --git a/arch/powerpc/boot/dts/b4qds.dtsi b/arch/powerpc/boot/dts/b4qds.dtsi
index 6188583..b30fa5d 100644
--- a/arch/powerpc/boot/dts/b4qds.dtsi
+++ b/arch/powerpc/boot/dts/b4qds.dtsi
@@ -1,7 +1,7 @@
 /*
  * B4420DS Device Tree Source
  *
- * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2012 - 2014 Freescale Semiconductor, Inc.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -104,10 +104,27 @@
device_type = "memory";
};
 
+   reserved-memory {
+   #address-cells = <2>;
+   #size-cells = <2>;
+   ranges;
+
+   bman_fbpr: bman-fbpr {
+   compatible = "fsl,bman-fbpr";
+   alloc-ranges = <0 0 0x 0x>;
+   size = <0 0x100>;
+   alignment = <0 0x100>;
+   };
+   };
+
dcsr: dcsr@f {
ranges = <0x 0xf 0x 0x01052000>;
};
 
+   bportals: bman-portals@ff400 {
+   ranges = <0x0 0xf 0xf400 0x200>;
+   };
+
soc: soc@ffe00 {
ranges = <0x 0xf 0xfe00 0x100>;
reg = <0xf 0xfe00 0 0x1000>;
diff --git a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi 
b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
index f356ed2..2dd61fa 100644
--- a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
@@ -1,7 +1,7 @@
 /*
  * B4860 Silicon/SoC Device Tree Source (post include)
  *
- * Copyright 2012 Freescale Semiconductor Inc.
+ * Copyright 2012 - 2014 Freescale Semiconductor Inc.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -109,6 +109,64 @@
};
 };
 
+&bportals {
+   bman-portal@38000 {
+   compatible = "fsl,bman-portal";
+   reg = <0x38000 0x4000>, <0x100e000 0x1000>;
+   interrupts = <133 2 0 0>;
+   };
+   bman-portal@3c000 {
+   compatible = "fsl,bman-portal";
+   reg = <0x3c000 0x4000>, <0x100f000 0x1000>;
+   interrupts = <135 2 0 0>;
+   };
+   bman-portal@4 {
+   compatible = "fsl,bman-portal";
+   reg = <0x4 0x4000>, <0x101 0x1000>;
+   interrupts = <137 2 0 0>;
+   };
+   bman-portal@44000 {
+   compatible = "fsl,bman-portal";
+   reg = <0x44000 0x4000>, <0x1011000 0x1000>;
+   interrupts = <139 2 0 0>;
+   };
+   bman-portal@48000 {
+   compatible = "fsl,bman-portal";
+   reg = <0x48000 0x4000>, <0x1012000 0x1000>;
+   interrupts = <141 2 0 0>;
+   };
+   bman-portal@4c000 {
+   compatible = "fsl,bman-portal";
+   reg = <0x4c000 0x4000>, <0x1013000 0x1000>;
+   interrupts = <143 2 0 0>;
+   };
+   bman-portal@5 {
+   compatible = "fsl,bman-portal";
+ 

[PATCH v4 4/6] powerpc/mpc85xx: Create dts components for the FSL QorIQ DPAA QMan

[Emil Medve]

From: Kumar Gala 

Change-Id: I16e63db731e55a3d60d4e147573c1af8718082d3
Signed-off-by: Kumar Gala 
Signed-off-by: Geoff Thorpe 
Signed-off-by: Hai-Ying Wang 
[Emil Medve: Sync with the upstream binding]
Signed-off-by: Emil Medve 
---
 arch/powerpc/boot/dts/fsl/qoriq-qman1-portals.dtsi | 101 +
 arch/powerpc/boot/dts/fsl/qoriq-qman1.dtsi |  41 +
 arch/powerpc/boot/dts/fsl/qoriq-qman3.dtsi |  41 +
 3 files changed, 183 insertions(+)
 create mode 100644 arch/powerpc/boot/dts/fsl/qoriq-qman1-portals.dtsi
 create mode 100644 arch/powerpc/boot/dts/fsl/qoriq-qman1.dtsi
 create mode 100644 arch/powerpc/boot/dts/fsl/qoriq-qman3.dtsi

diff --git a/arch/powerpc/boot/dts/fsl/qoriq-qman1-portals.dtsi 
b/arch/powerpc/boot/dts/fsl/qoriq-qman1-portals.dtsi
new file mode 100644
index 000..05d51ac
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-qman1-portals.dtsi
@@ -0,0 +1,101 @@
+/*
+ * QorIQ QMan Portal device tree stub for 10 portals & 15 pool channels
+ *
+ * Copyright 2011 - 2014 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ *  notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ *  notice, this list of conditions and the following disclaimer in the
+ *  documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ *  names of its contributors may be used to endorse or promote products
+ *  derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+&qportals {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "simple-bus";
+
+   qportal0: qman-portal@0 {
+   compatible = "fsl,qman-portal";
+   reg = <0x0 0x4000>, <0x10 0x1000>;
+   interrupts = <104 2 0 0>;
+   fsl,qman-channel-id = <0x0>;
+   };
+   qportal1: qman-portal@4000 {
+   compatible = "fsl,qman-portal";
+   reg = <0x4000 0x4000>, <0x101000 0x1000>;
+   interrupts = <106 2 0 0>;
+   fsl,qman-channel-id = <1>;
+   };
+   qportal2: qman-portal@8000 {
+   compatible = "fsl,qman-portal";
+   reg = <0x8000 0x4000>, <0x102000 0x1000>;
+   interrupts = <108 2 0 0>;
+   fsl,qman-channel-id = <2>;
+   };
+   qportal3: qman-portal@c000 {
+   compatible = "fsl,qman-portal";
+   reg = <0xc000 0x4000>, <0x103000 0x1000>;
+   interrupts = <110 2 0 0>;
+   fsl,qman-channel-id = <3>;
+   };
+   qportal4: qman-portal@1 {
+   compatible = "fsl,qman-portal";
+   reg = <0x1 0x4000>, <0x104000 0x1000>;
+   interrupts = <112 2 0 0>;
+   fsl,qman-channel-id = <4>;
+   };
+   qportal5: qman-portal@14000 {
+   compatible = "fsl,qman-portal";
+   reg = <0x14000 0x4000>, <0x105000 0x1000>;
+   interrupts = <114 2 0 0>;
+   fsl,qman-channel-id = <5>;
+   };
+   qportal6: qman-portal@18000 {
+   compatible = "fsl,qman-portal";
+   reg = <0x18000 0x4000>, <0x106000 0x1000>;
+   interrupts = <116 2 0 0>;
+   fsl,qman-channel-id = <6>;
+   };
+
+   qportal7: qman-portal@1c000 {
+   compatible = "fsl,qman-portal";
+   reg = <0x1c000 0x4000>, <0x107000 0x1000>;
+   interrupts = <118 2 0 0>;
+   fsl,qman-channel-id = <7>;
+   };
+   qportal8: qman-portal@2 {
+   compatible = "fsl,qman-portal";
+   reg = <0x2 0x4000>

[PATCH v4 3/6] powerpc/mpc85xx: Create dts components for the FSL QorIQ DPAA BMan

[Emil Medve]

From: Kumar Gala 

Change-Id: I16e63db731e55a3d60d4e147573c1af8718082d3
Signed-off-by: Kumar Gala 
Signed-off-by: Geoff Thorpe 
Signed-off-by: Hai-Ying Wang 
[Emil Medve: Sync with the upstream binding]
Signed-off-by: Emil Medve 
---
 arch/powerpc/boot/dts/fsl/qoriq-bman1-portals.dtsi | 90 ++
 arch/powerpc/boot/dts/fsl/qoriq-bman1.dtsi | 41 ++
 2 files changed, 131 insertions(+)
 create mode 100644 arch/powerpc/boot/dts/fsl/qoriq-bman1-portals.dtsi
 create mode 100644 arch/powerpc/boot/dts/fsl/qoriq-bman1.dtsi

diff --git a/arch/powerpc/boot/dts/fsl/qoriq-bman1-portals.dtsi 
b/arch/powerpc/boot/dts/fsl/qoriq-bman1-portals.dtsi
new file mode 100644
index 000..5022432
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-bman1-portals.dtsi
@@ -0,0 +1,90 @@
+/*
+ * QorIQ BMan Portal device tree stub for 10 portals
+ *
+ * Copyright 2011 - 2014 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ *  notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ *  notice, this list of conditions and the following disclaimer in the
+ *  documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ *  names of its contributors may be used to endorse or promote products
+ *  derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+&bportals {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "simple-bus";
+
+   bman-portal@0 {
+   compatible = "fsl,bman-portal";
+   reg = <0x0 0x4000>, <0x10 0x1000>;
+   interrupts = <105 2 0 0>;
+   };
+   bman-portal@4000 {
+   compatible = "fsl,bman-portal";
+   reg = <0x4000 0x4000>, <0x101000 0x1000>;
+   interrupts = <107 2 0 0>;
+   };
+   bman-portal@8000 {
+   compatible = "fsl,bman-portal";
+   reg = <0x8000 0x4000>, <0x102000 0x1000>;
+   interrupts = <109 2 0 0>;
+   };
+   bman-portal@c000 {
+   compatible = "fsl,bman-portal";
+   reg = <0xc000 0x4000>, <0x103000 0x1000>;
+   interrupts = <111 2 0 0>;
+   };
+   bman-portal@1 {
+   compatible = "fsl,bman-portal";
+   reg = <0x1 0x4000>, <0x104000 0x1000>;
+   interrupts = <113 2 0 0>;
+   };
+   bman-portal@14000 {
+   compatible = "fsl,bman-portal";
+   reg = <0x14000 0x4000>, <0x105000 0x1000>;
+   interrupts = <115 2 0 0>;
+   };
+   bman-portal@18000 {
+   compatible = "fsl,bman-portal";
+   reg = <0x18000 0x4000>, <0x106000 0x1000>;
+   interrupts = <117 2 0 0>;
+   };
+   bman-portal@1c000 {
+   compatible = "fsl,bman-portal";
+   reg = <0x1c000 0x4000>, <0x107000 0x1000>;
+   interrupts = <119 2 0 0>;
+   };
+   bman-portal@2 {
+   compatible = "fsl,bman-portal";
+   reg = <0x2 0x4000>, <0x108000 0x1000>;
+   interrupts = <121 2 0 0>;
+   };
+   bman-portal@24000 {
+   compatible = "fsl,bman-portal";
+   reg = <0x24000 0x4000>, <0x109000 0x1000>;
+   interrupts = <123 2 0 0>;
+   };
+};
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-bman1.dtsi 
b/arch/powerpc/boot/dts/fsl/qoriq-bman1.dtsi
new file mode 100644
index 000..3b5e350
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-bman1.dtsi
@@ -0,0 +1,41 @@
+/*
+ * QorIQ BMan device tree stub [ controller @ offset 0x31a000 ]
+ *
+ * Copyright 2011 - 201

[PATCH v4 1/6] dt/bindings: bman: Add phandle to the portals

[Emil Medve]

This supports SoC(s) with multiple BMan instances

Signed-off-by: Emil Medve 
---
 Documentation/devicetree/bindings/soc/fsl/bman.txt | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/Documentation/devicetree/bindings/soc/fsl/bman.txt 
b/Documentation/devicetree/bindings/soc/fsl/bman.txt
index 9f80bf8..4fc4a6e 100644
--- a/Documentation/devicetree/bindings/soc/fsl/bman.txt
+++ b/Documentation/devicetree/bindings/soc/fsl/bman.txt
@@ -36,6 +36,11 @@ are located at offsets 0xbf8 and 0xbfc
Value type: 
Definition: Standard property. The error interrupt
 
+- fsl,bman-portals
+   Usage:  Required
+   Value type: 
+   Definition: Phandle to this BMan's instance portals
+
 - fsl,liodn
Usage:  See pamu.txt
Value type: 
@@ -104,6 +109,10 @@ The example below shows a BMan FBPR dynamic allocation 
memory node
 
 The example below shows a (P4080) BMan CCSR-space node
 
+   bportals: bman-portals@ff400 {
+   ...
+   };
+
crypto@30 {
...
fsl,bman = <&bman, 2>;
@@ -115,6 +124,7 @@ The example below shows a (P4080) BMan CCSR-space node
reg = <0x31a000 0x1000>;
interrupts = <16 2 1 2>;
fsl,liodn = <0x17>;
+   fsl,bman-portals = <&bportals>;
memory-region = <&bman_fbpr>;
};
 
-- 
2.2.0

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[PATCH v4 0/6] powerpc/mpc85xx: Add FSL QorIQ DPAA B/QMan support to device tree(s)

[Emil Medve]

v4: Add binding for the portals phandle
Fix portals phandle

v3: Remove no-map
Adjust alloc-ranges for the 32-/36-bit SoC(s)

v2: Remove some reserved-memory properties
Split the patchset per IP block
Refined patch assignment

Emil Medve (2):
  dt/bindings: bman: Add phandle to the portals
  dt/bindings: qman: Add phandle to the portals

Kumar Gala (4):
  powerpc/mpc85xx: Create dts components for the FSL QorIQ DPAA BMan
  powerpc/mpc85xx: Create dts components for the FSL QorIQ DPAA QMan
  powerpc/mpc85xx: Add FSL QorIQ DPAA BMan support to device tree(s)
  powerpc/mpc85xx: Add FSL QorIQ DPAA QMan support to device tree(s)

 Documentation/devicetree/bindings/soc/fsl/bman.txt |  10 +
 Documentation/devicetree/bindings/soc/fsl/qman.txt |  10 +
 arch/powerpc/boot/dts/b4qds.dtsi   |  35 +-
 arch/powerpc/boot/dts/fsl/b4860si-post.dtsi| 129 -
 arch/powerpc/boot/dts/fsl/b4si-post.dtsi   | 180 ++-
 arch/powerpc/boot/dts/fsl/p1023si-post.dtsi|  61 ++-
 arch/powerpc/boot/dts/fsl/p2041si-post.dtsi|   9 +-
 arch/powerpc/boot/dts/fsl/p3041si-post.dtsi|   9 +-
 arch/powerpc/boot/dts/fsl/p4080si-post.dtsi|   9 +-
 arch/powerpc/boot/dts/fsl/p5020si-post.dtsi|   9 +-
 arch/powerpc/boot/dts/fsl/p5040si-post.dtsi|   9 +-
 arch/powerpc/boot/dts/fsl/qoriq-bman1-portals.dtsi |  90 
 arch/powerpc/boot/dts/fsl/qoriq-bman1.dtsi |  41 ++
 arch/powerpc/boot/dts/fsl/qoriq-qman1-portals.dtsi | 101 
 arch/powerpc/boot/dts/fsl/qoriq-qman1.dtsi |  41 ++
 arch/powerpc/boot/dts/fsl/qoriq-qman3.dtsi |  41 ++
 arch/powerpc/boot/dts/fsl/t1040si-post.dtsi| 128 -
 arch/powerpc/boot/dts/fsl/t2081si-post.dtsi| 216 +++-
 arch/powerpc/boot/dts/fsl/t4240si-post.dtsi| 568 -
 arch/powerpc/boot/dts/kmcoge4.dts  |  33 ++
 arch/powerpc/boot/dts/oca4080.dts  |  33 ++
 arch/powerpc/boot/dts/p1023rdb.dts |  36 +-
 arch/powerpc/boot/dts/p2041rdb.dts |  35 +-
 arch/powerpc/boot/dts/p3041ds.dts  |  35 +-
 arch/powerpc/boot/dts/p4080ds.dts  |  35 +-
 arch/powerpc/boot/dts/p5020ds.dts  |  35 +-
 arch/powerpc/boot/dts/p5040ds.dts  |  35 +-
 arch/powerpc/boot/dts/t104xqds.dtsi|  35 +-
 arch/powerpc/boot/dts/t104xrdb.dtsi|  32 ++
 arch/powerpc/boot/dts/t208xqds.dtsi|  35 +-
 arch/powerpc/boot/dts/t208xrdb.dtsi|  33 ++
 arch/powerpc/boot/dts/t4240qds.dts |  35 +-
 arch/powerpc/boot/dts/t4240rdb.dts |  33 ++
 33 files changed, 2154 insertions(+), 22 deletions(-)
 create mode 100644 arch/powerpc/boot/dts/fsl/qoriq-bman1-portals.dtsi
 create mode 100644 arch/powerpc/boot/dts/fsl/qoriq-bman1.dtsi
 create mode 100644 arch/powerpc/boot/dts/fsl/qoriq-qman1-portals.dtsi
 create mode 100644 arch/powerpc/boot/dts/fsl/qoriq-qman1.dtsi
 create mode 100644 arch/powerpc/boot/dts/fsl/qoriq-qman3.dtsi

-- 
2.2.0
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[PATCH v4 2/6] dt/bindings: qman: Add phandle to the portals

[Emil Medve]

This supports SoC(s) with multiple QMan instances

Signed-off-by: Emil Medve 
---
 Documentation/devicetree/bindings/soc/fsl/qman.txt | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/Documentation/devicetree/bindings/soc/fsl/qman.txt 
b/Documentation/devicetree/bindings/soc/fsl/qman.txt
index 063e3a0..85d6059 100644
--- a/Documentation/devicetree/bindings/soc/fsl/qman.txt
+++ b/Documentation/devicetree/bindings/soc/fsl/qman.txt
@@ -38,6 +38,11 @@ are located at offsets 0xbf8 and 0xbfc
Value type: 
Definition: Standard property. The error interrupt
 
+- fsl,qman-portals
+   Usage:  Required
+   Value type: 
+   Definition: Phandle to this QMan's instance portals
+
 - fsl,liodn
Usage:  See pamu.txt
Value type: 
@@ -127,6 +132,10 @@ The example below shows a QMan FQD and a PFDR dynamic 
allocation memory nodes
 
 The example below shows a (P4080) QMan CCSR-space node
 
+   qportals: qman-portals@ff420 {
+   ...
+   };
+
clockgen: global-utilities@e1000 {
...
sysclk: sysclk {
@@ -154,6 +163,7 @@ The example below shows a (P4080) QMan CCSR-space node
reg = <0x318000 0x1000>;
interrupts = <16 2 1 3>
fsl,liodn = <0x16>;
+   fsl,qman-portals = <&qportals>;
memory-region = <&qman_fqd &qman_pfdr>;
clocks = <&platform_pll 1>;
};
-- 
2.2.0

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[PATCH v3 3/3] clk: ppc-corenet: fix section mismatch warning

[Kevin Hao]

In order to fix the following section mismatch warning:
  WARNING: drivers/clk/built-in.o(.data+0xe4): Section mismatch in reference 
from the variable ppc_corenet_clk_driver to the function 
.init.text:ppc_corenet_clk_probe()
  The variable ppc_corenet_clk_driver references
  the function __init ppc_corenet_clk_probe()
  If the reference is valid then annotate the
  variable with __init* or __refdata (see linux/init.h) or name the variable:
  *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console

  WARNING: drivers/clk/built-in.o(.data+0x10c): Section mismatch in reference 
from the variable ppc_corenet_clk_driver to the variable 
.init.rodata:ppc_clk_ids
  The variable ppc_corenet_clk_driver references
  the variable __initconst ppc_clk_ids
  If the reference is valid then annotate the
  variable with __init* or __refdata (see linux/init.h) or name the variable:
  *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console

We can't just add the __init annotation to ppc_corenet_clk_driver or
remove the __init from ppc_corenet_clk_probe() and ppc_clk_ids.
So choose to use CLK_OF_DECLARE to scan and init the clock devices.

Signed-off-by: Kevin Hao 
Acked-by: Scott Wood 
Acked-by: Michael Turquette 
---
v3: Rebase on next and add ack.

v2: Avoid to invoke of_clk_init() in a board specific file.

 drivers/clk/clk-ppc-corenet.c | 43 ++-
 1 file changed, 6 insertions(+), 37 deletions(-)

diff --git a/drivers/clk/clk-ppc-corenet.c b/drivers/clk/clk-ppc-corenet.c
index 0a47d6f49cd6..57a2de47d2cb 100644
--- a/drivers/clk/clk-ppc-corenet.c
+++ b/drivers/clk/clk-ppc-corenet.c
@@ -267,40 +267,9 @@ static void __init sysclk_init(struct device_node *node)
if (!IS_ERR(clk))
of_clk_add_provider(np, of_clk_src_simple_get, clk);
 }
-
-static const struct of_device_id clk_match[] __initconst = {
-   { .compatible = "fsl,qoriq-sysclk-1.0", .data = sysclk_init, },
-   { .compatible = "fsl,qoriq-sysclk-2.0", .data = sysclk_init, },
-   { .compatible = "fsl,qoriq-core-pll-1.0", .data = core_pll_init, },
-   { .compatible = "fsl,qoriq-core-pll-2.0", .data = core_pll_init, },
-   { .compatible = "fsl,qoriq-core-mux-1.0", .data = core_mux_init, },
-   { .compatible = "fsl,qoriq-core-mux-2.0", .data = core_mux_init, },
-   {}
-};
-
-static int __init ppc_corenet_clk_probe(struct platform_device *pdev)
-{
-   of_clk_init(clk_match);
-
-   return 0;
-}
-
-static const struct of_device_id ppc_clk_ids[] __initconst = {
-   { .compatible = "fsl,qoriq-clockgen-1.0", },
-   { .compatible = "fsl,qoriq-clockgen-2.0", },
-   {}
-};
-
-static struct platform_driver ppc_corenet_clk_driver = {
-   .driver = {
-   .name = "ppc_corenet_clock",
-   .of_match_table = ppc_clk_ids,
-   },
-   .probe = ppc_corenet_clk_probe,
-};
-
-static int __init ppc_corenet_clk_init(void)
-{
-   return platform_driver_register(&ppc_corenet_clk_driver);
-}
-subsys_initcall(ppc_corenet_clk_init);
+CLK_OF_DECLARE(qoriq_sysclk_1, "fsl,qoriq-sysclk-1.0", sysclk_init);
+CLK_OF_DECLARE(qoriq_sysclk_2, "fsl,qoriq-sysclk-2.0", sysclk_init);
+CLK_OF_DECLARE(qoriq_core_pll_1, "fsl,qoriq-core-pll-1.0", core_pll_init);
+CLK_OF_DECLARE(qoriq_core_pll_2, "fsl,qoriq-core-pll-2.0", core_pll_init);
+CLK_OF_DECLARE(qoriq_core_mux_1, "fsl,qoriq-core-mux-1.0", core_mux_init);
+CLK_OF_DECLARE(qoriq_core_mux_2, "fsl,qoriq-core-mux-2.0", core_mux_init);
-- 
1.9.3

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[PATCH v3 2/3] powerpc: call of_clk_init() from time_init()

[Kevin Hao]

So the boards which has COMMON_CLK enabled don't have to
invoke this in its board specific file.

Signed-off-by: Kevin Hao 
Acked-by: Scott Wood 
Acked-by: Michael Turquette 
---
v3: Add ack.

v2: A new patch in v2.

 arch/powerpc/kernel/time.c|  5 +
 arch/powerpc/platforms/512x/clock-commonclk.c | 11 +--
 2 files changed, 10 insertions(+), 6 deletions(-)

diff --git a/arch/powerpc/kernel/time.c b/arch/powerpc/kernel/time.c
index fa7c4f12104f..df9fa05b5fd3 100644
--- a/arch/powerpc/kernel/time.c
+++ b/arch/powerpc/kernel/time.c
@@ -54,6 +54,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 #include 
@@ -943,6 +944,10 @@ void __init time_init(void)
 
init_decrementer_clockevent();
tick_setup_hrtimer_broadcast();
+
+#ifdef CONFIG_COMMON_CLK
+   of_clk_init(NULL);
+#endif
 }
 
 
diff --git a/arch/powerpc/platforms/512x/clock-commonclk.c 
b/arch/powerpc/platforms/512x/clock-commonclk.c
index 6eb614a271fb..f691bcabd710 100644
--- a/arch/powerpc/platforms/512x/clock-commonclk.c
+++ b/arch/powerpc/platforms/512x/clock-commonclk.c
@@ -1168,6 +1168,11 @@ static void mpc5121_clk_provide_backwards_compat(void)
}
 }
 
+/*
+ * The "fixed-clock" nodes (which includes the oscillator node if the board's
+ * DT provides one) has already been scanned by the of_clk_init() in
+ * time_init().
+ */
 int __init mpc5121_clk_init(void)
 {
struct device_node *clk_np;
@@ -1187,12 +1192,6 @@ int __init mpc5121_clk_init(void)
mpc512x_clk_preset_data();
 
/*
-* have the device tree scanned for "fixed-clock" nodes (which
-* includes the oscillator node if the board's DT provides one)
-*/
-   of_clk_init(NULL);
-
-   /*
 * add a dummy clock for those situations where a clock spec is
 * required yet no real clock is involved
 */
-- 
1.9.3

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[PATCH v3 1/3] Revert "clk: ppc-corenet: Fix Section mismatch warning"

[Kevin Hao]

This reverts commit da788acb28386aa896224e784954bb73c99ff26c.

That commit tried to fix the section mismatch warning by moving the
ppc_corenet_clk_driver struct to init section. This is definitely wrong
because the kernel would free the memories occupied by this struct
after boot while this driver is still registered in the driver core.
The kernel would panic when accessing this driver struct.

Cc: sta...@vger.kernel.org # 3.17
Signed-off-by: Kevin Hao 
Acked-by: Scott Wood 
Acked-by: Michael Turquette 
---
v3: Cc stable and add ack.

v2: A new patch in v2.

 drivers/clk/clk-ppc-corenet.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/clk-ppc-corenet.c b/drivers/clk/clk-ppc-corenet.c
index b6e6c85507a5..0a47d6f49cd6 100644
--- a/drivers/clk/clk-ppc-corenet.c
+++ b/drivers/clk/clk-ppc-corenet.c
@@ -291,7 +291,7 @@ static const struct of_device_id ppc_clk_ids[] __initconst 
= {
{}
 };
 
-static struct platform_driver ppc_corenet_clk_driver __initdata = {
+static struct platform_driver ppc_corenet_clk_driver = {
.driver = {
.name = "ppc_corenet_clock",
.of_match_table = ppc_clk_ids,
-- 
1.9.3

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[PATCH v3 0/3] fix a kernel panic on fsl corenet board when CONFIG_CLK_PPC_CORENET is enabled

[Kevin Hao]

I have done a boot test on p5040ds and mpc5121eads board.

v3:
  - Rebase on next.
  - CC stable for patch 1.
  - Add Scott and Michael's ack.

v2:
 - Revert the commit da788acb2838 first.
 - Invoke of_clk_init() from a common place.

v1
This tries to fix a kernel panic introduced by commit da788acb2838
("clk: ppc-corenet: Fix Section mismatch warning").


Kevin Hao (3):
  Revert "clk: ppc-corenet: Fix Section mismatch warning"
  powerpc: call of_clk_init() from time_init()
  clk: ppc-corenet: fix section mismatch warning

 arch/powerpc/kernel/time.c|  5 
 arch/powerpc/platforms/512x/clock-commonclk.c | 11 ---
 drivers/clk/clk-ppc-corenet.c | 43 ---
 3 files changed, 16 insertions(+), 43 deletions(-)

-- 
1.9.3

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