Re: [PATCH 1/3] powerpc: Don't use local named register variable in current_thread_info

2014-12-16 Thread Anton Blanchard 
Hi Alex,

> Git bisect managed to point me to this commit as the offender for
> OOPSes on e5500 and e6500 (and maybe the G4 as well, not sure).
> 
> Doing a git revert of this commit on top of linus/master makes things
> work fine for me again.

Ouch, sorry for that, I'll work to reproduce. What gcc version are you
using?

Anton
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RE: PROBLEM: USB isochronous urb leak on EHCI driver

2014-12-16 Thread Peter Chen 
 
> 
> My configuration:
> -
> 
> Host: Freescale i.MX512 with ARM Cortex A8 (USB 2.0 host controller) Linux
> kernel: 2.6.31, using EHCI USB driver
> Hub: 4-PORT USB 1.1 HUB (Texas Instruments PN: tusb2046b)
> Devices: 4 USB 1.1 audio codecs (Texas Instruments PN: pcm2901)
> 
> Note: each codec is being used in R/W access, so with 4 codecs, I have
> 4 playback and 4 capture streams.
> 
> My problem:
> ---
> 
> I have usb urb leaks when connecting more than 1 codec to the USB 1.1 Hub.
> (the result is that some of the audio data is not transferred, part of the 
> sound is
> simply missing) No problem when using only 1 of the 4 codecs connected to the
> hub; When I connect a second codec, the sound quality starts to degrade. With
> 3 codecs, we just cannot recognize a speach.
> 
> Tests and observations:
> ---
> 
> Since I have 3 usb ports available on the i.MX512, I tried to connect
> 3 codecs directly on USB ports: the sound is perfect on each of the three 
> ports.
> 
> I bought a consumer USB 2.0 Hub: no problem when using 3 codecs connected
> to that Hub, however, the audio will completly stop on all channels when
> connecting the 4th codec.
> 
> I checked the communication between the Hub (USB 1.1) and the Host
> controller (USB 2.0) with a scope and concluded that the communication speed
> is 1.5 MBytes/s has expected (so the communication is downgraded to USB 1.1,
> since codecs and hub are USB
> 1.1 devices).
> 
> Also, I know that there is physically enough bandwidth to transfer the data 
> for
> two reasons:
> 1) I have an older CPU with a USB 1.1 host controller (using the OHCI driver),
> using the same hub and the same codecs: works like a champ, using less than
> 50% of the available bandwidth (observed with a
> scope)
> 2) 1 audio stream is 32khz-mono, 16 bits = 64 kB/s,
> 4 codecs = 8 streams(R/W) x 64 kB/s = 512 kB/s (out of 1.5MB/s)
> 
> I noticed that my sound problem starts happening with only 2 codecs
> (4 streams, 256 kB/s). I first thought that it was a bandwidth limitation, so 
> I
> decided to connect only 1 codec using more bandwidth.
> I configured it to 48khz-stereo (16-bits), using 384 kB/s for both read and 
> write
> streams: no problem. With that configuration, the scope shows about 30% of
> total bandwidth usage (300us used out of 1ms periods). Then, I added a second
> codec (48khz-stereo-16bits): very strange, now the total bandwidth usage felt
> down to about 200us, which seems to keep the same, whatever the number of
> codec I add (I also tried 3 and 4...). So it looks like the scheduler is not 
> able to
> properly allocate Isochronous time slots when more than one device is
> connected to the hub. However, without the hub, it works perfectly.
> 

I am wonder if it is similar problem I met when using multiple interrupt 
transfers,
when you find you lose the data, try to run 'top' to show cpu utilization, if 
it is
close to 100%, it means the ehci can't queue request in time, so the host can't 
send IN
token in time.

Using a USB bus analyzer can also verify it.

Peter

> Another interresting fact is that at application level, the Read and Write
> operations are returning the good amount of bytes read/written.
> This is not the case at kernel level: I noticed that function "usb_submit_urb"
> (from /drivers/usb/core/urb.c) will only tranfer part of the "urbs" when the
> sound is degraded. I tried to figure out where the leak comes from without
> success. Also, there are no error messages from kernel so everything appears
> to work well, excepted that part of the sound is missing!
> 
> I can't change my hardware (this is in the hand of customers), so the only
> possible solution for me is to correct the software.
> 
> I tried to change my ehci driver with the one from kernel 2.6.39.4 but did not
> work, same problem.
> 
> Question:
> -
> 
> Before attempting to upgrade to an earlier kernel driver (this is a fairly big
> amount of work), I would really like to know if this problem would still be 
> in the
> 3.x kernels. Has anyone seen that issue in 3.x kernels?
> 
> I am pretty new to USB driver debugging, so any ideas of where/how to find
> solutions will be appreciated. Thank you very much in advance for the support.
> Also don't hesitate to redirect me if I'm not at the right place to ask these
> questions. I can also provide some code if someone need it to help.
> 
> Attached is a dump of my "dmesg" after startup.
> 
> Michael Tessier
> 
> 
> 
> 
> 
> 

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Re: [PATCH 1/3] powerpc: Don't use local named register variable in current_thread_info

2014-12-16 Thread Alexander Graf 
On 31.10.14 04:47, Anton Blanchard wrote:
> LLVM doesn't support local named register variables and is unlikely
> to. current_thread_info is using one, fix it by moving it out and
> calling it __current_r1().
> 
> I gave it a bit of an obscure name because we don't want anyone else
> using it - they should use current_stack_pointer(). This specific
> case is performance critical and we can't afford to call a function
> to get it. Furthermore it isn't important to know exactly where in
> the stack we are since we mask the lower bits.
> 
> Signed-off-by: Anton Blanchard 

Git bisect managed to point me to this commit as the offender for OOPSes
on e5500 and e6500 (and maybe the G4 as well, not sure).

Doing a git revert of this commit on top of linus/master makes things
work fine for me again.


Alex

Oops: Kernel access of bad area, sig: 11 [#2]
SMP NR_CPUS=16 CoreNet Generic
Modules linked in:
CPU: 1 PID: 339 Comm: kworker/1:1 Tainted: G  D
3.18.0-09423-g988adfd #1
Workqueue: rpciod .rpc_async_schedule
task: c001f6397500 ti: c001f6638000 task.ti: c001f6638000
NIP: c04817a4 LR: c04817a4 CTR: 
REGS: c001f663b0e0 TRAP: 0300   Tainted: G  D
(3.18.0-09423-g988adfd)
MSR: 80029000   CR: 24ad2e42  XER: 
DEAR: 202031303438355f ESR:  SOFTE: 1
GPR00: c04817a4 c001f663b360 c0988028 7f24333d
GPR04: 5ff5738c1f2ebfb1   08f8
GPR08: c0480ae8 2020313034383537 36204b4220617320 6469726563740a31
GPR12: 3937302d30312d30 cfff8780 c007f988 c001f64c1600
GPR16:    05dc
GPR20: c09b8028 c0007e034200 0548 c000
GPR24: c001f663b4b0 b225831e  0080
GPR28: 0548 08f8 0548 0094
NIP [c04817a4] .__skb_checksum+0x194/0x378
LR [c04817a4] .__skb_checksum+0x194/0x378
Call Trace:
[c001f663b360] [c04817a4] .__skb_checksum+0x194/0x378
(unreliable)
[c001f663b440] [c04819b4] .skb_checksum+0x2c/0x3c
[c001f663b4c0] [c04fd0a8] .udp4_hwcsum+0xa8/0x16c
[c001f663b560] [c04fd440] .udp_send_skb+0x2d4/0x370
[c001f663b600] [c04fd51c] .udp_push_pending_frames+0x40/0x94
[c001f663b680] [c04fec08] .udp_sendpage+0x150/0x1b4
[c001f663b770] [c050ae54] .inet_sendpage+0xa0/0x120
[c001f663b810] [c059c8cc] .xs_sendpages+0x2d0/0x30c
[c001f663b8d0] [c059cae4] .xs_udp_send_request+0x58/0x120
[c001f663b970] [c0598f04] .xprt_transmit+0x80/0x36c
[c001f663ba20] [c05942d8] .call_transmit+0x19c/0x254
[c001f663bab0] [c059ff64] .__rpc_execute+0xbc/0x3c0
[c001f663bb90] [c00797f8] .process_one_work+0x1c0/0x474
[c001f663bc40] [c007a518] .worker_thread+0x17c/0x54c
[c001f663bd30] [c007fa8c] .kthread+0x104/0x124
[c001f663be30] [c884] .ret_from_kernel_thread+0x58/0xd4
Instruction dump:
7d1f3a14 7c6a1850 e958 7fbd4050 786334e4 e90a 7c63ba14 f8490028
7c63ea14 7d0903a6 e84a0008 4e800421  7c641b78 78270464 e9580008
---[ end trace 51b7414695b0cafe ]---

note: kworker/1:1[339] exited with preempt_count 1
Unable to handle kernel paging request for data at address
0xffd8


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Re: [PATCH 13/18] powerpc/uaccess: fix sparse errors

2014-12-16 Thread Benjamin Herrenschmidt 
On Tue, 2014-12-16 at 18:47 +0200, Michael S. Tsirkin wrote:
> On Sun, Dec 14, 2014 at 06:52:51PM +0200, Michael S. Tsirkin wrote:
> > virtio wants to read bitwise types from userspace using get_user.  At the
> > moment this triggers sparse errors, since the value is passed through an
> > integer.
> > 
> > Fix that up using __force.
> > 
> > Signed-off-by: Michael S. Tsirkin 
> 
> Ping.
> Do powerpc maintainers consider fixing sparse errors
> applicable for 3.19?
> If yes, can you pls merge this patch?

Relax :-) Our patches are tracked in Patchwork and such fixes aren't
necessarily constrained by the merge window. Michael will probably
pick it up but don't expect systematic replies to patches in 2 days ...

Also, when sending a series like that where one of us only gets
CCed on one of the patch, it helps to make it clear whether you
only expect an ack or whether you expect us to take the patch.

Cheers,
Ben.
> > ---
> >  arch/powerpc/include/asm/uaccess.h | 6 +++---
> >  1 file changed, 3 insertions(+), 3 deletions(-)
> > 
> > diff --git a/arch/powerpc/include/asm/uaccess.h 
> > b/arch/powerpc/include/asm/uaccess.h
> > index 9485b43..a0c071d 100644
> > --- a/arch/powerpc/include/asm/uaccess.h
> > +++ b/arch/powerpc/include/asm/uaccess.h
> > @@ -284,7 +284,7 @@ do {
> > \
> > if (!is_kernel_addr((unsigned long)__gu_addr))  \
> > might_fault();  \
> > __get_user_size(__gu_val, __gu_addr, (size), __gu_err); \
> > -   (x) = (__typeof__(*(ptr)))__gu_val; \
> > +   (x) = (__force __typeof__(*(ptr)))__gu_val; \
> > __gu_err;   \
> >  })
> >  #endif /* __powerpc64__ */
> > @@ -297,7 +297,7 @@ do {
> > \
> > might_fault();  \
> > if (access_ok(VERIFY_READ, __gu_addr, (size)))  \
> > __get_user_size(__gu_val, __gu_addr, (size), __gu_err); \
> > -   (x) = (__typeof__(*(ptr)))__gu_val; \
> > +   (x) = (__force __typeof__(*(ptr)))__gu_val; 
> > \
> > __gu_err;   \
> >  })
> >  
> > @@ -308,7 +308,7 @@ do {
> > \
> > const __typeof__(*(ptr)) __user *__gu_addr = (ptr); \
> > __chk_user_ptr(ptr);\
> > __get_user_size(__gu_val, __gu_addr, (size), __gu_err); \
> > -   (x) = (__typeof__(*(ptr)))__gu_val; \
> > +   (x) = (__force __typeof__(*(ptr)))__gu_val; \
> > __gu_err;   \
> >  })
> >  
> > -- 
> > MST
> > 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
> the body of a message to majord...@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
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Re: [PATCH v2 1/3] powerpc/nvram: move generic code for nvram and pstore

2014-12-16 Thread Michael Ellerman 
On Tue, 2014-12-16 at 23:35 +0530, Hari Bathini wrote:
> With minor checks, we can move most of the code for nvram
> under pseries to a common place to be re-used by other
> powerpc platforms like powernv. This patch moves such
> common code to arch/powerpc/kernel/nvram_64.c file.

Sharing the code is great.

But, you need to keep in mind that it is very common for us to build kernels
with both POWERNV=y and PSERIES=y.

So you need to make sure you're only using CONFIG_PPC_PSERIES to protect things
that are optional on pseries. Not things that we *shouldn't* be doing on
powernv.

For example the logic in nvram_init_oops_partition() looks like it might do the
wrong thing for PSERIES=y POWERNV=y.

> diff --git a/arch/powerpc/include/asm/rtas.h b/arch/powerpc/include/asm/rtas.h
> index b390f55..a033fe9 100644
> --- a/arch/powerpc/include/asm/rtas.h
> +++ b/arch/powerpc/include/asm/rtas.h
> @@ -343,6 +343,8 @@ extern int early_init_dt_scan_rtas(unsigned long node,
>  extern void pSeries_log_error(char *buf, unsigned int err_type, int fatal);
>  
>  #ifdef CONFIG_PPC_PSERIES
> +extern unsigned long last_rtas_event;
> +extern int clobbering_unread_rtas_event(void);

You should add an empty version of this for !PSERIES, so you don't have to
ifdef all the call sites.

cheers


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Re: [PATCH 13/18] powerpc/uaccess: fix sparse errors

2014-12-16 Thread Michael Ellerman 
On Tue, 2014-12-16 at 18:47 +0200, Michael S. Tsirkin wrote:
> On Sun, Dec 14, 2014 at 06:52:51PM +0200, Michael S. Tsirkin wrote:
> > virtio wants to read bitwise types from userspace using get_user.  At the
> > moment this triggers sparse errors, since the value is passed through an
> > integer.
> > 
> > Fix that up using __force.
> > 
> > Signed-off-by: Michael S. Tsirkin 
> 
> Ping.

Ping? You only sent it two days ago. And you only responded to my questions
yesterday evening.

> Do powerpc maintainers consider fixing sparse errors
> applicable for 3.19?

Yeah, with your expanded explanation I'm fine with it.

> If yes, can you pls merge this patch?

Yes I will.

cheers


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[PATCH v2 3/3] pstore: add pstore support on powernv

2014-12-16 Thread Hari Bathini 
This patch extends pstore, a generic interface to platform dependent
persistent storage, support for powernv  platform to capture certain
useful information, during dying moments. Such support is already in
place for  pseries platform.  This patch re-uses most of that code.

Signed-off-by: Hari Bathini 
---
 arch/powerpc/kernel/nvram_64.c  |   25 +++--
 arch/powerpc/platforms/powernv/opal-nvram.c |   10 ++
 2 files changed, 33 insertions(+), 2 deletions(-)

diff --git a/arch/powerpc/kernel/nvram_64.c b/arch/powerpc/kernel/nvram_64.c
index dbff7f0..3afbc91 100644
--- a/arch/powerpc/kernel/nvram_64.c
+++ b/arch/powerpc/kernel/nvram_64.c
@@ -127,6 +127,14 @@ static size_t oops_data_sz;
 static struct z_stream_s stream;
 
 #ifdef CONFIG_PSTORE
+#ifdef CONFIG_PPC_POWERNV
+static struct nvram_os_partition skiboot_partition = {
+   .name = "ibm,skiboot",
+   .index = -1,
+   .os_partition = false
+};
+#endif
+
 #ifdef CONFIG_PPC_PSERIES
 static struct nvram_os_partition of_config_partition = {
.name = "of-config",
@@ -479,6 +487,16 @@ static ssize_t nvram_pstore_read(u64 *id, enum 
pstore_type_id *type,
time->tv_nsec = 0;
break;
 #endif
+#ifdef CONFIG_PPC_POWERNV
+   case PSTORE_TYPE_PPC_OPAL:
+   sig = NVRAM_SIG_FW;
+   part = &skiboot_partition;
+   *type = PSTORE_TYPE_PPC_OPAL;
+   *id = PSTORE_TYPE_PPC_OPAL;
+   time->tv_sec = 0;
+   time->tv_nsec = 0;
+   break;
+#endif
default:
return 0;
}
@@ -554,8 +572,11 @@ static int nvram_pstore_init(void)
 {
int rc = 0;
 
-   nvram_type_ids[2] = PSTORE_TYPE_PPC_RTAS;
-   nvram_type_ids[3] = PSTORE_TYPE_PPC_OF;
+   if (machine_is(pseries)) {
+   nvram_type_ids[2] = PSTORE_TYPE_PPC_RTAS;
+   nvram_type_ids[3] = PSTORE_TYPE_PPC_OF;
+   } else
+   nvram_type_ids[2] = PSTORE_TYPE_PPC_OPAL;
 
nvram_pstore_info.buf = oops_data;
nvram_pstore_info.bufsize = oops_data_sz;
diff --git a/arch/powerpc/platforms/powernv/opal-nvram.c 
b/arch/powerpc/platforms/powernv/opal-nvram.c
index f9896fd..9db4398 100644
--- a/arch/powerpc/platforms/powernv/opal-nvram.c
+++ b/arch/powerpc/platforms/powernv/opal-nvram.c
@@ -16,6 +16,7 @@
 #include 
 
 #include 
+#include 
 #include 
 
 static unsigned int nvram_size;
@@ -62,6 +63,15 @@ static ssize_t opal_nvram_write(char *buf, size_t count, 
loff_t *index)
return count;
 }
 
+static int __init opal_nvram_init_log_partitions(void)
+{
+   /* Scan nvram for partitions */
+   nvram_scan_partitions();
+   nvram_init_oops_partition(0);
+   return 0;
+}
+machine_arch_initcall(powernv, opal_nvram_init_log_partitions);
+
 void __init opal_nvram_init(void)
 {
struct device_node *np;

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[PATCH v2 2/3] pstore: Add pstore type id for firmware partition

2014-12-16 Thread Hari Bathini 
This patch adds a pstore type id to be used for opal specific
nvram partitions.

Signed-off-by: Hari Bathini 
---
 fs/pstore/inode.c  |3 +++
 include/linux/pstore.h |1 +
 2 files changed, 4 insertions(+)

diff --git a/fs/pstore/inode.c b/fs/pstore/inode.c
index 5041660..8e0c009 100644
--- a/fs/pstore/inode.c
+++ b/fs/pstore/inode.c
@@ -359,6 +359,9 @@ int pstore_mkfile(enum pstore_type_id type, char *psname, 
u64 id, int count,
case PSTORE_TYPE_PPC_COMMON:
sprintf(name, "powerpc-common-%s-%lld", psname, id);
break;
+   case PSTORE_TYPE_PPC_OPAL:
+   sprintf(name, "powerpc-opal-%s-%lld", psname, id);
+   break;
case PSTORE_TYPE_UNKNOWN:
sprintf(name, "unknown-%s-%lld", psname, id);
break;
diff --git a/include/linux/pstore.h b/include/linux/pstore.h
index ece0c6b..af44980 100644
--- a/include/linux/pstore.h
+++ b/include/linux/pstore.h
@@ -39,6 +39,7 @@ enum pstore_type_id {
PSTORE_TYPE_PPC_RTAS= 4,
PSTORE_TYPE_PPC_OF  = 5,
PSTORE_TYPE_PPC_COMMON  = 6,
+   PSTORE_TYPE_PPC_OPAL= 7,
PSTORE_TYPE_UNKNOWN = 255
 };
 

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[PATCH v2 1/3] powerpc/nvram: move generic code for nvram and pstore

2014-12-16 Thread Hari Bathini 
With minor checks, we can move most of the code for nvram
under pseries to a common place to be re-used by other
powerpc platforms like powernv. This patch moves such
common code to arch/powerpc/kernel/nvram_64.c file.

Signed-off-by: Hari Bathini 
---
 arch/powerpc/include/asm/nvram.h   |   50 ++
 arch/powerpc/include/asm/rtas.h|2 
 arch/powerpc/kernel/nvram_64.c |  660 
 arch/powerpc/platforms/pseries/nvram.c |  665 
 4 files changed, 716 insertions(+), 661 deletions(-)

diff --git a/arch/powerpc/include/asm/nvram.h b/arch/powerpc/include/asm/nvram.h
index b0fe0fe..09a518b 100644
--- a/arch/powerpc/include/asm/nvram.h
+++ b/arch/powerpc/include/asm/nvram.h
@@ -9,12 +9,43 @@
 #ifndef _ASM_POWERPC_NVRAM_H
 #define _ASM_POWERPC_NVRAM_H
 
-
+#include 
 #include 
 #include 
 #include 
 
+/*
+ * Set oops header version to distinguish between old and new format header.
+ * lnx,oops-log partition max size is 4000, header version > 4000 will
+ * help in identifying new header.
+ */
+#define OOPS_HDR_VERSION 5000
+
+struct err_log_info {
+   __be32 error_type;
+   __be32 seq_num;
+};
+
+struct nvram_os_partition {
+   const char *name;
+   int req_size;   /* desired size, in bytes */
+   int min_size;   /* minimum acceptable size (0 means req_size) */
+   long size;  /* size of data portion (excluding err_log_info) */
+   long index; /* offset of data portion of partition */
+   bool os_partition; /* partition initialized by OS, not FW */
+};
+
+struct oops_log_info {
+   __be16 version;
+   __be16 report_length;
+   __be64 timestamp;
+} __attribute__((packed));
+
+extern struct nvram_os_partition oops_log_partition;
+
 #ifdef CONFIG_PPC_PSERIES
+extern struct nvram_os_partition rtas_log_partition;
+
 extern int nvram_write_error_log(char * buff, int length,
 unsigned int err_type, unsigned int 
err_seq);
 extern int nvram_read_error_log(char * buff, int length,
@@ -50,6 +81,23 @@ extern void  pmac_xpram_write(int xpaddr, u8 data);
 /* Synchronize NVRAM */
 extern voidnvram_sync(void);
 
+/* Initialize NVRAM OS partition */
+extern int __init nvram_init_os_partition(struct nvram_os_partition *part);
+
+/* Initialize NVRAM oops partition */
+extern void __init nvram_init_oops_partition(int rtas_partition_exists);
+
+/* Read a NVRAM partition */
+extern int nvram_read_partition(struct nvram_os_partition *part, char *buff,
+   int length, unsigned int *err_type,
+   unsigned int *error_log_cnt);
+
+/* Write to NVRAM OS partition */
+extern int nvram_write_os_partition(struct nvram_os_partition *part,
+   char *buff, int length,
+   unsigned int err_type,
+   unsigned int error_log_cnt);
+
 /* Determine NVRAM size */
 extern ssize_t nvram_get_size(void);
 
diff --git a/arch/powerpc/include/asm/rtas.h b/arch/powerpc/include/asm/rtas.h
index b390f55..a033fe9 100644
--- a/arch/powerpc/include/asm/rtas.h
+++ b/arch/powerpc/include/asm/rtas.h
@@ -343,6 +343,8 @@ extern int early_init_dt_scan_rtas(unsigned long node,
 extern void pSeries_log_error(char *buf, unsigned int err_type, int fatal);
 
 #ifdef CONFIG_PPC_PSERIES
+extern unsigned long last_rtas_event;
+extern int clobbering_unread_rtas_event(void);
 extern int pseries_devicetree_update(s32 scope);
 extern void post_mobility_fixup(void);
 #endif
diff --git a/arch/powerpc/kernel/nvram_64.c b/arch/powerpc/kernel/nvram_64.c
index 34f7c9b..dbff7f0 100644
--- a/arch/powerpc/kernel/nvram_64.c
+++ b/arch/powerpc/kernel/nvram_64.c
@@ -26,6 +26,9 @@
 #include 
 #include 
 #include 
+#include 
+#include 
+#include 
 #include 
 #include 
 #include 
@@ -54,6 +57,663 @@ struct nvram_partition {
 
 static LIST_HEAD(nvram_partitions);
 
+#ifdef CONFIG_PPC_PSERIES
+struct nvram_os_partition rtas_log_partition = {
+   .name = "ibm,rtas-log",
+   .req_size = 2079,
+   .min_size = 1055,
+   .index = -1,
+   .os_partition = true
+};
+#endif
+
+struct nvram_os_partition oops_log_partition = {
+   .name = "lnx,oops-log",
+   .req_size = 4000,
+   .min_size = 2000,
+   .index = -1,
+   .os_partition = true
+};
+
+static const char *nvram_os_partitions[] = {
+#ifdef CONFIG_PPC_PSERIES
+   "ibm,rtas-log",
+#endif
+   "lnx,oops-log",
+   NULL
+};
+
+static void oops_to_nvram(struct kmsg_dumper *dumper,
+ enum kmsg_dump_reason reason);
+
+static struct kmsg_dumper nvram_kmsg_dumper = {
+   .dump = oops_to_nvram
+};
+
+/*
+ * For capturing and compressing an oops or panic report...
+
+ * big_oops_buf[] holds the uncompressed text we're capturing.
+ *
+ * oops_buf[] holds the compressed text, preceded by a oops header.
+ * oops header has u16 holding the version of oops header (to differ

[PATCH v2 0/3] powerpc/pstore: Add pstore support for nvram partitions

2014-12-16 Thread Hari Bathini 
This patch series adds pstore support on powernv platform to
read different nvram partitions and write compressed data to
oops-log nvram partition. As pseries platform already has
pstore support, this series moves most of the common code
for pseries and powernv platforms to a common file. Tested
the patches successfully on both pseries and powernv
platforms.

---

Hari Bathini (3):
  powerpc/nvram: move generic code for nvram and pstore
  pstore: Add pstore type id for firmware partition
  pstore: add pstore support on powernv


 arch/powerpc/include/asm/nvram.h|   50 ++
 arch/powerpc/include/asm/rtas.h |2 
 arch/powerpc/kernel/nvram_64.c  |  681 +++
 arch/powerpc/platforms/powernv/opal-nvram.c |   10 
 arch/powerpc/platforms/pseries/nvram.c  |  665 --
 fs/pstore/inode.c   |3 
 include/linux/pstore.h  |1 
 7 files changed, 751 insertions(+), 661 deletions(-)

--
- Hari

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Re: [PATCH 13/18] powerpc/uaccess: fix sparse errors

2014-12-16 Thread Michael S. Tsirkin 
On Sun, Dec 14, 2014 at 06:52:51PM +0200, Michael S. Tsirkin wrote:
> virtio wants to read bitwise types from userspace using get_user.  At the
> moment this triggers sparse errors, since the value is passed through an
> integer.
> 
> Fix that up using __force.
> 
> Signed-off-by: Michael S. Tsirkin 

Ping.
Do powerpc maintainers consider fixing sparse errors
applicable for 3.19?
If yes, can you pls merge this patch?

> ---
>  arch/powerpc/include/asm/uaccess.h | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/powerpc/include/asm/uaccess.h 
> b/arch/powerpc/include/asm/uaccess.h
> index 9485b43..a0c071d 100644
> --- a/arch/powerpc/include/asm/uaccess.h
> +++ b/arch/powerpc/include/asm/uaccess.h
> @@ -284,7 +284,7 @@ do {  
> \
>   if (!is_kernel_addr((unsigned long)__gu_addr))  \
>   might_fault();  \
>   __get_user_size(__gu_val, __gu_addr, (size), __gu_err); \
> - (x) = (__typeof__(*(ptr)))__gu_val; \
> + (x) = (__force __typeof__(*(ptr)))__gu_val; \
>   __gu_err;   \
>  })
>  #endif /* __powerpc64__ */
> @@ -297,7 +297,7 @@ do {  
> \
>   might_fault();  \
>   if (access_ok(VERIFY_READ, __gu_addr, (size)))  \
>   __get_user_size(__gu_val, __gu_addr, (size), __gu_err); \
> - (x) = (__typeof__(*(ptr)))__gu_val; \
> + (x) = (__force __typeof__(*(ptr)))__gu_val; 
> \
>   __gu_err;   \
>  })
>  
> @@ -308,7 +308,7 @@ do {  
> \
>   const __typeof__(*(ptr)) __user *__gu_addr = (ptr); \
>   __chk_user_ptr(ptr);\
>   __get_user_size(__gu_val, __gu_addr, (size), __gu_err); \
> - (x) = (__typeof__(*(ptr)))__gu_val; \
> + (x) = (__force __typeof__(*(ptr)))__gu_val; \
>   __gu_err;   \
>  })
>  
> -- 
> MST
> 
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[PATCH 04/11] powerpc/8xx: Take benefit of aligned PGDIR

2014-12-16 Thread Christophe Leroy 
L1 base address is now aligned so we can insert L1 index into r11 directly and
then preserve r10

Signed-off-by: Christophe Leroy 

---
 arch/powerpc/kernel/head_8xx.S | 34 +++---
 1 file changed, 15 insertions(+), 19 deletions(-)

diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index 2c329f1..ae05f28 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -326,16 +326,15 @@ InstructionTLBMiss:
ori r11, r11, (swapper_pg_dir-PAGE_OFFSET)@l
 3:
 #endif
-   /* Extract level 1 index */
-   rlwinm  r10, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 
29
-   lwzxr11, r10, r11   /* Get the level 1 entry */
-   rlwinm  r10, r11,0,0,19 /* Extract page descriptor page address */
+   /* Insert level 1 index */
+   rlwimi  r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 
29
+   lwz r11, 0(r11) /* Get the level 1 entry */
 
/* Load the MI_TWC with the attributes for this "segment." */
MTSPR_CPU6(SPRN_MI_TWC, r11, r3)/* Set segment attributes */
-   mfspr   r11, SPRN_SRR0  /* Get effective address of fault */
+   rlwinm  r11, r11,0,0,19 /* Extract page descriptor page address */
/* Extract level 2 index */
-   rlwinm  r11, r11, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29
+   rlwinm  r10, r10, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29
lwzxr10, r10, r11   /* Get the pte */
 
 #ifdef CONFIG_SWAP
@@ -380,13 +379,12 @@ DataStoreTLBMiss:
lis r11, (swapper_pg_dir-PAGE_OFFSET)@h
ori r11, r11, (swapper_pg_dir-PAGE_OFFSET)@l
 3:
-   /* Extract level 1 index */
-   rlwinm  r10, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 
29
-   lwzxr11, r10, r11   /* Get the level 1 entry */
+   /* Insert level 1 index */
+   rlwimi  r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 
29
+   lwz r11, 0(r11) /* Get the level 1 entry */
 
/* We have a pte table, so load fetch the pte from the table.
 */
-   mfspr   r10, SPRN_MD_EPN/* Get address of fault */
/* Extract level 2 index */
rlwinm  r10, r10, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29
rlwimi  r10, r11, 0, 0, 32 - PAGE_SHIFT - 1 /* Add level 2 base */
@@ -515,16 +513,14 @@ FixupDAR:/* Entry point for dcbx workaround. */
beq-3f  /* Branch if user space */
lis r11, (swapper_pg_dir-PAGE_OFFSET)@h
ori r11, r11, (swapper_pg_dir-PAGE_OFFSET)@l
-   /* Extract level 1 index */
-3: rlwinm  r10, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 
29
-   lwzxr11, r10, r11   /* Get the level 1 entry */
-   rlwinm  r10, r11,0,0,19 /* Extract page descriptor page address */
-   mfspr   r11, SPRN_SRR0  /* Get effective address of fault */
-   /* Extract level 2 index */
-   rlwinm  r11, r11, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29
-   lwzxr11, r10, r11   /* Get the pte */
+   /* Insert level 1 index */
+3: rlwimi  r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 
29
+   lwz r11, 0(r11) /* Get the level 1 entry */
+   rlwinm  r11, r11,0,0,19 /* Extract page descriptor page address */
+   /* Insert level 2 index */
+   rlwimi  r11, r10, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29
+   lwz r11, 0(r11) /* Get the pte */
/* concat physical page address(r11) and page offset(r10) */
-   mfspr   r10, SPRN_SRR0
rlwimi  r11, r10, 0, 32 - PAGE_SHIFT, 31
lwz r11,0(r11)
 /* Check if it really is a dcbx instruction. */
-- 
2.1.0

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[PATCH 09/11] powerpc/8xx: dont save CR in SCRATCH registers

2014-12-16 Thread Christophe Leroy 
CR only needs to be preserved when checking if we are handling a kernel address.
So we can preserve CR in a register:
- In ITLBMiss, check is done only when CONFIG_MODULES is defined. Otherwise we
don't need to do anything at all with CR.
- If CONFIG_8xx_CPU6 is defined, we have r3 available for saving CR
- Otherwise, we use r10, then we reload SRR0/MD_EPN into r10 when CR is restored

Signed-off-by: Christophe Leroy 

---
 arch/powerpc/kernel/head_8xx.S | 53 +-
 1 file changed, 37 insertions(+), 16 deletions(-)

diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index c89aed9..a073918 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -308,14 +308,10 @@ SystemCall:
 #endif
 
 InstructionTLBMiss:
+   EXCEPTION_PROLOG_0
 #ifdef CONFIG_8xx_CPU6
mtspr   SPRN_DAR, r3
 #endif
-   EXCEPTION_PROLOG_0
-   mfcrr10
-   mtspr   SPRN_SPRG_SCRATCH2, r10
-   mfspr   r10, SPRN_SRR0  /* Get effective address of fault */
-   DO_8xx_CPU15(r11, r10)
 
/* If we are faulting a kernel address, we have to use the
 * kernel page tables.
@@ -323,14 +319,33 @@ InstructionTLBMiss:
 #ifdef CONFIG_MODULES
/* Only modules will cause ITLB Misses as we always
 * pin the first 8MB of kernel memory */
+#ifdef CONFIG_8xx_CPU6
+   mfspr   r10, SPRN_SRR0  /* Get effective address of fault */
+   DO_8xx_CPU15(r11, r10)
+   mfcrr3
andis.  r11, r10, 0x8000/* Address >= 0x8000 */
+#else
+   mfspr   r11, SPRN_SRR0  /* Get effective address of fault */
+   DO_8xx_CPU15(r10, r11)
+   mfcrr10
+   andis.  r11, r11, 0x8000/* Address >= 0x8000 */
 #endif
mfspr   r11, SPRN_M_TW  /* Get level 1 table base address */
-#ifdef CONFIG_MODULES
beq 3f
lis r11, (swapper_pg_dir-PAGE_OFFSET)@ha
 3:
+#ifdef CONFIG_8xx_CPU6
+   mtcrr3
+#else
+   mtcrr10
+   mfspr   r10, SPRN_SRR0  /* Get effective address of fault */
 #endif
+#else /* CONFIG_MODULES */
+   mfspr   r10, SPRN_SRR0  /* Get effective address of fault */
+   DO_8xx_CPU15(r11, r10)
+   mfspr   r11, SPRN_M_TW  /* Get level 1 table base address */
+#endif /* CONFIG_MODULES */
+
/* Insert level 1 index */
rlwimi  r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 
29
lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11)/* Get the 
level 1 entry */
@@ -362,29 +377,37 @@ InstructionTLBMiss:
mfspr   r3, SPRN_DAR
mtspr   SPRN_DAR, r11   /* Tag DAR */
 #endif
-   mfspr   r10, SPRN_SPRG_SCRATCH2
-   mtcrr10
EXCEPTION_EPILOG_0
rfi
 
. = 0x1200
 DataStoreTLBMiss:
-#ifdef CONFIG_8xx_CPU6
-   mtspr   SPRN_DAR, r3
-#endif
EXCEPTION_PROLOG_0
-   mfcrr10
-   mtspr   SPRN_SPRG_SCRATCH2, r10
-   mfspr   r10, SPRN_MD_EPN
 
/* If we are faulting a kernel address, we have to use the
 * kernel page tables.
 */
+#ifdef CONFIG_8xx_CPU6
+   mtspr   SPRN_DAR, r3
+   mfcrr3
+   mfspr   r10, SPRN_MD_EPN
andis.  r11, r10, 0x8000
+#else
+   mfcrr10
+   mfspr   r11, SPRN_MD_EPN
+   andis.  r11, r11, 0x8000
+#endif
mfspr   r11, SPRN_M_TW  /* Get level 1 table base address */
beq 3f
lis r11, (swapper_pg_dir-PAGE_OFFSET)@ha
 3:
+#ifdef CONFIG_8xx_CPU6
+   mtcrr3
+#else
+   mtcrr10
+   mfspr   r10, SPRN_MD_EPN
+#endif
+
/* Insert level 1 index */
rlwimi  r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 
29
lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11)/* Get the 
level 1 entry */
@@ -441,8 +464,6 @@ DataStoreTLBMiss:
mfspr   r3, SPRN_DAR
 #endif
mtspr   SPRN_DAR, r11   /* Tag DAR */
-   mfspr   r10, SPRN_SPRG_SCRATCH2
-   mtcrr10
EXCEPTION_EPILOG_0
rfi
 
-- 
2.1.0

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[PATCH 10/11] powerpc/8xx: Use SPRG2 instead of DAR for saving r3

2014-12-16 Thread Christophe Leroy 
We now have SPRG2 available as in it not used anymore for saving CR, so we don't
need to crash DAR anymore for saving r3 for CPU6 ERRATA handling.

Signed-off-by: Christophe Leroy 

---
 arch/powerpc/kernel/head_8xx.S | 9 -
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index a073918..dbe110e 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -310,7 +310,7 @@ SystemCall:
 InstructionTLBMiss:
EXCEPTION_PROLOG_0
 #ifdef CONFIG_8xx_CPU6
-   mtspr   SPRN_DAR, r3
+   mtspr   SPRN_SPRG_SCRATCH2, r3
 #endif
 
/* If we are faulting a kernel address, we have to use the
@@ -374,8 +374,7 @@ InstructionTLBMiss:
 
/* Restore registers */
 #ifdef CONFIG_8xx_CPU6
-   mfspr   r3, SPRN_DAR
-   mtspr   SPRN_DAR, r11   /* Tag DAR */
+   mfspr   r3, SPRN_SPRG_SCRATCH2
 #endif
EXCEPTION_EPILOG_0
rfi
@@ -388,7 +387,7 @@ DataStoreTLBMiss:
 * kernel page tables.
 */
 #ifdef CONFIG_8xx_CPU6
-   mtspr   SPRN_DAR, r3
+   mtspr   SPRN_SPRG_SCRATCH2, r3
mfcrr3
mfspr   r10, SPRN_MD_EPN
andis.  r11, r10, 0x8000
@@ -461,7 +460,7 @@ DataStoreTLBMiss:
 
/* Restore registers */
 #ifdef CONFIG_8xx_CPU6
-   mfspr   r3, SPRN_DAR
+   mfspr   r3, SPRN_SPRG_SCRATCH2
 #endif
mtspr   SPRN_DAR, r11   /* Tag DAR */
EXCEPTION_EPILOG_0
-- 
2.1.0

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[PATCH 08/11] powerpc/8xx: Handle CR out of exception PROLOG/EPILOG

2014-12-16 Thread Christophe Leroy 
In order to be able to reduce scope during which CR is saved, we take
CR saving/restoring out of exception PROLOG and EPILOG

Signed-off-by: Christophe Leroy 

---
 arch/powerpc/kernel/head_8xx.S | 10 +++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index b3f3cb5..c89aed9 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -116,13 +116,13 @@ turn_on_mmu:
  */
 #define EXCEPTION_PROLOG   \
EXCEPTION_PROLOG_0; \
+   mfcrr10;\
EXCEPTION_PROLOG_1; \
EXCEPTION_PROLOG_2
 
 #define EXCEPTION_PROLOG_0 \
mtspr   SPRN_SPRG_SCRATCH0,r10; \
-   mtspr   SPRN_SPRG_SCRATCH1,r11; \
-   mfcrr10
+   mtspr   SPRN_SPRG_SCRATCH1,r11
 
 #define EXCEPTION_PROLOG_1 \
mfspr   r11,SPRN_SRR1;  /* check whether user or kernel */ \
@@ -162,7 +162,6 @@ turn_on_mmu:
  * Exception exit code.
  */
 #define EXCEPTION_EPILOG_0 \
-   mtcrr10;\
mfspr   r10,SPRN_SPRG_SCRATCH0; \
mfspr   r11,SPRN_SPRG_SCRATCH1
 
@@ -313,6 +312,7 @@ InstructionTLBMiss:
mtspr   SPRN_DAR, r3
 #endif
EXCEPTION_PROLOG_0
+   mfcrr10
mtspr   SPRN_SPRG_SCRATCH2, r10
mfspr   r10, SPRN_SRR0  /* Get effective address of fault */
DO_8xx_CPU15(r11, r10)
@@ -363,6 +363,7 @@ InstructionTLBMiss:
mtspr   SPRN_DAR, r11   /* Tag DAR */
 #endif
mfspr   r10, SPRN_SPRG_SCRATCH2
+   mtcrr10
EXCEPTION_EPILOG_0
rfi
 
@@ -372,6 +373,7 @@ DataStoreTLBMiss:
mtspr   SPRN_DAR, r3
 #endif
EXCEPTION_PROLOG_0
+   mfcrr10
mtspr   SPRN_SPRG_SCRATCH2, r10
mfspr   r10, SPRN_MD_EPN
 
@@ -440,6 +442,7 @@ DataStoreTLBMiss:
 #endif
mtspr   SPRN_DAR, r11   /* Tag DAR */
mfspr   r10, SPRN_SPRG_SCRATCH2
+   mtcrr10
EXCEPTION_EPILOG_0
rfi
 
@@ -465,6 +468,7 @@ InstructionTLBError:
. = 0x1400
 DataTLBError:
EXCEPTION_PROLOG_0
+   mfcrr10
 
mfspr   r11, SPRN_DAR
cmpwi   cr0, r11, RPN_PATTERN
-- 
2.1.0

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[PATCH 11/11] powerpc/8xx: Add support for TASK_SIZE greater than 0x80000000

2014-12-16 Thread Christophe Leroy 
By default, TASK_SIZE is set to 0x8000 for PPC_8xx, which is most likely
sufficient for most cases. However, kernel configuration allows to set TASK_SIZE
to another value, so the 8xx shall handle it.

Signed-off-by: Christophe Leroy 

---
 arch/powerpc/kernel/head_8xx.S | 29 +
 1 file changed, 21 insertions(+), 8 deletions(-)

diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index dbe110e..d380658 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -48,6 +48,19 @@
mtspr   spr, reg
 #endif
 
+/* Macro to test if an address is a kernel address */
+#if CONFIG_TASK_SIZE <= 0x8000
+#define IS_KERNEL(tmp, addr)   \
+   andis.  tmp, addr, 0x8000   /* Address >= 0x8000 */
+#define BRANCH_UNLESS_KERNEL(label)beq label
+#else
+#define IS_KERNEL(tmp, addr)   \
+   rlwinm  tmp, addr, 16, 16, 31;  \
+   cmpli   cr0, tmp, PAGE_OFFSET >> 16
+#define BRANCH_UNLESS_KERNEL(label)blt label
+#endif
+
+
 /*
  * Value for the bits that have fixed value in RPN entries.
  * Also used for tagging DAR for DTLBerror.
@@ -323,15 +336,15 @@ InstructionTLBMiss:
mfspr   r10, SPRN_SRR0  /* Get effective address of fault */
DO_8xx_CPU15(r11, r10)
mfcrr3
-   andis.  r11, r10, 0x8000/* Address >= 0x8000 */
+   IS_KERNEL(r11, r10)
 #else
mfspr   r11, SPRN_SRR0  /* Get effective address of fault */
DO_8xx_CPU15(r10, r11)
mfcrr10
-   andis.  r11, r11, 0x8000/* Address >= 0x8000 */
+   IS_KERNEL(r11, r11)
 #endif
mfspr   r11, SPRN_M_TW  /* Get level 1 table base address */
-   beq 3f
+   BRANCH_UNLESS_KERNEL(3f)
lis r11, (swapper_pg_dir-PAGE_OFFSET)@ha
 3:
 #ifdef CONFIG_8xx_CPU6
@@ -390,14 +403,14 @@ DataStoreTLBMiss:
mtspr   SPRN_SPRG_SCRATCH2, r3
mfcrr3
mfspr   r10, SPRN_MD_EPN
-   andis.  r11, r10, 0x8000
+   IS_KERNEL(r11, r10)
 #else
mfcrr10
mfspr   r11, SPRN_MD_EPN
-   andis.  r11, r11, 0x8000
+   IS_KERNEL(r11, r11)
 #endif
mfspr   r11, SPRN_M_TW  /* Get level 1 table base address */
-   beq 3f
+   BRANCH_UNLESS_KERNEL(3f)
lis r11, (swapper_pg_dir-PAGE_OFFSET)@ha
 3:
 #ifdef CONFIG_8xx_CPU6
@@ -536,9 +549,9 @@ FixupDAR:/* Entry point for dcbx workaround. */
mtspr   SPRN_SPRG_SCRATCH2, r10
/* fetch instruction from memory. */
mfspr   r10, SPRN_SRR0
-   andis.  r11, r10, 0x8000/* Address >= 0x8000 */
+   IS_KERNEL(r11, r10)
mfspr   r11, SPRN_M_TW  /* Get level 1 table base address */
-   beq 3f
+   BRANCH_UNLESS_KERNEL(3f)
lis r11, (swapper_pg_dir-PAGE_OFFSET)@ha
/* Insert level 1 index */
 3: rlwimi  r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 
29
-- 
2.1.0

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[PATCH 05/11] powerpc/8xx: Optimise access to swapper_pg_dir

2014-12-16 Thread Christophe Leroy 
All accessed to PGD entries are done via 0(r11).
By using lower part of swapper_pg_dir as load index to r11, we can remove the
ori instruction.

Signed-off-by: Christophe Leroy 

---
 arch/powerpc/kernel/head_8xx.S | 22 ++
 1 file changed, 10 insertions(+), 12 deletions(-)

diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index ae05f28..aa45225 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -322,13 +322,12 @@ InstructionTLBMiss:
mfspr   r11, SPRN_M_TW  /* Get level 1 table base address */
 #ifdef CONFIG_MODULES
beq 3f
-   lis r11, (swapper_pg_dir-PAGE_OFFSET)@h
-   ori r11, r11, (swapper_pg_dir-PAGE_OFFSET)@l
+   lis r11, (swapper_pg_dir-PAGE_OFFSET)@ha
 3:
 #endif
/* Insert level 1 index */
rlwimi  r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 
29
-   lwz r11, 0(r11) /* Get the level 1 entry */
+   lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11)/* Get the 
level 1 entry */
 
/* Load the MI_TWC with the attributes for this "segment." */
MTSPR_CPU6(SPRN_MI_TWC, r11, r3)/* Set segment attributes */
@@ -376,12 +375,11 @@ DataStoreTLBMiss:
andis.  r11, r10, 0x8000
mfspr   r11, SPRN_M_TW  /* Get level 1 table base address */
beq 3f
-   lis r11, (swapper_pg_dir-PAGE_OFFSET)@h
-   ori r11, r11, (swapper_pg_dir-PAGE_OFFSET)@l
+   lis r11, (swapper_pg_dir-PAGE_OFFSET)@ha
 3:
/* Insert level 1 index */
rlwimi  r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 
29
-   lwz r11, 0(r11) /* Get the level 1 entry */
+   lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11)/* Get the 
level 1 entry */
 
/* We have a pte table, so load fetch the pte from the table.
 */
@@ -510,12 +508,11 @@ FixupDAR:/* Entry point for dcbx workaround. */
mfspr   r10, SPRN_SRR0
andis.  r11, r10, 0x8000/* Address >= 0x8000 */
mfspr   r11, SPRN_M_TW  /* Get level 1 table base address */
-   beq-3f  /* Branch if user space */
-   lis r11, (swapper_pg_dir-PAGE_OFFSET)@h
-   ori r11, r11, (swapper_pg_dir-PAGE_OFFSET)@l
+   beq 3f
+   lis r11, (swapper_pg_dir-PAGE_OFFSET)@ha
/* Insert level 1 index */
 3: rlwimi  r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 
29
-   lwz r11, 0(r11) /* Get the level 1 entry */
+   lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11)/* Get the 
level 1 entry */
rlwinm  r11, r11,0,0,19 /* Extract page descriptor page address */
/* Insert level 2 index */
rlwimi  r11, r10, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29
@@ -670,8 +667,7 @@ start_here:
 * init's THREAD like the context switch code does, but this is
 * easier..until someone changes init's static structures.
 */
-   lis r6, swapper_pg_dir@h
-   ori r6, r6, swapper_pg_dir@l
+   lis r6, swapper_pg_dir@ha
tophys(r6,r6)
 #ifdef CONFIG_8xx_CPU6
lis r4, cpu6_errata_word@h
@@ -850,6 +846,8 @@ _GLOBAL(set_context)
stw r4, 0x4(r5)
 #endif
 
+   li  r5, (swapper_pg_dir-PAGE_OFFSET)@l
+   sub r4, r4, r5
 #ifdef CONFIG_8xx_CPU6
lis r6, cpu6_errata_word@h
ori r6, r6, cpu6_errata_word@l
-- 
2.1.0

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[PATCH 02/11] powerpc/8xx: remove tests on PGDIR entry validity

2014-12-16 Thread Christophe Leroy 
Kernel MMU handling code handles validity of entries via _PMD_PRESENT which
corresponds to V bit in MD_TWC and MI_TWC. When the V bit is not set, MPC8xx
triggers TLBError exception. So we don't have to check that and branch ourself
to TLBError. We can set TLB entries with non present entries, remove all those
tests and let the 8xx handle it. This reduce the number of cycle when the
entries are valid which is the case most of the time, and doesn't significantly
increase the time for handling invalid entries.

Signed-off-by: Christophe Leroy 

---
 arch/powerpc/kernel/head_8xx.S | 41 -
 1 file changed, 8 insertions(+), 33 deletions(-)

diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index 79b8a23..2c329f1 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -329,12 +329,9 @@ InstructionTLBMiss:
/* Extract level 1 index */
rlwinm  r10, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 
29
lwzxr11, r10, r11   /* Get the level 1 entry */
-   rlwinm. r10, r11,0,0,19 /* Extract page descriptor page address */
-   beq 2f  /* If zero, don't try to find a pte */
+   rlwinm  r10, r11,0,0,19 /* Extract page descriptor page address */
 
-   /* We have a pte table, so load the MI_TWC with the attributes
-* for this "segment."
-*/
+   /* Load the MI_TWC with the attributes for this "segment." */
MTSPR_CPU6(SPRN_MI_TWC, r11, r3)/* Set segment attributes */
mfspr   r11, SPRN_SRR0  /* Get effective address of fault */
/* Extract level 2 index */
@@ -342,13 +339,11 @@ InstructionTLBMiss:
lwzxr10, r10, r11   /* Get the pte */
 
 #ifdef CONFIG_SWAP
-   andi.   r11, r10, _PAGE_ACCESSED | _PAGE_PRESENT
-   cmpwi   cr0, r11, _PAGE_ACCESSED | _PAGE_PRESENT
-   li  r11, RPN_PATTERN
-   bne-cr0, 2f
-#else
-   li  r11, RPN_PATTERN
+   rlwinm  r11, r10, 32-5, _PAGE_PRESENT
+   and r11, r11, r10
+   rlwimi  r10, r11, 0, _PAGE_PRESENT
 #endif
+   li  r11, RPN_PATTERN
/* The Linux PTE won't go exactly into the MMU TLB.
 * Software indicator bits 21 and 28 must be clear.
 * Software indicator bits 24, 25, 26, and 27 must be
@@ -366,21 +361,6 @@ InstructionTLBMiss:
mfspr   r10, SPRN_SPRG_SCRATCH2
EXCEPTION_EPILOG_0
rfi
-2:
-   mfspr   r10, SPRN_SRR1
-   /* clear all error bits as TLB Miss
-* sets a few unconditionally
-   */
-   rlwinm  r10, r10, 0, 0x
-   mtspr   SPRN_SRR1, r10
-
-   /* Restore registers */
-#ifdef CONFIG_8xx_CPU6
-   mfspr   r3, SPRN_DAR
-   mtspr   SPRN_DAR, r11   /* Tag DAR */
-#endif
-   mfspr   r10, SPRN_SPRG_SCRATCH2
-   b   InstructionTLBError1
 
. = 0x1200
 DataStoreTLBMiss:
@@ -403,8 +383,6 @@ DataStoreTLBMiss:
/* Extract level 1 index */
rlwinm  r10, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 
29
lwzxr11, r10, r11   /* Get the level 1 entry */
-   rlwinm. r10, r11,0,0,19 /* Extract page descriptor page address */
-   beq 2f  /* If zero, don't try to find a pte */
 
/* We have a pte table, so load fetch the pte from the table.
 */
@@ -450,7 +428,7 @@ DataStoreTLBMiss:
 * set.  All other Linux PTE bits control the behavior
 * of the MMU.
 */
-2: li  r11, RPN_PATTERN
+   li  r11, RPN_PATTERN
rlwimi  r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */
MTSPR_CPU6(SPRN_MD_RPN, r10, r3)/* Update TLB entry */
 
@@ -469,10 +447,7 @@ DataStoreTLBMiss:
  */
. = 0x1300
 InstructionTLBError:
-   EXCEPTION_PROLOG_0
-InstructionTLBError1:
-   EXCEPTION_PROLOG_1
-   EXCEPTION_PROLOG_2
+   EXCEPTION_PROLOG
mr  r4,r12
mr  r5,r9
andis.  r10,r5,0x4000
-- 
2.1.0

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[PATCH 07/11] powerpc/8xx: macro for handling CPU15 errata

2014-12-16 Thread Christophe Leroy 
Having a macro will help keep clear code.

Signed-off-by: Christophe Leroy 

---
 arch/powerpc/kernel/head_8xx.S | 18 --
 1 file changed, 12 insertions(+), 6 deletions(-)

diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index b227902e..b3f3cb5 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -297,6 +297,17 @@ SystemCall:
  * We have to use the MD_xxx registers for the tablewalk because the
  * equivalent MI_xxx registers only perform the attribute functions.
  */
+
+#ifdef CONFIG_8xx_CPU15
+#define DO_8xx_CPU15(tmp, addr)\
+   additmp, addr, PAGE_SIZE;   \
+   tlbie   tmp;\
+   additmp, addr, PAGE_SIZE;   \
+   tlbie   tmp
+#else
+#define DO_8xx_CPU15(tmp, addr)
+#endif
+
 InstructionTLBMiss:
 #ifdef CONFIG_8xx_CPU6
mtspr   SPRN_DAR, r3
@@ -304,12 +315,7 @@ InstructionTLBMiss:
EXCEPTION_PROLOG_0
mtspr   SPRN_SPRG_SCRATCH2, r10
mfspr   r10, SPRN_SRR0  /* Get effective address of fault */
-#ifdef CONFIG_8xx_CPU15
-   addir11, r10, PAGE_SIZE
-   tlbie   r11
-   addir11, r10, -PAGE_SIZE
-   tlbie   r11
-#endif
+   DO_8xx_CPU15(r11, r10)
 
/* If we are faulting a kernel address, we have to use the
 * kernel page tables.
-- 
2.1.0

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[PATCH 00/11] powerpc8xx: Further optimisation of TLB handling

2014-12-16 Thread Christophe Leroy 
This patchset provides a further optimisation of TLB handling in the 8xx.
Main changes are based on:
- Using processor handling of PGD/PTE Validity bits instead of testing ourselves
the entries validity
- Aligning PGD address to allow direct bit manipulation
- Not saving registers like CR when not needed

It also adds support to any TASK_SIZE

Patchset:
01 - powerpc/8xx: remove remaining unnecessary code in FixupDAR
02 - powerpc/8xx: remove tests on PGDIR entry validity
03 - powerpc32: Use kmem_cache memory for PGDIR
04 - powerpc/8xx: Take benefit of aligned PGDIR
05 - powerpc/8xx: Optimise access to swapper_pg_dir
06 - powerpc/8xx: Remove duplicated code in set_context()
07 - powerpc/8xx: macro for handling CPU15 errata
08 - powerpc/8xx: Handle CR out of exception PROLOG/EPILOG
09 - powerpc/8xx: dont save CR in SCRATCH registers
10 - powerpc/8xx: Use SPRG2 instead of DAR for saving r3
11 - powerpc/8xx: Add support for TASK_SIZE greater than 0x8000

All changes have been successfully tested on MPC885

Signed-off-by: Christophe Leroy 
Tested-by: Christophe Leroy 

---
 arch/powerpc/include/asm/page.h  |  8 +++
 arch/powerpc/include/asm/pgtable-ppc32.h | 37 +---
 arch/powerpc/include/asm/pgtable.h   | 17 ---
 arch/powerpc/include/asm/pte-8xx.h   |  1 +
 arch/powerpc/include/asm/pte-common.h|  3 +++
 arch/powerpc/kernel/head_8xx.S   |  3 ---
 arch/powerpc/mm/pgtable_32.c | 14 
 7 files changed, 56 insertions(+), 27 deletions(-)
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[PATCH 03/11] powerpc32: Use kmem_cache memory for PGDIR

2014-12-16 Thread Christophe Leroy 
When pages are not 4K, PGDIR table is allocated with kmalloc(). In order to
optimise TLB handlers, aligned memory is needed. kmalloc() doesn't provide
aligned memory blocks, so lets use a kmem_cache pool instead.

Signed-off-by: Christophe Leroy 

---
 arch/powerpc/include/asm/pgtable-ppc32.h |  4 
 arch/powerpc/mm/pgtable_32.c | 16 ++--
 2 files changed, 18 insertions(+), 2 deletions(-)

diff --git a/arch/powerpc/include/asm/pgtable-ppc32.h 
b/arch/powerpc/include/asm/pgtable-ppc32.h
index 543bb8e..d323e8b 100644
--- a/arch/powerpc/include/asm/pgtable-ppc32.h
+++ b/arch/powerpc/include/asm/pgtable-ppc32.h
@@ -346,10 +346,14 @@ static inline void __ptep_set_access_flags(pte_t *ptep, 
pte_t entry)
 #define pte_to_pgoff(pte)  (pte_val(pte) >> 3)
 #define pgoff_to_pte(off)  ((pte_t) { ((off) << 3) | _PAGE_FILE })
 
+#ifndef CONFIG_PPC_4K_PAGES
+void pgtable_cache_init(void);
+#else
 /*
  * No page table caches to initialise
  */
 #define pgtable_cache_init()   do { } while (0)
+#endif
 
 extern int get_pteptr(struct mm_struct *mm, unsigned long addr, pte_t **ptep,
  pmd_t **pmdp);
diff --git a/arch/powerpc/mm/pgtable_32.c b/arch/powerpc/mm/pgtable_32.c
index cf11342..730dc2d 100644
--- a/arch/powerpc/mm/pgtable_32.c
+++ b/arch/powerpc/mm/pgtable_32.c
@@ -73,13 +73,25 @@ extern unsigned long p_mapped_by_tlbcam(phys_addr_t pa);
 
 #define PGDIR_ORDER(32 + PGD_T_LOG2 - PGDIR_SHIFT)
 
+#ifndef CONFIG_PPC_4K_PAGES
+static struct kmem_cache *pgtable_cache;
+
+void pgtable_cache_init(void)
+{
+   pgtable_cache = kmem_cache_create("PGDIR cache", 1 << PGDIR_ORDER,
+ 1 << PGDIR_ORDER, 0, NULL);
+   if (pgtable_cache == NULL)
+   panic("Couldn't allocate pgtable caches");
+}
+#endif
+
 pgd_t *pgd_alloc(struct mm_struct *mm)
 {
pgd_t *ret;
 
/* pgdir take page or two with 4K pages and a page fraction otherwise */
 #ifndef CONFIG_PPC_4K_PAGES
-   ret = kzalloc(1 << PGDIR_ORDER, GFP_KERNEL);
+   ret = kmem_cache_alloc(pgtable_cache, GFP_KERNEL | __GFP_ZERO);
 #else
ret = (pgd_t *)__get_free_pages(GFP_KERNEL|__GFP_ZERO,
PGDIR_ORDER - PAGE_SHIFT);
@@ -90,7 +102,7 @@ pgd_t *pgd_alloc(struct mm_struct *mm)
 void pgd_free(struct mm_struct *mm, pgd_t *pgd)
 {
 #ifndef CONFIG_PPC_4K_PAGES
-   kfree((void *)pgd);
+   kmem_cache_free(pgtable_cache, (void *)pgd);
 #else
free_pages((unsigned long)pgd, PGDIR_ORDER - PAGE_SHIFT);
 #endif
-- 
2.1.0

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[PATCH 01/11] powerpc/8xx: remove remaining unnecessary code in FixupDAR

2014-12-16 Thread Christophe Leroy 
Since commit 33fb845a6f01 ("powerpc/8xx: Don't use MD_TWC for walk"), MD_EPN and
MD_TWC are not writen anymore in FixupDAR so saving r3 has become useless.

Signed-off-by: Christophe Leroy 

---
 arch/powerpc/kernel/head_8xx.S | 6 --
 1 file changed, 6 deletions(-)

diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index 3d4b8ee..79b8a23 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -532,9 +532,6 @@ DARFixed:/* Return from dcbx instruction bug workaround */
  /* define if you don't want to use self modifying code */
 #define NO_SELF_MODIFYING_CODE
 FixupDAR:/* Entry point for dcbx workaround. */
-#ifdef CONFIG_8xx_CPU6
-   mtspr   SPRN_DAR, r3
-#endif
mtspr   SPRN_SPRG_SCRATCH2, r10
/* fetch instruction from memory. */
mfspr   r10, SPRN_SRR0
@@ -551,9 +548,6 @@ FixupDAR:/* Entry point for dcbx workaround. */
/* Extract level 2 index */
rlwinm  r11, r11, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29
lwzxr11, r10, r11   /* Get the pte */
-#ifdef CONFIG_8xx_CPU6
-   mfspr   r3, SPRN_DAR
-#endif
/* concat physical page address(r11) and page offset(r10) */
mfspr   r10, SPRN_SRR0
rlwimi  r11, r10, 0, 32 - PAGE_SHIFT, 31
-- 
2.1.0

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[PATCH 06/11] powerpc/8xx: Remove duplicated code in set_context()

2014-12-16 Thread Christophe Leroy 
Signed-off-by: Christophe Leroy 

---
 arch/powerpc/kernel/head_8xx.S | 10 --
 1 file changed, 4 insertions(+), 6 deletions(-)

diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index aa45225..b227902e 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -848,23 +848,21 @@ _GLOBAL(set_context)
 
li  r5, (swapper_pg_dir-PAGE_OFFSET)@l
sub r4, r4, r5
+   tophys  (r4, r4)
 #ifdef CONFIG_8xx_CPU6
lis r6, cpu6_errata_word@h
ori r6, r6, cpu6_errata_word@l
-   tophys  (r4, r4)
li  r7, 0x3f80
stw r7, 12(r6)
lwz r7, 12(r6)
+#endif
 mtspr   SPRN_M_TW, r4   /* Update MMU base address */
+#ifdef CONFIG_8xx_CPU6
li  r7, 0x3380
stw r7, 12(r6)
lwz r7, 12(r6)
-mtspr   SPRN_M_CASID, r3 /* Update context */
-#else
-mtspr   SPRN_M_CASID,r3/* Update context */
-   tophys  (r4, r4)
-   mtspr   SPRN_M_TW, r4   /* and pgd */
 #endif
+mtspr   SPRN_M_CASID, r3 /* Update context */
SYNC
blr
 
-- 
2.1.0

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Re: Disabled LocalPlus Controller (LPC) clock on MPC512x

2014-12-16 Thread Alexander Popov 

02.12.2014 13:47, Matteo Facchinetti пишет:

On 26/11/2014 12:49, Alexander Popov wrote:

Hello.

Hi.


Thanks for your reply, Matteo.
I've looked deeper and have more information about the crash.


My Freescale TWR-MPC5125 board instantly reboots if I touch
any physical address on the LocalPlus Bus (LPB) for the first time
when Linux has already booted.

This effect is reproduced by using /dev/mem or loading a kernel module
which works with any peripherals on LPB.

It took me some time to find out that such crash is caused by
clk_disable_unused() in drivers/clk/clk.c, which disables
LocalPlus Controller (LPC) clock if I don't touch LPB addresses in the
previous initcalls.


My first diagnosis was not correct: clk_disable_unused() doesn't disable
LPC clock because in arch/powerpc/platforms/512x/clock-commonclk.c
we call:
clk_prepare_enable(clks[MPC512x_CLK_LPC]);

But clk_disable_unused() disables NFC clock as unused which seems to be
a real reason of board crash.


So starting Linux with clk_ignore_unused bootparam
or inserting dummy LPB reading to some initcall is a temporary fix.


In fact clk_ignore_unused bootparam helps to avoid disabling NFC clock.
The board crash is reproduced again if I perform the following steps:
1. disable NFC clock in uboot by clearing NFC_EN bit in SCCR1 register,
2. boot Linux with clk_ignore_unused,
3. touch any LPB address.

At the same time disabling NFC clock and reading from LPB certainly
in uboot doesn't make MPC5125 reset instantly. So I can't reproduce
the crash in uboot. It looks like we do something wrong in Linux.


   - may be good to enable MPC512x_CLK_LPC only when localbus is enabled
by the dts
   - if enabled, MPC512x_CLK_LPC have to setup with CLK_IGNORE_UNUSED
flag because never get claimed by any driver.


This approach didn't help to fix the crash because in fact
clk_disable_unused() doesn't disable LPC clock as I wrote above.


I put in CC "Gerhard Sittig" also beacuse it might be interesting to
know his point of view as the author of mpc512x common clock driver.


Surely. Thanks.

Best regards,
Alexander

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