Re: [PATCH] powerpc/fsl: Add empty ranges to etsec2 dts files
This was a sort of unfortunate revelation on how things ‘change’.
While as it is, I found this problem, and ‘fixed’ my device tree source, had
this been for units ‘fielded’, I have to sleuth through some amount of kernel
code to find where the OF tree was parsed, and then ‘fix’ the kernel, as
changing the FDT eeprom image is not really a ‘good’ option for
units that are in use, and need a firmware update.
John Clark.
On Jan 14, 2015, at 12:35 PM, Martin Hicks [via linuxppc]
ml-node+s10917n8877...@n7.nabble.com wrote:
Perfect. I'm glad there's a patch.
mh
On Mon, Jan 12, 2015 at 4:31 PM, Scott Wood [hidden email] wrote:
On Mon, 2015-01-12 at 10:27 -0500, Martin Hicks wrote:
With an earlier change (746c9e9f - Fix PowerPC address parsing hack),
ethernet
has broken on Freescale boards such as the P1022. All ranges used by the
ethernet controllers are also covered by sub-devices that properly
declared the used ranges. The error shown is:
fsl-gianfar: probe of soc@ffe0:ethernet@b failed with error -12
Signed-off-by: Martin Hicks [hidden email]
---
arch/powerpc/boot/dts/fsl/pq3-etsec2-0.dtsi |1 +
arch/powerpc/boot/dts/fsl/pq3-etsec2-1.dtsi |1 +
arch/powerpc/boot/dts/fsl/pq3-etsec2-2.dtsi |1 +
3 files changed, 3 insertions(+)
http://patchwork.ozlabs.org/patch/422446/
diff --git a/arch/powerpc/boot/dts/fsl/pq3-etsec2-0.dtsi
b/arch/powerpc/boot/dts/fsl/pq3-etsec2-0.dtsi
index 1382fec..d1a6c48 100644
--- a/arch/powerpc/boot/dts/fsl/pq3-etsec2-0.dtsi
+++ b/arch/powerpc/boot/dts/fsl/pq3-etsec2-0.dtsi
@@ -43,6 +43,7 @@ mdio@24000 {
ethernet@b {
#address-cells = 1;
#size-cells = 1;
+ ranges = ;
The = is usually omitted for empty properties.
-Scott
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Re: [PATCH 1/2] MAINTAINERS: ibmvscsi driver maintainer change
On 01/12/2015 06:31 PM, Tyrel Datwyler wrote: Change maintainer of ibmvscsi driver to Tyrel Datwyler. Signed-off-by: Tyrel Datwyler tyr...@linux.vnet.ibm.com Cc: Nathan Fontenot nf...@linux.vnet.ibm.com Cc: Brian King brk...@linux.vnet.ibm.com Acked-by: Nathan Fontenot nf...@linux.vnet.ibm.com --- MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index 79b2e4b..a646b94 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4754,7 +4754,7 @@ S: Supported F: drivers/net/ethernet/ibm/ibmveth.* IBM Power Virtual SCSI Device Drivers -M: Nathan Fontenot nf...@linux.vnet.ibm.com +M: Tyrel Datwyler tyr...@linux.vnet.ibm.com L: linux-s...@vger.kernel.org S: Supported F: drivers/scsi/ibmvscsi/ibmvscsi* ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] powerpc/fsl: Add empty ranges to etsec2 dts files
Perfect. I'm glad there's a patch.
mh
On Mon, Jan 12, 2015 at 4:31 PM, Scott Wood scottw...@freescale.com wrote:
On Mon, 2015-01-12 at 10:27 -0500, Martin Hicks wrote:
With an earlier change (746c9e9f - Fix PowerPC address parsing hack),
ethernet
has broken on Freescale boards such as the P1022. All ranges used by the
ethernet controllers are also covered by sub-devices that properly
declared the used ranges. The error shown is:
fsl-gianfar: probe of soc@ffe0:ethernet@b failed with error -12
Signed-off-by: Martin Hicks m...@bork.org
---
arch/powerpc/boot/dts/fsl/pq3-etsec2-0.dtsi |1 +
arch/powerpc/boot/dts/fsl/pq3-etsec2-1.dtsi |1 +
arch/powerpc/boot/dts/fsl/pq3-etsec2-2.dtsi |1 +
3 files changed, 3 insertions(+)
http://patchwork.ozlabs.org/patch/422446/
diff --git a/arch/powerpc/boot/dts/fsl/pq3-etsec2-0.dtsi
b/arch/powerpc/boot/dts/fsl/pq3-etsec2-0.dtsi
index 1382fec..d1a6c48 100644
--- a/arch/powerpc/boot/dts/fsl/pq3-etsec2-0.dtsi
+++ b/arch/powerpc/boot/dts/fsl/pq3-etsec2-0.dtsi
@@ -43,6 +43,7 @@ mdio@24000 {
ethernet@b {
#address-cells = 1;
#size-cells = 1;
+ ranges = ;
The = is usually omitted for empty properties.
-Scott
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[PATCH] powerpc/mpic: Add DT option to skip readback after EOI
The readback is necessary in order to handle PCI posted
writes, or when the MPIC is handling interrupts in a loop
(ppc_md.get_irq). Newer MPIC versions don't require this
readback. Leave the option configurable using a device
tree entry.
This saves a MMIO trap per interrupt.
Signed-off-by: Scott Wood scottw...@freescale.com
Signed-off-by: Bogdan Purcareata bogdan.purcare...@freescale.com
---
Documentation/devicetree/bindings/powerpc/fsl/mpic.txt | 13 +
arch/powerpc/include/asm/mpic.h| 2 ++
arch/powerpc/sysdev/mpic.c | 8 +++-
3 files changed, 22 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/mpic.txt
b/Documentation/devicetree/bindings/powerpc/fsl/mpic.txt
index dc57446..9789094 100644
--- a/Documentation/devicetree/bindings/powerpc/fsl/mpic.txt
+++ b/Documentation/devicetree/bindings/powerpc/fsl/mpic.txt
@@ -77,6 +77,19 @@ PROPERTIES
in the global feature registers. If specified, this field will
override the value read from MPIC_GREG_FEATURE_LAST_SRC.
+ - mpic-eoi-no-readback
+ Usage: optional
+ Value type: empty
+ Definition: The presence of this property specifies that the
+ MPIC will not issue a readback when delivering the EOI for an
+ external interrupt. The readback operation is done by reading
+ the CPU WHOAMI register after writing to the CPU EOI register.
+ Originally, this was required due to the fact that the MPIC
+ operates at lower frequencies, or in scenarios where the MPIC
+ is connected through PCI with write posting. This is not the
+ case in an emulated environment (e.g. KVM guest), or in scenarios
+ where interrupts are not handled in a loop of get_irq() calls.
+
INTERRUPT SPECIFIER DEFINITION
Interrupt specifiers consists of 4 cells encoded as
diff --git a/arch/powerpc/include/asm/mpic.h b/arch/powerpc/include/asm/mpic.h
index 754f93d..e2a4146 100644
--- a/arch/powerpc/include/asm/mpic.h
+++ b/arch/powerpc/include/asm/mpic.h
@@ -386,6 +386,8 @@ extern struct bus_type mpic_subsys;
* from the BRR1 register).
*/
#define MPIC_FSL_HAS_EIMR 0x0001
+/* Dont bother with readback after MPIC EOI */
+#define MPIC_EOI_NO_READBACK 0x0002
/* MPIC HW modification ID */
#define MPIC_REGSET_MASK 0xf000
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index f3e8624..431f68e 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -656,7 +656,9 @@ static inline struct mpic * mpic_from_irq_data(struct
irq_data *d)
static inline void mpic_eoi(struct mpic *mpic)
{
mpic_cpu_write(MPIC_INFO(CPU_EOI), 0);
- (void)mpic_cpu_read(MPIC_INFO(CPU_WHOAMI));
+
+ if (!(mpic-flags MPIC_EOI_NO_READBACK))
+ (void)mpic_cpu_read(MPIC_INFO(CPU_WHOAMI));
}
/*
@@ -1290,6 +1292,10 @@ struct mpic * __init mpic_alloc(struct device_node *node,
flags |= MPIC_SINGLE_DEST_CPU;
if (of_device_is_compatible(node, fsl,mpic))
flags |= MPIC_FSL | MPIC_LARGE_VECTORS;
+ if (of_get_property(node, mpic-eoi-no-readback, NULL)) {
+ pr_debug(mpic: no readback activated);
+ flags |= MPIC_EOI_NO_READBACK;
+ }
mpic = kzalloc(sizeof(struct mpic), GFP_KERNEL);
if (mpic == NULL)
--
2.1.3
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Re: [PATCH v3 1/3] powerpc/nvram: move generic code for nvram and pstore
On 01/14/2015 10:01 AM, Michael Ellerman wrote: On Wed, 2014-12-24 at 17:28 +0530, Hari Bathini wrote: With minor checks, we can move most of the code for nvram under pseries to a common place to be re-used by other powerpc platforms like powernv. This patch moves such common code to arch/powerpc/kernel/nvram_64.c file. As I said in my reply to the previous version: ... you need to keep in mind that it is very common for us to build kernels with both POWERNV=y and PSERIES=y. So you need to make sure you're only using CONFIG_PPC_PSERIES to protect things that are optional on pseries. Not things that we *shouldn't* be doing on powernv. we could as well do away with the PPC_PSERIES flag in a couple of places in arch/powerpc/kernel/nvram_64.c, but doing that will unnecessarily add few extra variables for !PPC_PSERIES case. Please explain in your commit message how you have dealt with that. Sure. Will update the changelog Also, you broke the build for every config that doesn't have CONFIG_PPC_PSERIES, all 95 of them. This is pasemi_defconfig for example: My bad!clobbering_unread_rtas_event should have been static inline while defining under !PPC_PSERIES Thanks Hari LD arch/powerpc/mm/built-in.o arch/powerpc/mm/init_64.o: In function `clobbering_unread_rtas_event': init_64.c:(.opd+0x48): multiple definition of `clobbering_unread_rtas_event' arch/powerpc/mm/mem.o:mem.c:(.opd+0x90): first defined here arch/powerpc/mm/init_64.o: In function `.clobbering_unread_rtas_event': init_64.c:(.text+0x80): multiple definition of `.clobbering_unread_rtas_event' arch/powerpc/mm/mem.o:mem.c:(.text+0x2c0): first defined here CC arch/powerpc/kernel/udbg.o /home/kisskb/slave/src/scripts/Makefile.build:336: recipe for target 'arch/powerpc/mm/built-in.o' failed make[2]: *** [arch/powerpc/mm/built-in.o] Error 1 /home/kisskb/slave/src/Makefile:938: recipe for target 'arch/powerpc/mm' failed make[1]: *** [arch/powerpc/mm] Error 2 make[1]: *** Waiting for unfinished jobs cheers ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH] powerpc: Remove unused CPU_FTR_IABR
We removed the last usage of CPU_FTR_IABR in commit 1ad7d70562ee powerpc/xmon: Enable HW instruction breakpoint on POWER8. Mark it as free. Signed-off-by: Michael Ellerman m...@ellerman.id.au --- arch/powerpc/include/asm/cputable.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h index 22d5a7da9e68..5cf5a6d10685 100644 --- a/arch/powerpc/include/asm/cputable.h +++ b/arch/powerpc/include/asm/cputable.h @@ -165,7 +165,7 @@ extern const char *powerpc_base_platform; #define CPU_FTR_ARCH_201 LONG_ASM_CONST(0x0002) #define CPU_FTR_ARCH_206 LONG_ASM_CONST(0x0004) #define CPU_FTR_ARCH_207S LONG_ASM_CONST(0x0008) -#define CPU_FTR_IABR LONG_ASM_CONST(0x0010) +/* Free LONG_ASM_CONST(0x0010) */ #define CPU_FTR_MMCRA LONG_ASM_CONST(0x0020) #define CPU_FTR_CTRL LONG_ASM_CONST(0x0040) #define CPU_FTR_SMTLONG_ASM_CONST(0x0080) -- 2.1.0 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] powerpc: powernv: winkle: Restore LPCR with LPCR_PECE1 cleared
On Wed, 2015-01-14 at 16:43 +0530, Shreyas B. Prabhu wrote:
LPCR_PECE1 bit controls whether decrementer interrupts are allowed to
cause exit from power-saving mode. While waking up from winkle, restoring
LPCR with LPCR_PECE1 set (i.e Decrementer interrupts allowed) can cause
issue in the following scenario:
- All the threads in a core are offlined. The core enters deep winkle.
- Spurious interrupt wakes up a thread in the core. Here LPCR is restored
with LPCR_PECE1 bit set.
- Since it was a spurious interrupt on a offline thread, the thread clears
the interrupt and goes back to winkle.
- Here before the thread executes winkle and puts the core into deep winkle,
if a decrementer interrupt occurs on any of the sibling threads in the core
that thread wakes up.
- Since in offline loop we are flushing interrupt only in case of external
interrupt, the decrementer interrupt does not get flushed. So at this stage
the thread is stuck in this is loop of waking up at 0x100 due to decrementer
interrupt, not flushing the interrupt as only external interrupts get
flushed,
entering winkle, waking up at 0x100 again.
Fix this by programming PORE to restore LPCR with LPCR_PECE1 bit
cleared when waking up from winkle.
That sounds good.
But this makes the third place where we clear LPCR_PECE1, in addition to:
static int fastsleep_loop(struct cpuidle_device *dev,
struct cpuidle_driver *drv,
int index)
{
...
new_lpcr = old_lpcr;
/* Do not exit powersave upon decrementer as we've setup the timer
* offload.
*/
new_lpcr = ~LPCR_PECE1;
mtspr(SPRN_LPCR, new_lpcr);
And:
static void pnv_smp_cpu_kill_self(void)
{
...
/* We don't want to take decrementer interrupts while we are offline,
* so clear LPCR:PECE1. We keep PECE2 enabled.
*/
mtspr(SPRN_LPCR, mfspr(SPRN_LPCR) ~(u64)LPCR_PECE1);
So perhaps we can capture that logic in one place somehow?
cheers
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[PATCH] powerpc: Rename _TIF_SYSCALL_T_OR_A to _TIF_SYSCALL_DOTRACE
Once upon a time, at least 9 years ago ( 2.6.12), _TIF_SYSCALL_T_OR_A meant TRACE or AUDIT. But these days it means TRACE or AUDIT or SECCOMP or TRACEPOINT or NOHZ. All of those are implemented via syscall_dotrace() so rename the flag to that to try and clarify things. Signed-off-by: Michael Ellerman m...@ellerman.id.au --- arch/powerpc/include/asm/thread_info.h | 2 +- arch/powerpc/kernel/entry_32.S | 6 +++--- arch/powerpc/kernel/entry_64.S | 6 +++--- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/powerpc/include/asm/thread_info.h b/arch/powerpc/include/asm/thread_info.h index ebc4f165690a..c1efa05613f0 100644 --- a/arch/powerpc/include/asm/thread_info.h +++ b/arch/powerpc/include/asm/thread_info.h @@ -124,7 +124,7 @@ static inline struct thread_info *current_thread_info(void) #define _TIF_SYSCALL_TRACEPOINT(1TIF_SYSCALL_TRACEPOINT) #define _TIF_EMULATE_STACK_STORE (1TIF_EMULATE_STACK_STORE) #define _TIF_NOHZ (1TIF_NOHZ) -#define _TIF_SYSCALL_T_OR_A(_TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT | \ +#define _TIF_SYSCALL_DOTRACE (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT | \ _TIF_SECCOMP | _TIF_SYSCALL_TRACEPOINT | \ _TIF_NOHZ) diff --git a/arch/powerpc/kernel/entry_32.S b/arch/powerpc/kernel/entry_32.S index 10a093579191..da6379550fd2 100644 --- a/arch/powerpc/kernel/entry_32.S +++ b/arch/powerpc/kernel/entry_32.S @@ -337,7 +337,7 @@ _GLOBAL(DoSyscall) #endif /* CONFIG_TRACE_IRQFLAGS */ CURRENT_THREAD_INFO(r10, r1) lwz r11,TI_FLAGS(r10) - andi. r11,r11,_TIF_SYSCALL_T_OR_A + andi. r11,r11,_TIF_SYSCALL_DOTRACE bne-syscall_dotrace syscall_dotrace_cont: cmplwi 0,r0,NR_syscalls @@ -364,7 +364,7 @@ ret_from_syscall: MTMSRD(r10) lwz r9,TI_FLAGS(r12) li r8,-_LAST_ERRNO - andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP|_TIF_USER_WORK_MASK|_TIF_PERSYSCALL_MASK) + andi. r0,r9,(_TIF_SYSCALL_DOTRACE|_TIF_SINGLESTEP|_TIF_USER_WORK_MASK|_TIF_PERSYSCALL_MASK) bne-syscall_exit_work cmplw 0,r3,r8 blt+syscall_exit_cont @@ -501,7 +501,7 @@ syscall_exit_work: subir12,r12,TI_FLAGS 4: /* Anything which requires enabling interrupts? */ - andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP) + andi. r0,r9,(_TIF_SYSCALL_DOTRACE|_TIF_SINGLESTEP) beq ret_from_except /* Re-enable interrupts. There is no need to trace that with diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S index 194e46dcf08d..3291ed148bdf 100644 --- a/arch/powerpc/kernel/entry_64.S +++ b/arch/powerpc/kernel/entry_64.S @@ -151,7 +151,7 @@ END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLPAR) #endif CURRENT_THREAD_INFO(r11, r1) ld r10,TI_FLAGS(r11) - andi. r11,r10,_TIF_SYSCALL_T_OR_A + andi. r11,r10,_TIF_SYSCALL_DOTRACE bne syscall_dotrace .Lsyscall_dotrace_cont: cmpldi 0,r0,NR_syscalls @@ -214,7 +214,7 @@ syscall_exit: ld r9,TI_FLAGS(r12) li r11,-_LAST_ERRNO - andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP|_TIF_USER_WORK_MASK|_TIF_PERSYSCALL_MASK) + andi. r0,r9,(_TIF_SYSCALL_DOTRACE|_TIF_SINGLESTEP|_TIF_USER_WORK_MASK|_TIF_PERSYSCALL_MASK) bne-syscall_exit_work cmpld r3,r11 ld r5,_CCR(r1) @@ -307,7 +307,7 @@ syscall_exit_work: 4: /* Anything else left to do? */ SET_DEFAULT_THREAD_PPR(r3, r10) /* Set thread.ppr = 3 */ - andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP) + andi. r0,r9,(_TIF_SYSCALL_DOTRACE|_TIF_SINGLESTEP) beq ret_from_except_lite /* Re-enable interrupts */ -- 2.1.0 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH v3 1/3] powerpc/nvram: move generic code for nvram and pstore
On Wed, 2015-01-14 at 23:35 +0530, Hari Bathini wrote: On 01/14/2015 10:01 AM, Michael Ellerman wrote: On Wed, 2014-12-24 at 17:28 +0530, Hari Bathini wrote: With minor checks, we can move most of the code for nvram under pseries to a common place to be re-used by other powerpc platforms like powernv. This patch moves such common code to arch/powerpc/kernel/nvram_64.c file. As I said in my reply to the previous version: ... you need to keep in mind that it is very common for us to build kernels with both POWERNV=y and PSERIES=y. So you need to make sure you're only using CONFIG_PPC_PSERIES to protect things that are optional on pseries. Not things that we *shouldn't* be doing on powernv. we could as well do away with the PPC_PSERIES flag in a couple of places in arch/powerpc/kernel/nvram_64.c, but doing that will unnecessarily add few extra variables for !PPC_PSERIES case. Yep. I'm happy for them to be there, I just want you to explain in the changelog that you've thought about the PSERIES=y POWERNV=y case and why the code makes sense for that configuration. Please explain in your commit message how you have dealt with that. Sure. Will update the changelog Thanks. Also, you broke the build for every config that doesn't have CONFIG_PPC_PSERIES, all 95 of them. This is pasemi_defconfig for example: My bad! clobbering_unread_rtas_event should have been static inline while defining under !PPC_PSERIES Correct. Please make sure you test build at least some of the other configurations in future. I realise it's too time consuming to build all of them, but ideally for every config symbol you use in your patch you need to build a kernel config where that symbol =y and =n (and =m if it's tristate). cheers ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH V11 04/17] PCI: Store VF BAR size in pci_sriov
Currently we don't store the VF BAR size, and each time we calculate the
size by dividing the PF's IOV BAR size by total_VFs.
This patch stores the VF BAR size in pci_sriov and introduces a function to
retrieve it. Also, it adds a log message to show the total PF's IOV BAR
size.
Signed-off-by: Wei Yang weiy...@linux.vnet.ibm.com
---
drivers/pci/iov.c | 28
drivers/pci/pci.h |2 ++
include/linux/pci.h |3 +++
3 files changed, 25 insertions(+), 8 deletions(-)
diff --git a/drivers/pci/iov.c b/drivers/pci/iov.c
index 5f48201..b43628b 100644
--- a/drivers/pci/iov.c
+++ b/drivers/pci/iov.c
@@ -100,6 +100,14 @@ static void virtfn_remove_bus(struct pci_bus *physbus,
struct pci_bus *virtbus)
pci_remove_bus(virtbus);
}
+resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
+{
+ if (!dev-is_physfn)
+ return 0;
+
+ return dev-sriov-res[resno - PCI_IOV_RESOURCES];
+}
+
static int virtfn_add(struct pci_dev *dev, int id, int reset)
{
int i;
@@ -135,8 +143,7 @@ static int virtfn_add(struct pci_dev *dev, int id, int
reset)
continue;
virtfn-resource[i].name = pci_name(virtfn);
virtfn-resource[i].flags = res-flags;
- size = resource_size(res);
- do_div(size, iov-total_VFs);
+ size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
virtfn-resource[i].start = res-start + size * id;
virtfn-resource[i].end = virtfn-resource[i].start + size - 1;
rc = request_resource(res, virtfn-resource[i]);
@@ -419,6 +426,12 @@ found:
pgsz = ~(pgsz - 1);
pci_write_config_dword(dev, pos + PCI_SRIOV_SYS_PGSIZE, pgsz);
+ iov = kzalloc(sizeof(*iov), GFP_KERNEL);
+ if (!iov) {
+ rc = -ENOMEM;
+ goto failed;
+ }
+
nres = 0;
for (i = 0; i PCI_SRIOV_NUM_BARS; i++) {
res = dev-resource + PCI_IOV_RESOURCES + i;
@@ -430,16 +443,15 @@ found:
rc = -EIO;
goto failed;
}
+ iov-res[res - dev-resource - PCI_IOV_RESOURCES] =
+ resource_size(res);
res-end = res-start + resource_size(res) * total - 1;
+ dev_info(dev-dev, VF BAR%d: %pR (for %d VFs),
+ (int)(res - dev-resource - PCI_IOV_RESOURCES),
+ res, total);
nres++;
}
- iov = kzalloc(sizeof(*iov), GFP_KERNEL);
- if (!iov) {
- rc = -ENOMEM;
- goto failed;
- }
-
iov-pos = pos;
iov-nres = nres;
iov-ctrl = ctrl;
diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
index 94faf97..b1c9fdd 100644
--- a/drivers/pci/pci.h
+++ b/drivers/pci/pci.h
@@ -241,6 +241,8 @@ struct pci_sriov {
struct pci_dev *dev;/* lowest numbered PF */
struct pci_dev *self; /* this PF */
struct mutex lock; /* lock for VF bus */
+ resource_size_t res[PCI_SRIOV_NUM_BARS];
+ /* VF BAR size */
};
#ifdef CONFIG_PCI_ATS
diff --git a/include/linux/pci.h b/include/linux/pci.h
index ae7a7ea..f0b5f87 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -1670,6 +1670,7 @@ int pci_num_vf(struct pci_dev *dev);
int pci_vfs_assigned(struct pci_dev *dev);
int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
int pci_sriov_get_totalvfs(struct pci_dev *dev);
+resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
#else
static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
{
@@ -1689,6 +1690,8 @@ static inline int pci_sriov_set_totalvfs(struct pci_dev
*dev, u16 numvfs)
{ return 0; }
static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
{ return 0; }
+static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int
resno)
+{ return 0; }
#endif
#if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
--
1.7.9.5
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[PATCH V11 05/17] PCI: Take additional PF's IOV BAR alignment in sizing and assigning
At resource sizing/assigning stage, resources are divided into two lists,
requested list and additional list, while the alignement of the additional
IOV BAR is not taken into the sizing and assigning procedure.
This is reasonable in the original implementation, since IOV BAR's
alignment is mostly the size of a PF BAR alignemt. This means the alignment
is already taken into consideration. While this rule may be violated on
some platform, eg. PowerNV platform.
This patch takes the additional IOV BAR alignment in sizing and assigning
stage explicitly. When system MMIO space is not enough, the PF's IOV BAR
alignment will not contribute to the bridge. When system MMIO space is
enough, the additional alignment will contribute to the bridge.
Also it take advantage of pci_dev_resource::min_align to store this
additional alignment.
Signed-off-by: Wei Yang weiy...@linux.vnet.ibm.com
---
drivers/pci/setup-bus.c | 85 +++
1 file changed, 71 insertions(+), 14 deletions(-)
diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c
index 0482235..08252c7 100644
--- a/drivers/pci/setup-bus.c
+++ b/drivers/pci/setup-bus.c
@@ -99,8 +99,8 @@ static void remove_from_list(struct list_head *head,
}
}
-static resource_size_t get_res_add_size(struct list_head *head,
- struct resource *res)
+static struct pci_dev_resource *res_to_dev_res(struct list_head *head,
+ struct resource *res)
{
struct pci_dev_resource *dev_res;
@@ -109,17 +109,37 @@ static resource_size_t get_res_add_size(struct list_head
*head,
int idx = res - dev_res-dev-resource[0];
dev_printk(KERN_DEBUG, dev_res-dev-dev,
-res[%d]=%pR get_res_add_size add_size %llx\n,
+res[%d]=%pR res_to_dev_res add_size %llx
min_align %llx\n,
idx, dev_res-res,
-(unsigned long long)dev_res-add_size);
+(unsigned long long)dev_res-add_size,
+(unsigned long long)dev_res-min_align);
- return dev_res-add_size;
+ return dev_res;
}
}
- return 0;
+ return NULL;
+}
+
+static resource_size_t get_res_add_size(struct list_head *head,
+ struct resource *res)
+{
+ struct pci_dev_resource *dev_res;
+
+ dev_res = res_to_dev_res(head, res);
+ return dev_res ? dev_res-add_size : 0;
+}
+
+static resource_size_t get_res_add_align(struct list_head *head,
+ struct resource *res)
+{
+ struct pci_dev_resource *dev_res;
+
+ dev_res = res_to_dev_res(head, res);
+ return dev_res ? dev_res-min_align : 0;
}
+
/* Sort resources by alignment */
static void pdev_sort_resources(struct pci_dev *dev, struct list_head *head)
{
@@ -368,8 +388,9 @@ static void __assign_resources_sorted(struct list_head
*head,
LIST_HEAD(save_head);
LIST_HEAD(local_fail_head);
struct pci_dev_resource *save_res;
- struct pci_dev_resource *dev_res, *tmp_res;
+ struct pci_dev_resource *dev_res, *tmp_res, *dev_res2;
unsigned long fail_type;
+ resource_size_t add_align, align;
/* Check if optional add_size is there */
if (!realloc_head || list_empty(realloc_head))
@@ -384,10 +405,38 @@ static void __assign_resources_sorted(struct list_head
*head,
}
/* Update res in head list with add_size in realloc_head list */
- list_for_each_entry(dev_res, head, list)
+ list_for_each_entry_safe(dev_res, tmp_res, head, list) {
dev_res-res-end += get_res_add_size(realloc_head,
dev_res-res);
+ /*
+* There are two kinds additional resources in the list:
+* 1. bridge resource -- IORESOURCE_STARTALIGN
+* 2. SRIOV resource -- IORESOURCE_SIZEALIGN
+* Here just fix the additional alignment for bridge
+*/
+ if (!(dev_res-res-flags IORESOURCE_STARTALIGN))
+ continue;
+
+ add_align = get_res_add_align(realloc_head, dev_res-res);
+
+ /* Reorder the list by their alignment */
+ if (add_align dev_res-res-start) {
+ dev_res-res-start = add_align;
+ dev_res-res-end = add_align +
+ resource_size(dev_res-res);
+
+ list_for_each_entry(dev_res2, head, list) {
+ align = pci_resource_alignment(dev_res2-dev,
+ dev_res2-res);
+ if
[PATCH V11 06/17] powerpc/pci: Add PCI resource alignment documentation
In order to enable SRIOV on PowerNV platform, the PF's IOV BAR needs to be adjusted: 1. size expaned 2. aligned to M64BT size This patch documents this change on the reason and how. Signed-off-by: Wei Yang weiy...@linux.vnet.ibm.com --- .../powerpc/pci_iov_resource_on_powernv.txt| 215 1 file changed, 215 insertions(+) create mode 100644 Documentation/powerpc/pci_iov_resource_on_powernv.txt diff --git a/Documentation/powerpc/pci_iov_resource_on_powernv.txt b/Documentation/powerpc/pci_iov_resource_on_powernv.txt new file mode 100644 index 000..10d4ac2 --- /dev/null +++ b/Documentation/powerpc/pci_iov_resource_on_powernv.txt @@ -0,0 +1,215 @@ +Wei Yang weiy...@linux.vnet.ibm.com +Benjamin Herrenschmidt b...@au1.ibm.com +26 Aug 2014 + +This document describes the requirement from hardware for PCI MMIO resource +sizing and assignment on PowerNV platform and how generic PCI code handle this +requirement. The first two sections describes the concept to PE and the +implementation on P8 (IODA2) + +1. General Introduction on the Purpose of PE +PE stands for Partitionable Endpoint. + +The concept of PE is a way to group the various resources associated +with a device or a set of device to provide isolation between partitions +(ie. filtering of DMA, MSIs etc...) and to provide a mechanism to freeze +a device that is causing errors in order to limit the possibility of +propagation of bad data. + +There is thus, in HW, a table of PE states that contains a pair of +frozen state bits (one for MMIO and one for DMA, they get set together +but can be cleared independently) for each PE. + +When a PE is frozen, all stores in any direction are dropped and all loads +return all 1's value. MSIs are also blocked. There's a bit more state that +captures things like the details of the error that caused the freeze etc... +but that's not critical. + +The interesting part is how the various type of PCIe transactions (MMIO, +DMA,...) are matched to their corresponding PEs. + +Following section provides a rough description of what we have on P8 (IODA2). +Keep in mind that this is all per PHB (host bridge). Each PHB is a completely +separate HW entity which replicates the entire logic, so has its own set +of PEs etc... + +2. Implementation of PE on P8 (IODA2) +First, P8 has 256 PEs per PHB. + + * Inbound + +For DMA, MSIs and inbound PCIe error messages, we have a table (in memory but +accessed in HW by the chip) that provides a direct correspondence between +a PCIe RID (bus/dev/fn) with a PE number. We call this the RTT. + + - For DMA we then provide an entire address space for each PE that can contains +two windows, depending on the value of PCI bit 59. Each window can then be +configured to be remapped via a TCE table (iommu translation table), which has +various configurable characteristics which we can describe another day. + + - For MSIs, we have two windows in the address space (one at the top of the 32-bit +space and one much higher) which, via a combination of the address and MSI value, +will result in one of the 2048 interrupts per bridge being triggered. There's +a PE value in the interrupt controller descriptor table as well which is compared +with the PE obtained from the RTT to authorize the device to emit that specific +interrupt. + + - Error messages just use the RTT. + + * Outbound. That's where the tricky part is. + +The PHB basically has a concept of windows from the CPU address space to the +PCI address space. There is one M32 window and 16 M64 windows. They have different +characteristics. First what they have in common: they are configured to forward a +configurable portion of the CPU address space to the PCIe bus and must be naturally +aligned power of two in size. The rest is different: + + - The M32 window: + +* It is limited to 4G in size + +* It drops the top bits of the address (above the size) and replaces them with +a configurable value. This is typically used to generate 32-bit PCIe accesses. We +configure that window at boot from FW and don't touch it from Linux, it's usually +set to forward a 2G portion of address space from the CPU to PCIe +0x8000_..0x_. (Note: The top 64K are actually reserved for MSIs but +this is not a problem at this point, we just need to ensure Linux doesn't assign +anything there, the M32 logic ignores that however and will forward in that space +if we try). + +* It is divided into 256 segments of equal size. A table in the chip provides +for each of these 256 segments a PE#. That allows to essentially assign portions +of the MMIO space to PEs on a segment granularity. For a 2G window, this is 8M. + +Now, this is the main window we use in Linux today (excluding SR-IOV). We +basically use the trick of forcing the bridge MMIO windows onto a segment +alignment/granularity so that the space behind a bridge can be assigned to a PE. + +Ideally we would like to be able to have individual functions
Re: [PATCH 3/3] CXL: Add reset to sysfs
Excerpts from Ryan Grimm's message of 2015-01-15 13:56:41 +1100:
+What: /sys/class/cxl/card/reset
+Date: October 2014
+Contact:linuxppc-dev@lists.ozlabs.org
+Description:write only
+Writing 1 here will issue a PERST to card.
...
+static ssize_t reset_adapter_store(struct device *device,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+struct cxl *adapter = to_cxl_adapter(device);
+int rc;
+
+if ((rc = cxl_reset(adapter)))
+return rc;
+return count;
+}
Looks like we reset the card no matter what is written to that file?
I like the description better - add a test here to match what it says.
Cheers,
-Ian
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[PATCH V11 08/17] powrepc/pci: Refactor pci_dn
From: Gavin Shan gws...@linux.vnet.ibm.com
pci_dn is the extension of PCI device node and it's created from
device node. Unfortunately, VFs that are enabled dynamically by
PF's driver and they don't have corresponding device nodes, and
pci_dn. The patch refactors pci_dn to support VFs:
* pci_dn is organized as a hierarchy tree. VF's pci_dn is put
to the child list of pci_dn of PF's bridge. pci_dn of other
device put to the child list of pci_dn of its upstream bridge.
* VF's pci_dn is expected to be created dynamically when PF
enabling VFs. VF's pci_dn will be destroyed when PF disabling
VFs. pci_dn of other device is still created from device node
as before.
* For one particular PCI device (VF or not), its pci_dn can be
found from pdev-dev.archdata.firmware_data, PCI_DN(devnode),
or parent's list. The fast path (fetching pci_dn through PCI
device instance) is populated during early fixup time.
Signed-off-by: Gavin Shan gws...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/device.h |3 +
arch/powerpc/include/asm/pci-bridge.h | 14 +-
arch/powerpc/kernel/pci_dn.c | 242 -
arch/powerpc/platforms/powernv/pci-ioda.c | 16 ++
4 files changed, 270 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/include/asm/device.h
b/arch/powerpc/include/asm/device.h
index 38faede..29992cd 100644
--- a/arch/powerpc/include/asm/device.h
+++ b/arch/powerpc/include/asm/device.h
@@ -34,6 +34,9 @@ struct dev_archdata {
#ifdef CONFIG_SWIOTLB
dma_addr_t max_direct_dma_addr;
#endif
+#ifdef CONFIG_PPC64
+ void*firmware_data;
+#endif
#ifdef CONFIG_EEH
struct eeh_dev *edev;
#endif
diff --git a/arch/powerpc/include/asm/pci-bridge.h
b/arch/powerpc/include/asm/pci-bridge.h
index 725247b..c1b7dd5 100644
--- a/arch/powerpc/include/asm/pci-bridge.h
+++ b/arch/powerpc/include/asm/pci-bridge.h
@@ -89,6 +89,7 @@ struct pci_controller {
#ifdef CONFIG_PPC64
unsigned long buid;
+ void *firmware_data;
#endif /* CONFIG_PPC64 */
void *private_data;
@@ -150,9 +151,13 @@ static inline int isa_vaddr_is_ioport(void __iomem
*address)
struct iommu_table;
struct pci_dn {
+ int flags;
+#define PCI_DN_FLAG_IOV_VF 0x01
+
int busno; /* pci bus number */
int devfn; /* pci device and function number */
+ struct pci_dn *parent;
struct pci_controller *phb;/* for pci devices */
struct iommu_table *iommu_table; /* for phb's or bridges */
struct device_node *node; /* back-pointer to the device_node */
@@ -167,14 +172,19 @@ struct pci_dn {
#ifdef CONFIG_PPC_POWERNV
int pe_number;
#endif
+ struct list_head child_list;
+ struct list_head list;
};
/* Get the pointer to a device_node's pci_dn */
#define PCI_DN(dn) ((struct pci_dn *) (dn)-data)
+extern struct pci_dn *pci_get_pdn_by_devfn(struct pci_bus *bus,
+ int devfn);
extern struct pci_dn *pci_get_pdn(struct pci_dev *pdev);
-
-extern void * update_dn_pci_info(struct device_node *dn, void *data);
+extern struct pci_dn *add_dev_pci_info(struct pci_dev *pdev, u16 vf_num);
+extern void remove_dev_pci_info(struct pci_dev *pdev, u16 vf_num);
+extern void *update_dn_pci_info(struct device_node *dn, void *data);
static inline int pci_device_from_OF_node(struct device_node *np,
u8 *bus, u8 *devfn)
diff --git a/arch/powerpc/kernel/pci_dn.c b/arch/powerpc/kernel/pci_dn.c
index 1f61fab..6536573 100644
--- a/arch/powerpc/kernel/pci_dn.c
+++ b/arch/powerpc/kernel/pci_dn.c
@@ -32,12 +32,224 @@
#include asm/ppc-pci.h
#include asm/firmware.h
+/*
+ * The function is used to find the firmware data of one
+ * specific PCI device, which is attached to the indicated
+ * PCI bus. For VFs, their firmware data is linked to that
+ * one of PF's bridge. For other devices, their firmware
+ * data is linked to that of their bridge.
+ */
+static struct pci_dn *pci_bus_to_pdn(struct pci_bus *bus)
+{
+ struct pci_bus *pbus;
+ struct device_node *dn;
+ struct pci_dn *pdn;
+
+ /*
+* We probably have virtual bus which doesn't
+* have associated bridge.
+*/
+ pbus = bus;
+ while (pbus) {
+ if (pci_is_root_bus(pbus) || pbus-self)
+ break;
+
+ pbus = pbus-parent;
+ }
+
+ /*
+* Except virtual bus, all PCI buses should
+* have device nodes.
+*/
+ dn = pci_bus_to_OF_node(pbus);
+ pdn = dn ? PCI_DN(dn) : NULL;
+
+ return pdn;
+}
+
+struct pci_dn *pci_get_pdn_by_devfn(struct pci_bus *bus,
+ int devfn)
+{
+ struct device_node *dn = NULL;
+ struct pci_dn *parent, *pdn;
+ struct
[PATCH V11 09/17] powerpc/pci: remove pci_dn-pcidev field
The field pci_dn-pcidev is assigned but not used.
This patch removes this field.
Signed-off-by: Wei Yang weiy...@linux.vnet.ibm.com
Acked-by: Gavin Shan gws...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/pci-bridge.h |1 -
arch/powerpc/platforms/powernv/pci-ioda.c |1 -
2 files changed, 2 deletions(-)
diff --git a/arch/powerpc/include/asm/pci-bridge.h
b/arch/powerpc/include/asm/pci-bridge.h
index c1b7dd5..334e745 100644
--- a/arch/powerpc/include/asm/pci-bridge.h
+++ b/arch/powerpc/include/asm/pci-bridge.h
@@ -164,7 +164,6 @@ struct pci_dn {
int pci_ext_config_space; /* for pci devices */
- struct pci_dev *pcidev;/* back-pointer to the pci device */
#ifdef CONFIG_EEH
struct eeh_dev *edev; /* eeh device */
#endif
diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c
b/arch/powerpc/platforms/powernv/pci-ioda.c
index 5a8e6b1..665f57c 100644
--- a/arch/powerpc/platforms/powernv/pci-ioda.c
+++ b/arch/powerpc/platforms/powernv/pci-ioda.c
@@ -832,7 +832,6 @@ static void pnv_ioda_setup_same_PE(struct pci_bus *bus,
struct pnv_ioda_pe *pe)
pci_name(dev));
continue;
}
- pdn-pcidev = dev;
pdn-pe_number = pe-pe_number;
pe-dma_weight += pnv_ioda_dma_weight(dev);
if ((pe-flags PNV_IODA_PE_BUS_ALL) dev-subordinate)
--
1.7.9.5
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[PATCH V11 07/17] powerpc/pci: Don't unset pci resources for VFs
If we're going to reassign resources with flag PCI_REASSIGN_ALL_RSRC, all
resources will be cleaned out during device header fixup time and then get
reassigned by PCI core. However, the VF resources won't be reassigned and
thus, we shouldn't clean them out.
This patch adds a condition. If the pci_dev is a VF, skip the resource
unset process.
Signed-off-by: Wei Yang weiy...@linux.vnet.ibm.com
---
arch/powerpc/kernel/pci-common.c |4
1 file changed, 4 insertions(+)
diff --git a/arch/powerpc/kernel/pci-common.c b/arch/powerpc/kernel/pci-common.c
index 37d512d..889f743 100644
--- a/arch/powerpc/kernel/pci-common.c
+++ b/arch/powerpc/kernel/pci-common.c
@@ -788,6 +788,10 @@ static void pcibios_fixup_resources(struct pci_dev *dev)
pci_name(dev));
return;
}
+
+ if (dev-is_virtfn)
+ return;
+
for (i = 0; i DEVICE_COUNT_RESOURCE; i++) {
struct resource *res = dev-resource + i;
struct pci_bus_region reg;
--
1.7.9.5
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Re: [PATCH 1/3] CXL: Add image control to sysfs
While I think of it - if we change this on boot we should also change reset_image_select to match the currently loaded image. e.g. if reset_loads_image has defaulted to off and reset_image_select has defaulted to factory, but the user image has been loaded - that way we avoid unexpectedly switching to factory if the card gets reset. Nevermind - I see you have done exactly this in patch 3 :-) -Ian ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 1/3] CXL: Add image control to sysfs
On Thu, 2015-01-15 at 15:41 +1100, Ian Munsie wrote: Excerpts from Ryan Grimm's message of 2015-01-15 13:56:39 +1100: Add reset_loads_image and reset_image_select to sysfs. reset_image_select identifies which image will be loaded to the card on the next PERST. Valid entries are: user and factory. reset_loads_image defines functionality on a PERST. Value of 0 means PERST will not cause image load. A power cycle is required to load the image. Value of 1 means PERST will cause image load. sysfs updates the cxl struct in the driver then calls cxl_update_image_control to write the vals in the VSEC. Let's combine both of these into a single sysfs file, with none, user and factory options and have the show read functions handle mapping those three options to the two bits in the register. Of the two names I'd probably go with reset_image_select. Three words, all can be verbs, two can be nouns, it's not too clear. Maybe load_image_on_perst ? cheers ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH V11 15/17] powerpc/powernv: Allocate VF PE
VFs are created, when pci device is enabled.
This patch tries best to assign maximum resources and PEs for VF when pci
device is enabled. Enough M64 assigned to cover the IOV BAR, IOV BAR is
shifted to meet the PE# indicated by M64. VF's pdn-pdev and
pdn-pe_number are fixed.
Signed-off-by: Wei Yang weiy...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/pci-bridge.h |4 +
arch/powerpc/kernel/pci_dn.c | 11 +
arch/powerpc/platforms/powernv/pci-ioda.c | 451 -
arch/powerpc/platforms/powernv/pci.c | 18 ++
arch/powerpc/platforms/powernv/pci.h |7 +
5 files changed, 476 insertions(+), 15 deletions(-)
diff --git a/arch/powerpc/include/asm/pci-bridge.h
b/arch/powerpc/include/asm/pci-bridge.h
index b857ec4..d61c384 100644
--- a/arch/powerpc/include/asm/pci-bridge.h
+++ b/arch/powerpc/include/asm/pci-bridge.h
@@ -172,6 +172,10 @@ struct pci_dn {
int pe_number;
#ifdef CONFIG_PCI_IOV
u16 max_vfs;/* number of VFs IOV BAR expended */
+ u16 vf_pes; /* VF PE# under this PF */
+ int offset; /* PE# for the first VF PE */
+#define IODA_INVALID_M64(-1)
+ int m64_wins[PCI_SRIOV_NUM_BARS];
#endif /* CONFIG_PCI_IOV */
#endif
struct list_head child_list;
diff --git a/arch/powerpc/kernel/pci_dn.c b/arch/powerpc/kernel/pci_dn.c
index 6536573..36aaa8e 100644
--- a/arch/powerpc/kernel/pci_dn.c
+++ b/arch/powerpc/kernel/pci_dn.c
@@ -218,6 +218,17 @@ void remove_dev_pci_info(struct pci_dev *pdev, u16 vf_num)
struct pci_dn *pdn, *tmp;
int i;
+ /*
+* VF and VF PE is create/released dynamicly, which we need to
+* bind/unbind them. Otherwise when re-enable SRIOV, the VF and VF PE
+* would be mismatched.
+*/
+ if (pdev-is_virtfn) {
+ pdn = pci_get_pdn(pdev);
+ pdn-pe_number = IODA_INVALID_PE;
+ return;
+ }
+
/* Only support IOV PF for now */
if (!pdev-is_physfn)
return;
diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c
b/arch/powerpc/platforms/powernv/pci-ioda.c
index 62bb2eb..94fe6e1 100644
--- a/arch/powerpc/platforms/powernv/pci-ioda.c
+++ b/arch/powerpc/platforms/powernv/pci-ioda.c
@@ -45,6 +45,9 @@
#include powernv.h
#include pci.h
+/* 256M DMA window, 4K TCE pages, 8 bytes TCE */
+#define TCE32_TABLE_SIZE ((0x1000 / 0x1000) * 8)
+
static void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,
const char *fmt, ...)
{
@@ -57,11 +60,18 @@ static void pe_level_printk(const struct pnv_ioda_pe *pe,
const char *level,
vaf.fmt = fmt;
vaf.va = args;
- if (pe-pdev)
+ if (pe-flags PNV_IODA_PE_DEV)
strlcpy(pfix, dev_name(pe-pdev-dev), sizeof(pfix));
- else
+ else if (pe-flags (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
sprintf(pfix, %04x:%02x ,
pci_domain_nr(pe-pbus), pe-pbus-number);
+#ifdef CONFIG_PCI_IOV
+ else if (pe-flags PNV_IODA_PE_VF)
+ sprintf(pfix, %04x:%02x:%2x.%d,
+ pci_domain_nr(pe-parent_dev-bus),
+ (pe-rid 0xff00) 8,
+ PCI_SLOT(pe-rid), PCI_FUNC(pe-rid));
+#endif /* CONFIG_PCI_IOV*/
printk(%spci %s: [PE# %.3d] %pV,
level, pfix, pe-pe_number, vaf);
@@ -567,7 +577,7 @@ static int pnv_ioda_set_peltv(struct pnv_phb *phb,
bool is_add)
{
struct pnv_ioda_pe *slave;
- struct pci_dev *pdev;
+ struct pci_dev *pdev = NULL;
int ret;
/*
@@ -606,8 +616,12 @@ static int pnv_ioda_set_peltv(struct pnv_phb *phb,
if (pe-flags (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS))
pdev = pe-pbus-self;
- else
+ else if (pe-flags PNV_IODA_PE_DEV)
pdev = pe-pdev-bus-self;
+#ifdef CONFIG_PCI_IOV
+ else if (pe-flags PNV_IODA_PE_VF)
+ pdev = pe-parent_dev-bus-self;
+#endif /* CONFIG_PCI_IOV */
while (pdev) {
struct pci_dn *pdn = pci_get_pdn(pdev);
struct pnv_ioda_pe *parent;
@@ -625,6 +639,89 @@ static int pnv_ioda_set_peltv(struct pnv_phb *phb,
return 0;
}
+#ifdef CONFIG_PCI_IOV
+static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
+{
+ struct pci_dev *parent;
+ uint8_t bcomp, dcomp, fcomp;
+ int64_t rc;
+ long rid_end, rid;
+
+ /* Currently, we just deconfigure VF PE. Bus PE will always there.*/
+ if (pe-pbus) {
+ int count;
+
+ dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
+ fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
+ parent = pe-pbus-self;
+ if (pe-flags PNV_IODA_PE_BUS_ALL)
+ count = pe-pbus-busn_res.end -
[PATCH V11 13/17] powerpc/powernv: Implement pcibios_iov_resource_alignment() on powernv
This patch implements the pcibios_iov_resource_alignment() on powernv
platform.
On PowerNV platform, there are 3 cases for the IOV BAR:
1. initial state, the IOV BAR size is multiple times of VF BAR size
2. after expanded, the IOV BAR size is expanded to meet the M64 segment size
3. sizing stage, the IOV BAR is truncated to 0
pnv_pci_iov_resource_alignment() handle these three cases respectively.
Signed-off-by: Wei Yang weiy...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/machdep.h|3 +++
arch/powerpc/kernel/pci-common.c | 14 ++
arch/powerpc/platforms/powernv/pci-ioda.c | 20
3 files changed, 37 insertions(+)
diff --git a/arch/powerpc/include/asm/machdep.h
b/arch/powerpc/include/asm/machdep.h
index 965547c..12e8eb8 100644
--- a/arch/powerpc/include/asm/machdep.h
+++ b/arch/powerpc/include/asm/machdep.h
@@ -252,6 +252,9 @@ struct machdep_calls {
#ifdef CONFIG_PCI_IOV
void (*pcibios_fixup_sriov)(struct pci_bus *bus);
+ resource_size_t (*pcibios_iov_resource_alignment)(struct pci_dev *,
+ int resno,
+ resource_size_t
align);
#endif /* CONFIG_PCI_IOV */
/* Called to shutdown machine specific hardware not already controlled
diff --git a/arch/powerpc/kernel/pci-common.c b/arch/powerpc/kernel/pci-common.c
index 832b7e1..8751dfb 100644
--- a/arch/powerpc/kernel/pci-common.c
+++ b/arch/powerpc/kernel/pci-common.c
@@ -130,6 +130,20 @@ void pcibios_reset_secondary_bus(struct pci_dev *dev)
pci_reset_secondary_bus(dev);
}
+#ifdef CONFIG_PCI_IOV
+resource_size_t pcibios_iov_resource_alignment(struct pci_dev *pdev,
+int resno,
+resource_size_t align)
+{
+ if (ppc_md.pcibios_iov_resource_alignment)
+ return ppc_md.pcibios_iov_resource_alignment(pdev,
+ resno,
+ align);
+
+ return 0;
+}
+#endif /* CONFIG_PCI_IOV */
+
static resource_size_t pcibios_io_size(const struct pci_controller *hose)
{
#ifdef CONFIG_PPC64
diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c
b/arch/powerpc/platforms/powernv/pci-ioda.c
index 6704fdf..8bad2b0 100644
--- a/arch/powerpc/platforms/powernv/pci-ioda.c
+++ b/arch/powerpc/platforms/powernv/pci-ioda.c
@@ -1953,6 +1953,25 @@ static resource_size_t pnv_pci_window_alignment(struct
pci_bus *bus,
return phb-ioda.io_segsize;
}
+#ifdef CONFIG_PCI_IOV
+static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev,
+ int resno,
+ resource_size_t
align)
+{
+ struct pci_dn *pdn = pci_get_pdn(pdev);
+ resource_size_t iov_align;
+
+ iov_align = resource_size(pdev-resource[resno]);
+ if (iov_align)
+ return iov_align;
+
+ if (pdn-max_vfs)
+ return pdn-max_vfs * align;
+
+ return align;
+}
+#endif /* CONFIG_PCI_IOV */
+
/* Prevent enabling devices for which we couldn't properly
* assign a PE
*/
@@ -2155,6 +2174,7 @@ static void __init pnv_pci_init_ioda_phb(struct
device_node *np,
ppc_md.pcibios_reset_secondary_bus = pnv_pci_reset_secondary_bus;
#ifdef CONFIG_PCI_IOV
ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_sriov;
+ ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment;
#endif /* CONFIG_PCI_IOV */
pci_add_flags(PCI_REASSIGN_ALL_RSRC);
--
1.7.9.5
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[PATCH 2/3] CXL: Snoop control
Add mode to opal call. SNOOP control turns CAPP unit snooping on/off. This is
needed for the following reset patch, which turns snoops off in the CAPP
recovery path.
Signed-off-by: Ryan Grimm gr...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/opal.h | 12
arch/powerpc/include/asm/pnv-pci.h| 2 +-
arch/powerpc/platforms/powernv/pci-ioda.c | 4 ++--
drivers/misc/cxl/pci.c| 6 +-
4 files changed, 20 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/include/asm/opal.h b/arch/powerpc/include/asm/opal.h
index 5d073e5..965e232 100644
--- a/arch/powerpc/include/asm/opal.h
+++ b/arch/powerpc/include/asm/opal.h
@@ -676,6 +676,18 @@ enum {
OPAL_PHB3_NUM_PEST_REGS = 256
};
+/* CAPI modes for PHB */
+enum {
+OPAL_PHB_CAPI_MODE_PCIE = 0,
+OPAL_PHB_CAPI_MODE_CAPI = 1,
+OPAL_PHB_CAPI_MODE_SNOOP_OFF= 2,
+OPAL_PHB_CAPI_MODE_SNOOP_ON = 3,
+};
+
+/* CAPI feature flags (in device-tree) */
+#define OPAL_PHB_CAPI_FLAG_SNOOP_CONTROL0x0001
+#define OPAL_PHB_CAPI_FLAG_REVERT_TO_PCIE 0x0002
+
struct OpalIoPhbErrorCommon {
__be32 version;
__be32 ioType;
diff --git a/arch/powerpc/include/asm/pnv-pci.h
b/arch/powerpc/include/asm/pnv-pci.h
index f09a22f..e18082c 100644
--- a/arch/powerpc/include/asm/pnv-pci.h
+++ b/arch/powerpc/include/asm/pnv-pci.h
@@ -13,7 +13,7 @@
#include linux/pci.h
#include misc/cxl.h
-int pnv_phb_to_cxl(struct pci_dev *dev);
+int pnv_phb_to_cxl(struct pci_dev *dev, uint64_t mode);
int pnv_cxl_ioda_msi_setup(struct pci_dev *dev, unsigned int hwirq,
unsigned int virq);
int pnv_cxl_alloc_hwirqs(struct pci_dev *dev, int num);
diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c
b/arch/powerpc/platforms/powernv/pci-ioda.c
index 468a0f2..acacc1b 100644
--- a/arch/powerpc/platforms/powernv/pci-ioda.c
+++ b/arch/powerpc/platforms/powernv/pci-ioda.c
@@ -1363,7 +1363,7 @@ struct device_node *pnv_pci_to_phb_node(struct pci_dev
*dev)
}
EXPORT_SYMBOL(pnv_pci_to_phb_node);
-int pnv_phb_to_cxl(struct pci_dev *dev)
+int pnv_phb_to_cxl(struct pci_dev *dev, uint64_t mode)
{
struct pci_controller *hose = pci_bus_to_host(dev-bus);
struct pnv_phb *phb = hose-private_data;
@@ -1376,7 +1376,7 @@ int pnv_phb_to_cxl(struct pci_dev *dev)
pe_info(pe, Switching PHB to CXL\n);
- rc = opal_pci_set_phb_cxl_mode(phb-opal_id, 1, pe-pe_number);
+ rc = opal_pci_set_phb_cxl_mode(phb-opal_id, mode, pe-pe_number);
if (rc)
dev_err(dev-dev, opal_pci_set_phb_cxl_mode failed: %i\n,
rc);
diff --git a/drivers/misc/cxl/pci.c b/drivers/misc/cxl/pci.c
index 26cacc1..9aa95f9 100644
--- a/drivers/misc/cxl/pci.c
+++ b/drivers/misc/cxl/pci.c
@@ -924,7 +924,7 @@ static struct cxl *cxl_init_adapter(struct pci_dev *dev)
if ((rc = init_implementation_adapter_regs(adapter, dev)))
goto err3;
- if ((rc = pnv_phb_to_cxl(dev)))
+ if ((rc = pnv_phb_to_cxl(dev, OPAL_PHB_CAPI_MODE_CAPI)))
goto err3;
if ((rc = cxl_register_psl_err_irq(adapter)))
@@ -1009,6 +1009,10 @@ static int cxl_probe(struct pci_dev *dev, const struct
pci_device_id *id)
dev_err(dev-dev, AFU %i failed to initialise: %i\n,
slice, rc);
}
+ if ((rc = pnv_phb_to_cxl(dev, OPAL_PHB_CAPI_MODE_SNOOP_ON))) {
+ dev_err(dev-dev, enable capp snoops: %i\n, rc);
+ }
+
return 0;
}
--
1.9.1
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[PATCH 1/3] CXL: Add image control to sysfs
Add reset_loads_image and reset_image_select to sysfs.
reset_image_select identifies which image will be loaded to the card on the
next PERST. Valid entries are: user and factory.
reset_loads_image defines functionality on a PERST. Value of 0 means PERST
will not cause image load. A power cycle is required to load the image. Value
of 1 means PERST will cause image load.
sysfs updates the cxl struct in the driver then calls cxl_update_image_control
to write the vals in the VSEC.
Signed-off-by: Ryan Grimm gr...@linux.vnet.ibm.com
---
Documentation/ABI/testing/sysfs-class-cxl | 15
drivers/misc/cxl/cxl.h| 1 +
drivers/misc/cxl/pci.c| 35 ++
drivers/misc/cxl/sysfs.c | 60 +++
4 files changed, 111 insertions(+)
diff --git a/Documentation/ABI/testing/sysfs-class-cxl
b/Documentation/ABI/testing/sysfs-class-cxl
index 554405e..134cfaf 100644
--- a/Documentation/ABI/testing/sysfs-class-cxl
+++ b/Documentation/ABI/testing/sysfs-class-cxl
@@ -127,3 +127,18 @@ Contact:linuxppc-dev@lists.ozlabs.org
Description:read only
Will return user or factory depending on the image loaded
onto the card.
+
+What: /sys/class/cxl/card/reset_image_select
+Date: December 2014
+Contact:linuxppc-dev@lists.ozlabs.org
+Description:read/write
+Identifies which image will be loaded to the card on the next
+PERST. Valid entries are: user and factory.
+
+What: /sys/class/cxl/card/reset_loads_image
+Date: December 2014
+Contact:linuxppc-dev@lists.ozlabs.org
+Description:read/write
+Value of 0 means PERST will not cause image load. A power
+cycle is required to load the image. Value of 1 means PERST
+will cause image load.
diff --git a/drivers/misc/cxl/cxl.h b/drivers/misc/cxl/cxl.h
index 0df0438..518c4c6 100644
--- a/drivers/misc/cxl/cxl.h
+++ b/drivers/misc/cxl/cxl.h
@@ -488,6 +488,7 @@ void cxl_release_one_irq(struct cxl *adapter, int hwirq);
int cxl_alloc_irq_ranges(struct cxl_irq_ranges *irqs, struct cxl *adapter,
unsigned int num);
void cxl_release_irq_ranges(struct cxl_irq_ranges *irqs, struct cxl *adapter);
int cxl_setup_irq(struct cxl *adapter, unsigned int hwirq, unsigned int virq);
+int cxl_update_image_control(struct cxl *adapter);
/* common == phyp + powernv */
struct cxl_process_element_common {
diff --git a/drivers/misc/cxl/pci.c b/drivers/misc/cxl/pci.c
index f801c28..26cacc1 100644
--- a/drivers/misc/cxl/pci.c
+++ b/drivers/misc/cxl/pci.c
@@ -362,6 +362,41 @@ int cxl_setup_irq(struct cxl *adapter, unsigned int hwirq,
return pnv_cxl_ioda_msi_setup(dev, hwirq, virq);
}
+int cxl_update_image_control(struct cxl *adapter)
+{
+ struct pci_dev *dev = to_pci_dev(adapter-dev.parent);
+ int rc;
+ int vsec;
+ u8 image_state;
+
+ if (!(vsec = find_cxl_vsec(dev))) {
+ dev_err(dev-dev, ABORTING: CXL VSEC not found!\n);
+ return -ENODEV;
+ }
+
+ if ((rc = CXL_READ_VSEC_IMAGE_STATE(dev, vsec, image_state))) {
+ dev_err(dev-dev, failed to read image state: %i\n, rc);
+ return rc;
+ }
+
+ if (adapter-perst_loads_image)
+ image_state |= CXL_VSEC_PERST_LOADS_IMAGE;
+ else
+ image_state = ~CXL_VSEC_PERST_LOADS_IMAGE;
+
+ if (adapter-perst_select_user)
+ image_state |= CXL_VSEC_PERST_SELECT_USER;
+ else
+ image_state = ~CXL_VSEC_PERST_SELECT_USER;
+
+ if ((rc = CXL_WRITE_VSEC_IMAGE_STATE(dev, vsec, image_state))) {
+ dev_err(dev-dev, failed to update image control: %i\n, rc);
+ return rc;
+ }
+
+ return 0;
+}
+
int cxl_alloc_one_irq(struct cxl *adapter)
{
struct pci_dev *dev = to_pci_dev(adapter-dev.parent);
diff --git a/drivers/misc/cxl/sysfs.c b/drivers/misc/cxl/sysfs.c
index 461bdbd..06f554b 100644
--- a/drivers/misc/cxl/sysfs.c
+++ b/drivers/misc/cxl/sysfs.c
@@ -56,11 +56,71 @@ static ssize_t image_loaded_show(struct device *device,
return scnprintf(buf, PAGE_SIZE, factory\n);
}
+static ssize_t reset_loads_image_show(struct device *device,
+struct device_attribute *attr,
+char *buf)
+{
+ struct cxl *adapter = to_cxl_adapter(device);
+ return sprintf(buf, %d\n, adapter-perst_loads_image);
+}
+
+static ssize_t reset_loads_image_store(struct device *device,
+struct device_attribute *attr,
+const char *buf, size_t count)
+{
+ struct cxl *adapter = to_cxl_adapter(device);
+ unsigned long val;
+ int rc;
+
+if (kstrtoul(buf, 0, val) 0)
+return -EINVAL;
+
+adapter-perst_loads_image = !!val;
+
RE: [PATCH v3 1/3] Revert clk: ppc-corenet: Fix Section mismatch warning
PING!
Thanks,
Yuantian
-Original Message-
From: Kevin Hao [mailto:haoke...@gmail.com]
Sent: Wednesday, December 03, 2014 4:54 PM
To: linuxppc-dev@lists.ozlabs.org
Cc: Benjamin Herrenschmidt; Wood Scott-B07421; Mike Turquette; Lu
Jingchang-B35083; Gerhard Sittig; Tang Yuantian-B29983
Subject: [PATCH v3 1/3] Revert clk: ppc-corenet: Fix Section mismatch
warning
This reverts commit da788acb28386aa896224e784954bb73c99ff26c.
That commit tried to fix the section mismatch warning by moving the
ppc_corenet_clk_driver struct to init section. This is definitely wrong
because the
kernel would free the memories occupied by this struct after boot while this
driver is still registered in the driver core.
The kernel would panic when accessing this driver struct.
Cc: sta...@vger.kernel.org # 3.17
Signed-off-by: Kevin Hao haoke...@gmail.com
Acked-by: Scott Wood scottw...@freescale.com
Acked-by: Michael Turquette mturque...@linaro.org
---
v3: Cc stable and add ack.
v2: A new patch in v2.
drivers/clk/clk-ppc-corenet.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/clk-ppc-corenet.c b/drivers/clk/clk-ppc-corenet.c
index
b6e6c85507a5..0a47d6f49cd6 100644
--- a/drivers/clk/clk-ppc-corenet.c
+++ b/drivers/clk/clk-ppc-corenet.c
@@ -291,7 +291,7 @@ static const struct of_device_id ppc_clk_ids[] __initconst
= {
{}
};
-static struct platform_driver ppc_corenet_clk_driver __initdata = {
+static struct platform_driver ppc_corenet_clk_driver = {
.driver = {
.name = ppc_corenet_clock,
.of_match_table = ppc_clk_ids,
--
1.9.3
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Re: [PATCH] pseries/le: Fix endiannes issue in RTAS call from xmon
On Mon, 2014-11-24 at 15:07 +0100, Laurent Dufour wrote: On pseries system (LPAR) xmon failed to enter when running in LE mode, system is hunging. Inititating xmon will lead to such an output on the console: SysRq : Entering xmon cpu 0x15: Vector: 0 at [c003f39ffb10] pc: c007ed7c: sysrq_handle_xmon+0x5c/0x70 lr: c007ed7c: sysrq_handle_xmon+0x5c/0x70 sp: c003f39ffc70 msr: 80009033 current = 0xc003fafa7180 paca= 0xc7d75e80 softe: 0irq_happened: 0x01 pid = 14617, comm = bash Bad kernel stack pointer fafb4b0 at eca7cc4 cpu 0x15: Vector: 300 (Data Access) at [c7f07d40] pc: 0eca7cc4 lr: 0eca7c44 sp: fafb4b0 msr: 80001000 dar: 1000 dsisr: 4200 current = 0xc003fafa7180 paca= 0xc7d75e80 softe: 0irq_happened: 0x01 pid = 14617, comm = bash cpu 0x15: Exception 300 (Data Access) in xmon, returning to main loop xmon: WARNING: bad recursive fault on cpu 0x15 The root cause is that xmon is calling RTAS to turn off the surveillance when entering xmon, and RTAS is requiring big endian parameters. This patch is byte swapping the RTAS arguments when running in LE mode. Signed-off-by: Laurent Dufour lduf...@linux.vnet.ibm.com --- arch/powerpc/xmon/xmon.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c index b988b5addf86..c8efbb37d6e0 100644 --- a/arch/powerpc/xmon/xmon.c +++ b/arch/powerpc/xmon/xmon.c @@ -293,10 +293,10 @@ static inline void disable_surveillance(void) args.token = rtas_token(set-indicator); if (args.token == RTAS_UNKNOWN_SERVICE) return; I just noticed we're not handling the token correctly here. It is be32 also. cheers ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 2/3] CXL: Snoop control
Excerpts from Ryan Grimm's message of 2015-01-15 13:56:40 +1100:
Add mode to opal call. SNOOP control turns CAPP unit snooping on/off. This
is
needed for the following reset patch, which turns snoops off in the CAPP
recovery path.
Looking at patch 3 in this series I think this description needs to be
updated, as it doesn't seem to turn off snoops?
+/* CAPI modes for PHB */
+enum {
+OPAL_PHB_CAPI_MODE_PCIE = 0,
+OPAL_PHB_CAPI_MODE_CAPI = 1,
+OPAL_PHB_CAPI_MODE_SNOOP_OFF= 2,
+OPAL_PHB_CAPI_MODE_SNOOP_ON = 3,
+};
Spaces have been used for indention here
+/* CAPI feature flags (in device-tree) */
+#define OPAL_PHB_CAPI_FLAG_SNOOP_CONTROL0x0001
+#define OPAL_PHB_CAPI_FLAG_REVERT_TO_PCIE 0x0002
It doesn't look like these are used?
-int pnv_phb_to_cxl(struct pci_dev *dev)
+int pnv_phb_to_cxl(struct pci_dev *dev, uint64_t mode)
Should we rename this function since it no longer just sets the PHB to
CXL mode? Maybe something like pnv_phb_set_cxl_mode?
+if ((rc = pnv_phb_to_cxl(dev, OPAL_PHB_CAPI_MODE_SNOOP_ON))) {
+dev_err(dev-dev, enable capp snoops: %i\n, rc);
+}
Ok, we turn on snooping here, but I don't see where we turned it off -
has patch 3 changed so that never happens?
Also - why this late in in the init sequence? Not saying it's wrong, just
wondering if this has to happen after all the AFUs have been initialised, or if
it can happen earlier in the adapter initialisation, like when we set
the PHB to capi mode?
Cheers,
-Ian
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[PATCH V11 00/17] Enable SRIOV on Power8
This patchset enables the SRIOV on POWER8. The gerneral idea is put each VF into one individual PE and allocate required resources like MMIO/DMA/MSI. The major difficulty comes from the MMIO allocation and adjustment for PF's IOV BAR. On P8, we use M64BT to cover a PF's IOV BAR, which could make an individual VF sit in its own PE. This gives more flexiblity, while at the mean time it brings on some restrictions on the PF's IOV BAR size and alignment. To achieve this effect, we need to do some hack on pci devices's resources. 1. Expand the IOV BAR properly. Done by pnv_pci_ioda_fixup_iov_resources(). 2. Shift the IOV BAR properly. Done by pnv_pci_vf_resource_shift(). 3. IOV BAR alignment is calculated by arch dependent function instead of an individual VF BAR size. Done by pnv_pcibios_sriov_resource_alignment(). 4. Take the IOV BAR alignment into consideration in the sizing and assigning. This is achieved by commit: PCI: Take additional IOV BAR alignment in sizing and assigning Test Environment: The SRIOV device tested is Emulex Lancer(10df:e220) and Mellanox ConnectX-3(15b3:1003) on POWER8. Examples on pass through a VF to guest through vfio: 1. unbind the original driver and bind to vfio-pci driver echo :06:0d.0 /sys/bus/pci/devices/:06:0d.0/driver/unbind echo 1102 0002 /sys/bus/pci/drivers/vfio-pci/new_id Note: this should be done for each device in the same iommu_group 2. Start qemu and pass device through vfio /home/ywywyang/git/qemu-impreza/ppc64-softmmu/qemu-system-ppc64 \ -M pseries -m 2048 -enable-kvm -nographic \ -drive file=/home/ywywyang/kvm/fc19.img \ -monitor telnet:localhost:5435,server,nowait -boot cd \ -device spapr-pci-vfio-host-bridge,id=CXGB3,iommu=26,index=6 Verify this is the exact VF response: 1. ping from a machine in the same subnet(the broadcast domain) 2. run arp -n on this machine 9.115.251.20 ether 00:00:c9:df:ed:bf C eth0 3. ifconfig in the guest # ifconfig eth1 eth1: flags=4163UP,BROADCAST,RUNNING,MULTICAST mtu 1500 inet 9.115.251.20 netmask 255.255.255.0 broadcast 9.115.251.255 inet6 fe80::200:c9ff:fedf:edbf prefixlen 64 scopeid 0x20link ether 00:00:c9:df:ed:bf txqueuelen 1000 (Ethernet) RX packets 175 bytes 13278 (12.9 KiB) RX errors 0 dropped 0 overruns 0 frame 0 TX packets 58 bytes 9276 (9.0 KiB) TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0 4. They have the same MAC address Note: make sure you shutdown other network interfaces in guest. --- v11: * fix some compile warning v10: * remove weak function pcibios_iov_resource_size() the VF BAR size is stored in pci_sriov structure and retrieved from pci_iov_resource_size() * Use Reserve additional instead of Expand to be more acurate in the change log * add log message to show the PF's IOV BAR final size * add pcibios_sriov_enable/disable() weak funcion in sriov_enable/disable() for arch setup before enable VFs. Like the arch could fix up the BDF for VFs, since the change of NumVFs would affect the BDF of VFs. * Add some explanation of PE on Power arch in the documentation v9: * make the change log consistent in the terminology PF's IOV BAR - the SRIOV BAR in PF VF's BAR - the normal BAR in VF's view * rename all newly introduced function from _sriov_ to _iov_ * rename the document to Documentation/powerpc/pci_iov_resource_on_powernv.txt * add the vendor id and device id of the tested devices * change return value from EINVAL to ENOSYS for pci_iov_virtfn_bus() and pci_iov_virtfn_devfn() when it is called on PF or SRIOV is not configured * rebase on 3.18-rc2 and tested v8: * use weak funcion pcibios_sriov_resource_size() instead of some flag to retrieve the IOV BAR size. * add a document Documentation/powerpc/pci_resource.txt to explain the design. * make pci_iov_virtfn_bus()/pci_iov_virtfn_devfn() not inline. * extract a function res_to_dev_res(), so that it is more general to get additional size and alignment * fix one contention which is introduced in powrepc/pci: Refactor pci_dn. the root cause is pci_get_slot() takes pci_bus_sem and leads to dead lock. v7: * add IORESOURCE_ARCH flag for IOV BAR on powernv platform. * when IOV BAR has IORESOURCE_ARCH flag, the size is retrieved from hardware directly. If not, calculate as usual. * reorder the patch set, group them by subsystem: PCI, powerpc, powernv * rebase it on 3.16-rc6 v6: * remove pcibios_enable_sriov()/pcibios_disable_sriov() weak function similar function is moved to
[PATCH V11 02/17] PCI/IOV: add VF enable/disable hook
VFs are dynamically created/released when driver enable them. On some
platforms, like PowerNV, special resources are necessary to enable VFs.
This patch adds two hooks for platform initialization before creating the
VFs.
Signed-off-by: Wei Yang weiy...@linux.vnet.ibm.com
---
drivers/pci/iov.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/drivers/pci/iov.c b/drivers/pci/iov.c
index e76d1a0..933d8cc 100644
--- a/drivers/pci/iov.c
+++ b/drivers/pci/iov.c
@@ -213,6 +213,11 @@ static void virtfn_remove(struct pci_dev *dev, int id, int
reset)
pci_dev_put(dev);
}
+int __weak pcibios_sriov_enable(struct pci_dev *pdev, u16 vf_num)
+{
+ return 0;
+}
+
static int sriov_enable(struct pci_dev *dev, int nr_virtfn)
{
int rc;
@@ -223,6 +228,7 @@ static int sriov_enable(struct pci_dev *dev, int nr_virtfn)
struct pci_dev *pdev;
struct pci_sriov *iov = dev-sriov;
int bars = 0;
+ int retval;
if (!nr_virtfn)
return 0;
@@ -297,6 +303,12 @@ static int sriov_enable(struct pci_dev *dev, int nr_virtfn)
if (nr_virtfn initial)
initial = nr_virtfn;
+ if ((retval = pcibios_sriov_enable(dev, initial))) {
+ dev_err(dev-dev, Failure %d from pcibios_sriov_setup()\n,
+ retval);
+ return retval;
+ }
+
for (i = 0; i initial; i++) {
rc = virtfn_add(dev, i, 0);
if (rc)
@@ -325,6 +337,11 @@ failed:
return rc;
}
+int __weak pcibios_sriov_disable(struct pci_dev *pdev, u16 vf_num)
+{
+ return 0;
+}
+
static void sriov_disable(struct pci_dev *dev)
{
int i;
@@ -336,6 +353,8 @@ static void sriov_disable(struct pci_dev *dev)
for (i = 0; i iov-num_VFs; i++)
virtfn_remove(dev, i, 0);
+ pcibios_sriov_disable(dev, iov-num_VFs);
+
iov-ctrl = ~(PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE);
pci_cfg_access_lock(dev);
pci_write_config_word(dev, iov-pos + PCI_SRIOV_CTRL, iov-ctrl);
--
1.7.9.5
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[PATCH V11 01/17] PCI/IOV: Export interface for retrieve VF's BDF
When implementing the SR-IOV on PowerNV platform, some resource reservation
is needed for VFs which don't exist at the bootup stage. To do the match
between resources and VFs, the code need to get the VF's BDF in advance.
In this patch, it exports the interface to retrieve VF's BDF:
* Make the virtfn_bus as an interface
* Make the virtfn_devfn as an interface
* Rename them with more specific name
* Code cleanup in pci_sriov_resource_alignment()
Signed-off-by: Wei Yang weiy...@linux.vnet.ibm.com
---
drivers/pci/iov.c | 22 +-
include/linux/pci.h | 11 +++
2 files changed, 24 insertions(+), 9 deletions(-)
diff --git a/drivers/pci/iov.c b/drivers/pci/iov.c
index ea3a82c..e76d1a0 100644
--- a/drivers/pci/iov.c
+++ b/drivers/pci/iov.c
@@ -19,14 +19,18 @@
#define VIRTFN_ID_LEN 16
-static inline u8 virtfn_bus(struct pci_dev *dev, int id)
+int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
{
+ if (!dev-is_physfn)
+ return -EINVAL;
return dev-bus-number + ((dev-devfn + dev-sriov-offset +
dev-sriov-stride * id) 8);
}
-static inline u8 virtfn_devfn(struct pci_dev *dev, int id)
+int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
{
+ if (!dev-is_physfn)
+ return -EINVAL;
return (dev-devfn + dev-sriov-offset +
dev-sriov-stride * id) 0xff;
}
@@ -62,7 +66,7 @@ static inline void pci_iov_max_bus_range(struct pci_dev *dev)
for ( ; total = 0; total--) {
pci_iov_set_numvfs(dev, total);
- busnr = virtfn_bus(dev, iov-total_VFs - 1);
+ busnr = pci_iov_virtfn_bus(dev, iov-total_VFs - 1);
if (busnr max)
max = busnr;
}
@@ -108,7 +112,7 @@ static int virtfn_add(struct pci_dev *dev, int id, int
reset)
struct pci_bus *bus;
mutex_lock(iov-dev-sriov-lock);
- bus = virtfn_add_bus(dev-bus, virtfn_bus(dev, id));
+ bus = virtfn_add_bus(dev-bus, pci_iov_virtfn_bus(dev, id));
if (!bus)
goto failed;
@@ -116,7 +120,7 @@ static int virtfn_add(struct pci_dev *dev, int id, int
reset)
if (!virtfn)
goto failed0;
- virtfn-devfn = virtfn_devfn(dev, id);
+ virtfn-devfn = pci_iov_virtfn_devfn(dev, id);
virtfn-vendor = dev-vendor;
pci_read_config_word(dev, iov-pos + PCI_SRIOV_VF_DID, virtfn-device);
pci_setup_device(virtfn);
@@ -179,8 +183,8 @@ static void virtfn_remove(struct pci_dev *dev, int id, int
reset)
struct pci_sriov *iov = dev-sriov;
virtfn = pci_get_domain_bus_and_slot(pci_domain_nr(dev-bus),
-virtfn_bus(dev, id),
-virtfn_devfn(dev, id));
+pci_iov_virtfn_bus(dev, id),
+pci_iov_virtfn_devfn(dev, id));
if (!virtfn)
return;
@@ -255,7 +259,7 @@ static int sriov_enable(struct pci_dev *dev, int nr_virtfn)
iov-offset = offset;
iov-stride = stride;
- if (virtfn_bus(dev, nr_virtfn - 1) dev-bus-busn_res.end) {
+ if (pci_iov_virtfn_bus(dev, nr_virtfn - 1) dev-bus-busn_res.end) {
dev_err(dev-dev, SR-IOV: bus number out of range\n);
return -ENOMEM;
}
@@ -551,7 +555,7 @@ resource_size_t pci_sriov_resource_alignment(struct pci_dev
*dev, int resno)
if (!reg)
return 0;
-__pci_read_base(dev, pci_bar_unknown, tmp, reg);
+ __pci_read_base(dev, pci_bar_unknown, tmp, reg);
return resource_alignment(tmp);
}
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 360a966..74ef944 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -1658,6 +1658,9 @@ int pci_ext_cfg_avail(void);
void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
#ifdef CONFIG_PCI_IOV
+int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
+int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);
+
int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
void pci_disable_sriov(struct pci_dev *dev);
int pci_num_vf(struct pci_dev *dev);
@@ -1665,6 +1668,14 @@ int pci_vfs_assigned(struct pci_dev *dev);
int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
int pci_sriov_get_totalvfs(struct pci_dev *dev);
#else
+static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
+{
+ return -ENOSYS;
+}
+static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
+{
+ return -ENOSYS;
+}
static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
{ return -ENODEV; }
static inline void pci_disable_sriov(struct pci_dev *dev) { }
--
1.7.9.5
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Re: [PATCH 1/3] CXL: Add image control to sysfs
Excerpts from Ryan Grimm's message of 2015-01-15 13:56:39 +1100:
Add reset_loads_image and reset_image_select to sysfs.
reset_image_select identifies which image will be loaded to the card on the
next PERST. Valid entries are: user and factory.
reset_loads_image defines functionality on a PERST. Value of 0 means PERST
will not cause image load. A power cycle is required to load the image.
Value
of 1 means PERST will cause image load.
sysfs updates the cxl struct in the driver then calls cxl_update_image_control
to write the vals in the VSEC.
Let's combine both of these into a single sysfs file, with none,
user and factory options and have the show read functions handle
mapping those three options to the two bits in the register.
Of the two names I'd probably go with reset_image_select.
+What: /sys/class/cxl/card/reset_loads_image
+Date: December 2014
+Contact:linuxppc-dev@lists.ozlabs.org
+Description:read/write
+Value of 0 means PERST will not cause image load. A power
+cycle is required to load the image. Value of 1 means PERST
+will cause image load.
It also seems to be that having this disabled also means that PERST
doesn't fully reset the card. Might want to clarify that somewhat and
recommend it only be disabled for debugging purposes (e.g. to retain
the contents of the PSL trace arrays across a reset), and to always
enable it for production.
At the moment we don't set it at boot - we just go with whatever the
card is already set to do. I'm thinking it might be a good idea to
always set this bit on boot so the only time it's disabled is if a user
has explicitly gone and disabled it.
+static ssize_t reset_loads_image_show(struct device *device,
+ struct device_attribute *attr,
+ char *buf)
+{
+struct cxl *adapter = to_cxl_adapter(device);
+return sprintf(buf, %d\n, adapter-perst_loads_image);
We've used scnprintf for the other sysfs reads in this file, why sprintf
here?
+static ssize_t reset_loads_image_store(struct device *device,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+struct cxl *adapter = to_cxl_adapter(device);
+unsigned long val;
+int rc;
+
+if (kstrtoul(buf, 0, val) 0)
+return -EINVAL;
+
+adapter-perst_loads_image = !!val;
+if ((rc = cxl_update_image_control(adapter)))
+return rc;
Seems to be some indentation mismatches here - some lines are using
spaces other are using tabs. Please use tabs for everything.
+static ssize_t reset_image_select_store(struct device *device,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+struct cxl *adapter = to_cxl_adapter(device);
+int rc;
+
+if (!strncmp(buf, user, 4))
+adapter-perst_select_user = true;
+else if (!strncmp(buf, factory, 7))
+adapter-perst_select_user = false;
+else
+return -EINVAL;
More indentation mismatches here.
Cheers,
-Ian
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Re: [PATCH 3/3] CXL: Add reset to sysfs
Excerpts from Ryan Grimm's message of 2015-01-15 13:56:41 +1100:
This allows an image to be downloaded to the flash without rebooting the
machine. The driver perform a PERST, which results in FPGA image downloaded
to
flash and the CAPP unit enters recovery. CAPP recovery triggers an HMI, which
is handled by EEH in Linux. EEH removes the driver, calls into Sapphire to
reinitialize the PHB, and then loads the driver.
reset_image_select must be set to user and reset_load_image set to 1. The
driver writes user to the vsec if a user image was loaded. It writes 1 to
reset_load_image on initialization by default. Other values could be used by
hand for debugging purposes.
That last paragraph will need to be updated if we merge those two sysfs
files into one. Might as well mention an example of why someone might do
a reset with no image selected for reload, e.g. the PSL trace arrays are
preserved, which can be read out through debugfs after the card comes
back up.
+What: /sys/class/cxl/card/reset
+Date: October 2014
+Contact:linuxppc-dev@lists.ozlabs.org
+Description:write only
+Writing 1 here will issue a PERST to card.
..., which may cause the card to reload the FPGA image depending on the
settings of reset_image_select.
+if ((rc = pci_set_pcie_reset_state(dev, pcie_warm_reset))) {
Can you add a comment here to explain why we first do a warm reset?
+dev_err(dev-dev, cxl: pcie_warm_reset failed\n);
+return rc;
+}
+
+/* Do mmio read to trigger EEH. Retry for a few seconds. */
This seems a little unusual - can you expand this comment a little to
explain *why* we are using this method to trigger an EEH and reset the
card?
+i = 0;
+while ((val = mmio_read32be(adapter-p1_mmio) != 0x)
+(i 5)) {
+msleep(500);
+i++;
+}
+
+if (val != 0x)
+dev_err(dev-dev, cxl: PERST failed to trigger EEH\n);
+
+return rc;
Some of the indentation here is a bit funky - some lines are using tabs,
others are using spaces.
@@ -806,8 +837,8 @@ static int cxl_read_vsec(struct cxl *adapter, struct
pci_dev *dev)
CXL_READ_VSEC_BASE_IMAGE(dev, vsec, adapter-base_image);
CXL_READ_VSEC_IMAGE_STATE(dev, vsec, image_state);
adapter-user_image_loaded = !!(image_state
CXL_VSEC_USER_IMAGE_LOADED);
-adapter-perst_loads_image = !!(image_state
CXL_VSEC_PERST_LOADS_IMAGE);
-adapter-perst_select_user = !!(image_state
CXL_VSEC_PERST_SELECT_USER);
+adapter-perst_loads_image = true;
+adapter-perst_select_user = !!(image_state
CXL_VSEC_USER_IMAGE_LOADED);
...
+if ((rc = cxl_update_image_control(adapter)))
+goto err2;
Thanks - that seems like a better default than what we had before,
should make things more stable :)
Cheers,
-Ian
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Re: [PATCH 1/3] CXL: Add image control to sysfs
Excerpts from Michael Ellerman's message of 2015-01-15 16:07:17 +1100: Of the two names I'd probably go with reset_image_select. Three words, all can be verbs, two can be nouns, it's not too clear. Maybe load_image_on_perst ? Works for me :) Cheers, -Ian ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH] fsl/smp: add low power boot support to replace spin boot
From: Wang Dongsheng dongsheng.w...@freescale.com
U-boot put non-boot cpus into an low power state(PW10/PW20 or DOZE) when cpu
powered up. To exit low power state kernel will send DOORBELL or MPIC-IPI
signal to all those CPUs.
e500/e500v2 use mpic to send IPI signal.
e500mc and later use doorbell to send IPI signal.
This feature tested on:
POWER UP TEST:
P1022DS(e500v2),96k times.
P4080(e500mc), 110k times.
T1024(e5500), 83k times.
T4240(e6500), 150k times.
CPU HOTPLUG TEST:
P1022DS(e500v2),1.4 million times.
P4080(e500mc), 1.8 million times.
T1024(e5500), 1.3 million times.
T4240(e6500), 1.1 million times.
Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com
diff --git a/arch/powerpc/include/asm/mpic.h b/arch/powerpc/include/asm/mpic.h
index 754f93d..8af6a25 100644
--- a/arch/powerpc/include/asm/mpic.h
+++ b/arch/powerpc/include/asm/mpic.h
@@ -474,6 +474,15 @@ extern int mpic_cpu_get_priority(void);
/* Set the current cpu priority for this cpu */
extern void mpic_cpu_set_priority(int prio);
+/* Set cpu priority */
+void mpic_set_cpu_priority(int nr, int prio);
+
+/* Set cpu EOI */
+void mpic_cpu_eoi_write(int cpu);
+
+/* CPU ACK interrupt */
+void mpic_cpu_ack(int cpu);
+
/* Request IPIs on primary mpic */
extern void mpic_request_ipis(void);
diff --git a/arch/powerpc/platforms/85xx/smp.c
b/arch/powerpc/platforms/85xx/smp.c
index d7c1e69..6c54632 100644
--- a/arch/powerpc/platforms/85xx/smp.c
+++ b/arch/powerpc/platforms/85xx/smp.c
@@ -193,6 +193,30 @@ static int smp_85xx_kick_cpu(int nr)
const u64 *cpu_rel_addr;
__iomem struct epapr_spin_table *spin_table;
struct device_node *np;
+
+ /*
+* DOORBELL:
+* When kernel kick one of cpus, all cpus will be wakenup. To make
+* sure that only the target cpu is effected, other cpus (by checking
+* spin_table-addr_l) should go back to low power state.
+*
+* U-boot has renumber the cpu PIR Why we need to set all of PIR to
+* the same value?
+* A: Before kernel kicking cpu, the doorbell message was not configured
+* for target cpu(cpu_messages-data). If we try to send a
+* non-configured message to target cpu, it cannot correctly receive
+* doorbell interrput. So SET ALL OF CPU'S PIR to the same value to
+* let all cpus catch the interrupt.
+*
+* Why set PIR to zero?
+* A: U-boot cannot know how many cpus will be kicked up(Kernel allow us
+* to configure NR_CPUS) and IPI is a per_cpu variable, u-boot cannot
+* set a appropriate PIR for every cpu, but the boot cpu(CPU0) always be
+* there. U-boot set PIR to zero as a default PIR ID for each CPU, so
+* initialize the kick_cpus to 0.
+*/
+ u32 kick_cpus = 0;
+
int hw_cpu = get_hard_smp_processor_id(nr);
int ioremappable;
int ret = 0;
@@ -251,8 +275,7 @@ static int smp_85xx_kick_cpu(int nr)
spin_table = phys_to_virt(*cpu_rel_addr);
local_irq_save(flags);
-#ifdef CONFIG_PPC32
-#ifdef CONFIG_HOTPLUG_CPU
+#if defined(CONFIG_PPC32) defined(CONFIG_HOTPLUG_CPU)
/* Corresponding to generic_set_cpu_dead() */
generic_set_cpu_up(nr);
@@ -292,11 +315,58 @@ static int smp_85xx_kick_cpu(int nr)
__secondary_hold_acknowledge = -1;
}
#endif
+
flush_spin_table(spin_table);
- out_be32(spin_table-pir, hw_cpu);
+ /*
+* U-boot will wait kernel send eoi to MPIC, after EOI has send
+* kernel will set PIR for uboot, let uboot know EOI has send.
+*/
+ out_be32(spin_table-pir, 0);
+
+#ifdef CONFIG_PPC32
out_be32(spin_table-addr_l, __pa(__early_start));
+#else
+ out_be64((u64 *)(spin_table-addr_h),
+__pa(ppc_function_entry(generic_secondary_smp_init)));
+#endif
flush_spin_table(spin_table);
+ /*
+* e500, e500v2 need to use MPIC to send IPI signal, so we need to
+* open IPI firstly.
+*/
+ if (!cpu_has_feature(CPU_FTR_DBELL)) {
+ mpic_set_cpu_priority(nr, 0);
+ kick_cpus = nr;
+ }
+
+ /* Let cpu exit low power state, and from u-boot jump to kernel */
+ arch_send_call_function_single_ipi(kick_cpus);
+
+ /*
+* Let we ACK interrput and Send EOI signal to finish INT server
+* U-boot has read EPR to ACK interrput when MPIC work in external
+* proxy mode. Without the external proxy facility, we need to read
+* MPIC ACK register.
+*
+* There just ACK interrput, we don't need to get the interrupt vector
+* and to handle it. Because there just IPI or DOORBELL interrupt to
+* make u-boot exit low power state and jump to kernel.
+*/
+ mpic_cpu_ack(nr);
+ /* Send EOI to clear ISR bit to remove interrupt from service */
+ mpic_cpu_eoi_write(nr);
+
+ /* After wakeup CPU disable
[PATCH 2/2] clk: ppc-corenet: rename driver to clk-qoriq
From: Tang Yuantian yuantian.t...@freescale.com
Freescale introduced new ARM-based socs which using the compatible
clock IP block with PowerPC-based socs'. So this driver can be used
on both platforms.
Updated relevant descriptions and renamed this driver to better
represent its meaning and keep the function of driver untouched.
Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
Documentation/devicetree/bindings/clock/qoriq-clock.txt | 5 +++--
drivers/clk/Kconfig | 10 +-
drivers/clk/Makefile| 2 +-
drivers/clk/{clk-ppc-corenet.c = clk-qoriq.c} | 6 +++---
drivers/cpufreq/Kconfig.powerpc | 2 +-
5 files changed, 13 insertions(+), 12 deletions(-)
rename drivers/clk/{clk-ppc-corenet.c = clk-qoriq.c} (98%)
diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
index 266ff9d..df4a259 100644
--- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
+++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
@@ -1,6 +1,6 @@
-* Clock Block on Freescale CoreNet Platforms
+* Clock Block on Freescale QorIQ Platforms
-Freescale CoreNet chips take primary clocking input from the external
+Freescale qoriq chips take primary clocking input from the external
SYSCLK signal. The SYSCLK input (frequency) is multiplied using
multiple phase locked loops (PLL) to create a variety of frequencies
which can then be passed to a variety of internal logic, including
@@ -29,6 +29,7 @@ Required properties:
* fsl,t4240-clockgen
* fsl,b4420-clockgen
* fsl,b4860-clockgen
+ * fsl,ls1021a-clockgen
Chassis clock strings include:
* fsl,qoriq-clockgen-1.0: for chassis 1.0 clocks
* fsl,qoriq-clockgen-2.0: for chassis 2.0 clocks
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 3f44f29..a896fbc 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -101,12 +101,12 @@ config COMMON_CLK_AXI_CLKGEN
Support for the Analog Devices axi-clkgen pcore clock generator for
Xilinx
FPGAs. It is commonly used in Analog Devices' reference designs.
-config CLK_PPC_CORENET
- bool Clock driver for PowerPC corenet platforms
- depends on PPC_E500MC OF
+config CLK_QORIQ
+ bool Clock driver for Freescale QorIQ platforms
+ depends on (PPC_E500MC || ARM) OF
---help---
- This adds the clock driver support for Freescale PowerPC corenet
- platforms using common clock framework.
+ This adds the clock driver support for Freescale QorIQ platforms
+ using common clock framework.
config COMMON_CLK_XGENE
bool Clock driver for APM XGene SoC
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index d5fba5b..4ff94cd 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -30,7 +30,7 @@ obj-$(CONFIG_ARCH_MOXART) += clk-moxart.o
obj-$(CONFIG_ARCH_NOMADIK) += clk-nomadik.o
obj-$(CONFIG_ARCH_NSPIRE) += clk-nspire.o
obj-$(CONFIG_COMMON_CLK_PALMAS)+= clk-palmas.o
-obj-$(CONFIG_CLK_PPC_CORENET) += clk-ppc-corenet.o
+obj-$(CONFIG_CLK_QORIQ)+= clk-qoriq.o
obj-$(CONFIG_COMMON_CLK_RK808) += clk-rk808.o
obj-$(CONFIG_COMMON_CLK_S2MPS11) += clk-s2mps11.o
obj-$(CONFIG_COMMON_CLK_SI5351)+= clk-si5351.o
diff --git a/drivers/clk/clk-ppc-corenet.c b/drivers/clk/clk-qoriq.c
similarity index 98%
rename from drivers/clk/clk-ppc-corenet.c
rename to drivers/clk/clk-qoriq.c
index 5e9bb18..f9b7eb4 100644
--- a/drivers/clk/clk-ppc-corenet.c
+++ b/drivers/clk/clk-qoriq.c
@@ -5,7 +5,7 @@
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
- * clock driver for Freescale PowerPC corenet SoCs.
+ * clock driver for Freescale QorIQ SoCs.
*/
#include linux/clk-provider.h
#include linux/io.h
@@ -166,7 +166,7 @@ static void __init core_pll_init(struct device_node *np)
base = of_iomap(np, 0);
if (!base) {
- pr_err(clk-ppc: iomap error\n);
+ pr_err(clk-qoriq: iomap error\n);
return;
}
@@ -260,7 +260,7 @@ static void __init sysclk_init(struct device_node *node)
u32 rate;
if (!np) {
- pr_err(ppc-clk: could not get parent node\n);
+ pr_err(qoriq-clk: could not get parent node\n);
return;
}
diff --git a/drivers/cpufreq/Kconfig.powerpc b/drivers/cpufreq/Kconfig.powerpc
index 72564b7..7ea2441 100644
--- a/drivers/cpufreq/Kconfig.powerpc
+++ b/drivers/cpufreq/Kconfig.powerpc
@@ -26,7 +26,7 @@ config CPU_FREQ_MAPLE
config PPC_CORENET_CPUFREQ
tristate CPU frequency scaling driver for Freescale E500MC SoCs
depends on PPC_E500MC OF COMMON_CLK
- select CLK_PPC_CORENET
+
[PATCH 1/2] clock: redefine variable clocks_per_pll as a struct member
From: Tang Yuantian yuantian.t...@freescale.com
redefine variable clocks_per_pll as a struct member
If there are multiple PLL clock nodes, this variable will
get overwritten. Redefining it as a struct member can avoid that.
Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
These patches are based on following three patches which are acked
by Scott wood scottw...@freescale.com:
1. http://patchwork.ozlabs.org/patch/417292/
Revert clk: ppc-corenet: Fix Section mismatch warning
2. http://patchwork.ozlabs.org/patch/417295/
powerpc: call of_clk_init() from time_init()
3. http://patchwork.ozlabs.org/patch/417297/
clk: ppc-corenet: fix section mismatch warning
drivers/clk/clk-ppc-corenet.c | 22 +++---
1 file changed, 15 insertions(+), 7 deletions(-)
diff --git a/drivers/clk/clk-ppc-corenet.c b/drivers/clk/clk-ppc-corenet.c
index 57a2de4..5e9bb18 100644
--- a/drivers/clk/clk-ppc-corenet.c
+++ b/drivers/clk/clk-ppc-corenet.c
@@ -19,6 +19,7 @@
struct cmux_clk {
struct clk_hw hw;
void __iomem *reg;
+ unsigned int clk_per_pll;
u32 flags;
};
@@ -27,14 +28,12 @@ struct cmux_clk {
#define CLKSEL_ADJUST BIT(0)
#define to_cmux_clk(p) container_of(p, struct cmux_clk, hw)
-static unsigned int clocks_per_pll;
-
static int cmux_set_parent(struct clk_hw *hw, u8 idx)
{
struct cmux_clk *clk = to_cmux_clk(hw);
u32 clksel;
- clksel = ((idx / clocks_per_pll) 2) + idx % clocks_per_pll;
+ clksel = ((idx / clk-clk_per_pll) 2) + idx % clk-clk_per_pll;
if (clk-flags CLKSEL_ADJUST)
clksel += 8;
clksel = (clksel 0xf) CLKSEL_SHIFT;
@@ -52,7 +51,7 @@ static u8 cmux_get_parent(struct clk_hw *hw)
clksel = (clksel CLKSEL_SHIFT) 0xf;
if (clk-flags CLKSEL_ADJUST)
clksel -= 8;
- clksel = (clksel 2) * clocks_per_pll + clksel % 4;
+ clksel = (clksel 2) * clk-clk_per_pll + clksel % 4;
return clksel;
}
@@ -72,6 +71,7 @@ static void __init core_mux_init(struct device_node *np)
u32 offset;
const char *clk_name;
const char **parent_names;
+ struct of_phandle_args clkspec;
rc = of_property_read_u32(np, reg, offset);
if (rc) {
@@ -105,6 +105,17 @@ static void __init core_mux_init(struct device_node *np)
goto err_clk;
}
+ rc = of_parse_phandle_with_args(np, clocks, #clock-cells, 0,
+ clkspec);
+ if (rc) {
+ pr_err(%s: parse clock node error\n, __func__);
+ goto err_clk;
+ }
+
+ cmux_clk-clk_per_pll = of_property_count_strings(clkspec.np,
+ clock-output-names);
+ of_node_put(clkspec.np);
+
node = of_find_compatible_node(NULL, NULL, fsl,p4080-clockgen);
if (node (offset = 0x80))
cmux_clk-flags = CLKSEL_ADJUST;
@@ -181,9 +192,6 @@ static void __init core_pll_init(struct device_node *np)
goto err_map;
}
- /* output clock number per PLL */
- clocks_per_pll = count;
-
subclks = kzalloc(sizeof(struct clk *) * count, GFP_KERNEL);
if (!subclks) {
pr_err(%s: could not allocate subclks\n, __func__);
--
2.1.0.27.g96db324
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH V11 10/17] powerpc/powernv: Use pci_dn in PCI config accessor
The PCI config accessors rely on device node. Unfortunately, VFs
don't have corresponding device nodes. So we have to switch to
pci_dn for PCI config access.
Signed-off-by: Gavin Shan gws...@linux.vnet.ibm.com
---
arch/powerpc/platforms/powernv/eeh-powernv.c | 14 +-
arch/powerpc/platforms/powernv/pci.c | 69 ++
arch/powerpc/platforms/powernv/pci.h |4 +-
3 files changed, 40 insertions(+), 47 deletions(-)
diff --git a/arch/powerpc/platforms/powernv/eeh-powernv.c
b/arch/powerpc/platforms/powernv/eeh-powernv.c
index 1d19e79..c63b6c1 100644
--- a/arch/powerpc/platforms/powernv/eeh-powernv.c
+++ b/arch/powerpc/platforms/powernv/eeh-powernv.c
@@ -419,21 +419,31 @@ static inline bool powernv_eeh_cfg_blocked(struct
device_node *dn)
static int powernv_eeh_read_config(struct device_node *dn,
int where, int size, u32 *val)
{
+ struct pci_dn *pdn = PCI_DN(dn);
+
+ if (!pdn)
+ return PCIBIOS_DEVICE_NOT_FOUND;
+
if (powernv_eeh_cfg_blocked(dn)) {
*val = 0x;
return PCIBIOS_SET_FAILED;
}
- return pnv_pci_cfg_read(dn, where, size, val);
+ return pnv_pci_cfg_read(pdn, where, size, val);
}
static int powernv_eeh_write_config(struct device_node *dn,
int where, int size, u32 val)
{
+ struct pci_dn *pdn = PCI_DN(dn);
+
+ if (!pdn)
+ return PCIBIOS_DEVICE_NOT_FOUND;
+
if (powernv_eeh_cfg_blocked(dn))
return PCIBIOS_SET_FAILED;
- return pnv_pci_cfg_write(dn, where, size, val);
+ return pnv_pci_cfg_write(pdn, where, size, val);
}
/**
diff --git a/arch/powerpc/platforms/powernv/pci.c
b/arch/powerpc/platforms/powernv/pci.c
index 4945e87..b7d4b9d 100644
--- a/arch/powerpc/platforms/powernv/pci.c
+++ b/arch/powerpc/platforms/powernv/pci.c
@@ -366,9 +366,9 @@ static void pnv_pci_handle_eeh_config(struct pnv_phb *phb,
u32 pe_no)
spin_unlock_irqrestore(phb-lock, flags);
}
-static void pnv_pci_config_check_eeh(struct pnv_phb *phb,
-struct device_node *dn)
+static void pnv_pci_config_check_eeh(struct pci_dn *pdn)
{
+ struct pnv_phb *phb = pdn-phb-private_data;
u8 fstate;
__be16 pcierr;
int pe_no;
@@ -379,7 +379,7 @@ static void pnv_pci_config_check_eeh(struct pnv_phb *phb,
* setup that yet. So all ER errors should be mapped to
* reserved PE.
*/
- pe_no = PCI_DN(dn)-pe_number;
+ pe_no = pdn-pe_number;
if (pe_no == IODA_INVALID_PE) {
if (phb-type == PNV_PHB_P5IOC2)
pe_no = 0;
@@ -407,8 +407,7 @@ static void pnv_pci_config_check_eeh(struct pnv_phb *phb,
}
cfg_dbg( - EEH check, bdfn=%04x PE#%d fstate=%x\n,
- (PCI_DN(dn)-busno 8) | (PCI_DN(dn)-devfn),
- pe_no, fstate);
+ (pdn-busno 8) | (pdn-devfn), pe_no, fstate);
/* Clear the frozen state if applicable */
if (fstate == OPAL_EEH_STOPPED_MMIO_FREEZE ||
@@ -425,10 +424,9 @@ static void pnv_pci_config_check_eeh(struct pnv_phb *phb,
}
}
-int pnv_pci_cfg_read(struct device_node *dn,
+int pnv_pci_cfg_read(struct pci_dn *pdn,
int where, int size, u32 *val)
{
- struct pci_dn *pdn = PCI_DN(dn);
struct pnv_phb *phb = pdn-phb-private_data;
u32 bdfn = (pdn-busno 8) | pdn-devfn;
s64 rc;
@@ -462,10 +460,9 @@ int pnv_pci_cfg_read(struct device_node *dn,
return PCIBIOS_SUCCESSFUL;
}
-int pnv_pci_cfg_write(struct device_node *dn,
+int pnv_pci_cfg_write(struct pci_dn *pdn,
int where, int size, u32 val)
{
- struct pci_dn *pdn = PCI_DN(dn);
struct pnv_phb *phb = pdn-phb-private_data;
u32 bdfn = (pdn-busno 8) | pdn-devfn;
@@ -489,18 +486,17 @@ int pnv_pci_cfg_write(struct device_node *dn,
}
#if CONFIG_EEH
-static bool pnv_pci_cfg_check(struct pci_controller *hose,
- struct device_node *dn)
+static bool pnv_pci_cfg_check(struct pci_dn *pdn)
{
struct eeh_dev *edev = NULL;
- struct pnv_phb *phb = hose-private_data;
+ struct pnv_phb *phb = pdn-phb-private_data;
/* EEH not enabled ? */
if (!(phb-flags PNV_PHB_FLAG_EEH))
return true;
/* PE reset or device removed ? */
- edev = of_node_to_eeh_dev(dn);
+ edev = pdn-edev;
if (edev) {
if (edev-pe
(edev-pe-state EEH_PE_CFG_BLOCKED))
@@ -513,8 +509,7 @@ static bool pnv_pci_cfg_check(struct pci_controller *hose,
return true;
}
#else
-static inline pnv_pci_cfg_check(struct pci_controller *hose,
- struct device_node *dn)
+static inline pnv_pci_cfg_check(struct pci_dn *pdn)
{
return true;
}
@@ -524,32 +519,26
[PATCH V11 12/17] powerpc/powernv: Reserve additional space for IOV BAR according to the number of total_pe
On PHB3, PF IOV BAR will be covered by M64 BAR to have better PE isolation.
Mostly the total_pe number is different from the total_VFs, which will lead
to a conflict between MMIO space and the PE number.
For example, total_VFs is 128 and total_pe is 256, then the second half of
M64 BAR space will be part of other PCI device, which may already belongs
to other PEs.
This patch reserve additional space for the PF IOV BAR, which is total_pe
number of VF's BAR size. By doing so, it prevents the conflict.
Signed-off-by: Wei Yang weiy...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/machdep.h|4 ++
arch/powerpc/include/asm/pci-bridge.h |3 ++
arch/powerpc/kernel/pci-common.c |5 +++
arch/powerpc/platforms/powernv/pci-ioda.c | 59 +
4 files changed, 71 insertions(+)
diff --git a/arch/powerpc/include/asm/machdep.h
b/arch/powerpc/include/asm/machdep.h
index c8175a3..965547c 100644
--- a/arch/powerpc/include/asm/machdep.h
+++ b/arch/powerpc/include/asm/machdep.h
@@ -250,6 +250,10 @@ struct machdep_calls {
/* Reset the secondary bus of bridge */
void (*pcibios_reset_secondary_bus)(struct pci_dev *dev);
+#ifdef CONFIG_PCI_IOV
+ void (*pcibios_fixup_sriov)(struct pci_bus *bus);
+#endif /* CONFIG_PCI_IOV */
+
/* Called to shutdown machine specific hardware not already controlled
* by other drivers.
*/
diff --git a/arch/powerpc/include/asm/pci-bridge.h
b/arch/powerpc/include/asm/pci-bridge.h
index 334e745..b857ec4 100644
--- a/arch/powerpc/include/asm/pci-bridge.h
+++ b/arch/powerpc/include/asm/pci-bridge.h
@@ -170,6 +170,9 @@ struct pci_dn {
#define IODA_INVALID_PE(-1)
#ifdef CONFIG_PPC_POWERNV
int pe_number;
+#ifdef CONFIG_PCI_IOV
+ u16 max_vfs;/* number of VFs IOV BAR expended */
+#endif /* CONFIG_PCI_IOV */
#endif
struct list_head child_list;
struct list_head list;
diff --git a/arch/powerpc/kernel/pci-common.c b/arch/powerpc/kernel/pci-common.c
index 889f743..832b7e1 100644
--- a/arch/powerpc/kernel/pci-common.c
+++ b/arch/powerpc/kernel/pci-common.c
@@ -1636,6 +1636,11 @@ void pcibios_scan_phb(struct pci_controller *hose)
if (ppc_md.pcibios_fixup_phb)
ppc_md.pcibios_fixup_phb(hose);
+#ifdef CONFIG_PCI_IOV
+ if (ppc_md.pcibios_fixup_sriov)
+ ppc_md.pcibios_fixup_sriov(bus);
+#endif /* CONFIG_PCI_IOV */
+
/* Configure PCI Express settings */
if (bus !pci_has_flag(PCI_PROBE_ONLY)) {
struct pci_bus *child;
diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c
b/arch/powerpc/platforms/powernv/pci-ioda.c
index 31335a7..6704fdf 100644
--- a/arch/powerpc/platforms/powernv/pci-ioda.c
+++ b/arch/powerpc/platforms/powernv/pci-ioda.c
@@ -1721,6 +1721,62 @@ static void pnv_pci_init_ioda_msis(struct pnv_phb *phb)
static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { }
#endif /* CONFIG_PCI_MSI */
+#ifdef CONFIG_PCI_IOV
+static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev)
+{
+ struct pci_controller *hose;
+ struct pnv_phb *phb;
+ struct resource *res;
+ int i;
+ resource_size_t size;
+ struct pci_dn *pdn;
+
+ if (!pdev-is_physfn || pdev-is_added)
+ return;
+
+ hose = pci_bus_to_host(pdev-bus);
+ phb = hose-private_data;
+
+ pdn = pci_get_pdn(pdev);
+ pdn-max_vfs = 0;
+
+ for (i = PCI_IOV_RESOURCES; i = PCI_IOV_RESOURCE_END; i++) {
+ res = pdev-resource[i];
+ if (!res-flags || res-parent)
+ continue;
+ if (!pnv_pci_is_mem_pref_64(res-flags)) {
+ dev_warn(pdev-dev, Skipping expanding IOV BAR %pR
on %s\n,
+res, pci_name(pdev));
+ continue;
+ }
+
+ dev_dbg(pdev-dev, Fixing VF BAR[%d] %pR to\n, i, res);
+ size = pci_iov_resource_size(pdev, i);
+ res-end = res-start + size * phb-ioda.total_pe - 1;
+ dev_dbg(pdev-dev,%pR\n, res);
+ dev_info(pdev-dev, VF BAR%d: %pR (expanded to %d VFs for PE
alignment),
+ i - PCI_IOV_RESOURCES,
+ res, phb-ioda.total_pe);
+ }
+ pdn-max_vfs = phb-ioda.total_pe;
+}
+
+static void pnv_pci_ioda_fixup_sriov(struct pci_bus *bus)
+{
+ struct pci_dev *pdev;
+ struct pci_bus *b;
+
+ list_for_each_entry(pdev, bus-devices, bus_list) {
+ b = pdev-subordinate;
+
+ if (b)
+ pnv_pci_ioda_fixup_sriov(b);
+
+ pnv_pci_ioda_fixup_iov_resources(pdev);
+ }
+}
+#endif /* CONFIG_PCI_IOV */
+
/*
* This function is supposed to be called on basis of PE from top
* to bottom style. So the the I/O or MMIO segment assigned to
@@ -2097,6 +2153,9 @@
[PATCH V11 11/17] powerpc/powernv: Allocate pe-iommu_table dynamically
Current iommu_table of a PE is a static field. This will have a problem
when iommu_free_table is called.
This patch allocate iommu_table dynamically.
Signed-off-by: Wei Yang weiy...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/iommu.h |3 +++
arch/powerpc/platforms/powernv/pci-ioda.c | 26 ++
arch/powerpc/platforms/powernv/pci.h |2 +-
3 files changed, 18 insertions(+), 13 deletions(-)
diff --git a/arch/powerpc/include/asm/iommu.h b/arch/powerpc/include/asm/iommu.h
index 9cfa370..5574eeb 100644
--- a/arch/powerpc/include/asm/iommu.h
+++ b/arch/powerpc/include/asm/iommu.h
@@ -78,6 +78,9 @@ struct iommu_table {
struct iommu_group *it_group;
#endif
void (*set_bypass)(struct iommu_table *tbl, bool enable);
+#ifdef CONFIG_PPC_POWERNV
+ void *data;
+#endif
};
/* Pure 2^n version of get_order */
diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c
b/arch/powerpc/platforms/powernv/pci-ioda.c
index 665f57c..31335a7 100644
--- a/arch/powerpc/platforms/powernv/pci-ioda.c
+++ b/arch/powerpc/platforms/powernv/pci-ioda.c
@@ -890,6 +890,10 @@ static void pnv_ioda_setup_bus_PE(struct pci_bus *bus, int
all)
return;
}
+ pe-tce32_table = kzalloc_node(sizeof(struct iommu_table),
+ GFP_KERNEL, hose-node);
+ pe-tce32_table-data = pe;
+
/* Associate it with all child devices */
pnv_ioda_setup_same_PE(bus, pe);
@@ -979,7 +983,7 @@ static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb,
struct pci_dev *pdev
pe = phb-ioda.pe_array[pdn-pe_number];
WARN_ON(get_dma_ops(pdev-dev) != dma_iommu_ops);
- set_iommu_table_base_and_group(pdev-dev, pe-tce32_table);
+ set_iommu_table_base_and_group(pdev-dev, pe-tce32_table);
}
static int pnv_pci_ioda_dma_set_mask(struct pnv_phb *phb,
@@ -1006,7 +1010,7 @@ static int pnv_pci_ioda_dma_set_mask(struct pnv_phb *phb,
} else {
dev_info(pdev-dev, Using 32-bit DMA via iommu\n);
set_dma_ops(pdev-dev, dma_iommu_ops);
- set_iommu_table_base(pdev-dev, pe-tce32_table);
+ set_iommu_table_base(pdev-dev, pe-tce32_table);
}
*pdev-dev.dma_mask = dma_mask;
return 0;
@@ -1043,9 +1047,9 @@ static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe,
list_for_each_entry(dev, bus-devices, bus_list) {
if (add_to_iommu_group)
set_iommu_table_base_and_group(dev-dev,
- pe-tce32_table);
+ pe-tce32_table);
else
- set_iommu_table_base(dev-dev, pe-tce32_table);
+ set_iommu_table_base(dev-dev, pe-tce32_table);
if (dev-subordinate)
pnv_ioda_setup_bus_dma(pe, dev-subordinate,
@@ -1135,8 +1139,7 @@ static void pnv_pci_ioda2_tce_invalidate(struct
pnv_ioda_pe *pe,
void pnv_pci_ioda_tce_invalidate(struct iommu_table *tbl,
__be64 *startp, __be64 *endp, bool rm)
{
- struct pnv_ioda_pe *pe = container_of(tbl, struct pnv_ioda_pe,
- tce32_table);
+ struct pnv_ioda_pe *pe = tbl-data;
struct pnv_phb *phb = pe-phb;
if (phb-type == PNV_PHB_IODA1)
@@ -1202,7 +1205,7 @@ static void pnv_pci_ioda_setup_dma_pe(struct pnv_phb *phb,
}
/* Setup linux iommu table */
- tbl = pe-tce32_table;
+ tbl = pe-tce32_table;
pnv_pci_setup_iommu_table(tbl, addr, TCE32_TABLE_SIZE * segs,
base 28, IOMMU_PAGE_SHIFT_4K);
@@ -1240,8 +1243,7 @@ static void pnv_pci_ioda_setup_dma_pe(struct pnv_phb *phb,
static void pnv_pci_ioda2_set_bypass(struct iommu_table *tbl, bool enable)
{
- struct pnv_ioda_pe *pe = container_of(tbl, struct pnv_ioda_pe,
- tce32_table);
+ struct pnv_ioda_pe *pe = tbl-data;
uint16_t window_id = (pe-pe_number 1 ) + 1;
int64_t rc;
@@ -1286,10 +1288,10 @@ static void pnv_pci_ioda2_setup_bypass_pe(struct
pnv_phb *phb,
pe-tce_bypass_base = 1ull 59;
/* Install set_bypass callback for VFIO */
- pe-tce32_table.set_bypass = pnv_pci_ioda2_set_bypass;
+ pe-tce32_table-set_bypass = pnv_pci_ioda2_set_bypass;
/* Enable bypass by default */
- pnv_pci_ioda2_set_bypass(pe-tce32_table, true);
+ pnv_pci_ioda2_set_bypass(pe-tce32_table, true);
}
static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
@@ -1337,7 +1339,7 @@ static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb
*phb,
}
/* Setup linux iommu table */
- tbl = pe-tce32_table;
+ tbl = pe-tce32_table;
pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, 0,
IOMMU_PAGE_SHIFT_4K);
Re: [PATCH 3/3] CXL: Add reset to sysfs
@@ -806,8 +837,8 @@ static int cxl_read_vsec(struct cxl *adapter, struct pci_dev *dev) CXL_READ_VSEC_BASE_IMAGE(dev, vsec, adapter-base_image); CXL_READ_VSEC_IMAGE_STATE(dev, vsec, image_state); adapter-user_image_loaded = !!(image_state CXL_VSEC_USER_IMAGE_LOADED); -adapter-perst_loads_image = !!(image_state CXL_VSEC_PERST_LOADS_IMAGE); -adapter-perst_select_user = !!(image_state CXL_VSEC_PERST_SELECT_USER); +adapter-perst_loads_image = true; +adapter-perst_select_user = !!(image_state CXL_VSEC_USER_IMAGE_LOADED); ... +if ((rc = cxl_update_image_control(adapter))) +goto err2; Thanks - that seems like a better default than what we had before, should make things more stable :) In fact, would you mind pulling this part out into a separate patch? It seems like a serious contender to go to stable as it might help with cards that get into a funny state and don't come back up properly after a reboot (symptoms are that the adapter wide tlbia / slbia times out and the driver aborts initialisation). Cheers, -Ian ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[patch added to the 3.12 stable tree] powerpc/powernv: Switch off MMU before entering nap/sleep/rvwinkle mode
From: Paul Mackerras pau...@samba.org This patch has been added to the 3.12 stable tree. If you have any objections, please let us know. === commit 8117ac6a6c2fa0f847ff6a21a1f32c8d2c8501d0 upstream. Currently, when going idle, we set the flag indicating that we are in nap mode (paca-kvm_hstate.hwthread_state) and then execute the nap (or sleep or rvwinkle) instruction, all with the MMU on. This is bad for two reasons: (a) the architecture specifies that those instructions must be executed with the MMU off, and in fact with only the SF, HV, ME and possibly RI bits set, and (b) this introduces a race, because as soon as we set the flag, another thread can switch the MMU to a guest context. If the race is lost, this thread will typically start looping on relocation-on ISIs at 0xc...4400. This fixes it by setting the MSR as required by the architecture before setting the flag or executing the nap/sleep/rvwinkle instruction. [ shre...@linux.vnet.ibm.com: Edited to handle LE ] Signed-off-by: Paul Mackerras pau...@samba.org Signed-off-by: Shreyas B. Prabhu shre...@linux.vnet.ibm.com Cc: Benjamin Herrenschmidt b...@kernel.crashing.org Cc: Michael Ellerman m...@ellerman.id.au Cc: linuxppc-dev@lists.ozlabs.org Signed-off-by: Michael Ellerman m...@ellerman.id.au Signed-off-by: Jiri Slaby jsl...@suse.cz --- arch/powerpc/include/asm/reg.h| 1 + arch/powerpc/kernel/idle_power7.S | 16 2 files changed, 17 insertions(+) diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h index cb9c1740cee0..390e09872b77 100644 --- a/arch/powerpc/include/asm/reg.h +++ b/arch/powerpc/include/asm/reg.h @@ -116,6 +116,7 @@ /* Server variant */ #define MSR_ (MSR_ME | MSR_RI | MSR_IR | MSR_DR | MSR_ISF |MSR_HV) +#define MSR_IDLE (MSR_ME | MSR_SF | MSR_HV) #define MSR_KERNEL (MSR_ | MSR_64BIT) #define MSR_USER32 (MSR_ | MSR_PR | MSR_EE) #define MSR_USER64 (MSR_USER32 | MSR_64BIT) diff --git a/arch/powerpc/kernel/idle_power7.S b/arch/powerpc/kernel/idle_power7.S index e11863f4e595..df930727f73b 100644 --- a/arch/powerpc/kernel/idle_power7.S +++ b/arch/powerpc/kernel/idle_power7.S @@ -84,6 +84,22 @@ _GLOBAL(power7_nap) std r9,_MSR(r1) std r1,PACAR1(r13) + /* +* Go to real mode to do the nap, as required by the architecture. +* Also, we need to be in real mode before setting hwthread_state, +* because as soon as we do that, another thread can switch +* the MMU context to the guest. +*/ + LOAD_REG_IMMEDIATE(r5, MSR_IDLE) + li r6, MSR_RI + andcr6, r9, r6 + LOAD_REG_ADDR(r7, power7_enter_nap_mode) + mtmsrd r6, 1 /* clear RI before setting SRR0/1 */ + mtspr SPRN_SRR0, r7 + mtspr SPRN_SRR1, r5 + rfid + +power7_enter_nap_mode: #ifdef CONFIG_KVM_BOOK3S_64_HV /* Tell KVM we're napping */ li r4,KVM_HWTHREAD_IN_NAP -- 2.2.1 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[git pull] Please pull mpe/linux.git powerpc-3.19-4 tag
Hi Linus, Please pull some more powerpc fixes for 3.19: The following changes since commit eaa27f34e91a14cdceed26ed6c6793ec1d186115: linux 3.19-rc4 (2015-01-11 12:44:53 -0800) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/mpe/linux.git tags/powerpc-3.19-4 for you to fetch changes up to a87e810f61b49f19bd29ea564b7cd1e92e43d989: powerpc: Work around gcc bug in current_thread_info() (2015-01-12 16:40:02 +1100) Anton Blanchard (1): powernv: Fix OPAL tracepoint code Ian Munsie (1): cxl: Fix issues when unmapping contexts Michael Ellerman (1): powerpc: Work around gcc bug in current_thread_info() arch/powerpc/include/asm/thread_info.h | 13 ++-- arch/powerpc/platforms/powernv/opal-wrappers.S | 1 - drivers/misc/cxl/context.c | 82 -- drivers/misc/cxl/file.c| 14 +++-- 4 files changed, 78 insertions(+), 32 deletions(-) signature.asc Description: This is a digitally signed message part ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
RE: [PATCH] fsl/smp: add low power boot support to replace spin boot
Hi all,
U-boot patch link:
http://patchwork.ozlabs.org/patch/429265/
Regards,
-Dongsheng
-Original Message-
From: Dongsheng Wang [mailto:dongsheng.w...@freescale.com]
Sent: Thursday, January 15, 2015 2:06 PM
To: Wood Scott-B07421; Sun York-R58495; Li Yang-Leo-R58472
Cc: linuxppc-dev@lists.ozlabs.org; Wang Dongsheng-B40534
Subject: [PATCH] fsl/smp: add low power boot support to replace spin boot
From: Wang Dongsheng dongsheng.w...@freescale.com
U-boot put non-boot cpus into an low power state(PW10/PW20 or DOZE) when cpu
powered up. To exit low power state kernel will send DOORBELL or MPIC-IPI
signal to all those CPUs.
e500/e500v2 use mpic to send IPI signal.
e500mc and later use doorbell to send IPI signal.
This feature tested on:
POWER UP TEST:
P1022DS(e500v2),96k times.
P4080(e500mc), 110k times.
T1024(e5500), 83k times.
T4240(e6500), 150k times.
CPU HOTPLUG TEST:
P1022DS(e500v2),1.4 million times.
P4080(e500mc), 1.8 million times.
T1024(e5500), 1.3 million times.
T4240(e6500), 1.1 million times.
Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com
diff --git a/arch/powerpc/include/asm/mpic.h b/arch/powerpc/include/asm/mpic.h
index 754f93d..8af6a25 100644
--- a/arch/powerpc/include/asm/mpic.h
+++ b/arch/powerpc/include/asm/mpic.h
@@ -474,6 +474,15 @@ extern int mpic_cpu_get_priority(void);
/* Set the current cpu priority for this cpu */
extern void mpic_cpu_set_priority(int prio);
+/* Set cpu priority */
+void mpic_set_cpu_priority(int nr, int prio);
+
+/* Set cpu EOI */
+void mpic_cpu_eoi_write(int cpu);
+
+/* CPU ACK interrupt */
+void mpic_cpu_ack(int cpu);
+
/* Request IPIs on primary mpic */
extern void mpic_request_ipis(void);
diff --git a/arch/powerpc/platforms/85xx/smp.c
b/arch/powerpc/platforms/85xx/smp.c
index d7c1e69..6c54632 100644
--- a/arch/powerpc/platforms/85xx/smp.c
+++ b/arch/powerpc/platforms/85xx/smp.c
@@ -193,6 +193,30 @@ static int smp_85xx_kick_cpu(int nr)
const u64 *cpu_rel_addr;
__iomem struct epapr_spin_table *spin_table;
struct device_node *np;
+
+ /*
+ * DOORBELL:
+ * When kernel kick one of cpus, all cpus will be wakenup. To make
+ * sure that only the target cpu is effected, other cpus (by checking
+ * spin_table-addr_l) should go back to low power state.
+ *
+ * U-boot has renumber the cpu PIR Why we need to set all of PIR to
+ * the same value?
+ * A: Before kernel kicking cpu, the doorbell message was not configured
+ * for target cpu(cpu_messages-data). If we try to send a
+ * non-configured message to target cpu, it cannot correctly receive
+ * doorbell interrput. So SET ALL OF CPU'S PIR to the same value to
+ * let all cpus catch the interrupt.
+ *
+ * Why set PIR to zero?
+ * A: U-boot cannot know how many cpus will be kicked up(Kernel allow us
+ * to configure NR_CPUS) and IPI is a per_cpu variable, u-boot cannot
+ * set a appropriate PIR for every cpu, but the boot cpu(CPU0) always be
+ * there. U-boot set PIR to zero as a default PIR ID for each CPU, so
+ * initialize the kick_cpus to 0.
+ */
+ u32 kick_cpus = 0;
+
int hw_cpu = get_hard_smp_processor_id(nr);
int ioremappable;
int ret = 0;
@@ -251,8 +275,7 @@ static int smp_85xx_kick_cpu(int nr)
spin_table = phys_to_virt(*cpu_rel_addr);
local_irq_save(flags);
-#ifdef CONFIG_PPC32
-#ifdef CONFIG_HOTPLUG_CPU
+#if defined(CONFIG_PPC32) defined(CONFIG_HOTPLUG_CPU)
/* Corresponding to generic_set_cpu_dead() */
generic_set_cpu_up(nr);
@@ -292,11 +315,58 @@ static int smp_85xx_kick_cpu(int nr)
__secondary_hold_acknowledge = -1;
}
#endif
+
flush_spin_table(spin_table);
- out_be32(spin_table-pir, hw_cpu);
+ /*
+ * U-boot will wait kernel send eoi to MPIC, after EOI has send
+ * kernel will set PIR for uboot, let uboot know EOI has send.
+ */
+ out_be32(spin_table-pir, 0);
+
+#ifdef CONFIG_PPC32
out_be32(spin_table-addr_l, __pa(__early_start));
+#else
+ out_be64((u64 *)(spin_table-addr_h),
+ __pa(ppc_function_entry(generic_secondary_smp_init)));
+#endif
flush_spin_table(spin_table);
+ /*
+ * e500, e500v2 need to use MPIC to send IPI signal, so we need to
+ * open IPI firstly.
+ */
+ if (!cpu_has_feature(CPU_FTR_DBELL)) {
+ mpic_set_cpu_priority(nr, 0);
+ kick_cpus = nr;
+ }
+
+ /* Let cpu exit low power state, and from u-boot jump to kernel */
+ arch_send_call_function_single_ipi(kick_cpus);
+
+ /*
+ * Let we ACK interrput and Send EOI signal to finish INT server
+ * U-boot has read EPR to ACK interrput when MPIC work in external
+ * proxy mode. Without the external proxy facility, we need to read
+ * MPIC ACK
[PATCH V11 03/17] PCI: Add weak pcibios_iov_resource_alignment() interface
The alignment of PF's IOV BAR is designed to be the individual size of a
VF's BAR size. This works fine for many platforms, but on PowerNV platform
it needs some change.
The original alignment works, since at sizing and assigning stage the
requirement is from an individual VF's BAR size instead of the PF's IOV
BAR. This is the reason for the original code to just retrieve the
individual VF BAR size as the alignment.
On PowerNV platform, it is required to align the whole PF IOV BAR to a
hardware segment. Based on this fact, the alignment of PF's IOV BAR should
be calculated seperately.
This patch introduces a weak pcibios_iov_resource_alignment() interface,
which gives platform a chance to implement specific method to calculate
the PF's IOV BAR alignment.
Signed-off-by: Wei Yang weiy...@linux.vnet.ibm.com
---
drivers/pci/iov.c | 11 ++-
include/linux/pci.h |3 +++
2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/iov.c b/drivers/pci/iov.c
index 933d8cc..5f48201 100644
--- a/drivers/pci/iov.c
+++ b/drivers/pci/iov.c
@@ -556,6 +556,12 @@ int pci_iov_resource_bar(struct pci_dev *dev, int resno)
4 * (resno - PCI_IOV_RESOURCES);
}
+resource_size_t __weak pcibios_iov_resource_alignment(struct pci_dev *dev,
+ int resno, resource_size_t align)
+{
+ return align;
+}
+
/**
* pci_sriov_resource_alignment - get resource alignment for VF BAR
* @dev: the PCI device
@@ -570,12 +576,15 @@ resource_size_t pci_sriov_resource_alignment(struct
pci_dev *dev, int resno)
{
struct resource tmp;
int reg = pci_iov_resource_bar(dev, resno);
+ resource_size_t align;
if (!reg)
return 0;
__pci_read_base(dev, pci_bar_unknown, tmp, reg);
- return resource_alignment(tmp);
+ align = resource_alignment(tmp);
+
+ return pcibios_iov_resource_alignment(dev, resno, align);
}
/**
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 74ef944..ae7a7ea 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -1163,6 +1163,9 @@ unsigned char pci_bus_max_busnr(struct pci_bus *bus);
void pci_setup_bridge(struct pci_bus *bus);
resource_size_t pcibios_window_alignment(struct pci_bus *bus,
unsigned long type);
+resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev,
+int resno,
+resource_size_t align);
#define PCI_VGA_STATE_CHANGE_BRIDGE (1 0)
#define PCI_VGA_STATE_CHANGE_DECODES (1 1)
--
1.7.9.5
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH V11 17/17] powerpc/powernv: Group VF PE when IOV BAR is big on PHB3
When IOV BAR is big, each of it is covered by 4 M64 window. This leads to
several VF PE sits in one PE in terms of M64.
This patch group VF PEs according to the M64 allocation.
Signed-off-by: Wei Yang weiy...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/pci-bridge.h |2 +-
arch/powerpc/platforms/powernv/pci-ioda.c | 188 +++--
2 files changed, 149 insertions(+), 41 deletions(-)
diff --git a/arch/powerpc/include/asm/pci-bridge.h
b/arch/powerpc/include/asm/pci-bridge.h
index 7156486..ad39a42 100644
--- a/arch/powerpc/include/asm/pci-bridge.h
+++ b/arch/powerpc/include/asm/pci-bridge.h
@@ -177,7 +177,7 @@ struct pci_dn {
#define M64_PER_IOV 4
int m64_per_iov;
#define IODA_INVALID_M64(-1)
- int m64_wins[PCI_SRIOV_NUM_BARS];
+ int m64_wins[PCI_SRIOV_NUM_BARS][M64_PER_IOV];
#endif /* CONFIG_PCI_IOV */
#endif
struct list_head child_list;
diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c
b/arch/powerpc/platforms/powernv/pci-ioda.c
index 23ea873..8456ae8 100644
--- a/arch/powerpc/platforms/powernv/pci-ioda.c
+++ b/arch/powerpc/platforms/powernv/pci-ioda.c
@@ -1093,26 +1093,27 @@ static int pnv_pci_vf_release_m64(struct pci_dev *pdev)
struct pci_controller *hose;
struct pnv_phb*phb;
struct pci_dn *pdn;
- inti;
+ inti, j;
bus = pdev-bus;
hose = pci_bus_to_host(bus);
phb = hose-private_data;
pdn = pci_get_pdn(pdev);
- for (i = 0; i PCI_SRIOV_NUM_BARS; i++) {
- if (pdn-m64_wins[i] == IODA_INVALID_M64)
- continue;
- opal_pci_phb_mmio_enable(phb-opal_id,
- OPAL_M64_WINDOW_TYPE, pdn-m64_wins[i], 0);
- clear_bit(pdn-m64_wins[i], phb-ioda.m64_bar_alloc);
- pdn-m64_wins[i] = IODA_INVALID_M64;
- }
+ for (i = 0; i PCI_SRIOV_NUM_BARS; i++)
+ for (j = 0; j M64_PER_IOV; j++) {
+ if (pdn-m64_wins[i][j] == IODA_INVALID_M64)
+ continue;
+ opal_pci_phb_mmio_enable(phb-opal_id,
+ OPAL_M64_WINDOW_TYPE, pdn-m64_wins[i][j], 0);
+ clear_bit(pdn-m64_wins[i][j],
phb-ioda.m64_bar_alloc);
+ pdn-m64_wins[i][j] = IODA_INVALID_M64;
+ }
return 0;
}
-static int pnv_pci_vf_assign_m64(struct pci_dev *pdev)
+static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 vf_num)
{
struct pci_bus*bus;
struct pci_controller *hose;
@@ -1120,17 +1121,33 @@ static int pnv_pci_vf_assign_m64(struct pci_dev *pdev)
struct pci_dn *pdn;
unsigned int win;
struct resource *res;
- inti;
+ inti, j;
int64_trc;
+ inttotal_vfs;
+ resource_size_tsize, start;
+ intpe_num;
+ intvf_groups;
+ intvf_per_group;
bus = pdev-bus;
hose = pci_bus_to_host(bus);
phb = hose-private_data;
pdn = pci_get_pdn(pdev);
+ total_vfs = pci_sriov_get_totalvfs(pdev);
/* Initialize the m64_wins to IODA_INVALID_M64 */
for (i = 0; i PCI_SRIOV_NUM_BARS; i++)
- pdn-m64_wins[i] = IODA_INVALID_M64;
+ for (j = 0; j M64_PER_IOV; j++)
+ pdn-m64_wins[i][j] = IODA_INVALID_M64;
+
+ if (pdn-m64_per_iov == M64_PER_IOV) {
+ vf_groups = (vf_num = M64_PER_IOV) ? vf_num: M64_PER_IOV;
+ vf_per_group = (vf_num = M64_PER_IOV)? 1:
+ __roundup_pow_of_two(vf_num) / pdn-m64_per_iov;
+ } else {
+ vf_groups = 1;
+ vf_per_group = 1;
+ }
for (i = 0; i PCI_SRIOV_NUM_BARS; i++) {
res = pdev-resource + PCI_IOV_RESOURCES + i;
@@ -1140,33 +1157,61 @@ static int pnv_pci_vf_assign_m64(struct pci_dev *pdev)
if (!pnv_pci_is_mem_pref_64(res-flags))
continue;
- do {
- win = find_next_zero_bit(phb-ioda.m64_bar_alloc,
- phb-ioda.m64_bar_idx + 1, 0);
-
- if (win = phb-ioda.m64_bar_idx + 1)
- goto m64_failed;
- } while (test_and_set_bit(win, phb-ioda.m64_bar_alloc));
+ for (j = 0; j vf_groups; j++) {
+ do {
+ win =
find_next_zero_bit(phb-ioda.m64_bar_alloc,
+ phb-ioda.m64_bar_idx + 1, 0);
+
+ if (win = phb-ioda.m64_bar_idx + 1)
+ goto m64_failed;
+
[PATCH V11 16/17] powerpc/powernv: Reserve additional space for IOV BAR, with m64_per_iov supported
M64 aperture size is limited on PHB3. When the IOV BAR is too big, this
will exceed the limitation and failed to be assigned.
This patch introduce a different mechanism based on the IOV BAR size:
IOV BAR size is smaller than 64M, expand to total_pe.
IOV BAR size is bigger than 64M, roundup power2.
Signed-off-by: Wei Yang weiy...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/pci-bridge.h |2 ++
arch/powerpc/platforms/powernv/pci-ioda.c | 33 ++---
2 files changed, 32 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/include/asm/pci-bridge.h
b/arch/powerpc/include/asm/pci-bridge.h
index d61c384..7156486 100644
--- a/arch/powerpc/include/asm/pci-bridge.h
+++ b/arch/powerpc/include/asm/pci-bridge.h
@@ -174,6 +174,8 @@ struct pci_dn {
u16 max_vfs;/* number of VFs IOV BAR expended */
u16 vf_pes; /* VF PE# under this PF */
int offset; /* PE# for the first VF PE */
+#define M64_PER_IOV 4
+ int m64_per_iov;
#define IODA_INVALID_M64(-1)
int m64_wins[PCI_SRIOV_NUM_BARS];
#endif /* CONFIG_PCI_IOV */
diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c
b/arch/powerpc/platforms/powernv/pci-ioda.c
index 94fe6e1..23ea873 100644
--- a/arch/powerpc/platforms/powernv/pci-ioda.c
+++ b/arch/powerpc/platforms/powernv/pci-ioda.c
@@ -2180,6 +2180,7 @@ static void pnv_pci_ioda_fixup_iov_resources(struct
pci_dev *pdev)
int i;
resource_size_t size;
struct pci_dn *pdn;
+ int mul, total_vfs;
if (!pdev-is_physfn || pdev-is_added)
return;
@@ -2190,6 +2191,32 @@ static void pnv_pci_ioda_fixup_iov_resources(struct
pci_dev *pdev)
pdn = pci_get_pdn(pdev);
pdn-max_vfs = 0;
+ total_vfs = pci_sriov_get_totalvfs(pdev);
+ pdn-m64_per_iov = 1;
+ mul = phb-ioda.total_pe;
+
+ for (i = PCI_IOV_RESOURCES; i = PCI_IOV_RESOURCE_END; i++) {
+ res = pdev-resource[i];
+ if (!res-flags || res-parent)
+ continue;
+ if (!pnv_pci_is_mem_pref_64(res-flags)) {
+ dev_warn(pdev-dev, non M64 IOV BAR %pR on %s\n,
+ res, pci_name(pdev));
+ continue;
+ }
+
+ size = pci_iov_resource_size(pdev, i);
+
+ /* bigger than 64M */
+ if (size (1 26)) {
+ dev_info(pdev-dev, PowerNV: VF BAR[%d] size
+ is bigger than 64M, roundup power2\n,
i);
+ pdn-m64_per_iov = M64_PER_IOV;
+ mul = __roundup_pow_of_two(total_vfs);
+ break;
+ }
+ }
+
for (i = PCI_IOV_RESOURCES; i = PCI_IOV_RESOURCE_END; i++) {
res = pdev-resource[i];
if (!res-flags || res-parent)
@@ -2202,13 +2229,13 @@ static void pnv_pci_ioda_fixup_iov_resources(struct
pci_dev *pdev)
dev_dbg(pdev-dev, Fixing VF BAR[%d] %pR to\n, i, res);
size = pci_iov_resource_size(pdev, i);
- res-end = res-start + size * phb-ioda.total_pe - 1;
+ res-end = res-start + size * mul - 1;
dev_dbg(pdev-dev,%pR\n, res);
dev_info(pdev-dev, VF BAR%d: %pR (expanded to %d VFs for PE
alignment),
i - PCI_IOV_RESOURCES,
- res, phb-ioda.total_pe);
+ res, mul);
}
- pdn-max_vfs = phb-ioda.total_pe;
+ pdn-max_vfs = mul;
}
static void pnv_pci_ioda_fixup_sriov(struct pci_bus *bus)
--
1.7.9.5
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[PATCH V11 14/17] powerpc/powernv: Shift VF resource with an offset
On PowrNV platform, resource position in M64 implies the PE# the resource
belongs to. In some particular case, adjustment of a resource is necessary
to locate it to a correct position in M64.
This patch introduces a function to shift the 'real' PF IOV BAR address
according to an offset.
Signed-off-by: Wei Yang weiy...@linux.vnet.ibm.com
---
arch/powerpc/platforms/powernv/pci-ioda.c | 31 +
1 file changed, 31 insertions(+)
diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c
b/arch/powerpc/platforms/powernv/pci-ioda.c
index 8bad2b0..62bb2eb 100644
--- a/arch/powerpc/platforms/powernv/pci-ioda.c
+++ b/arch/powerpc/platforms/powernv/pci-ioda.c
@@ -14,6 +14,7 @@
#include linux/kernel.h
#include linux/pci.h
#include linux/crash_dump.h
+#include linux/pci_regs.h
#include linux/debugfs.h
#include linux/delay.h
#include linux/string.h
@@ -749,6 +750,36 @@ static unsigned int pnv_ioda_dma_weight(struct pci_dev
*dev)
return 10;
}
+#ifdef CONFIG_PCI_IOV
+static void pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset)
+{
+ struct pci_dn *pdn = pci_get_pdn(dev);
+ int i;
+ struct resource *res;
+ resource_size_t size;
+
+ if (!dev-is_physfn)
+ return;
+
+ for (i = PCI_IOV_RESOURCES; i = PCI_IOV_RESOURCE_END; i++) {
+ res = dev-resource[i];
+ if (!res-flags || !res-parent)
+ continue;
+
+ if (!pnv_pci_is_mem_pref_64(res-flags))
+ continue;
+
+ dev_info(dev-dev, Shifting VF BAR %pR to\n, res);
+ size = pci_iov_resource_size(dev, i);
+ res-start += size*offset;
+
+ dev_info(dev-dev, %pR\n, res);
+ pci_update_resource(dev, i);
+ }
+ pdn-max_vfs -= offset;
+}
+#endif /* CONFIG_PCI_IOV */
+
#if 0
static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev)
{
--
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[PATCH 3/3] CXL: Add reset to sysfs
This allows an image to be downloaded to the flash without rebooting the
machine. The driver perform a PERST, which results in FPGA image downloaded to
flash and the CAPP unit enters recovery. CAPP recovery triggers an HMI, which
is handled by EEH in Linux. EEH removes the driver, calls into Sapphire to
reinitialize the PHB, and then loads the driver.
reset_image_select must be set to user and reset_load_image set to 1. The
driver writes user to the vsec if a user image was loaded. It writes 1 to
reset_load_image on initialization by default. Other values could be used by
hand for debugging purposes.
Signed-off-by: Ryan Grimm gr...@linux.vnet.ibm.com
---
Documentation/ABI/testing/sysfs-class-cxl | 6 +
drivers/misc/cxl/cxl.h| 1 +
drivers/misc/cxl/pci.c| 38 +--
drivers/misc/cxl/sysfs.c | 13 +++
4 files changed, 56 insertions(+), 2 deletions(-)
diff --git a/Documentation/ABI/testing/sysfs-class-cxl
b/Documentation/ABI/testing/sysfs-class-cxl
index 134cfaf..389cf24 100644
--- a/Documentation/ABI/testing/sysfs-class-cxl
+++ b/Documentation/ABI/testing/sysfs-class-cxl
@@ -142,3 +142,9 @@ Description:read/write
Value of 0 means PERST will not cause image load. A power
cycle is required to load the image. Value of 1 means PERST
will cause image load.
+
+What: /sys/class/cxl/card/reset
+Date: October 2014
+Contact:linuxppc-dev@lists.ozlabs.org
+Description:write only
+Writing 1 here will issue a PERST to card.
diff --git a/drivers/misc/cxl/cxl.h b/drivers/misc/cxl/cxl.h
index 518c4c6..6a6a487 100644
--- a/drivers/misc/cxl/cxl.h
+++ b/drivers/misc/cxl/cxl.h
@@ -489,6 +489,7 @@ int cxl_alloc_irq_ranges(struct cxl_irq_ranges *irqs,
struct cxl *adapter, unsig
void cxl_release_irq_ranges(struct cxl_irq_ranges *irqs, struct cxl *adapter);
int cxl_setup_irq(struct cxl *adapter, unsigned int hwirq, unsigned int virq);
int cxl_update_image_control(struct cxl *adapter);
+int cxl_reset(struct cxl *adapter);
/* common == phyp + powernv */
struct cxl_process_element_common {
diff --git a/drivers/misc/cxl/pci.c b/drivers/misc/cxl/pci.c
index 9aa95f9..a93daa0 100644
--- a/drivers/misc/cxl/pci.c
+++ b/drivers/misc/cxl/pci.c
@@ -21,6 +21,7 @@
#include asm/msi_bitmap.h
#include asm/pci-bridge.h /* for struct pci_controller */
#include asm/pnv-pci.h
+#include asm/io.h
#include cxl.h
@@ -742,6 +743,36 @@ static void cxl_remove_afu(struct cxl_afu *afu)
device_unregister(afu-dev);
}
+int cxl_reset(struct cxl *adapter)
+{
+ struct pci_dev *dev = to_pci_dev(adapter-dev.parent);
+ int rc;
+ int i;
+ u32 val;
+
+ dev_info(dev-dev, CXL reset\n);
+
+ for (i = 0; i adapter-slices; i++)
+ cxl_remove_afu(adapter-afu[i]);
+
+ if ((rc = pci_set_pcie_reset_state(dev, pcie_warm_reset))) {
+ dev_err(dev-dev, cxl: pcie_warm_reset failed\n);
+ return rc;
+ }
+
+ /* Do mmio read to trigger EEH. Retry for a few seconds. */
+ i = 0;
+while ((val = mmio_read32be(adapter-p1_mmio) != 0x)
+ (i 5)) {
+msleep(500);
+ i++;
+}
+
+if (val != 0x)
+dev_err(dev-dev, cxl: PERST failed to trigger EEH\n);
+
+ return rc;
+}
static int cxl_map_adapter_regs(struct cxl *adapter, struct pci_dev *dev)
{
@@ -806,8 +837,8 @@ static int cxl_read_vsec(struct cxl *adapter, struct
pci_dev *dev)
CXL_READ_VSEC_BASE_IMAGE(dev, vsec, adapter-base_image);
CXL_READ_VSEC_IMAGE_STATE(dev, vsec, image_state);
adapter-user_image_loaded = !!(image_state
CXL_VSEC_USER_IMAGE_LOADED);
- adapter-perst_loads_image = !!(image_state
CXL_VSEC_PERST_LOADS_IMAGE);
- adapter-perst_select_user = !!(image_state
CXL_VSEC_PERST_SELECT_USER);
+ adapter-perst_loads_image = true;
+ adapter-perst_select_user = !!(image_state
CXL_VSEC_USER_IMAGE_LOADED);
CXL_READ_VSEC_NAFUS(dev, vsec, adapter-slices);
CXL_READ_VSEC_AFU_DESC_OFF(dev, vsec, afu_desc_off);
@@ -915,6 +946,9 @@ static struct cxl *cxl_init_adapter(struct pci_dev *dev)
if ((rc = cxl_vsec_looks_ok(adapter, dev)))
goto err2;
+ if ((rc = cxl_update_image_control(adapter)))
+ goto err2;
+
if ((rc = cxl_map_adapter_regs(adapter, dev)))
goto err2;
diff --git a/drivers/misc/cxl/sysfs.c b/drivers/misc/cxl/sysfs.c
index 06f554b..7ebd7e3 100644
--- a/drivers/misc/cxl/sysfs.c
+++ b/drivers/misc/cxl/sysfs.c
@@ -56,6 +56,18 @@ static ssize_t image_loaded_show(struct device *device,
return scnprintf(buf, PAGE_SIZE, factory\n);
}
+static ssize_t reset_adapter_store(struct device *device,
+ struct device_attribute *attr,
+
[PATCH v2 09/10] PCI, powerpc: clip firmware assigned resource under parent bridge's
Some bios put range that is not fully coverred by root bus resources.
Try to clip them and update them in pci bridge bars.
We'd like to fix other arches instead of just x86.
Link: https://bugzilla.kernel.org/show_bug.cgi?id=85491
Reported-by: Marek Kordik kordikma...@gmail.com
Fixes: 5b28541552ef (PCI: Restrict 64-bit prefetchable bridge windows to
64-bit resources)
Signed-off-by: Yinghai Lu ying...@kernel.org
Cc: Benjamin Herrenschmidt b...@kernel.crashing.org
Cc: Paul Mackerras pau...@samba.org
Cc: Michael Ellerman m...@ellerman.id.au
Cc: Gavin Shan gws...@linux.vnet.ibm.com
Cc: Anton Blanchard an...@samba.org
Cc: Sebastian Ott seb...@linux.vnet.ibm.com
Cc: Wei Yang weiy...@linux.vnet.ibm.com
Cc: Andrew Murray amur...@embedded-bits.co.uk
Cc: linuxppc-dev@lists.ozlabs.org
---
arch/powerpc/kernel/pci-common.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/kernel/pci-common.c b/arch/powerpc/kernel/pci-common.c
index 37d512d..2a525c9 100644
--- a/arch/powerpc/kernel/pci-common.c
+++ b/arch/powerpc/kernel/pci-common.c
@@ -1184,6 +1184,8 @@ static void pcibios_allocate_bus_resources(struct pci_bus
*bus)
pr, (pr pr-name) ? pr-name : nil);
if (pr !(pr-flags IORESOURCE_UNSET)) {
+ struct pci_dev *dev = bus-self;
+
if (request_resource(pr, res) == 0)
continue;
/*
@@ -1193,6 +1195,11 @@ static void pcibios_allocate_bus_resources(struct
pci_bus *bus)
*/
if (reparent_resources(pr, res) == 0)
continue;
+
+ if (dev i PCI_BRIDGE_RESOURCE_NUM
+ pci_claim_bridge_resource(dev,
+ i + PCI_BRIDGE_RESOURCES) == 0)
+ continue;
}
pr_warning(PCI: Cannot allocate resource region
%d of PCI bridge %d, will remap\n, i, bus-number);
@@ -1401,7 +1408,10 @@ void pcibios_claim_one_bus(struct pci_bus *bus)
(unsigned long long)r-end,
(unsigned int)r-flags);
- pci_claim_resource(dev, i);
+ if (pci_claim_resource(dev, i) == 0)
+ continue;
+
+ pci_claim_bridge_resource(dev, i);
}
}
--
1.8.4.5
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Re: [PATCH 1/3] CXL: Add image control to sysfs
Excerpts from Ian Munsie's message of 2015-01-15 15:41:24 +1100: At the moment we don't set it at boot - we just go with whatever the card is already set to do. I'm thinking it might be a good idea to always set this bit on boot so the only time it's disabled is if a user has explicitly gone and disabled it. While I think of it - if we change this on boot we should also change reset_image_select to match the currently loaded image. e.g. if reset_loads_image has defaulted to off and reset_image_select has defaulted to factory, but the user image has been loaded - that way we avoid unexpectedly switching to factory if the card gets reset. Cheers, -Ian ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] powerpc/mpic: Add DT option to skip readback after EOI
On Wed, 2015-01-14 at 11:57 +, Bogdan Purcareata wrote: The readback is necessary in order to handle PCI posted writes, That is unclear. or when the MPIC is handling interrupts in a loop (ppc_md.get_irq). I'm questioning this one as well -- if reading WHOAMI is sufficient to sync with the EOI, why wouldn't reading INTACK work as well? Newer MPIC versions don't require this readback. Leave the option configurable using a device tree entry. This saves a MMIO trap per interrupt. Signed-off-by: Scott Wood scottw...@freescale.com Signed-off-by: Bogdan Purcareata bogdan.purcare...@freescale.com You should note changes (e.g. with a [] note between signoffs) if it differs from the original... -Scott ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] selftests/powerpc: Add .gitignore for powerpc selftests
On 01/13/2015 07:15 PM, Michael Ellerman wrote: On Tue, 2015-01-13 at 17:16 -0700, Shuah Khan wrote: Please add a commit log. What does it need to say? Explain the change the patch is making. Please see Documentation/SubmittingPatches for details. Looks like this patch is no longer needed as I see a new patch added to the series from Anshuman Khandual. On 01/13/2015 04:49 PM, Michael Ellerman wrote: Signed-off-by: Michael Ellerman m...@ellerman.id.au --- .../testing/selftests/powerpc/copyloops/.gitignore | 4 tools/testing/selftests/powerpc/mm/.gitignore | 1 + tools/testing/selftests/powerpc/pmu/.gitignore | 3 +++ tools/testing/selftests/powerpc/pmu/ebb/.gitignore | 22 ++ .../selftests/powerpc/primitives/.gitignore| 1 + tools/testing/selftests/powerpc/tm/.gitignore | 1 + 6 files changed, 32 insertions(+) create mode 100644 tools/testing/selftests/powerpc/copyloops/.gitignore create mode 100644 tools/testing/selftests/powerpc/mm/.gitignore create mode 100644 tools/testing/selftests/powerpc/pmu/.gitignore create mode 100644 tools/testing/selftests/powerpc/pmu/ebb/.gitignore create mode 100644 tools/testing/selftests/powerpc/primitives/.gitignore create mode 100644 tools/testing/selftests/powerpc/tm/.gitignore Please create a single .gitignore for all targets right under tools/testing/selftests/powerpc instead of multiple .gitignore files. Why? Having separate files makes it less likely we'll get merge conflicts between different test subdirectores, it also makes it more likely someone adding a test will notice they need to update the .gitignore in the same directory. It is a matter of reducing the number of files. I am fine with creating one per directory, if that fits in better with powerpc tests. -- Shuah -- Shuah Khan Sr. Linux Kernel Developer Open Source Innovation Group Samsung Research America (Silicon Valley) shua...@osg.samsung.com | (970) 217-8978 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 1/3] powerpc/pmac: Fix DT refcount imbalance in pmac_pic_probe_oldstyle
of_find_node_by_name() calls of_node_put() on its from parameter,
which must not be done on master, as it's still in use, and will be
released manually later. This may cause a zero kref refcount.
Use of_get_child_by_name() instead to fix this.
Signed-off-by: Geert Uytterhoeven geert+rene...@glider.be
Cc: linuxppc-dev@lists.ozlabs.org
---
Compile-tested only
---
arch/powerpc/platforms/powermac/pic.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/platforms/powermac/pic.c
b/arch/powerpc/platforms/powermac/pic.c
index 4c24bf60d39d2834..90ada1209c118902 100644
--- a/arch/powerpc/platforms/powermac/pic.c
+++ b/arch/powerpc/platforms/powermac/pic.c
@@ -321,7 +321,7 @@ static void __init pmac_pic_probe_oldstyle(void)
max_irqs = max_real_irqs = 64;
/* We might have a second cascaded heathrow */
- slave = of_find_node_by_name(master, mac-io);
+ slave = of_get_child_by_name(master, mac-io);
/* Check ordering of master slave */
if (of_device_is_compatible(master, gatwick)) {
--
1.9.1
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Re: offlining cpus breakage
On Wednesday 07 January 2015 03:07 PM, Alexey Kardashevskiy wrote:
Hi!
ppc64_cpu --smt=off produces multiple error on the latest upstream kernel
(sha1 bdec419):
NMI watchdog: BUG: soft lockup - CPU#20 stuck for 23s! [swapper/20:0]
or
INFO: rcu_sched detected stalls on CPUs/tasks: { 2 7 8 9 10 11 12 13 14 15
16 17 18 19 20 21 22 23 2
4 25 26 27 28 29 30 31} (detected by 6, t=2102 jiffies, g=1617, c=1616,
q=1441)
and many others, all about lockups
I did bisecting and found out that reverting these helps:
77b54e9f213f76a23736940cf94bcd765fc00f40 powernv/powerpc: Add winkle
support for offline cpus
7cba160ad789a3ad7e68b92bf20eaad6ed171f80 powernv/cpuidle: Redesign idle
states management
8eb8ac89a364305d05ad16be983b7890eb462cc3 powerpc/powernv: Enable Offline
CPUs to enter deep idle states
btw reverting just two of them produces a compile error.
It is pseries_le_defconfig, POWER8 machine:
timebase: 51200
platform: PowerNV
model : palmetto
machine : PowerNV palmetto
firmware: OPAL v3
The bug scenario is as follows:
In fastsleep decrementer state is not maintained, thus a cpu entering
fastsleep offloads its timer to a different cpu (lets call this
broadcast cpu). Now in the event that this broadcast cpu is offlined, it
assigns a new cpu with the task to handle broadcasting.
If this new cpu is one of the cpus which had entered fastsleep, its
decrementer will have been in an invalid state. This cpu has been woken
up by a need resched ipi (to take up the task of broadcasting) as
opposed to a broadcast ipi. The decrementer state is fixed only on a
broadcast ipi and not on a need resched ipi. Because of this, its timers
don't fire. Consequently it cannot wake up any cpu relying on broadcast ipi.
This scenario of a cpu that takes up the task of broadcasting being in
fastsleep is a corner case. This almost never happens on machines with
more number of cores. This explains why Alexey was able to hit it easily
on palmetto.
We'll be posting out a fix for this soon.
Thanks,
Shreyas
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[PATCH] powerpc: powernv: winkle: Restore LPCR with LPCR_PECE1 cleared
LPCR_PECE1 bit controls whether decrementer interrupts are allowed to cause exit from power-saving mode. While waking up from winkle, restoring LPCR with LPCR_PECE1 set (i.e Decrementer interrupts allowed) can cause issue in the following scenario: - All the threads in a core are offlined. The core enters deep winkle. - Spurious interrupt wakes up a thread in the core. Here LPCR is restored with LPCR_PECE1 bit set. - Since it was a spurious interrupt on a offline thread, the thread clears the interrupt and goes back to winkle. - Here before the thread executes winkle and puts the core into deep winkle, if a decrementer interrupt occurs on any of the sibling threads in the core that thread wakes up. - Since in offline loop we are flushing interrupt only in case of external interrupt, the decrementer interrupt does not get flushed. So at this stage the thread is stuck in this is loop of waking up at 0x100 due to decrementer interrupt, not flushing the interrupt as only external interrupts get flushed, entering winkle, waking up at 0x100 again. Fix this by programming PORE to restore LPCR with LPCR_PECE1 bit cleared when waking up from winkle. Signed-off-by: Shreyas B. Prabhu shre...@linux.vnet.ibm.com Cc: Michael Ellerman m...@ellerman.id.au Cc: Paul Mackerras pau...@samba.org Cc: Benjamin Herrenschmidt b...@kernel.crashing.org Cc: linuxppc-dev@lists.ozlabs.org --- This issue is separate from the issue which Alexey has reported. Fix for that is still pending. arch/powerpc/platforms/powernv/setup.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/powerpc/platforms/powernv/setup.c b/arch/powerpc/platforms/powernv/setup.c index ad0e32e..83067b1 100644 --- a/arch/powerpc/platforms/powernv/setup.c +++ b/arch/powerpc/platforms/powernv/setup.c @@ -298,7 +298,7 @@ int pnv_save_sprs_for_winkle(void) * all cpus at boot. Get these reg values of current cpu and use the * same accross all cpus. */ - uint64_t lpcr_val = mfspr(SPRN_LPCR); + uint64_t lpcr_val = mfspr(SPRN_LPCR) ~(u64)LPCR_PECE1; uint64_t hid0_val = mfspr(SPRN_HID0); uint64_t hid1_val = mfspr(SPRN_HID1); uint64_t hid4_val = mfspr(SPRN_HID4); -- 1.9.3 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
