Re: [PATCH 1/2] powerpc/powernv: display reason for Malfunction Alert HMI.

[Stewart Smith]

Mahesh J Salgaonkar  writes:
> From: Mahesh Salgaonkar 
>
> The V2 version of HMI event now carries additional information for
> Malfunction Alert. It now contains error information about CORE and NX
> checkstop. This patch checks and displays the check stop reason before
> panic.
>
> Signed-off-by: Mahesh Salgaonkar 

Acked in a the-api-is-present-in-firmware capacity.

Although patch should be against opal-api.h now rather than opal.h, so
that needs fixing before merging.

So,
Somewhat-Nearly-Acked-by: Stewart Smith 

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Re: [PATCH v10 0/3] Generic IOMMU pooled allocator

[David Miller]

From: Sowmini Varadhan 
Date: Thu,  9 Apr 2015 15:33:29 -0400

> v10: resend patchv9 without RFC tag, and a new mail Message-Id,
> (previous non-RFC attempt did not show up on the patchwork queue?)

Yes, if the patch is identical the patch postings hashes to the same
value as the RFC ones, and therefore patchwork thinks it's a dup.

I asked the patchwork maintainer to adjust this behavior in the
future if he can.

Nevertheless, thanks for posting, I was aware of the update.

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[PATCH v10 2/3] sparc: Make sparc64 use scalable lib/iommu-common.c functions

[Sowmini Varadhan]

In iperf experiments running linux as the Tx side (TCP client) with
10 threads results in a severe performance drop when TSO is disabled,
indicating a weakness in the software that can be avoided by using
the scalable IOMMU arena DMA allocation.

Baseline numbers before this patch:
   with default settings (TSO enabled) :9-9.5 Gbps
   Disable TSO using ethtool- drops badly:  2-3 Gbps.

After this patch, iperf client with 10 threads, can give a
throughput of at least 8.5 Gbps, even when TSO is disabled.

Signed-off-by: Sowmini Varadhan 
Acked-by: Benjamin Herrenschmidt 
---
v2: moved sparc specific fileds into iommu_sparc
v3: converted all sparc users of iommu, so lot of cleanup and streamlining
v4: David Miller review change:
- s/IOMMU_ERROR_CODE/DMA_ERROR_CODE
- reverts pci_impl.h (now that all iommu usage has been converted)
v5: benh/aik feedback modifies the function signatures: pass in 
modified args to iommmu_tbl_pool_init() and iommu_tbl_range_free()
v6: removed iommu_tbl_ops. Pass flush_all as function pointer to 
iommu_tbl_pool_init
v7: move pool_hash initialization to iommu_tbl_pool_init()
v8: BenH comments
v9: more BenH comments
v10: resend without RFC tag, and new mail message-id

 arch/sparc/include/asm/iommu_64.h |7 +-
 arch/sparc/kernel/iommu.c |  172 +--
 arch/sparc/kernel/iommu_common.h  |8 --
 arch/sparc/kernel/pci_sun4v.c |  183 +
 4 files changed, 128 insertions(+), 242 deletions(-)

diff --git a/arch/sparc/include/asm/iommu_64.h 
b/arch/sparc/include/asm/iommu_64.h
index 2b9321a..cd0d69f 100644
--- a/arch/sparc/include/asm/iommu_64.h
+++ b/arch/sparc/include/asm/iommu_64.h
@@ -16,6 +16,7 @@
 #define IOPTE_WRITE   0x0002UL
 
 #define IOMMU_NUM_CTXS 4096
+#include 
 
 struct iommu_arena {
unsigned long   *map;
@@ -24,11 +25,10 @@ struct iommu_arena {
 };
 
 struct iommu {
+   struct iommu_map_table  tbl;
spinlock_t  lock;
-   struct iommu_arena  arena;
-   void(*flush_all)(struct iommu *);
+   u32 dma_addr_mask;
iopte_t *page_table;
-   u32 page_table_map_base;
unsigned long   iommu_control;
unsigned long   iommu_tsbbase;
unsigned long   iommu_flush;
@@ -40,7 +40,6 @@ struct iommu {
unsigned long   dummy_page_pa;
unsigned long   ctx_lowest_free;
DECLARE_BITMAP(ctx_bitmap, IOMMU_NUM_CTXS);
-   u32 dma_addr_mask;
 };
 
 struct strbuf {
diff --git a/arch/sparc/kernel/iommu.c b/arch/sparc/kernel/iommu.c
index bfa4d0c..5320689 100644
--- a/arch/sparc/kernel/iommu.c
+++ b/arch/sparc/kernel/iommu.c
@@ -13,6 +13,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #ifdef CONFIG_PCI
 #include 
@@ -45,8 +46,9 @@
   "i" (ASI_PHYS_BYPASS_EC_E))
 
 /* Must be invoked under the IOMMU lock. */
-static void iommu_flushall(struct iommu *iommu)
+static void iommu_flushall(struct iommu_map_table *iommu_map_table)
 {
+   struct iommu *iommu = container_of(iommu_map_table, struct iommu, tbl);
if (iommu->iommu_flushinv) {
iommu_write(iommu->iommu_flushinv, ~(u64)0);
} else {
@@ -87,94 +89,6 @@ static inline void iopte_make_dummy(struct iommu *iommu, 
iopte_t *iopte)
iopte_val(*iopte) = val;
 }
 
-/* Based almost entirely upon the ppc64 iommu allocator.  If you use the 
'handle'
- * facility it must all be done in one pass while under the iommu lock.
- *
- * On sun4u platforms, we only flush the IOMMU once every time we've passed
- * over the entire page table doing allocations.  Therefore we only ever 
advance
- * the hint and cannot backtrack it.
- */
-unsigned long iommu_range_alloc(struct device *dev,
-   struct iommu *iommu,
-   unsigned long npages,
-   unsigned long *handle)
-{
-   unsigned long n, end, start, limit, boundary_size;
-   struct iommu_arena *arena = &iommu->arena;
-   int pass = 0;
-
-   /* This allocator was derived from x86_64's bit string search */
-
-   /* Sanity check */
-   if (unlikely(npages == 0)) {
-   if (printk_ratelimit())
-   WARN_ON(1);
-   return DMA_ERROR_CODE;
-   }
-
-   if (handle && *handle)
-   start = *handle;
-   else
-   start = arena->hint;
-
-   limit = arena->limit;
-
-   /* The case below can happen if we have a small segment appended
-* to a large, or when the previous alloc was at the very end of
-* the available space. If so, go back to the beginning and flush.
-*/
-   if (start >= limit) {
-   start = 0;
-   if (iommu->flush_all)
-   iommu->flush_all(iommu);
- 

[PATCH v10 1/3] Break up monolithic iommu table/lock into finer graularity pools and lock

[Sowmini Varadhan]

Investigation of multithreaded iperf experiments on an ethernet
interface show the iommu->lock as the hottest lock identified by
lockstat, with something of the order of  21M contentions out of
27M acquisitions, and an average wait time of 26 us for the lock.
This is not efficient. A more scalable design is to follow the ppc
model, where the iommu_map_table has multiple pools, each stretching
over a segment of the map, and with a separate lock for each pool.
This model allows for better parallelization of the iommu map search.

This patch adds the iommu range alloc/free function infrastructure.

Signed-off-by: Sowmini Varadhan 
Acked-by: Benjamin Herrenschmidt 
---
v2 changes:
  - incorporate David Miller editorial comments: sparc specific
fields moved from iommu-common into sparc's iommu_64.h
  - make the npools value an input parameter, for the case when
the iommu map size is not very large
  - cookie_to_index mapping, and optimizations for span-boundary
check, for use case such as LDC.
v3: eliminate iommu_sparc, rearrange the ->demap indirection to
be invoked under the pool lock.

v4: David Miller review changes:
  - s/IOMMU_ERROR_CODE/DMA_ERROR_CODE
  - page_table_map_base and page_table_shift are unsigned long, not u32.

v5: Feedback from b...@kernel.crashing.org and a...@ozlabs.ru
  - removed ->cookie_to_index and ->demap indirection: caller should
invoke these as needed before calling into the generic allocator

v6: Benh/DaveM discussion eliminationg iommu_tbl_ops, but retaining flush_all
optimization.

v7: one-time initialization of pool_hash from iommu_tbl_pool_init()

v8: Benh code review comments.

v9: More Benh code review comments, added dma_mask, align_order logic to
iommu_tbl_range_alloc.

v10: resend without RFC tag, and new mail message-id

 include/linux/iommu-common.h |   51 
 lib/Makefile |2 +-
 lib/iommu-common.c   |  266 ++
 3 files changed, 318 insertions(+), 1 deletions(-)
 create mode 100644 include/linux/iommu-common.h
 create mode 100644 lib/iommu-common.c

diff --git a/include/linux/iommu-common.h b/include/linux/iommu-common.h
new file mode 100644
index 000..bbced83
--- /dev/null
+++ b/include/linux/iommu-common.h
@@ -0,0 +1,51 @@
+#ifndef _LINUX_IOMMU_COMMON_H
+#define _LINUX_IOMMU_COMMON_H
+
+#include 
+#include 
+#include 
+
+#define IOMMU_POOL_HASHBITS 4
+#define IOMMU_NR_POOLS  (1 << IOMMU_POOL_HASHBITS)
+
+struct iommu_pool {
+   unsigned long   start;
+   unsigned long   end;
+   unsigned long   hint;
+   spinlock_t  lock;
+};
+
+struct iommu_map_table {
+   unsigned long   table_map_base;
+   unsigned long   table_shift;
+   unsigned long   nr_pools;
+   void(*lazy_flush)(struct iommu_map_table *);
+   unsigned long   poolsize;
+   struct iommu_pool   pools[IOMMU_NR_POOLS];
+   u32 flags;
+#defineIOMMU_HAS_LARGE_POOL0x0001
+#defineIOMMU_NO_SPAN_BOUND 0x0002
+#defineIOMMU_NEED_FLUSH0x0004
+   struct iommu_pool   large_pool;
+   unsigned long   *map;
+};
+
+extern void iommu_tbl_pool_init(struct iommu_map_table *iommu,
+   unsigned long num_entries,
+   u32 table_shift,
+   void (*lazy_flush)(struct iommu_map_table *),
+   bool large_pool, u32 npools,
+   bool skip_span_boundary_check);
+
+extern unsigned long iommu_tbl_range_alloc(struct device *dev,
+  struct iommu_map_table *iommu,
+  unsigned long npages,
+  unsigned long *handle,
+  unsigned long mask,
+  unsigned int align_order);
+
+extern void iommu_tbl_range_free(struct iommu_map_table *iommu,
+u64 dma_addr, unsigned long npages,
+unsigned long entry);
+
+#endif
diff --git a/lib/Makefile b/lib/Makefile
index 58f74d2..60c22e6 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -106,7 +106,7 @@ obj-$(CONFIG_AUDIT_GENERIC) += audit.o
 obj-$(CONFIG_AUDIT_COMPAT_GENERIC) += compat_audit.o
 
 obj-$(CONFIG_SWIOTLB) += swiotlb.o
-obj-$(CONFIG_IOMMU_HELPER) += iommu-helper.o
+obj-$(CONFIG_IOMMU_HELPER) += iommu-helper.o iommu-common.o
 obj-$(CONFIG_FAULT_INJECTION) += fault-inject.o
 obj-$(CONFIG_NOTIFIER_ERROR_INJECTION) += notifier-error-inject.o
 obj-$(CONFIG_CPU_NOTIFIER_ERROR_INJECT) += cpu-notifier-error-inject.o
diff --git a/lib/iommu-common.c b/lib/iommu-common.c
new file mode 100644
index 000..b99f1d7
--- /dev/null
+++ b/lib/iommu-common.c
@@ -0,0 +1,266 @@
+/*
+ * IOMMU mmap management and range allocation

[PATCH v10 3/3] sparc: Make LDC use common iommu poll management functions

[Sowmini Varadhan]

Note that this conversion is only being done to consolidate the
code and ensure that the common code provides the sufficient
abstraction. It is not expected to result in any noticeable
performance improvement, as there is typically one ldc_iommu
per vnet_port, and each one has 8k entries, with a typical
request for 1-4 pages.  Thus LDC uses npools == 1.

Signed-off-by: Sowmini Varadhan 
Acked-by: Benjamin Herrenschmidt 
---
v3: added this file to be a consumer of the common iommu library
v4: removed ->cookie_to_index and ->demap from iommu_tbl_ops and instead
inline these calls into ldc before calling into iommu-common
v6: remove iommu_tbl_ops
v7: move pool_hash initialization to iommu_tbl_pool_init
v8: BenH comments
v9: More BenH comments
v10: resend without RFC tag, and new mail message-id

 arch/sparc/kernel/ldc.c |  153 ---
 1 files changed, 65 insertions(+), 88 deletions(-)

diff --git a/arch/sparc/kernel/ldc.c b/arch/sparc/kernel/ldc.c
index 274a9f5..d2ae0f7 100644
--- a/arch/sparc/kernel/ldc.c
+++ b/arch/sparc/kernel/ldc.c
@@ -15,6 +15,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include 
 #include 
@@ -27,6 +28,10 @@
 #define DRV_MODULE_VERSION "1.1"
 #define DRV_MODULE_RELDATE "July 22, 2008"
 
+#define COOKIE_PGSZ_CODE   0xf000ULL
+#define COOKIE_PGSZ_CODE_SHIFT 60ULL
+
+
 static char version[] =
DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
 #define LDC_PACKET_SIZE64
@@ -98,10 +103,10 @@ static const struct ldc_mode_ops stream_ops;
 int ldom_domaining_enabled;
 
 struct ldc_iommu {
-   /* Protects arena alloc/free.  */
+   /* Protects ldc_unmap.  */
spinlock_t  lock;
-   struct iommu_arena  arena;
struct ldc_mtable_entry *page_table;
+   struct iommu_map_table  iommu_map_table;
 };
 
 struct ldc_channel {
@@ -998,31 +1003,59 @@ static void free_queue(unsigned long num_entries, struct 
ldc_packet *q)
free_pages((unsigned long)q, order);
 }
 
+static unsigned long ldc_cookie_to_index(u64 cookie, void *arg)
+{
+   u64 szcode = cookie >> COOKIE_PGSZ_CODE_SHIFT;
+   /* struct ldc_iommu *ldc_iommu = (struct ldc_iommu *)arg; */
+
+   cookie &= ~COOKIE_PGSZ_CODE;
+
+   return (cookie >> (13ULL + (szcode * 3ULL)));
+}
+
+static void ldc_demap(struct ldc_iommu *iommu, unsigned long id, u64 cookie,
+ unsigned long entry, unsigned long npages)
+{
+   struct ldc_mtable_entry *base;
+   unsigned long i, shift;
+
+   shift = (cookie >> COOKIE_PGSZ_CODE_SHIFT) * 3;
+   base = iommu->page_table + entry;
+   for (i = 0; i < npages; i++) {
+   if (base->cookie)
+   sun4v_ldc_revoke(id, cookie + (i << shift),
+base->cookie);
+   base->mte = 0;
+   }
+}
+
 /* XXX Make this configurable... XXX */
 #define LDC_IOTABLE_SIZE   (8 * 1024)
 
-static int ldc_iommu_init(struct ldc_channel *lp)
+static int ldc_iommu_init(const char *name, struct ldc_channel *lp)
 {
unsigned long sz, num_tsb_entries, tsbsize, order;
-   struct ldc_iommu *iommu = &lp->iommu;
+   struct ldc_iommu *ldc_iommu = &lp->iommu;
+   struct iommu_map_table *iommu = &ldc_iommu->iommu_map_table;
struct ldc_mtable_entry *table;
unsigned long hv_err;
int err;
 
num_tsb_entries = LDC_IOTABLE_SIZE;
tsbsize = num_tsb_entries * sizeof(struct ldc_mtable_entry);
-
-   spin_lock_init(&iommu->lock);
+   spin_lock_init(&ldc_iommu->lock);
 
sz = num_tsb_entries / 8;
sz = (sz + 7UL) & ~7UL;
-   iommu->arena.map = kzalloc(sz, GFP_KERNEL);
-   if (!iommu->arena.map) {
+   iommu->map = kzalloc(sz, GFP_KERNEL);
+   if (!iommu->map) {
printk(KERN_ERR PFX "Alloc of arena map failed, sz=%lu\n", sz);
return -ENOMEM;
}
-
-   iommu->arena.limit = num_tsb_entries;
+   iommu_tbl_pool_init(iommu, num_tsb_entries, PAGE_SHIFT,
+   NULL, false /* no large pool */,
+   1 /* npools */,
+   true /* skip span boundary check */);
 
order = get_order(tsbsize);
 
@@ -1037,7 +1070,7 @@ static int ldc_iommu_init(struct ldc_channel *lp)
 
memset(table, 0, PAGE_SIZE << order);
 
-   iommu->page_table = table;
+   ldc_iommu->page_table = table;
 
hv_err = sun4v_ldc_set_map_table(lp->id, __pa(table),
 num_tsb_entries);
@@ -1049,31 +1082,32 @@ static int ldc_iommu_init(struct ldc_channel *lp)
 
 out_free_table:
free_pages((unsigned long) table, order);
-   iommu->page_table = NULL;
+   ldc_iommu->page_table = NULL;
 
 out_free_map:
-   kfree(iommu->arena.map);
-   iommu->arena.map = NULL;
+   kfree(iommu->map);
+   iomm

[PATCH v10 0/3] Generic IOMMU pooled allocator

[Sowmini Varadhan]

Investigation of network performance on Sparc shows a high
degree of locking contention in the IOMMU allocator, and it
was noticed that the PowerPC code has a better locking model.

This patch series tries to extract the generic parts of the 
PowerPC code so that it can be shared across multiple PCI
devices and architectures.

v10: resend patchv9 without RFC tag, and a new mail Message-Id,
(previous non-RFC attempt did not show up on the patchwork queue?)

Full revision history below:
v2 changes:
  - incorporate David Miller editorial comments: sparc specific
fields moved from iommu-common into sparc's iommu_64.h
  - make the npools value an input parameter, for the case when
the iommu map size is not very large
  - cookie_to_index mapping, and optimizations for span-boundary
check, for use case such as LDC.

v3: eliminate iommu_sparc, rearrange the ->demap indirection to
be invoked under the pool lock.

v4: David Miller review changes:
  - s/IOMMU_ERROR_CODE/DMA_ERROR_CODE
  - page_table_map_base and page_table_shift are unsigned long, not u32.

v5: removed ->cookie_to_index and ->demap indirection from the
iommu_tbl_ops The caller needs to call these functions as needed,
before invoking the generic arena allocator functions.
Added the "skip_span_boundary" argument to iommu_tbl_pool_init() for
those callers like LDC which do no care about span boundary checks.

v6: removed iommu_tbl_ops, and instead pass the ->flush_all as
an indirection to iommu_tbl_pool_init(); only invoke ->flush_all
when there is no large_pool, based on the assumption that large-pool
usage is infrequently encountered

v7: moved pool_hash initialization to lib/iommu-common.c and cleaned up
code duplication from sun4v/sun4u/ldc. 

v8: Addresses BenH comments with one exception: I've left the
IOMMU_POOL_HASH as is, so that powerpc can tailor it to their
convenience.  Discard trylock for simple spin_lock to acquire pool

v9: Addresses latest BenH comments: need_flush checks, add support
for dma mask and align_order. 

v10: resend without RFC tag, and new mail Message-Id.

Sowmini Varadhan (3):
  Break up monolithic iommu table/lock into finer graularity pools and
lock
  Make sparc64 use scalable lib/iommu-common.c functions
  Make LDC use common iommu poll management functions

 arch/sparc/include/asm/iommu_64.h |7 +-
 arch/sparc/kernel/iommu.c |  172 ++--
 arch/sparc/kernel/iommu_common.h  |8 -
 arch/sparc/kernel/ldc.c   |  153 +
 arch/sparc/kernel/pci_sun4v.c |  183 --
 include/linux/iommu-common.h  |   51 +++
 lib/Makefile  |2 +-
 lib/iommu-common.c|  266 +
 8 files changed, 511 insertions(+), 331 deletions(-)
 create mode 100644 include/linux/iommu-common.h
 create mode 100644 lib/iommu-common.c

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Re: [v2] dt/bindings: qoriq-clock: Add binding for FMan clock mux

[Scott Wood]

On Thu, 2015-04-09 at 02:18 -0500, Liberman Igal-B31950 wrote:
> 
> 
> Regards,
> Igal Liberman.
> 
> > -Original Message-
> > From: Wood Scott-B07421
> > Sent: Thursday, April 09, 2015 12:12 AM
> > To: Liberman Igal-B31950
> > Cc: devicet...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org
> > Subject: Re: [v2] dt/bindings: qoriq-clock: Add binding for FMan clock mux
> > 
> > On Wed, 2015-04-08 at 10:43 +0300, Igal.Liberman wrote:
> > > @@ -76,6 +77,52 @@ Required properties:
> > >
> > >  Recommended properties:
> > >  - clocks: Should be the phandle of input parent clock
> > > + For "fsl,fman-clk-mux" clock there are several options for parent
> > > + clock (clock provider), the parent is determined according to the
> > > + Reset Configuration Word of the specific device:
> > > + * P2041, P3041:
> > > + * 0 - equal to platform PLL divided by 2
> > > + * 1 - equal to PLL2 divided by 2
> > > + * P4080 (Both FMans):
> > > + * 0 - equal to platform PLL divided by 2
> > > + * 1 - equal to PLL3 divided by 2
> > ...
> > 
> > 
> > Again, the clock specifier format is determined by the clock provider, not 
> > the
> > clock consumer.
> > 
> 
> Scott,
> The "clocks" property contains all possible clock providers, right?
> In the text above I'm trying to explain how the FMan clock provider is 
> determined and what are the options for each SoC.
> Do you think that we shouldn't have this explanation? Can you please 
> elaborate?

I'm saying that the clock specifiers must be the same regardless of the
node that is consuming the clock.  You can't define certain values as
only being "for fsl,fman-clk-mux".

-Scott


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Re: [PATCH] powerpc/dts: Add some SoC specific "fsl,*-device-config" compatibles

[Scott Wood]

On Thu, 2015-04-09 at 09:21 +0300, Igal.Liberman wrote:
> From: Igal Liberman 
> 
> This patch is required for: https://patchwork.ozlabs.org/patch/459584/

If it's required for that patch, why aren't they part of a patchset
rather than independently posted?  I don't see any mention of a
dependency in that patch, so how would I have known not to apply it?

> Signed-off-by: Igal Liberman 
> ---
>  arch/powerpc/boot/dts/fsl/b4420si-post.dtsi |3 ++-
>  arch/powerpc/boot/dts/fsl/b4860si-post.dtsi |3 ++-
>  arch/powerpc/boot/dts/fsl/b4si-post.dtsi|3 ++-
>  arch/powerpc/boot/dts/fsl/p2041si-post.dtsi |3 ++-
>  arch/powerpc/boot/dts/fsl/p3041si-post.dtsi |3 ++-
>  arch/powerpc/boot/dts/fsl/p4080si-post.dtsi |3 ++-
>  arch/powerpc/boot/dts/fsl/p5020si-post.dtsi |3 ++-
>  7 files changed, 14 insertions(+), 7 deletions(-)
> 
> diff --git a/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi 
> b/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
> index 1ea8602..9b14f24 100644
> --- a/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
> +++ b/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
> @@ -77,7 +77,8 @@
>   };
>  
>   guts: global-utilities@e {
> - compatible = "fsl,b4420-device-config", 
> "fsl,qoriq-device-config-2.0";
> + compatible = "fsl,b4420-device-config", "fsl,b4-device-config",
> +   "fsl,qoriq-device-config-2.0";

Why?

-Scott


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Re: [PATCH] dt/bindings: fsl/guts: Added global-utilities compatibles

[Scott Wood]

On Thu, 2015-04-09 at 09:19 +0300, Igal.Liberman wrote:
> From: Igal Liberman 
> 
> Signed-off-by: Igal Liberman 
> ---
>  .../devicetree/bindings/powerpc/fsl/guts.txt   |   14 ++
>  1 file changed, 14 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/powerpc/fsl/guts.txt 
> b/Documentation/devicetree/bindings/powerpc/fsl/guts.txt
> index 7f150b5..e4f0ac2 100644
> --- a/Documentation/devicetree/bindings/powerpc/fsl/guts.txt
> +++ b/Documentation/devicetree/bindings/powerpc/fsl/guts.txt
> @@ -9,6 +9,20 @@ Required properties:
>  
>   - compatible : Should define the compatible device type for
> global-utilities.
> +   Possible compatibles:
> + "fsl,qoriq-device-config-1.0"
> + "fsl,p2041-device-config"
> + "fsl,p3041-device-config"
> + "fsl,p4080-device-config"
> + "fsl,p5020-device-config"
> + "fsl,p5040-device-config"
> + "fsl,qoriq-device-config-2.0"
> + "fsl,b4860-device-config"
> + "fsl,b4420-device-config"
> + "fsl,b4-device-config"
> + "fsl,t1040-device-config"
> + "fsl,t2080-device-config"
> + "fsl,t4240-device-config"

There's no need to list every chip here.  Just list the ones that aren't
chips, plus "fsl,-device-config".

As for fsl,b4-device-config, does that exist in any final dtb (as
opposed to b4si-post.dtsi)?  The b4420 and b4860 dtsi files both
overwrite that compatible.

-Scott


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Re: [PATCH v2 2/2] mmc: host: Add some quirks to be read from fdt in sdhci-pltm.c

[Suman Tripathi]

On 30 March 2015 at 16:46, Suman Tripathi  wrote:
> This patch adds some quirks support to be read from fdt.
>
> Signed-off-by: Suman Tripathi 
> ---
>  drivers/mmc/host/sdhci-pltfm.c | 15 +++
>  1 file changed, 15 insertions(+)
>
> diff --git a/drivers/mmc/host/sdhci-pltfm.c b/drivers/mmc/host/sdhci-pltfm.c
> index bef250e..9f6a4b9 100644
> --- a/drivers/mmc/host/sdhci-pltfm.c
> +++ b/drivers/mmc/host/sdhci-pltfm.c
> @@ -85,6 +85,21 @@ void sdhci_get_of_property(struct platform_device *pdev)
>
> if (of_get_property(np, "broken-cd", NULL))
> host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
> +
> +   if (of_get_property(np, "delay-after-power", NULL))
> +   host->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER;
> +
> +   if (of_get_property(np, "no-hispd", NULL))
> +   host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT;
> +
> +   if (of_get_property(np, "broken-adma", NULL))
> +   host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
> +
> +   if (of_get_property(np, "broken-dma", NULL))
> +   host->quirks |= SDHCI_QUIRK_BROKEN_DMA;
> +
> +   if (of_get_property(np, "no-cmd23", NULL))
> +   host->quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23;

Can't at least some of these be distinguished from what sdhci variant
that is being used? Instead of having them in DT...

We are using arasan controller in our SOC. So reusing a the existing
sdhci-of-arasan driver. Due to H/W issues we require this quirks. So
for us only option left to pass the info is DTS or ACPI table.

Kind regards
Uffe

On Thu, Apr 9, 2015 at 9:40 PM, Suman Tripathi  wrote:
> On 30 March 2015 at 16:46, Suman Tripathi  wrote:
>> This patch adds some quirks support to be read from fdt.
>>
>> Signed-off-by: Suman Tripathi 
>> ---
>>  drivers/mmc/host/sdhci-pltfm.c | 15 +++
>>  1 file changed, 15 insertions(+)
>>
>> diff --git a/drivers/mmc/host/sdhci-pltfm.c
>> b/drivers/mmc/host/sdhci-pltfm.c
>> index bef250e..9f6a4b9 100644
>> --- a/drivers/mmc/host/sdhci-pltfm.c
>> +++ b/drivers/mmc/host/sdhci-pltfm.c
>> @@ -85,6 +85,21 @@ void sdhci_get_of_property(struct platform_device
>> *pdev)
>>
>> if (of_get_property(np, "broken-cd", NULL))
>> host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
>> +
>> +   if (of_get_property(np, "delay-after-power", NULL))
>> +   host->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER;
>> +
>> +   if (of_get_property(np, "no-hispd", NULL))
>> +   host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT;
>> +
>> +   if (of_get_property(np, "broken-adma", NULL))
>> +   host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
>> +
>> +   if (of_get_property(np, "broken-dma", NULL))
>> +   host->quirks |= SDHCI_QUIRK_BROKEN_DMA;
>> +
>> +   if (of_get_property(np, "no-cmd23", NULL))
>> +   host->quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23;
>
> Can't at least some of these be distinguished from what sdhci variant
> that is being used? Instead of having them in DT...
>
> We are using arasan controller in our SOC. So reusing a the existing
> sdhci-of-arasan driver. Due to H/W issues we require this quirks. So for us
> only option left to pass the info is DTS or ACPI table.
>
> Kind regards
> Uffe
>
> On Wed, Apr 8, 2015 at 3:10 PM, Ulf Hansson  wrote:
>>
>> On 30 March 2015 at 16:46, Suman Tripathi  wrote:
>> > This patch adds some quirks support to be read from fdt.
>> >
>> > Signed-off-by: Suman Tripathi 
>> > ---
>> >  drivers/mmc/host/sdhci-pltfm.c | 15 +++
>> >  1 file changed, 15 insertions(+)
>> >
>> > diff --git a/drivers/mmc/host/sdhci-pltfm.c
>> > b/drivers/mmc/host/sdhci-pltfm.c
>> > index bef250e..9f6a4b9 100644
>> > --- a/drivers/mmc/host/sdhci-pltfm.c
>> > +++ b/drivers/mmc/host/sdhci-pltfm.c
>> > @@ -85,6 +85,21 @@ void sdhci_get_of_property(struct platform_device
>> > *pdev)
>> >
>> > if (of_get_property(np, "broken-cd", NULL))
>> > host->quirks |=
>> > SDHCI_QUIRK_BROKEN_CARD_DETECTION;
>> > +
>> > +   if (of_get_property(np, "delay-after-power", NULL))
>> > +   host->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER;
>> > +
>> > +   if (of_get_property(np, "no-hispd", NULL))
>> > +   host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT;
>> > +
>> > +   if (of_get_property(np, "broken-adma", NULL))
>> > +   host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
>> > +
>> > +   if (of_get_property(np, "broken-dma", NULL))
>> > +   host->quirks |= SDHCI_QUIRK_BROKEN_DMA;
>> > +
>> > +   if (of_get_property(np, "no-cmd23", NULL))
>> > +   host->quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23;
>>
>> Can't at least some of

[PATCH 2/2] powerpc/powernv: Pull all HMI events before panic.

[Mahesh J Salgaonkar]

From: Mahesh Salgaonkar 

In the event of unrecovered HMI the existing code panics as soon as
it receives the first unrecovered HMI event. This makes host to report
partial information about HMIs before panic. There may be more errors
which would have caused the HMI and hence more HMI event would have been
generated waiting to be pulled by host. This patch implements a logic to
pull and display all the HMI event before going down panic path.

Signed-off-by: Mahesh Salgaonkar 
---
 arch/powerpc/platforms/powernv/opal-hmi.c |   26 --
 1 file changed, 24 insertions(+), 2 deletions(-)

diff --git a/arch/powerpc/platforms/powernv/opal-hmi.c 
b/arch/powerpc/platforms/powernv/opal-hmi.c
index 2668225..26e0f3f 100644
--- a/arch/powerpc/platforms/powernv/opal-hmi.c
+++ b/arch/powerpc/platforms/powernv/opal-hmi.c
@@ -235,6 +235,8 @@ static void hmi_event_handler(struct work_struct *work)
struct OpalHMIEvent *hmi_evt;
struct OpalHmiEvtNode *msg_node;
uint8_t disposition;
+   struct opal_msg msg;
+   int unrecoverable = 0;
 
spin_lock_irqsave(&opal_hmi_evt_lock, flags);
while (!list_empty(&opal_hmi_evt_list)) {
@@ -250,14 +252,34 @@ static void hmi_event_handler(struct work_struct *work)
 
/*
 * Check if HMI event has been recovered or not. If not
-* then we can't continue, invoke panic.
+* then kernel can't continue, we need to panic.
+* But before we do that, display all the HMI event
+* available on the list and set unrecoverable flag to 1.
 */
if (disposition != OpalHMI_DISPOSITION_RECOVERED)
-   panic("Unrecoverable HMI exception");
+   unrecoverable = 1;
 
spin_lock_irqsave(&opal_hmi_evt_lock, flags);
}
spin_unlock_irqrestore(&opal_hmi_evt_lock, flags);
+
+   if (unrecoverable) {
+   /* Pull all HMI events from OPAL before we panic. */
+   while (opal_get_msg(__pa(&msg), sizeof(msg)) == OPAL_SUCCESS) {
+   u32 type;
+
+   type = be32_to_cpu(msg.msg_type);
+
+   /* skip if not HMI event */
+   if (type != OPAL_MSG_HMI_EVT)
+   continue;
+
+   /* HMI event info starts from param[0] */
+   hmi_evt = (struct OpalHMIEvent *)&msg.params[0];
+   print_hmi_event_info(hmi_evt);
+   }
+   panic("Unrecoverable HMI exception");
+   }
 }
 
 static DECLARE_WORK(hmi_event_work, hmi_event_handler);

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[PATCH 1/2] powerpc/powernv: display reason for Malfunction Alert HMI.

[Mahesh J Salgaonkar]

From: Mahesh Salgaonkar 

The V2 version of HMI event now carries additional information for
Malfunction Alert. It now contains error information about CORE and NX
checkstop. This patch checks and displays the check stop reason before
panic.

Signed-off-by: Mahesh Salgaonkar 
---
 arch/powerpc/include/asm/opal.h   |   61 +
 arch/powerpc/platforms/powernv/opal-hmi.c |  132 +
 2 files changed, 193 insertions(+)

diff --git a/arch/powerpc/include/asm/opal.h b/arch/powerpc/include/asm/opal.h
index 9ee0a30..19f7468 100644
--- a/arch/powerpc/include/asm/opal.h
+++ b/arch/powerpc/include/asm/opal.h
@@ -487,6 +487,7 @@ struct OpalMemoryErrorData {
 /* HMI interrupt event */
 enum OpalHMI_Version {
OpalHMIEvt_V1 = 1,
+   OpalHMIEvt_V2 = 2,
 };
 
 enum OpalHMI_Severity {
@@ -516,6 +517,49 @@ enum OpalHMI_ErrType {
OpalHMI_ERROR_HYP_RESOURCE,
 };
 
+enum OpalHMI_XstopType {
+   CHECKSTOP_TYPE_UNKNOWN  =   0,
+   CHECKSTOP_TYPE_CORE =   1,
+   CHECKSTOP_TYPE_NX   =   2,
+};
+
+enum OpalHMI_CoreXstopReason {
+   CORE_CHECKSTOP_IFU_REGFILE  = 0x0001,
+   CORE_CHECKSTOP_IFU_LOGIC= 0x0002,
+   CORE_CHECKSTOP_PC_DURING_RECOV  = 0x0004,
+   CORE_CHECKSTOP_ISU_REGFILE  = 0x0008,
+   CORE_CHECKSTOP_ISU_LOGIC= 0x0010,
+   CORE_CHECKSTOP_FXU_LOGIC= 0x0020,
+   CORE_CHECKSTOP_VSU_LOGIC= 0x0040,
+   CORE_CHECKSTOP_PC_RECOV_IN_MAINT_MODE   = 0x0080,
+   CORE_CHECKSTOP_LSU_REGFILE  = 0x0100,
+   CORE_CHECKSTOP_PC_FWD_PROGRESS  = 0x0200,
+   CORE_CHECKSTOP_LSU_LOGIC= 0x0400,
+   CORE_CHECKSTOP_PC_LOGIC = 0x0800,
+   CORE_CHECKSTOP_PC_HYP_RESOURCE  = 0x1000,
+   CORE_CHECKSTOP_PC_HANG_RECOV_FAILED = 0x2000,
+   CORE_CHECKSTOP_PC_AMBI_HANG_DETECTED= 0x4000,
+   CORE_CHECKSTOP_PC_DEBUG_TRIG_ERR_INJ= 0x8000,
+   CORE_CHECKSTOP_PC_SPRD_HYP_ERR_INJ  = 0x0001,
+};
+
+enum OpalHMI_NestAccelXstopReason {
+   NX_CHECKSTOP_SHM_INVAL_STATE_ERR= 0x0001,
+   NX_CHECKSTOP_DMA_INVAL_STATE_ERR_1  = 0x0002,
+   NX_CHECKSTOP_DMA_INVAL_STATE_ERR_2  = 0x0004,
+   NX_CHECKSTOP_DMA_CH0_INVAL_STATE_ERR= 0x0008,
+   NX_CHECKSTOP_DMA_CH1_INVAL_STATE_ERR= 0x0010,
+   NX_CHECKSTOP_DMA_CH2_INVAL_STATE_ERR= 0x0020,
+   NX_CHECKSTOP_DMA_CH3_INVAL_STATE_ERR= 0x0040,
+   NX_CHECKSTOP_DMA_CH4_INVAL_STATE_ERR= 0x0080,
+   NX_CHECKSTOP_DMA_CH5_INVAL_STATE_ERR= 0x0100,
+   NX_CHECKSTOP_DMA_CH6_INVAL_STATE_ERR= 0x0200,
+   NX_CHECKSTOP_DMA_CH7_INVAL_STATE_ERR= 0x0400,
+   NX_CHECKSTOP_DMA_CRB_UE = 0x0800,
+   NX_CHECKSTOP_DMA_CRB_SUE= 0x1000,
+   NX_CHECKSTOP_PBI_ISN_UE = 0x2000,
+};
+
 struct OpalHMIEvent {
uint8_t version;/* 0x00 */
uint8_t severity;   /* 0x01 */
@@ -526,6 +570,23 @@ struct OpalHMIEvent {
__be64  hmer;
/* TFMR register. Valid only for TFAC and TFMR_PARITY error type. */
__be64  tfmr;
+
+   /* version 2 and later */
+   union {
+   /*
+* checkstop info (Core/NX).
+* Valid for OpalHMI_ERROR_MALFUNC_ALERT.
+*/
+   struct {
+   uint8_t xstop_type; /* enum OpalHMI_XstopType */
+   uint8_t reserved_1[3];
+   __be32  xstop_reason;
+   union {
+   __be32 pir; /* for CHECKSTOP_TYPE_CORE */
+   __be32 chip_id; /* for CHECKSTOP_TYPE_NX */
+   } u;
+   } xstop_error;
+   } u;
 };
 
 enum {
diff --git a/arch/powerpc/platforms/powernv/opal-hmi.c 
b/arch/powerpc/platforms/powernv/opal-hmi.c
index b322bfb..2668225 100644
--- a/arch/powerpc/platforms/powernv/opal-hmi.c
+++ b/arch/powerpc/platforms/powernv/opal-hmi.c
@@ -35,9 +35,134 @@ struct OpalHmiEvtNode {
struct list_head list;
struct OpalHMIEvent hmi_evt;
 };
+
+struct xstop_reason {
+   uint32_t xstop_reason;
+   const char *unit_failed;
+   const char *description;
+};
+
 static LIST_HEAD(opal_hmi_evt_list);
 static DEFINE_SPINLOCK(opal_hmi_evt_lock);
 
+static void print_core_checkstop_reason(const char *level,
+   struct OpalHMIEvent *hmi_evt)
+{
+   int i;
+   static const struct xstop_reason xstop_reason[] = {
+   { CORE_CHECKSTOP_IFU_REGFILE, "IFU",
+   "RegFile core check stop" },
+   { CORE_CHECKSTOP_IFU_LOGIC, "IFU", "Logic core check stop"

Re: [PATCH 3/3] powerpc: Include linux/jump_label.h to get HAVE_JUMP_LABEL define

[Steven Rostedt]

On Thu,  9 Apr 2015 13:51:32 +1000
Anton Blanchard  wrote:

> Commit 1bc9e47aa8e4 ("powerpc/jump_label: Use HAVE_JUMP_LABEL")
> converted uses of CONFIG_JUMP_LABEL to HAVE_JUMP_LABEL in
> some assembly files.
> 
> HAVE_JUMP_LABEL is defined in linux/jump_label.h, so we need to
> include this or we always get the non jump label fallback code.
> 
> Fixes: 1bc9e47aa8e4 ("powerpc/jump_label: Use HAVE_JUMP_LABEL")
> Signed-off-by: Anton Blanchard 

Acked-by: Steven Rostedt 

-- Steve
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Re: [PATCH 2/3] jump_label: Allow jump labels to be used in assembly

[Steven Rostedt]

On Thu,  9 Apr 2015 13:51:31 +1000
Anton Blanchard  wrote:

> To use jump labels in assembly we need the HAVE_JUMP_LABEL define,
> so we select a fallback version if the toolchain does not support
> them.
> 
> Modify linux/jump_label.h so it can be included by assembly files.
> We also need to add -DCC_HAVE_ASM_GOTO to KBUILD_AFLAGS.
> 
> Signed-off-by: Anton Blanchard 

Acked-by: Steven Rostedt 

-- Steve
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Re: [PATCH 1/3] jump_label: Allow asm/jump_label.h to be included in assembly

[Steven Rostedt]

On Thu,  9 Apr 2015 13:51:30 +1000
Anton Blanchard  wrote:

> Wrap asm/jump_label.h for all archs with #ifndef __ASSEMBLY__.
> Since these are kernel only headers, we don't need #ifdef __KERNEL__
> so can simplify things a bit.
> 
> If an architecture wants to use jump labels in assembly, it
> will still need to define a macro to create the __jump_table
> entries (see ARCH_STATIC_BRANCH in the powerpc asm/jump_label.h
> for an example).
> 
> Signed-off-by: Anton Blanchard 
> ---
>  arch/arm/include/asm/jump_label.h   | 5 ++---
>  arch/arm64/include/asm/jump_label.h | 8 
>  arch/mips/include/asm/jump_label.h  | 7 +++
>  arch/s390/include/asm/jump_label.h  | 3 +++
>  arch/sparc/include/asm/jump_label.h | 5 ++---
>  arch/x86/include/asm/jump_label.h   | 5 ++---
>  6 files changed, 16 insertions(+), 17 deletions(-)
> 
> diff --git a/arch/arm/include/asm/jump_label.h 
> b/arch/arm/include/asm/jump_label.h

Acked-by: Steven Rostedt 

-- Steve
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Re: [V6,1/9] elf: Add new powerpc specifc core note sections

[Anshuman Khandual]

On 04/09/2015 04:41 AM, Michael Neuling wrote:
> On Wed, 2015-04-08 at 19:50 +0200, Ulrich Weigand wrote:
>> Anshuman Khandual  wrote on 23.03.2015
>> 11:34:30:
>>
 With that in mind, do we have a way to set the top 32bits of the MSR
 (which contain the TM bits) when ptracing 32 bit processes?  I can't
 find anything like that in this patch set.
>>>
>>> No, we dont have that yet. When ptracing in 32-bit mode the MSR value
>>> which can be viewed or set from the user space through PTRACE_GETREGS
>>> PTRACE_SETREGS call is it's lower 32 bits only. Either we can club
>>> the upper 32 bits of MSR as part of one of the ELF core notes we are
>>> adding in the patch series or we can create one more separate ELF core
>>> note for that purpose. Let me know your opinion on this.
>>
>> I'm not sure I understand this.  I thought we had the following:
>>
>> - If the process calling ptrace is itself 64-bit (which is how GDB is
>>   built on all current Linux distributions), then PTRACE_GETREGS etc.
>>   will *always* operate on 64-bit register sets, even if the target
>>   process is 32-bit.
>>
>> - If the process calling ptrace is 32-bit, then PTRACE_GETREGS will
>>   operate on 32-bit register sets.   However, there is a separate
>>   PTRACE_GETREGS64 / PTRACE_SETREGS64 call that will also provide
>>   the opportunity to operate on the full 64-bit register set.  Both
>>   apply independently of whether the target process is 32-bit or
>>   64-bit.
>>
>> Is this not correct?
> 
> I think you're correct.  We should be right.  I'd forgotten about the
> GET/SETREGS64 interfaces.

In that case, is the patch series complete and okay ? Is there any thing
else we need to verify other than waiting for the GDB test results which
Edjunior has been working on. But I am not aware of the status on the GDB
test development front.

Edjunior,

Do you have any updates ?

Regards
Anshuman


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Re: [V2, 06/12] selftests, powerpc: Add test for system wide DSCR default

[Anshuman Khandual]

On 04/09/2015 04:01 PM, Anshuman Khandual wrote:
> On 03/27/2015 05:31 PM, Michael Ellerman wrote:
>> On Tue, 2015-13-01 at 10:22:34 UTC, Anshuman Khandual wrote:
>>> This patch adds a test case for the system wide DSCR default
>>> value, which when changed through it's sysfs interface must
>>> be visible to all threads reading DSCR either through the
>>> privilege state SPR or the problem state SPR. The DSCR value
>>> change should be immediate as well.
>>
>> ...
>>
>>> +
>>> +/* Default DSCR access */
>>> +unsigned long get_default_dscr(void)
>>> +{
>>> +   int fd = -1;
>>> +   char buf[16];
>>> +   unsigned long val;
>>> +
>>> +   if (fd == -1) {
>>> +   fd = open(DSCR_DEFAULT, O_RDONLY);
>>> +   if (fd == -1) {
>>> +   perror("open() failed\n");
>>> +   exit(1);
>>> +   }
>>> +   }
>>> +   memset(buf, 0, sizeof(buf));
>>> +   lseek(fd, 0, SEEK_SET);
>>> +   read(fd, buf, sizeof(buf));
>>
> 
> Normally, I build the test cases like
> 
> $cd tools/testing/selftests/powerpc/
> $make dscr
> 
> with these compiler flags "-Wall -O2 -flto -Wall -Werror" which
> is still working for me. Then I figured out that the read and
> write declaration in unistd.h header file has "_wur" in it.
> 
> extern ssize_t read (int __fd, void *__buf, size_t __nbytes) __wur;
> extern ssize_t write (int __fd, const void *__buf, size_t __n) __wur;
> 
> Then some how the compiler (GCC 4.8.3) is not complaining about it.
> 
>>
>> This and the other tests are failing to build:
>>
>> In file included from dscr_default_test.c:16:0:
>> dscr.h: In function ‘get_default_dscr’:
>> dscr.h:93:6: error: ignoring return value of ‘read’, declared with 
>> attribute warn_unused_result [-Werror=unused-result]
>>   read(fd, buf, sizeof(buf));
>>   ^
>> dscr.h: In function ‘set_default_dscr’:
>> dscr.h:112:7: error: ignoring return value of ‘write’, declared with 
>> attribute warn_unused_result [-Werror=unused-result]
>>   write(fd, buf, strlen(buf));
>>^
>> cc1: all warnings being treated as errors
> 
> Anyways, I can change the header file helper functions if you would like.
> BTW, the patch series does not apply as it is and requires rebasing. Would
> send out a new version of it.

The rebased patch series works as expected like this version and all the tests
pass. I would add a  .gitignore file for this new test directory. Please let me
know if there are other changes which need to be done. Thanks !!

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[PATCH] powerpc/config: Enable bnx2x on ppc64 and pseries defconfigs

[Anton Blanchard]

Signed-off-by: Anton Blanchard 
---
 arch/powerpc/configs/ppc64_defconfig  | 1 +
 arch/powerpc/configs/pseries_defconfig| 1 +
 arch/powerpc/configs/pseries_le_defconfig | 1 +
 3 files changed, 3 insertions(+)

diff --git a/arch/powerpc/configs/ppc64_defconfig 
b/arch/powerpc/configs/ppc64_defconfig
index 3315c9f..a6ed742 100644
--- a/arch/powerpc/configs/ppc64_defconfig
+++ b/arch/powerpc/configs/ppc64_defconfig
@@ -157,6 +157,7 @@ CONFIG_ACENIC=m
 CONFIG_ACENIC_OMIT_TIGON_I=y
 CONFIG_PCNET32=y
 CONFIG_TIGON3=y
+CONFIG_BNX2X=m
 CONFIG_CHELSIO_T1=m
 CONFIG_BE2NET=m
 CONFIG_S2IO=m
diff --git a/arch/powerpc/configs/pseries_defconfig 
b/arch/powerpc/configs/pseries_defconfig
index c2e39f6..d09c723 100644
--- a/arch/powerpc/configs/pseries_defconfig
+++ b/arch/powerpc/configs/pseries_defconfig
@@ -154,6 +154,7 @@ CONFIG_ACENIC=m
 CONFIG_ACENIC_OMIT_TIGON_I=y
 CONFIG_PCNET32=y
 CONFIG_TIGON3=y
+CONFIG_BNX2X=m
 CONFIG_CHELSIO_T1=m
 CONFIG_BE2NET=m
 CONFIG_S2IO=m
diff --git a/arch/powerpc/configs/pseries_le_defconfig 
b/arch/powerpc/configs/pseries_le_defconfig
index 09bc96e..5ad0253 100644
--- a/arch/powerpc/configs/pseries_le_defconfig
+++ b/arch/powerpc/configs/pseries_le_defconfig
@@ -155,6 +155,7 @@ CONFIG_ACENIC=m
 CONFIG_ACENIC_OMIT_TIGON_I=y
 CONFIG_PCNET32=y
 CONFIG_TIGON3=y
+CONFIG_BNX2X=m
 CONFIG_CHELSIO_T1=m
 CONFIG_BE2NET=m
 CONFIG_S2IO=m
-- 
2.1.0

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Re: [V2, 06/12] selftests, powerpc: Add test for system wide DSCR default

[Anshuman Khandual]

On 03/27/2015 05:31 PM, Michael Ellerman wrote:
> On Tue, 2015-13-01 at 10:22:34 UTC, Anshuman Khandual wrote:
>> This patch adds a test case for the system wide DSCR default
>> value, which when changed through it's sysfs interface must
>> be visible to all threads reading DSCR either through the
>> privilege state SPR or the problem state SPR. The DSCR value
>> change should be immediate as well.
> 
> ...
> 
>> +
>> +/* Default DSCR access */
>> +unsigned long get_default_dscr(void)
>> +{
>> +int fd = -1;
>> +char buf[16];
>> +unsigned long val;
>> +
>> +if (fd == -1) {
>> +fd = open(DSCR_DEFAULT, O_RDONLY);
>> +if (fd == -1) {
>> +perror("open() failed\n");
>> +exit(1);
>> +}
>> +}
>> +memset(buf, 0, sizeof(buf));
>> +lseek(fd, 0, SEEK_SET);
>> +read(fd, buf, sizeof(buf));
> 

Normally, I build the test cases like

$cd tools/testing/selftests/powerpc/
$make dscr

with these compiler flags "-Wall -O2 -flto -Wall -Werror" which
is still working for me. Then I figured out that the read and
write declaration in unistd.h header file has "_wur" in it.

extern ssize_t read (int __fd, void *__buf, size_t __nbytes) __wur;
extern ssize_t write (int __fd, const void *__buf, size_t __n) __wur;

Then some how the compiler (GCC 4.8.3) is not complaining about it.

> 
> This and the other tests are failing to build:
> 
> In file included from dscr_default_test.c:16:0:
> dscr.h: In function ‘get_default_dscr’:
> dscr.h:93:6: error: ignoring return value of ‘read’, declared with 
> attribute warn_unused_result [-Werror=unused-result]
>   read(fd, buf, sizeof(buf));
>   ^
> dscr.h: In function ‘set_default_dscr’:
> dscr.h:112:7: error: ignoring return value of ‘write’, declared with 
> attribute warn_unused_result [-Werror=unused-result]
>   write(fd, buf, strlen(buf));
>^
> cc1: all warnings being treated as errors

Anyways, I can change the header file helper functions if you would like.
BTW, the patch series does not apply as it is and requires rebasing. Would
send out a new version of it.

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[PATCH] powerpc/dts: Add some SoC specific "fsl, *-device-config" compatibles

[Igal . Liberman]

From: Igal Liberman 

This patch is required for: https://patchwork.ozlabs.org/patch/459584/

Signed-off-by: Igal Liberman 
---
 arch/powerpc/boot/dts/fsl/b4420si-post.dtsi |3 ++-
 arch/powerpc/boot/dts/fsl/b4860si-post.dtsi |3 ++-
 arch/powerpc/boot/dts/fsl/b4si-post.dtsi|3 ++-
 arch/powerpc/boot/dts/fsl/p2041si-post.dtsi |3 ++-
 arch/powerpc/boot/dts/fsl/p3041si-post.dtsi |3 ++-
 arch/powerpc/boot/dts/fsl/p4080si-post.dtsi |3 ++-
 arch/powerpc/boot/dts/fsl/p5020si-post.dtsi |3 ++-
 7 files changed, 14 insertions(+), 7 deletions(-)

diff --git a/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi 
b/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
index 1ea8602..9b14f24 100644
--- a/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
@@ -77,7 +77,8 @@
};
 
guts: global-utilities@e {
-   compatible = "fsl,b4420-device-config", 
"fsl,qoriq-device-config-2.0";
+   compatible = "fsl,b4420-device-config", "fsl,b4-device-config",
+ "fsl,qoriq-device-config-2.0";
};
 
global-utilities@e1000 {
diff --git a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi 
b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
index 02ccde6..74a9f5f 100644
--- a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
@@ -248,7 +248,8 @@
};
 
guts: global-utilities@e {
-   compatible = "fsl,b4860-device-config", 
"fsl,qoriq-device-config-2.0";
+   compatible = "fsl,b4860-device-config", "fsl,b4-device-config",
+"fsl,qoriq-device-config-2.0";
};
 
global-utilities@e1000 {
diff --git a/arch/powerpc/boot/dts/fsl/b4si-post.dtsi 
b/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
index f8c325e..babb076 100644
--- a/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
@@ -391,7 +391,8 @@
 /include/ "qoriq-mpic4.3.dtsi"
 
guts: global-utilities@e {
-   compatible = "fsl,b4-device-config";
+   compatible = "fsl,b4-device-config",
+ "fsl,qoriq-device-config-2.0";
reg = <0xe 0xe00>;
fsl,has-rstcr;
fsl,liodn-bits = <12>;
diff --git a/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi 
b/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
index 1f18b8b..a7ae5ae 100644
--- a/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
@@ -311,7 +311,8 @@
 /include/ "qoriq-mpic.dtsi"
 
guts: global-utilities@e {
-   compatible = "fsl,qoriq-device-config-1.0";
+   compatible = "fsl,p2041-device-config",
+ "fsl,qoriq-device-config-1.0";
reg = <0xe 0xe00>;
fsl,has-rstcr;
#sleep-cells = <1>;
diff --git a/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi 
b/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
index a555d24..89d08d6 100644
--- a/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
@@ -338,7 +338,8 @@
 /include/ "qoriq-mpic.dtsi"
 
guts: global-utilities@e {
-   compatible = "fsl,qoriq-device-config-1.0";
+   compatible = "fsl,p3041-device-config",
+ "fsl,qoriq-device-config-1.0";
reg = <0xe 0xe00>;
fsl,has-rstcr;
#sleep-cells = <1>;
diff --git a/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi 
b/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
index 0fe7281..1863d6a 100644
--- a/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
@@ -358,7 +358,8 @@
 /include/ "qoriq-mpic.dtsi"
 
guts: global-utilities@e {
-   compatible = "fsl,qoriq-device-config-1.0";
+   compatible = "fsl,p4080-device-config",
+ "fsl,qoriq-device-config-1.0";
reg = <0xe 0xe00>;
fsl,has-rstcr;
#sleep-cells = <1>;
diff --git a/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi 
b/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
index a34ca20..d979d01 100644
--- a/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
@@ -343,7 +343,8 @@
 /include/ "qoriq-mpic.dtsi"
 
guts: global-utilities@e {
-   compatible = "fsl,qoriq-device-config-1.0";
+   compatible = "fsl,p5020-device-config",
+ "fsl,qoriq-device-config-1.0";
reg = <0xe 0xe00>;
fsl,has-rstcr;
#sleep-cells = <1>;
-- 
1.7.9.5

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[PATCH] dt/bindings: fsl/guts: Added global-utilities compatibles

[Igal . Liberman]

From: Igal Liberman 

Signed-off-by: Igal Liberman 
---
 .../devicetree/bindings/powerpc/fsl/guts.txt   |   14 ++
 1 file changed, 14 insertions(+)

diff --git a/Documentation/devicetree/bindings/powerpc/fsl/guts.txt 
b/Documentation/devicetree/bindings/powerpc/fsl/guts.txt
index 7f150b5..e4f0ac2 100644
--- a/Documentation/devicetree/bindings/powerpc/fsl/guts.txt
+++ b/Documentation/devicetree/bindings/powerpc/fsl/guts.txt
@@ -9,6 +9,20 @@ Required properties:
 
  - compatible : Should define the compatible device type for
global-utilities.
+   Possible compatibles:
+   "fsl,qoriq-device-config-1.0"
+   "fsl,p2041-device-config"
+   "fsl,p3041-device-config"
+   "fsl,p4080-device-config"
+   "fsl,p5020-device-config"
+   "fsl,p5040-device-config"
+   "fsl,qoriq-device-config-2.0"
+   "fsl,b4860-device-config"
+   "fsl,b4420-device-config"
+   "fsl,b4-device-config"
+   "fsl,t1040-device-config"
+   "fsl,t2080-device-config"
+   "fsl,t4240-device-config"
  - reg : Offset and length of the register set for the device.
 
 Recommended properties:
-- 
1.7.9.5

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Re: [PATCH V2] tty: serial: Add const to struct uart_ops declarations

[Thierry Reding]

On Sun, Apr 05, 2015 at 11:24:54AM -0700, Joe Perches wrote:
[...]
>  drivers/tty/serial/serial-tegra.c   | 2 +-

Acked-by: Thierry Reding 


pgpMuP0DtU6my.pgp
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[PATCH 1/4 v3] powerpc/fsl-booke: Add device tree support for T1024/T1023 SoC

[Shengzhou Liu]

The T1024 SoC includes the following function and features:
- Two 64-bit Power architecture e5500 cores, up to 1.4GHz
- private 256KB L2 cache each core and shared 256KB CoreNet platform cache (CPC)
- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving 
support
- Data Path Acceleration Architecture (DPAA) incorporating acceleration
- Four MAC for 1G/2.5G/10G network interfaces (RGMII, SGMII, QSGMII, XFI)
- High-speed peripheral interfaces
  - Three PCI Express 2.0 controllers
- Additional peripheral interfaces
  - One SATA 2.0 controller
  - Two USB 2.0 controllers with integrated PHY
  - Enhanced secure digital host controller (SD/eSDHC/eMMC)
  - Enhanced serial peripheral interface (eSPI)
  - Four I2C controllers
  - Four 2-pin UARTs or two 4-pin UARTs
  - Integrated Flash Controller supporting NAND and NOR flash
- Two 8-channel DMA engines
- Multicore programmable interrupt controller (PIC)
- LCD interface (DIU) with 12 bit dual data rate
- QUICC Engine block supporting TDM, HDLC, and UART
- Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
- Support for hardware virtualization and partitioning enforcement
- QorIQ Platform's Trust Architecture 2.0

Signed-off-by: Shengzhou Liu 
---
v3: use qoriq-clockgen2.dtsi
v2: Integrated scott's comments.
note: qoriq-tdm1.0.dtsi depends on patch 
http://patchwork.ozlabs.org/patch/457605/

 arch/powerpc/boot/dts/fsl/t1023si-post.dtsi | 330 
 arch/powerpc/boot/dts/fsl/t1024si-post.dtsi | 102 +
 arch/powerpc/boot/dts/fsl/t102xsi-pre.dtsi  |  87 
 3 files changed, 519 insertions(+)
 create mode 100644 arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
 create mode 100644 arch/powerpc/boot/dts/fsl/t1024si-post.dtsi
 create mode 100644 arch/powerpc/boot/dts/fsl/t102xsi-pre.dtsi

diff --git a/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi 
b/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
new file mode 100644
index 000..dbe6578
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
@@ -0,0 +1,330 @@
+/*
+ * T1023 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2014 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ *  notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ *  notice, this list of conditions and the following disclaimer in the
+ *  documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ *  names of its contributors may be used to endorse or promote products
+ *  derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+&ifc {
+   #address-cells = <2>;
+   #size-cells = <1>;
+   compatible = "fsl,ifc", "simple-bus";
+   interrupts = <25 2 0 0>;
+};
+
+&pci0 {
+   compatible = "fsl,t1023-pcie", "fsl,qoriq-pcie-v2.4", "fsl,qoriq-pcie";
+   device_type = "pci";
+   #size-cells = <2>;
+   #address-cells = <3>;
+   bus-range = <0x0 0xff>;
+   interrupts = <20 2 0 0>;
+   fsl,iommu-parent = <&pamu0>;
+   pcie@0 {
+   reg = <0 0 0 0 0>;
+   #interrupt-cells = <1>;
+   #size-cells = <2>;
+   #address-cells = <3>;
+   device_type = "pci";
+   interrupts = <20 2 0 0>;
+   interrupt-map-mask = <0xf800 0 0 7>;
+   interrupt-map = <
+   /* IDSEL 0x0 */
+    0 0 1 &mpic 40 1 0 0
+    0 0 2 &mpic 1 1 0 0
+    0 0 3 &mpic 2 1 0 0
+    0 0 4 &mpic 3 1 0 0
+   >;
+   };
+};
+
+&pci1 {
+   comp

[PATCH 4/4 v3] powerpc/fsl-booke: Add T1023 RDB board support

[Shengzhou Liu]

T1023RDB is a Freescale Reference Design Board that hosts T1023 SoC.

T1023RDB board Overview
---
- T1023 SoC integrating two 64-bit e5500 cores up to 1.4GHz
- CoreNet fabric supporting coherent and noncoherent transactions with
  prioritization and bandwidth allocation
- Memory: 2GB Micron MT40A512M8HX unbuffered 32-bit fixed DDR4 without ECC
- Accelerator: DPAA components consist of FMan, BMan, QMan, DCE and SEC
- Ethernet interfaces:
  - one 1G RGMII port on-board(RTL8211F PHY)
  - one 1G SGMII port on-board(RTL8211F PHY)
  - one 2.5G SGMII port on-board(AQR105 PHY)
- PCIe: Two Mini-PCIe connectors on-board.
- SerDes: 4 lanes up to 10.3125GHz
- NOR:  128MB S29GL01GS110TFIV10 Spansion NOR Flash
- NAND: 512MB S34MS04G200BFI000 Spansion NAND Flash
- eSPI: 64MB S25FL512SAGMFI010 Spansion SPI flash
- USB: one Type-A USB 2.0 port with internal PHY
- eSDHC: support SD/MMC card and eMMC flash on-board
- 256Kbit M24256 I2C EEPROM
- RTC: Real-time clock DS1339 on I2C bus
- UART: one serial port on-board with RJ45 connector
- Debugging: JTAG/COP for T1023 debugging

Signed-off-by: Shengzhou Liu 
---
v3: no change
v2: no change

 arch/powerpc/boot/dts/t1023rdb.dts| 151 ++
 arch/powerpc/platforms/85xx/corenet_generic.c |   1 +
 2 files changed, 152 insertions(+)
 create mode 100644 arch/powerpc/boot/dts/t1023rdb.dts

diff --git a/arch/powerpc/boot/dts/t1023rdb.dts 
b/arch/powerpc/boot/dts/t1023rdb.dts
new file mode 100644
index 000..3780e68
--- /dev/null
+++ b/arch/powerpc/boot/dts/t1023rdb.dts
@@ -0,0 +1,151 @@
+/*
+ * T1023 RDB Device Tree Source
+ *
+ * Copyright 2014 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ *  notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ *  notice, this list of conditions and the following disclaimer in the
+ *  documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ *  names of its contributors may be used to endorse or promote products
+ *  derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ "fsl/t102xsi-pre.dtsi"
+
+/ {
+   model = "fsl,T1023RDB";
+   compatible = "fsl,T1023RDB";
+   #address-cells = <2>;
+   #size-cells = <2>;
+   interrupt-parent = <&mpic>;
+
+   ifc: localbus@ffe124000 {
+   reg = <0xf 0xfe124000 0 0x2000>;
+   ranges = <0 0 0xf 0xe800 0x0800
+ 1 0 0xf 0xff80 0x0001>;
+
+   nor@0,0 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   status = "disabled";
+   compatible = "cfi-flash";
+   reg = <0x0 0x0 0x800>;
+   bank-width = <2>;
+   device-width = <1>;
+   };
+
+   nand@1,0 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "fsl,ifc-nand";
+   reg = <0x2 0x0 0x1>;
+   };
+   };
+
+   memory {
+   device_type = "memory";
+   };
+
+   dcsr: dcsr@f {
+   ranges = <0x 0xf 0x 0x01072000>;
+   };
+
+   soc: soc@ffe00 {
+   ranges = <0x 0xf 0xfe00 0x100>;
+   reg = <0xf 0xfe00 0 0x1000>;
+   spi@11 {
+   flash@0 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+ 

[PATCH 3/4 v3] powerpc/fsl-booke: Add T1024 RDB board support

[Shengzhou Liu]

T1024RDB is a Freescale Reference Design Board that hosts the T1024 SoC.

T1024RDB board Overview
---
- Processor: T1024 SoC integrating two 64-bit e5500 cores up to 1.4GHz
- Memory: 64-bit 4GB DDR3L UDIMM with ECC and interleaving support
- Ethernet: two 1G RGMII ports, one 2.5G SGMII port and one 10G Base-T port
- Accelerator: DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC
- SerDes: 4 lanes up to 10.3125GHz
- IFC: 128MB NOR Flash, 1GB NAND Flash and CPLD system controlling
- PCIe: one PCIe slot and two Mini-PCIe connectors on-board
- USB: two Type-A USB2.0 ports with internal PHY
- eSDHC: one SDHC/MMC/eMMC connector
- eSPI: one 64MB N25Q512 SPI flash
- QE-TDM: support TDM Riser card
   - 32-bit RISC controller for flexible support of the communications 
peripherals
   - Serial DMA channel for receive and transmit on all serial channels
   - Two universal communication controllers, supporting TDM, HDLC, and UART
- I2C: four I2C controllers
- UART: two UART on board
- Deep sleep power management support

Signed-off-by: Shengzhou Liu 
---
v3: no change.
v2: Integrated scott's comments.

 arch/powerpc/boot/dts/t1024rdb.dts| 185 ++
 arch/powerpc/platforms/85xx/Kconfig   |   2 +-
 arch/powerpc/platforms/85xx/corenet_generic.c |   1 +
 3 files changed, 187 insertions(+), 1 deletion(-)
 create mode 100644 arch/powerpc/boot/dts/t1024rdb.dts

diff --git a/arch/powerpc/boot/dts/t1024rdb.dts 
b/arch/powerpc/boot/dts/t1024rdb.dts
new file mode 100644
index 000..eb1d51b
--- /dev/null
+++ b/arch/powerpc/boot/dts/t1024rdb.dts
@@ -0,0 +1,185 @@
+/*
+ * T1024 RDB Device Tree Source
+ *
+ * Copyright 2014 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ *  notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ *  notice, this list of conditions and the following disclaimer in the
+ *  documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ *  names of its contributors may be used to endorse or promote products
+ *  derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ "fsl/t102xsi-pre.dtsi"
+
+/ {
+   model = "fsl,T1024RDB";
+   compatible = "fsl,T1024RDB";
+   #address-cells = <2>;
+   #size-cells = <2>;
+   interrupt-parent = <&mpic>;
+
+   ifc: localbus@ffe124000 {
+   reg = <0xf 0xfe124000 0 0x2000>;
+   ranges = <0 0 0xf 0xe800 0x0800
+ 2 0 0xf 0xff80 0x0001
+ 3 0 0xf 0xffdf 0x8000>;
+
+   nor@0,0 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "cfi-flash";
+   reg = <0x0 0x0 0x800>;
+   bank-width = <2>;
+   device-width = <1>;
+   };
+
+   nand@1,0 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "fsl,ifc-nand";
+   reg = <0x2 0x0 0x1>;
+   };
+
+   board-control@2,0 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "fsl,t1024-cpld";
+   reg = <3 0 0x300>;
+   ranges = <0 3 0 0x300>;
+   bank-width = <1>;
+   device-width = <1>;
+   };
+   };
+
+   memory {
+   device_type = "memory";
+   };
+
+   dcsr:

[PATCH 2/4 v3] powerpc/fsl-booke: Add T1024 QDS board support

[Shengzhou Liu]

Add support for Freescale T1024/T1023 QorIQ Development System Board.

T1024QDS is a high-performance computing evaluation, development and
test platform for T1024 QorIQ Power Architecture processor.

T1024QDS board Overview
---
- T1024 SoC integrating two 64-bit e5500 cores up to 1.4GHz
- CoreNet fabric supporting coherent and noncoherent transactions with
  prioritization and bandwidth allocation
- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving 
support
- Accelerator: DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC
- Ethernet interfaces:
  - Two 10M/100M/1G RGMII ports on-board
  - Three 1G/2.5Gbps SGMII ports
  - Four 1Gbps QSGMII ports
  - one 10Gbps XFI or 10G Base-KR interface
- SerDes: 4 lanes up to 10.3125GHz Supporting SGMII/QSGMII, XFI, PCIe, SATA and 
Aurora
- PCIe: Three PCI Express controllers with five PCIe slots.
- IFC: 128MB NOR Flash, 2GB NAND Flash, PromJet debug port and Qixis FPGA
- Video: DIU supports video up to 1280x1024x32 bpp.
  - Chrontel CH7201 for HDMI connection.
  - TI DS90C387R for direct LCD connection.
  - Raw (not encoded) video connector for testing or other encoders.
- QUICC Engine block
  - 32-bit RISC controller for flexible support of the communications 
peripherals
  - Serial DMA channel for receive and transmit on all serial channels
  - Two universal communication controllers, supporting TDM, HDLC, and UART
- Deep sleep power management implementaion (wakeup from 
GPIO/Timer/Ethernet/USB)
- eSPI: Three SPI flash devices.
- SATA: one SATA 2.O.
- USB: Two USB2.0 ports with internal PHY (one Type-A and one micro Type 
mini-AB)
- eSDHC: Support SD, SDHC, SDXC and MMC/eMMC.
- I2C: Four I2C controllers.
- UART: Two UART on board.

Signed-off-by: Shengzhou Liu 
---
v3: no change
v2: no change

 arch/powerpc/boot/dts/t1024qds.dts| 251 ++
 arch/powerpc/platforms/85xx/Kconfig   |   2 +-
 arch/powerpc/platforms/85xx/corenet_generic.c |   1 +
 3 files changed, 253 insertions(+), 1 deletion(-)
 create mode 100644 arch/powerpc/boot/dts/t1024qds.dts

diff --git a/arch/powerpc/boot/dts/t1024qds.dts 
b/arch/powerpc/boot/dts/t1024qds.dts
new file mode 100644
index 000..14122cf
--- /dev/null
+++ b/arch/powerpc/boot/dts/t1024qds.dts
@@ -0,0 +1,251 @@
+/*
+ * T1024 QDS Device Tree Source
+ *
+ * Copyright 2014 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ *  notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ *  notice, this list of conditions and the following disclaimer in the
+ *  documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ *  names of its contributors may be used to endorse or promote products
+ *  derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ "fsl/t102xsi-pre.dtsi"
+
+/ {
+   model = "fsl,T1024QDS";
+   compatible = "fsl,T1024QDS";
+   #address-cells = <2>;
+   #size-cells = <2>;
+   interrupt-parent = <&mpic>;
+
+   ifc: localbus@ffe124000 {
+   reg = <0xf 0xfe124000 0 0x2000>;
+   ranges = <0 0 0xf 0xe800 0x0800
+ 2 0 0xf 0xff80 0x0001
+ 3 0 0xf 0xffdf 0x8000>;
+
+   nor@0,0 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "cfi-flash";
+   reg = <0x0 0x0 0x800>;
+   bank-width = <2>;
+   device-width = <1>;
+   };
+
+   nand@2,0 {
+

[v2] clk: qoriq: Add support for the FMan clock

[Igal . Liberman]

From: Igal Liberman 

v2: - Added clock maintainers
- Cached FMan clock parent during initialization
- Register the clock after checking if the hardware exists
- updated error messages

Signed-off-by: Igal Liberman 
---
 drivers/clk/clk-qoriq.c |  208 +++
 1 file changed, 208 insertions(+)

diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
index cda90a9..d588e90 100644
--- a/drivers/clk/clk-qoriq.c
+++ b/drivers/clk/clk-qoriq.c
@@ -19,6 +19,8 @@
 #include 
 #include 
 
+#include 
+
 struct cmux_clk {
struct clk_hw hw;
void __iomem *reg;
@@ -155,6 +157,211 @@ err_name:
kfree(parent_names);
 }
 
+/* Table for matching compatible strings, for device tree
+ * guts node, for QorIQ SOCs.
+ * "fsl,qoriq-device-config-2.0" corresponds to T4 & B4
+ * SOCs. For the older SOCs "fsl,qoriq-device-config-1.0"
+ * string would be used.
+ */
+
+static const struct of_device_id guts_device_ids[] = {
+   { .compatible = "fsl,qoriq-device-config-1.0", },
+   { .compatible = "fsl,qoriq-device-config-2.0", },
+   {}
+};
+
+/* P2, P3, P4, P5 */
+#define FM1_CLK_SEL_SHIFT  30
+#define FM1_CLK_SELBIT(FM1_CLK_SEL_SHIFT)
+#define FM2_CLK_SEL_SHIFT  29
+#define FM2_CLK_SELBIT(FM2_CLK_SEL_SHIFT)
+#define HWA_ASYNC_DIV_SHIFT26
+#define HWA_ASYNC_DIV  BIT(HWA_ASYNC_DIV_SHIFT)
+
+/* B4, T2 */
+#define HWA_CGA_M1_CLK_SEL_SHIFT   29
+#define HWA_CGA_M1_CLK_SEL (BIT(HWA_CGA_M1_CLK_SEL_SHIFT + 2) |\
+BIT(HWA_CGA_M1_CLK_SEL_SHIFT + 1) |\
+BIT(HWA_CGA_M1_CLK_SEL_SHIFT))
+
+/* T4240 */
+#define HWA_CGB_M1_CLK_SEL_SHIFT   26
+#define HWA_CGB_M1_CLK_SEL (BIT(HWA_CGB_M1_CLK_SEL_SHIFT + 2) |\
+BIT(HWA_CGB_M1_CLK_SEL_SHIFT + 1) |\
+BIT(HWA_CGB_M1_CLK_SEL_SHIFT))
+#define HWA_CGB_M2_CLK_SEL_SHIFT   3
+#define HWA_CGB_M2_CLK_SEL (BIT(HWA_CGB_M2_CLK_SEL_SHIFT + 2) |\
+BIT(HWA_CGB_M2_CLK_SEL_SHIFT + 1) |\
+BIT(HWA_CGB_M2_CLK_SEL_SHIFT))
+
+static u8 get_fm_clk_parent(struct clk_hw *hw)
+{
+   return hw->init->flags;
+}
+
+static const struct clk_ops fm_clk_ops = {
+   .get_parent = get_fm_clk_parent,
+};
+
+static int get_fm_clk_idx(int fm_id, int *fm_clk_idx)
+{
+   struct ccsr_guts __iomem *guts_regs = NULL;
+   struct device_node *guts;
+   uint32_t reg = 0;
+   int clk_src = 0;
+
+   guts = of_find_matching_node(NULL, guts_device_ids);
+   if (!guts) {
+   pr_err("could not find GUTS node\n");
+   return -ENODEV;
+   }
+
+   guts_regs = of_iomap(guts, 0);
+   of_node_put(guts);
+   if (!guts_regs) {
+   pr_err("ioremap of GUTS node failed\n");
+   return -ENODEV;
+   }
+
+   if (of_device_is_compatible(guts, "fsl,p1023-guts") ||
+   of_device_is_compatible(guts, "fsl,t1040-device-config")) {
+   /* P1023 and T1040 have only one optional clock source */
+   *fm_clk_idx = 0;
+   } else if (of_device_is_compatible(guts, "fsl,p2041-device-config") ||
+  of_device_is_compatible(guts, "fsl,p3041-device-config") ||
+  of_device_is_compatible(guts, "fsl,p4080-device-config")) {
+   /* Read RCW*/
+   reg = ioread32be(&guts_regs->rcwsr[7]);
+
+   if (fm_id == 0)
+   *fm_clk_idx = (reg & FM1_CLK_SEL) >>
+   FM1_CLK_SEL_SHIFT;
+   else
+   *fm_clk_idx = (reg & FM2_CLK_SEL) >>
+   FM2_CLK_SEL_SHIFT;
+   } else if (of_device_is_compatible(guts, "fsl,p5020-device-config") ||
+  of_device_is_compatible(guts, "fsl,p5040-device-config")) {
+   /* Read RCW */
+   reg = ioread32be(&guts_regs->rcwsr[7]);
+
+   if (fm_id == 0)
+   clk_src = (reg & FM1_CLK_SEL) >> FM1_CLK_SEL_SHIFT;
+   else
+   clk_src = (reg & FM2_CLK_SEL) >> FM2_CLK_SEL_SHIFT;
+
+   if (clk_src == 0) {
+   *fm_clk_idx = 0;
+   } else {
+   clk_src = (reg & HWA_ASYNC_DIV) >> HWA_ASYNC_DIV_SHIFT;
+   *fm_clk_idx = clk_src + 1;
+   }
+   } else if (of_device_is_compatible(guts, "fsl,b4-device-config") ||
+  of_device_is_compatible(guts, "fsl,t2080-device-config")) {
+   /* Read RCW */
+   reg = ioread32be(&guts_regs->rcwsr[7]);
+
+   clk_src = (reg & HWA_CGA_M1_CLK_SEL) >>
+   

Re: [PATCH 0/2] powerpc/kvm: Enable running guests on RT Linux

[Purcareata Bogdan]

On 04.04.2015 00:26, Scott Wood wrote:

On Fri, 2015-04-03 at 11:07 +0300, Purcareata Bogdan wrote:

On 03.04.2015 02:11, Scott Wood wrote:

On Fri, 2015-03-27 at 19:07 +0200, Purcareata Bogdan wrote:

On 27.02.2015 03:05, Scott Wood wrote:

On Thu, 2015-02-26 at 14:31 +0100, Sebastian Andrzej Siewior wrote:

On 02/26/2015 02:02 PM, Paolo Bonzini wrote:



On 24/02/2015 00:27, Scott Wood wrote:

This isn't a host PIC driver.  It's guest PIC emulation, some of which
is indeed not suitable for a rawlock (in particular, openpic_update_irq
which loops on the number of vcpus, with a loop body that calls
IRQ_check() which loops over all pending IRQs).


The question is what behavior is wanted of code that isn't quite
RT-ready.  What is preferred, bugs or bad latency?

If the answer is bad latency (which can be avoided simply by not running
KVM on a RT kernel in production), patch 1 can be applied.  If the

can be applied *but* makes no difference if applied or not.


answer is bugs, patch 1 is not upstream material.

I myself prefer to have bad latency; if something takes a spinlock in
atomic context, that spinlock should be raw.  If it hurts (latency),
don't do it (use the affected code).


The problem, that is fixed by this s/spin_lock/raw_spin_lock/, exists
only in -RT. There is no change upstream. In general we fix such things
in -RT first and forward the patches upstream if possible. This convert
thingy would be possible.
Bug fixing comes before latency no matter if RT or not. Converting
every lock into a rawlock is not always the answer.
Last thing I read from Scott is that he is not entirely sure if this is
the right approach or not and patch #1 was not acked-by him either.

So for now I wait for Scott's feedback and maybe a backtrace :)


Obviously leaving it in a buggy state is not what we want -- but I lean
towards a short term "fix" of putting "depends on !PREEMPT_RT" on the
in-kernel MPIC emulation (which is itself just an optimization -- you
can still use KVM without it).  This way people don't enable it with RT
without being aware of the issue, and there's more of an incentive to
fix it properly.

I'll let Bogdan supply the backtrace.


So about the backtrace. Wasn't really sure how to "catch" this, so what
I did was to start a 24 VCPUs guest on a 24 CPU board, and in the guest
run 24 netperf flows with an external back to back board of the same
kind. I assumed this would provide the sufficient VCPUs and external
interrupt to expose an alleged culprit.

With regards to measuring the latency, I thought of using ftrace,
specifically the preemptirqsoff latency histogram. Unfortunately, I
wasn't able to capture any major differences between running a guest
with in-kernel MPIC emulation (with the openpic raw_spinlock_conversion
applied) vs. no in-kernel MPIC emulation. Function profiling
(trace_stat) shows that in the second case there's a far greater time
spent in kvm_handle_exit (100x), but overall, the maximum latencies for
preemptirqsoff don't look that much different.

Here are the max numbers (preemptirqsoff) for the 24 CPUs, on the host
RT Linux, sorted in descending order, expressed in microseconds:

In-kernel MPIC  QEMU MPIC
39755105


What are you measuring?  Latency in the host, or in the guest?


This is in the host kernel.


Those are terrible numbers in both cases.  Can you use those tracing
tools to find out what the code path is for QEMU MPIC?


After more careful inspection, I noticed that those big-big numbers
(couple of milliseconds) are isolated cases, and in fact 99.99% of those
latencies top to somewhere around 800us. I also have a feeling that the
isolated huge latencies might have something to do with
enabling/disabling tracing, since those numbers don't come up at all in
the actual trace output, only in the latency histogram. From what I
know, there are two separate mechanisms - the function tracer and the
latency histogram.

Now, about that max 800us - there are 2 things that are enabled by
default, and can cause bad latency:
1. scheduler load balancing - latency can top to up to 800us (as seen in
the trace output).
2. RT throttling - which calls sched_rt_period_timer, which cycles
through the runqueues of all CPUs - latency can top to 600us.

I'm mentioning these since the trace output for the max preemptirqsoff
period was always "stolen" by these activities, basically hiding
anything related to the kvm in-kernel openpic.

I disabled both of them, and now the max preemptirqsoff trace shows a
transition between a vhost thread and the qemu process, involving a
timer and external interrupt (do_irq), which you can see at the end of
this e-mail. Not much particularly related to the kvm openpic (but
perhaps I'm not able to understand it entirely). The trace for QEMU
MPIC looks pretty much the same.

So at this point I was getting kinda frustrated so I decided to measure
the time spend in kvm_mpic_write and kvm_mpic_read. I assumed these were
the main ent

Re: [PATCH 3/3] powerpc: Include linux/jump_label.h to get HAVE_JUMP_LABEL define

[Michael Ellerman]

On Thu, 2015-04-09 at 13:51 +1000, Anton Blanchard wrote:
> Commit 1bc9e47aa8e4 ("powerpc/jump_label: Use HAVE_JUMP_LABEL")
> converted uses of CONFIG_JUMP_LABEL to HAVE_JUMP_LABEL in
> some assembly files.
> 
> HAVE_JUMP_LABEL is defined in linux/jump_label.h, so we need to
> include this or we always get the non jump label fallback code.
> 
> Fixes: 1bc9e47aa8e4 ("powerpc/jump_label: Use HAVE_JUMP_LABEL")
> Signed-off-by: Anton Blanchard 
> ---
>  arch/powerpc/platforms/powernv/opal-wrappers.S | 2 +-
>  arch/powerpc/platforms/pseries/hvCall.S| 2 +-
>  arch/powerpc/platforms/pseries/lpar.c  | 2 +-
>  3 files changed, 3 insertions(+), 3 deletions(-)

Acked-by: Michael Ellerman 


I assume it's best for Andrew to take this series with all the cross-archness?

cheers


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RE: [v2] dt/bindings: qoriq-clock: Add binding for FMan clock mux

[igal.liber...@freescale.com]

Regards,
Igal Liberman.

> -Original Message-
> From: Wood Scott-B07421
> Sent: Thursday, April 09, 2015 12:12 AM
> To: Liberman Igal-B31950
> Cc: devicet...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org
> Subject: Re: [v2] dt/bindings: qoriq-clock: Add binding for FMan clock mux
> 
> On Wed, 2015-04-08 at 10:43 +0300, Igal.Liberman wrote:
> > @@ -76,6 +77,52 @@ Required properties:
> >
> >  Recommended properties:
> >  - clocks: Should be the phandle of input parent clock
> > +   For "fsl,fman-clk-mux" clock there are several options for parent
> > +   clock (clock provider), the parent is determined according to the
> > +   Reset Configuration Word of the specific device:
> > +   * P2041, P3041:
> > +   * 0 - equal to platform PLL divided by 2
> > +   * 1 - equal to PLL2 divided by 2
> > +   * P4080 (Both FMans):
> > +   * 0 - equal to platform PLL divided by 2
> > +   * 1 - equal to PLL3 divided by 2
> ...
> 
> 
> Again, the clock specifier format is determined by the clock provider, not the
> clock consumer.
> 

Scott,
The "clocks" property contains all possible clock providers, right?
In the text above I'm trying to explain how the FMan clock provider is 
determined and what are the options for each SoC.
Do you think that we shouldn't have this explanation? Can you please elaborate?

Igal.

> -Scott
> 

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Re: [PATCH 3/3] powerpc: Include linux/jump_label.h to get HAVE_JUMP_LABEL define

[Peter Zijlstra]

On Thu, Apr 09, 2015 at 01:51:32PM +1000, Anton Blanchard wrote:
> Commit 1bc9e47aa8e4 ("powerpc/jump_label: Use HAVE_JUMP_LABEL")
> converted uses of CONFIG_JUMP_LABEL to HAVE_JUMP_LABEL in
> some assembly files.
> 
> HAVE_JUMP_LABEL is defined in linux/jump_label.h, so we need to
> include this or we always get the non jump label fallback code.
> 
> Fixes: 1bc9e47aa8e4 ("powerpc/jump_label: Use HAVE_JUMP_LABEL")
> Signed-off-by: Anton Blanchard 

Acked-by: Peter Zijlstra (Intel) 
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Re: [PATCH 2/3] jump_label: Allow jump labels to be used in assembly

[Peter Zijlstra]

On Thu, Apr 09, 2015 at 01:51:31PM +1000, Anton Blanchard wrote:
> To use jump labels in assembly we need the HAVE_JUMP_LABEL define,
> so we select a fallback version if the toolchain does not support
> them.
> 
> Modify linux/jump_label.h so it can be included by assembly files.
> We also need to add -DCC_HAVE_ASM_GOTO to KBUILD_AFLAGS.
> 
> Signed-off-by: Anton Blanchard 

Acked-by: Peter Zijlstra (Intel) 
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Re: [PATCH 1/3] jump_label: Allow asm/jump_label.h to be included in assembly

[Peter Zijlstra]

On Thu, Apr 09, 2015 at 01:51:30PM +1000, Anton Blanchard wrote:
> Wrap asm/jump_label.h for all archs with #ifndef __ASSEMBLY__.
> Since these are kernel only headers, we don't need #ifdef __KERNEL__
> so can simplify things a bit.
> 
> If an architecture wants to use jump labels in assembly, it
> will still need to define a macro to create the __jump_table
> entries (see ARCH_STATIC_BRANCH in the powerpc asm/jump_label.h
> for an example).
> 
> Signed-off-by: Anton Blanchard 

Acked-by: Peter Zijlstra (Intel) 
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