Re: [PATCH] powerpc/pasemi,cbe: Do not process decremeter or external wakeup from powersave
On Fri, 17 Mar 2017 17:12:11 +1100
Michael Ellerman wrote:
> Michael Ellerman writes:
>
> > Nicholas Piggin writes:
> >
> >> Hi,
> >>
> >> I would like to start using a dedicated stack for system reset interrupt
> >> and treat it as a Linux nmi, which makes it tricky to call complex
> >> interrupt handlers directly from the system reset trap handler.
> >>
> >> So I would like to remove the decrementer and external handler calls from
> >> Cell and Pasemi platforms' system reset handler. I think we can just
> >> remove them if they can be handled when they re-fire as normal interrupts?
> >> At the moment I don't have environments set up to test if this works.
> >
> > My QS22 has booted OK with it applied, so it seems OK.
> >
> > I'll test it a bit more tomorrow.
>
> OK, seems fine, and I have a trace that shows it's definitely going
> through that path:
Thanks for testing it.
> 1) |.default_idle_call() {
> 1) | .arch_cpu_idle() {
> 1) |.cbe_power_save() {
> 1) 0.128 us| .prep_irq_for_idle();
> 1) | .system_reset_exception() {
> 1) 0.512 us|.cbe_system_reset_exception();
> 1) 6.016 us| }
> 1) | .do_IRQ() {
It seems to do the right thing. I think decrementer should be working
proprely by setting it to 1 to get another exception?
In that case I will add a changelog and submit the patch.
Thanks,
Nick
[PATCH kernel] KVM: PPC: Add MMIO emulation for stdx (store doubleword indexed)
This adds missing stdx emulation which allow Mellanox driver from recent kernels work when MMIO emulation is enforced in the userspace. Signed-off-by: Alexey Kardashevskiy --- arch/powerpc/include/asm/ppc-opcode.h | 1 + arch/powerpc/kvm/emulate_loadstore.c | 6 ++ 2 files changed, 7 insertions(+) diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h index e7d6d86563ee..ca1bbe49590b 100644 --- a/arch/powerpc/include/asm/ppc-opcode.h +++ b/arch/powerpc/include/asm/ppc-opcode.h @@ -92,6 +92,7 @@ #define OP_31_XOP_TRAP_64 68 #define OP_31_XOP_DCBF 86 #define OP_31_XOP_LBZX 87 +#define OP_31_XOP_STDX 149 #define OP_31_XOP_STWX 151 #define OP_31_XOP_STBX 215 #define OP_31_XOP_LBZUX 119 diff --git a/arch/powerpc/kvm/emulate_loadstore.c b/arch/powerpc/kvm/emulate_loadstore.c index 6d3c0ee1d744..9fdbeb8ea86c 100644 --- a/arch/powerpc/kvm/emulate_loadstore.c +++ b/arch/powerpc/kvm/emulate_loadstore.c @@ -82,6 +82,12 @@ int kvmppc_emulate_loadstore(struct kvm_vcpu *vcpu) kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed); break; + case OP_31_XOP_STDX: + emulated = kvmppc_handle_store(run, vcpu, + kvmppc_get_gpr(vcpu, rs), + 8, 1); + break; + case OP_31_XOP_STWX: emulated = kvmppc_handle_store(run, vcpu, kvmppc_get_gpr(vcpu, rs), -- 2.11.0
Re: [PATCH V2 10/11] powerpc/mm/radix: Make max pfn bits a variable
Paul Mackerras writes: > On Thu, Mar 16, 2017 at 04:02:08PM +0530, Aneesh Kumar K.V wrote: >> This makes max pysical address bits a variable so that hash and radix >> translation mode can choose what value to use. In this patch we also switch >> the >> radix translation mode to use 57 bits. This make it resilient to future >> changes >> to max pfn supported by platforms. >> >> This patch is split from the previous one to make the review easier. >> >> Signed-off-by: Aneesh Kumar K.V > > Why do we need to do this now? It seems like this will add overhead > every time we set a PTE for no current benefit. I was trying to make sure that radix kernel can run on future version of hardware where the max pfn bit is different. -aneesh
Re: [PATCH] powerpc/64s: fix idle wakeup potential to clobber registers
Hi ,
On Fri, Mar 17, 2017 at 03:13:20PM +1000, Nicholas Piggin wrote:
> We concluded there may be a window where the idle wakeup code could
> get to pnv_wakeup_tb_loss (which clobbers non-volatile GPRs), but the
> hardware may set SRR1[46:47] to 01b (no state loss) which would
> result in the wakeup code failing to restore non-volatile GPRs.
>
> I was not able to trigger this condition with trivial tests on
> real hardware or simulator, but the ISA (at least 2.07) seems to
> allow for it, and Gautham says that it can happen if there is an
> exception pending when the sleep/winkle instruction is executed.
>
> Signed-off-by: Nicholas Piggin
Acked-by: Gautham R. Shenoy
This fix should go into stable v4.8,v4.9 and v4.10.
Prior to commit 83289f909a72 ("powerpc/powernv: Rename idle_power7.S
to idle_book3s.S"), pnv_wakeup_tb_loss was explicitly restoring all
the GPRs to the saved value. So we are good for all the previous
kernel versions.
> ---
> arch/powerpc/kernel/idle_book3s.S | 20 +---
> 1 file changed, 17 insertions(+), 3 deletions(-)
>
> diff --git a/arch/powerpc/kernel/idle_book3s.S
> b/arch/powerpc/kernel/idle_book3s.S
> index 995728736677..6fd08219248d 100644
> --- a/arch/powerpc/kernel/idle_book3s.S
> +++ b/arch/powerpc/kernel/idle_book3s.S
> @@ -449,9 +449,23 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
> _GLOBAL(pnv_wakeup_tb_loss)
> ld r1,PACAR1(r13)
> /*
> - * Before entering any idle state, the NVGPRs are saved in the stack
> - * and they are restored before switching to the process context. Hence
> - * until they are restored, they are free to be used.
> + * Before entering any idle state, the NVGPRs are saved in the stack.
> + * If there was a state loss, or PACA_NAPSTATELOST was set, then the
> + * NVGPRs are restored. If we are here, it is likely that state is lost,
> + * but not guaranteed -- neither ISA207 nor ISA300 tests to reach
> + * here are the same as the test to restore NVGPRS:
> + * PACA_THREAD_IDLE_STATE test for ISA207, PSSCR test for ISA300,
> + * and SRR1 test for restoring NVGPRs.
> + *
> + * We are about to clobber NVGPRs now, so set NAPSTATELOST to
> + * guarantee they will always be restored. This might be tightened
> + * with careful reading of specs (particularly for ISA300) but this
> + * is already a slow wakeup path and it's simpler to be safe.
> + */
> + li r0,1
> + stb r0,PACA_NAPSTATELOST(r13)
> +
> + /*
>*
>* Save SRR1 and LR in NVGPRs as they might be clobbered in
>* opal_call() (called in CHECK_HMI_INTERRUPT). SRR1 is required
> --
> 2.11.0
>
--
Thanks and Regards
gautham.
Re: [PATCH] powerpc/pasemi, cbe: Do not process decremeter or external wakeup from powersave
Nicholas Piggin writes:
> On Fri, 17 Mar 2017 17:12:11 +1100
> Michael Ellerman wrote:
>> Michael Ellerman writes:
>> > Nicholas Piggin writes:
>> >> I would like to start using a dedicated stack for system reset interrupt
>> >> and treat it as a Linux nmi, which makes it tricky to call complex
>> >> interrupt handlers directly from the system reset trap handler.
>> >>
>> >> So I would like to remove the decrementer and external handler calls from
>> >> Cell and Pasemi platforms' system reset handler. I think we can just
>> >> remove them if they can be handled when they re-fire as normal interrupts?
>> >> At the moment I don't have environments set up to test if this works.
>> >
>> > My QS22 has booted OK with it applied, so it seems OK.
>> >
>> > I'll test it a bit more tomorrow.
>>
>> OK, seems fine, and I have a trace that shows it's definitely going
>> through that path:
>
> Thanks for testing it.
>
>> 1) |.default_idle_call() {
>> 1) | .arch_cpu_idle() {
>> 1) |.cbe_power_save() {
>> 1) 0.128 us| .prep_irq_for_idle();
>> 1) | .system_reset_exception() {
>> 1) 0.512 us|.cbe_system_reset_exception();
>> 1) 6.016 us| }
>> 1) | .do_IRQ() {
>
> It seems to do the right thing. I think decrementer should be working
> proprely by setting it to 1 to get another exception?
Yeah it is. It wasn't showing up in traces but I fixed that and here it
is below.
I'll try and test pasemi on Monday, but this looks fine for Cell.
cheers
1) |.default_idle_call() {
1) | .arch_cpu_idle() {
1) |.cbe_power_save() {
1) 0.192 us| .prep_irq_for_idle();
1) | .system_reset_exception() {
1) 0.320 us|.cbe_system_reset_exception();
1) 6.016 us| }
1) | .timer_interrupt() {
1) |.irq_enter() {
1) 0.768 us| .rcu_irq_enter();
1) | .tick_irq_enter() {
1) 0.256 us|.tick_check_oneshot_broadcast_this_cpu();
1) |.ktime_get() {
1) 0.192 us| .timebase_read();
1) 5.504 us|}
1) |.update_ts_time_stats() {
1) 0.640 us| .nr_iowait_cpu();
1) 6.656 us|}
1) + 28.160 us | }
1) | ._local_bh_enable() {
1) 0.192 us|.__local_bh_enable();
1) 5.120 us| }
1) | .vtime_account_irq_enter() {
1) |.vtime_account_idle() {
1) 0.320 us| .vtime_delta.isra.5();
1) 5.504 us|}
1) + 10.560 us | }
1) + 66.048 us |}
1) |.__timer_interrupt() {
1) | .hrtimer_interrupt() {
1) 0.448 us|._raw_spin_lock();
1) |.ktime_get_update_offsets_now() {
1) 0.256 us| .timebase_read();
1) 5.760 us|}
1) |.__hrtimer_run_queues() {
1) 0.960 us| .__remove_hrtimer();
1) | .tick_sched_timer() {
1) |.ktime_get() {
1) 0.320 us| .timebase_read();
1) 5.888 us|}
1) |.tick_sched_do_timer() {
1) | .tick_do_update_jiffies64.part.14() {
1) 0.384 us|._raw_spin_lock();
1) |.do_timer() {
1) 0.640 us| .calc_global_load();
1) 5.632 us|}
1) |.update_wall_time() {
1) 0.576 us| ._raw_spin_lock_irqsave();
1) 0.192 us| .timebase_read();
1) 0.192 us| .ntp_tick_length();
1) 0.256 us| .ntp_tick_length();
1) 0.192 us| .ntp_tick_length();
1) | .timekeeping_update() {
1) 0.192 us|.ntp_get_next_leap();
1) 1.600 us|.update_vsyscall_old();
1) |.raw_notifier_call_chain() {
1) 0.768 us| .notifier_call_chain();
1) 5.760 us|}
1) 0.768 us|.update_fast_timekeeper();
1) 0.384 us|.update_fast_timekeeper();
1) + 34.304 us |
Re: [PATCH 1/3] cxl: Re-factor cxl_pci_afu_read_err_buffer()
Le 14/03/2017 à 05:06, Vaibhav Jain a écrit :
This patch moves,renames and re-factors the function
afu_pci_afu_err_buffer(). The function is now moved to native.c from
pci.c and renamed as native_afu_read_err_buffer().
Also the ability of copying data from h/w enforcing 4/8 byte aligned
access is useful and better shared across other functions. So this
patch moves the core logic of existing cxl_pci_afu_read_err_buffer()
to a new function named __aligned_memcpy().The new implementation of
native_afu_read_err_buffer() is simply a call to __aligned_memcpy()
with appropriate actual parameters.
Signed-off-by: Vaibhav Jain
---
Acked-by: Frederic Barrat
drivers/misc/cxl/cxl.h| 3 ---
drivers/misc/cxl/native.c | 56 ++-
drivers/misc/cxl/pci.c| 44 -
3 files changed, 55 insertions(+), 48 deletions(-)
diff --git a/drivers/misc/cxl/cxl.h b/drivers/misc/cxl/cxl.h
index 79e60ec..ef683b7 100644
--- a/drivers/misc/cxl/cxl.h
+++ b/drivers/misc/cxl/cxl.h
@@ -739,9 +739,6 @@ static inline u64 cxl_p2n_read(struct cxl_afu *afu,
cxl_p2n_reg_t reg)
return ~0ULL;
}
-ssize_t cxl_pci_afu_read_err_buffer(struct cxl_afu *afu, char *buf,
- loff_t off, size_t count);
-
/* Internal functions wrapped in cxl_base to allow PHB to call them */
bool _cxl_pci_associate_default_context(struct pci_dev *dev, struct cxl_afu
*afu);
void _cxl_pci_disable_device(struct pci_dev *dev);
diff --git a/drivers/misc/cxl/native.c b/drivers/misc/cxl/native.c
index 7ae7105..20d3df6 100644
--- a/drivers/misc/cxl/native.c
+++ b/drivers/misc/cxl/native.c
@@ -1276,6 +1276,60 @@ static int native_afu_cr_write8(struct cxl_afu *afu, int
cr, u64 off, u8 in)
return rc;
}
+#define ERR_BUFF_MAX_COPY_SIZE PAGE_SIZE
+
+/*
+ * __aligned_memcpy:
+ * Copies count or max_read bytes (whichever is smaller) from src to dst buffer
+ * starting at offset off in src buffer. This specialized implementation of
+ * memcpy_fromio is needed as capi h/w only supports 4/8 bytes aligned access.
+ * So in case the requested offset/count arent 8 byte aligned the function uses
+ * a bounce buffer which can be max ERR_BUFF_MAX_COPY_SIZE == PAGE_SIZE
+ */
+static ssize_t __aligned_memcpy(void *dst, void __iomem *src, loff_t off,
+ size_t count, size_t max_read)
+{
+ loff_t aligned_start, aligned_end;
+ size_t aligned_length;
+ void *tbuf;
+
+ if (count == 0 || off < 0 || (size_t)off >= max_read)
+ return 0;
+
+ /* calculate aligned read window */
+ count = min((size_t)(max_read - off), count);
+ aligned_start = round_down(off, 8);
+ aligned_end = round_up(off + count, 8);
+ aligned_length = aligned_end - aligned_start;
+
+ /* max we can copy in one read is PAGE_SIZE */
+ if (aligned_length > ERR_BUFF_MAX_COPY_SIZE) {
+ aligned_length = ERR_BUFF_MAX_COPY_SIZE;
+ count = ERR_BUFF_MAX_COPY_SIZE - (off & 0x7);
+ }
+
+ /* use bounce buffer for copy */
+ tbuf = (void *)__get_free_page(GFP_TEMPORARY);
+ if (!tbuf)
+ return -ENOMEM;
+
+ /* perform aligned read from the mmio region */
+ memcpy_fromio(tbuf, src + aligned_start, aligned_length);
+ memcpy(dst, tbuf + (off & 0x7), count);
+
+ free_page((unsigned long)tbuf);
+
+ return count;
+}
+
+static ssize_t native_afu_read_err_buffer(struct cxl_afu *afu, char *buf,
+ loff_t off, size_t count)
+{
+ void __iomem *ebuf = afu->native->afu_desc_mmio + afu->eb_offset;
+
+ return __aligned_memcpy(buf, ebuf, off, count, afu->eb_len);
+}
+
const struct cxl_backend_ops cxl_native_ops = {
.module = THIS_MODULE,
.adapter_reset = cxl_pci_reset,
@@ -1294,7 +1348,7 @@ const struct cxl_backend_ops cxl_native_ops = {
.support_attributes = native_support_attributes,
.link_ok = cxl_adapter_link_ok,
.release_afu = cxl_pci_release_afu,
- .afu_read_err_buffer = cxl_pci_afu_read_err_buffer,
+ .afu_read_err_buffer = native_afu_read_err_buffer,
.afu_check_and_enable = native_afu_check_and_enable,
.afu_activate_mode = native_afu_activate_mode,
.afu_deactivate_mode = native_afu_deactivate_mode,
diff --git a/drivers/misc/cxl/pci.c b/drivers/misc/cxl/pci.c
index 91f6459..541dc9a 100644
--- a/drivers/misc/cxl/pci.c
+++ b/drivers/misc/cxl/pci.c
@@ -1051,50 +1051,6 @@ static int sanitise_afu_regs(struct cxl_afu *afu)
return 0;
}
-#define ERR_BUFF_MAX_COPY_SIZE PAGE_SIZE
-/*
- * afu_eb_read:
- * Called from sysfs and reads the afu error info buffer. The h/w only supports
- * 4/8 bytes aligned access. So in case the requested offset/count arent 8 byte
- * aligned the function uses a bounce buffer which can be max PAGE_SIZE.
- */
-ssize_t cxl_pci_afu_read_err_buffer(struct cxl_afu *afu, char *b
Re: [PATCH 2/3] cxl: Introduce afu_desc sysfs attribute
Hi Vaibhav,
There's one thing bugging me here, see below
Le 14/03/2017 à 05:06, Vaibhav Jain a écrit :
This patch introduces a new afu sysfs attribute named afu_desc. This
binary attribute provides access to raw contents of the afu descriptor
to user-space. Direct access to afu descriptor is useful for libcxl
that can use it to determine if the CXL card has been fenced or
provide application access to afu attributes beyond one defined in
CAIA.
We introduce three new backend-ops:
* afu_desc_size(): Return the size in bytes of the afu descriptor.
* afu_desc_read(): Copy into a provided buffer contents of afu
descriptor starting at specific offset.
* afu_desc_mmap(): Memory map the afu descriptor to the given
vm_area_struct.
If afu_desc_size() > 0 the afu_desc attribute gets created for the AFU.
The bin_attribute callbacks route the calls to corresponding cxl backend
implementation.
Signed-off-by: Vaibhav Jain
---
Documentation/ABI/testing/sysfs-class-cxl | 9 +++
drivers/misc/cxl/cxl.h| 9 +++
drivers/misc/cxl/sysfs.c | 45 +++
3 files changed, 63 insertions(+)
diff --git a/Documentation/ABI/testing/sysfs-class-cxl
b/Documentation/ABI/testing/sysfs-class-cxl
index 640f65e..9ac84c4 100644
--- a/Documentation/ABI/testing/sysfs-class-cxl
+++ b/Documentation/ABI/testing/sysfs-class-cxl
@@ -6,6 +6,15 @@ Example: The real path of the attribute
/sys/class/cxl/afu0.0s/irqs_max is
Slave contexts (eg. /sys/class/cxl/afu0.0s):
+What: /sys/class/cxl//afu_desc
+Date: March 2016
+Contact:linuxppc-dev@lists.ozlabs.org
+Description:read only
+AFU Descriptor contents. The contents of this file are
+ binary contents of the AFU descriptor. LIBCXL library can
+ use this file to read afu descriptor and in some special cases
+ determine if the cxl card has been fenced.
+
What: /sys/class/cxl//afu_err_buf
Date: September 2014
Contact:linuxppc-dev@lists.ozlabs.org
diff --git a/drivers/misc/cxl/cxl.h b/drivers/misc/cxl/cxl.h
index ef683b7..1c43d06 100644
--- a/drivers/misc/cxl/cxl.h
+++ b/drivers/misc/cxl/cxl.h
@@ -426,6 +426,9 @@ struct cxl_afu {
u64 eb_len, eb_offset;
struct bin_attribute attr_eb;
+ /* Afu descriptor */
+ struct bin_attribute attr_afud;
+
/* pointer to the vphb */
struct pci_controller *phb;
@@ -995,6 +998,12 @@ struct cxl_backend_ops {
int (*afu_cr_write16)(struct cxl_afu *afu, int cr_idx, u64 offset, u16
val);
int (*afu_cr_write32)(struct cxl_afu *afu, int cr_idx, u64 offset, u32
val);
ssize_t (*read_adapter_vpd)(struct cxl *adapter, void *buf, size_t
count);
+ /* Access to AFU descriptor */
+ ssize_t (*afu_desc_size)(struct cxl_afu *afu);
+ ssize_t (*afu_desc_read)(struct cxl_afu *afu, char *buf, loff_t off,
+size_t count);
+ int (*afu_desc_mmap)(struct cxl_afu *afu, struct file *filp,
+struct vm_area_struct *vma);
};
extern const struct cxl_backend_ops cxl_native_ops;
extern const struct cxl_backend_ops cxl_guest_ops;
diff --git a/drivers/misc/cxl/sysfs.c b/drivers/misc/cxl/sysfs.c
index a8b6d6a..fff3468 100644
--- a/drivers/misc/cxl/sysfs.c
+++ b/drivers/misc/cxl/sysfs.c
@@ -426,6 +426,26 @@ static ssize_t afu_eb_read(struct file *filp, struct
kobject *kobj,
return cxl_ops->afu_read_err_buffer(afu, buf, off, count);
}
+static ssize_t afu_desc_read(struct file *filp, struct kobject *kobj,
+struct bin_attribute *bin_attr, char *buf,
+loff_t off, size_t count)
+{
+ struct cxl_afu *afu = to_cxl_afu(kobj_to_dev(kobj));
+
+ return cxl_ops->afu_desc_read ?
+ cxl_ops->afu_desc_read(afu, buf, off, count) : -EIO;
+}
+
+static int afu_desc_mmap(struct file *filp, struct kobject *kobj,
+struct bin_attribute *attr, struct vm_area_struct *vma)
+{
+ struct cxl_afu *afu = to_cxl_afu(kobj_to_dev(kobj));
+
+ return cxl_ops->afu_desc_mmap ?
+ cxl_ops->afu_desc_mmap(afu, filp, vma) : -EINVAL;
+}
+
+
static struct device_attribute afu_attrs[] = {
__ATTR_RO(mmio_size),
__ATTR_RO(irqs_min),
@@ -625,6 +645,9 @@ void cxl_sysfs_afu_remove(struct cxl_afu *afu)
struct afu_config_record *cr, *tmp;
int i;
+ if (afu->attr_afud.size > 0)
+ device_remove_bin_file(&afu->dev, &afu->attr_afud);
+
/* remove the err buffer bin attribute */
if (afu->eb_len)
device_remove_bin_file(&afu->dev, &afu->attr_eb);
@@ -686,6 +709,28 @@ int cxl_sysfs_afu_add(struct cxl_afu *afu)
list_add(&cr->list, &afu->crs);
}
+ /* Create the sysfs binattr for afu-descriptor */
+ afu->attr_afud.size = cxl_ops->afu_desc_size ?
+
Re: [PATCH kernel] KVM: PPC: Add MMIO emulation for stdx (store doubleword indexed)
On 17/03/17 19:31, Alexey Kardashevskiy wrote: > This adds missing stdx emulation which allow Mellanox driver from > recent kernels work when MMIO emulation is enforced in the userspace. btw what would its load counterpart? Load Doubleword Indexed - ldx RT,RA,RB? > > Signed-off-by: Alexey Kardashevskiy > --- > arch/powerpc/include/asm/ppc-opcode.h | 1 + > arch/powerpc/kvm/emulate_loadstore.c | 6 ++ > 2 files changed, 7 insertions(+) > > diff --git a/arch/powerpc/include/asm/ppc-opcode.h > b/arch/powerpc/include/asm/ppc-opcode.h > index e7d6d86563ee..ca1bbe49590b 100644 > --- a/arch/powerpc/include/asm/ppc-opcode.h > +++ b/arch/powerpc/include/asm/ppc-opcode.h > @@ -92,6 +92,7 @@ > #define OP_31_XOP_TRAP_64 68 > #define OP_31_XOP_DCBF 86 > #define OP_31_XOP_LBZX 87 > +#define OP_31_XOP_STDX 149 > #define OP_31_XOP_STWX 151 > #define OP_31_XOP_STBX 215 > #define OP_31_XOP_LBZUX 119 > diff --git a/arch/powerpc/kvm/emulate_loadstore.c > b/arch/powerpc/kvm/emulate_loadstore.c > index 6d3c0ee1d744..9fdbeb8ea86c 100644 > --- a/arch/powerpc/kvm/emulate_loadstore.c > +++ b/arch/powerpc/kvm/emulate_loadstore.c > @@ -82,6 +82,12 @@ int kvmppc_emulate_loadstore(struct kvm_vcpu *vcpu) > kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed); > break; > > + case OP_31_XOP_STDX: > + emulated = kvmppc_handle_store(run, vcpu, > +kvmppc_get_gpr(vcpu, rs), > + 8, 1); > + break; > + > case OP_31_XOP_STWX: > emulated = kvmppc_handle_store(run, vcpu, > kvmppc_get_gpr(vcpu, rs), > -- Alexey
[PATCH] powerpc/pasemi, cbe: Do not process decremeter or external wakeup from powersave
Nicholas Piggin writes: > Hi, > > I would like to start using a dedicated stack for system reset interrupt > and treat it as a Linux nmi, which makes it tricky to call complex > interrupt handlers directly from the system reset trap handler. > > So I would like to remove the decrementer and external handler calls from > Cell and Pasemi platforms' system reset handler. I think we can just > remove them if they can be handled when they re-fire as normal interrupts? > At the moment I don't have environments set up to test if this works. It works fine with my AmigaOne X1000. (Nemo board with a P.A. Semi PA6T-1682M CPU) -- Christian
Re: [PATCH v3 02/10] Move GET_FIELD/SET_FIELD to vas.h
On Thu, Mar 16, 2017 at 11:33 PM, Sukadev Bhattiprolu
wrote:
> Move the GET_FIELD and SET_FIELD macros to vas.h as VAS and other
> users of VAS, including NX-842 can use those macros.
>
> There is a lot of related code between the VAS/NX kernel drivers
> and skiboot. For consistency switch the order of parameters in
> SET_FIELD to match the order in skiboot.
>
> Signed-off-by: Sukadev Bhattiprolu
Reviewed-by: Dan Streetman
also, can you change the MAINTAINERS file owner of the IBM Power 842
accelerator to yourself, or someone else at IBM? I no longer have
access to any of the ppc hardware, so it hardly makes sense for me to
remain the maintainer of it.
> ---
>
> Changelog[v3]
> - Fix order of parameters in nx-842 driver.
> ---
> arch/powerpc/include/asm/vas.h | 8 +++-
> drivers/crypto/nx/nx-842-powernv.c | 7 ---
> drivers/crypto/nx/nx-842.h | 5 -
> 3 files changed, 11 insertions(+), 9 deletions(-)
>
> diff --git a/arch/powerpc/include/asm/vas.h b/arch/powerpc/include/asm/vas.h
> index 6d35ce6..184eeb2 100644
> --- a/arch/powerpc/include/asm/vas.h
> +++ b/arch/powerpc/include/asm/vas.h
> @@ -37,7 +37,13 @@ enum vas_cop_type {
> VAS_COP_TYPE_MAX,
> };
>
> +/*
> + * Get/Set bit fields
> + */
> +#define GET_FIELD(m, v)(((v) & (m)) >> MASK_LSH(m))
> +#define MASK_LSH(m)(__builtin_ffsl(m) - 1)
> +#define SET_FIELD(m, v, val) \
> + (((v) & ~(m)) | typeof(v))(val)) << MASK_LSH(m)) & (m)))
>
> #endif /* __KERNEL__ */
> -
> #endif
> diff --git a/drivers/crypto/nx/nx-842-powernv.c
> b/drivers/crypto/nx/nx-842-powernv.c
> index 1710f80..3abb045 100644
> --- a/drivers/crypto/nx/nx-842-powernv.c
> +++ b/drivers/crypto/nx/nx-842-powernv.c
> @@ -22,6 +22,7 @@
>
> #include
> #include
> +#include
>
> MODULE_LICENSE("GPL");
> MODULE_AUTHOR("Dan Streetman ");
> @@ -424,9 +425,9 @@ static int nx842_powernv_function(const unsigned char
> *in, unsigned int inlen,
>
> /* set up CCW */
> ccw = 0;
> - ccw = SET_FIELD(ccw, CCW_CT, nx842_ct);
> - ccw = SET_FIELD(ccw, CCW_CI_842, 0); /* use 0 for hw auto-selection */
> - ccw = SET_FIELD(ccw, CCW_FC_842, fc);
> + ccw = SET_FIELD(CCW_CT, ccw, nx842_ct);
> + ccw = SET_FIELD(CCW_CI_842, ccw, 0); /* use 0 for hw auto-selection */
> + ccw = SET_FIELD(CCW_FC_842, ccw, fc);
>
> /* set up CRB's CSB addr */
> csb_addr = nx842_get_pa(csb) & CRB_CSB_ADDRESS;
> diff --git a/drivers/crypto/nx/nx-842.h b/drivers/crypto/nx/nx-842.h
> index a4eee3b..30929bd 100644
> --- a/drivers/crypto/nx/nx-842.h
> +++ b/drivers/crypto/nx/nx-842.h
> @@ -100,11 +100,6 @@ static inline unsigned long nx842_get_pa(void *addr)
> return page_to_phys(vmalloc_to_page(addr)) + offset_in_page(addr);
> }
>
> -/* Get/Set bit fields */
> -#define MASK_LSH(m)(__builtin_ffsl(m) - 1)
> -#define GET_FIELD(v, m)(((v) & (m)) >> MASK_LSH(m))
> -#define SET_FIELD(v, m, val) (((v) & ~(m)) | (((val) << MASK_LSH(m)) &
> (m)))
> -
> /**
> * This provides the driver's constraints. Different nx842 implementations
> * may have varying requirements. The constraints are:
> --
> 2.7.4
>
[PATCH] powerpc/powernv/cpuidle: Pass correct drv->cpumask for registration
drv->cpumask defaults to cpu_possible_mask in __cpuidle_driver_init(). This breaks cpuidle on powernv where sysfs files are not created for cpus in cpu_possible_mask that cannot be hot-added. Trying cpuidle_register_device() on cpu without sysfs node will cause crash like: cpu 0xf: Vector: 380 (Data SLB Access) at [c00ff1503490] pc: c022c8bc: string+0x34/0x60 lr: c022ed78: vsnprintf+0x284/0x42c sp: c00ff1503710 msr: 90009033 dar: 60006000 current = 0xc00ff148 paca= 0xcfe82d00 softe: 0irq_happened: 0x01 pid = 1, comm = swapper/8 Linux version 4.11.0-rc2 (sv@sagarika) (gcc version 4.9.4 (Buildroot 2017.02-4-gc28573e) ) #15 SMP Fri Mar 17 19:32:02 IST 2017 enter ? for help [link register ] c022ed78 vsnprintf+0x284/0x42c [c00ff1503710] c022ebb8 vsnprintf+0xc4/0x42c (unreliable) [c00ff1503800] c022ef40 vscnprintf+0x20/0x44 [c00ff1503830] c00ab61c vprintk_emit+0x94/0x2cc [c00ff15038a0] c00acc9c vprintk_func+0x60/0x74 [c00ff15038c0] c0619694 printk+0x38/0x4c [c00ff15038e0] c0224950 kobject_get+0x40/0x60 [c00ff1503950] c022507c kobject_add_internal+0x60/0x2c4 [c00ff15039e0] c0225350 kobject_init_and_add+0x70/0x78 [c00ff1503a60] c053c288 cpuidle_add_sysfs+0x9c/0xe0 [c00ff1503ae0] c053aeac cpuidle_register_device+0xd4/0x12c [c00ff1503b30] c053b108 cpuidle_register+0x98/0xcc [c00ff1503bc0] c085eaf0 powernv_processor_idle_init+0x140/0x1e0 [c00ff1503c60] c000cd60 do_one_initcall+0xc0/0x15c [c00ff1503d20] c0833e84 kernel_init_freeable+0x1a0/0x25c [c00ff1503dc0] c000d478 kernel_init+0x24/0x12c [c00ff1503e30] c000b564 ret_from_kernel_thread+0x5c/0x78 This patch fixes the issue by passing correct cpumask from powernv-cpuidle driver. Signed-off-by: Vaidyanathan Srinivasan --- drivers/cpuidle/cpuidle-powernv.c | 22 ++ 1 file changed, 22 insertions(+) diff --git a/drivers/cpuidle/cpuidle-powernv.c b/drivers/cpuidle/cpuidle-powernv.c index 3705930..e7a8c2a 100644 --- a/drivers/cpuidle/cpuidle-powernv.c +++ b/drivers/cpuidle/cpuidle-powernv.c @@ -175,6 +175,28 @@ static int powernv_cpuidle_driver_init(void) drv->state_count += 1; } + /* +* On PowerNV platform cpu_present may be less that cpu_possible +* in cases where firmware detects the cpu, but it is not available +* for OS. Such CPUs are not hotplugable at runtime on PowerNV +* platform and hence sysfs files are not created for those. +* Generic topology_init() would skip creating sysfs directories +* for cpus that are not present and not hotplugable later at +* runtime. +* +* drv->cpumask defaults to cpu_possible_mask in __cpuidle_driver_init(). +* This breaks cpuidle on powernv where sysfs files are not created for +* cpus in cpu_possible_mask that cannot be hot-added. +* +* Hence at runtime sysfs nodes are present for cpus only in +* cpu_present_mask. Trying cpuidle_register_device() on cpu without +* sysfs node is incorrect. +* +* Hence pass correct cpu mask to generic cpuidle driver. +*/ + + drv->cpumask = (struct cpumask *)cpu_present_mask; + return 0; } -- 2.9.3
[patch] KVM: PPC: Book3S HV: check for kmalloc errors in ioctl
kzalloc() won't actually fail because sizeof(*resize) is small, but
static checkers complain.
Signed-off-by: Dan Carpenter
diff --git a/arch/powerpc/kvm/book3s_64_mmu_hv.c
b/arch/powerpc/kvm/book3s_64_mmu_hv.c
index 8c68145ba1bd..710e491206ed 100644
--- a/arch/powerpc/kvm/book3s_64_mmu_hv.c
+++ b/arch/powerpc/kvm/book3s_64_mmu_hv.c
@@ -1487,6 +1487,10 @@ long kvm_vm_ioctl_resize_hpt_prepare(struct kvm *kvm,
/* start new resize */
resize = kzalloc(sizeof(*resize), GFP_KERNEL);
+ if (!resize) {
+ ret = -ENOMEM;
+ goto out;
+ }
resize->order = shift;
resize->kvm = kvm;
INIT_WORK(&resize->work, resize_hpt_prepare_work);
[PATCH] powerpc: fix /proc/self/stack
For the current task, the kernel stack would only tell the last time the
process was rescheduled, if ever. Use the current stack pointer for the
current task.
This is also consistent with some other architectures.
Signed-off-by: Thadeu Lima de Souza Cascardo
---
arch/powerpc/kernel/stacktrace.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/kernel/stacktrace.c b/arch/powerpc/kernel/stacktrace.c
index 6671195..2446066 100644
--- a/arch/powerpc/kernel/stacktrace.c
+++ b/arch/powerpc/kernel/stacktrace.c
@@ -59,7 +59,12 @@ EXPORT_SYMBOL_GPL(save_stack_trace);
void save_stack_trace_tsk(struct task_struct *tsk, struct stack_trace *trace)
{
- save_context_stack(trace, tsk->thread.ksp, tsk, 0);
+ unsigned long sp = tsk->thread.ksp;
+
+ if (tsk == current)
+ sp = current_stack_pointer();
+
+ save_context_stack(trace, sp, tsk, 0);
}
EXPORT_SYMBOL_GPL(save_stack_trace_tsk);
--
2.9.3
Re: [PATCH v3 7/7] mmc: Only descend into mmc directory when CONFIG_MMC is set
Hi Andrew, [auto build test ERROR on linus/master] [also build test ERROR on v4.11-rc2 next-20170310] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url: https://github.com/0day-ci/linux/commits/Andrew-F-Davis/Remove-unneeded-build-directory-traversals/20170318-040719 config: x86_64-rhel (attached as .config) compiler: gcc-6 (Debian 6.2.0-3) 6.2.0 20160901 reproduce: # save the attached .config to linux build tree make ARCH=x86_64 All errors (new ones prefixed by >>): >> ERROR: "sdhci_pci_get_data" [drivers/mmc/host/sdhci-pci.ko] undefined! >> ERROR: "sdhci_pci_spt_drive_strength" [drivers/mmc/host/sdhci-pci.ko] >> undefined! --- 0-DAY kernel test infrastructureOpen Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation .config.gz Description: application/gzip
Re: [PATCH v3 7/7] mmc: Only descend into mmc directory when CONFIG_MMC is set
Hi Andrew, [auto build test ERROR on linus/master] [also build test ERROR on v4.11-rc2 next-20170310] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url: https://github.com/0day-ci/linux/commits/Andrew-F-Davis/Remove-unneeded-build-directory-traversals/20170318-040719 config: x86_64-allmodconfig (attached as .config) compiler: gcc-6 (Debian 6.2.0-3) 6.2.0 20160901 reproduce: # save the attached .config to linux build tree make ARCH=x86_64 All errors (new ones prefixed by >>): arch/x86/built-in.o: In function `mrfld_sd_init': >> platform_mrfld_sd.c:(.init.text+0x397d5): undefined reference to >> `sdhci_pci_get_data' platform_mrfld_sd.c:(.init.text+0x397e3): undefined reference to `sdhci_pci_get_data' --- 0-DAY kernel test infrastructureOpen Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation .config.gz Description: application/gzip
Re: [PATCH] powerpc/powernv/cpuidle: Pass correct drv->cpumask for registration
Vaidy, Thanks for fixing this. > drv->cpumask defaults to cpu_possible_mask in __cpuidle_driver_init(). > This breaks cpuidle on powernv where sysfs files are not created for > cpus in cpu_possible_mask that cannot be hot-added. I think I prefer the longer description below than this. > This patch fixes the issue by passing correct cpumask from > powernv-cpuidle driver. Any reason the correct fix isn't to change __cpuidle_driver_init() to use present mask? Seems like any arch where present < possible is going to hit this. > Signed-off-by: Vaidyanathan Srinivasan Can we CC stable too. This breaks at least v4.10. > --- > drivers/cpuidle/cpuidle-powernv.c | 22 ++ > 1 file changed, 22 insertions(+) >
Re: [PATCH] powerpc/powernv/cpuidle: Pass correct drv->cpumask for registration
* Michael Neuling [2017-03-18 16:28:02]: > Vaidy, > > Thanks for fixing this. > > > drv->cpumask defaults to cpu_possible_mask in __cpuidle_driver_init(). > > This breaks cpuidle on powernv where sysfs files are not created for > > cpus in cpu_possible_mask that cannot be hot-added. > > I think I prefer the longer description below than this. [PATCH] powerpc/powernv/cpuidle: Pass correct drv->cpumask for drv->cpumask defaults to cpu_possible_mask in __cpuidle_driver_init(). This breaks cpuidle on powernv where sysfs files are not created for cpus in cpu_possible_mask that cannot be hot-added. On powernv platform cpu_present could be less than cpu_possible in cases where firmware detects the cpu, but it is not available for OS. Such cpus are not hotplugable at runtime on powernv and hence we skip creating sysfs files for these cpus. Trying cpuidle_register_device() on cpu without sysfs node will cause crash like: cpu 0xf: Vector: 380 (Data SLB Access) at [c00ff1503490] pc: c022c8bc: string+0x34/0x60 lr: c022ed78: vsnprintf+0x284/0x42c sp: c00ff1503710 msr: 90009033 dar: 60006000 current = 0xc00ff148 paca= 0xcfe82d00 softe: 0irq_happened: 0x01 pid = 1, comm = swapper/8 Linux version 4.11.0-rc2 (sv@sagarika) (gcc version 4.9.4 (Buildroot 2017.02-4-gc28573e) ) #15 SMP Fri Mar 17 19:32:02 IST 2017 enter ? for help [link register ] c022ed78 vsnprintf+0x284/0x42c [c00ff1503710] c022ebb8 vsnprintf+0xc4/0x42c (unreliable) [c00ff1503800] c022ef40 vscnprintf+0x20/0x44 [c00ff1503830] c00ab61c vprintk_emit+0x94/0x2cc [c00ff15038a0] c00acc9c vprintk_func+0x60/0x74 [c00ff15038c0] c0619694 printk+0x38/0x4c [c00ff15038e0] c0224950 kobject_get+0x40/0x60 [c00ff1503950] c022507c kobject_add_internal+0x60/0x2c4 [c00ff15039e0] c0225350 kobject_init_and_add+0x70/0x78 [c00ff1503a60] c053c288 cpuidle_add_sysfs+0x9c/0xe0 [c00ff1503ae0] c053aeac cpuidle_register_device+0xd4/0x12c [c00ff1503b30] c053b108 cpuidle_register+0x98/0xcc [c00ff1503bc0] c085eaf0 powernv_processor_idle_init+0x140/0x1e0 [c00ff1503c60] c000cd60 do_one_initcall+0xc0/0x15c [c00ff1503d20] c0833e84 kernel_init_freeable+0x1a0/0x25c [c00ff1503dc0] c000d478 kernel_init+0x24/0x12c [c00ff1503e30] c000b564 ret_from_kernel_thread+0x5c/0x78 This patch fixes the issue by passing correct cpumask from powernv-cpuidle driver. > > This patch fixes the issue by passing correct cpumask from > > powernv-cpuidle driver. > > Any reason the correct fix isn't to change __cpuidle_driver_init() to use > present mask? Seems like any arch where present < possible is going to hit > this. How to handle the sysfs nodes for cpus that are not in cpu_present mask is upto the arch/platform. During init, arch can choose to create sysfs nodes for cpu's that are not in present mask, which can be later hot-added and then onlined. In which case cpuidle driver should register for such cpus as well. The decision to allow a cpu to become available in cpu_present mask at runtime and handle the sysfs nodes are upto the arch/platform and not to be hard coded in generic driver. The generic cpuidle would like to register for all possible cpus if the arch driver does not override it. --Vaidy
