Re: [PATCH v5 0/4] powerpc patches for new Kconfig language
On Fri, 01 Jun 2018 23:22:27 +1000
Michael Ellerman wrote:
> Masahiro Yamada writes:
> > 2018-06-01 19:34 GMT+09:00 Michael Ellerman :
> ...
> >
> > Could you update your branch, please?
>
> Done.
>
> I've only pushed the first three patches this time, to avoid any
> confusion. Hopefully :)
>
> The top commit is:
>
> 1421dc6d4829 ("powerpc/kbuild: Use flags variables rather than overriding
> LD/CC/AS")
>
>
> For the fourth one you're welcome to add my ack when you apply it:
>
> Acked-by: Michael Ellerman
>
> > Then, I will re-pull the new one.
>
> Thanks! Sorry this took a while to get right, next time we'll be much
> better at it ;)
Thank you both for sorting out my mess.
Thanks,
Nick
[PATCH 08/11] macintosh/via-pmu: Replace via-pmu68k driver with via-pmu driver
Now that the PowerMac via-pmu driver supports m68k PowerBooks,
switch over to that driver and remove the via-pmu68k driver.
Don't call pmu_shutdown() or pmu_restart() on early PowerBooks:
the PMU device found in these PowerBooks isn't supported.
Cc: Geert Uytterhoeven
Tested-by: Stan Johnson
Signed-off-by: Finn Thain
---
arch/m68k/configs/mac_defconfig | 2 +-
arch/m68k/configs/multi_defconfig | 2 +-
arch/m68k/mac/config.c| 2 +-
arch/m68k/mac/misc.c | 54 +--
drivers/macintosh/Kconfig | 13 +-
drivers/macintosh/Makefile| 1 -
drivers/macintosh/adb.c | 2 +-
drivers/macintosh/via-pmu68k.c| 850 --
include/uapi/linux/pmu.h | 2 -
9 files changed, 15 insertions(+), 913 deletions(-)
delete mode 100644 drivers/macintosh/via-pmu68k.c
diff --git a/arch/m68k/configs/mac_defconfig b/arch/m68k/configs/mac_defconfig
index efbcaffa30ed..6b2ce72c5c9f 100644
--- a/arch/m68k/configs/mac_defconfig
+++ b/arch/m68k/configs/mac_defconfig
@@ -363,7 +363,7 @@ CONFIG_TCM_PSCSI=m
CONFIG_ADB=y
CONFIG_ADB_MACII=y
CONFIG_ADB_IOP=y
-CONFIG_ADB_PMU68K=y
+CONFIG_ADB_PMU=y
CONFIG_ADB_CUDA=y
CONFIG_INPUT_ADBHID=y
CONFIG_MAC_EMUMOUSEBTN=y
diff --git a/arch/m68k/configs/multi_defconfig
b/arch/m68k/configs/multi_defconfig
index e78a205d266a..aa8e78987e83 100644
--- a/arch/m68k/configs/multi_defconfig
+++ b/arch/m68k/configs/multi_defconfig
@@ -396,7 +396,7 @@ CONFIG_TCM_PSCSI=m
CONFIG_ADB=y
CONFIG_ADB_MACII=y
CONFIG_ADB_IOP=y
-CONFIG_ADB_PMU68K=y
+CONFIG_ADB_PMU=y
CONFIG_ADB_CUDA=y
CONFIG_INPUT_ADBHID=y
CONFIG_MAC_EMUMOUSEBTN=y
diff --git a/arch/m68k/mac/config.c b/arch/m68k/mac/config.c
index 36086cceb537..7b8e706cef9b 100644
--- a/arch/m68k/mac/config.c
+++ b/arch/m68k/mac/config.c
@@ -891,7 +891,7 @@ static void __init mac_identify(void)
#ifdef CONFIG_ADB_CUDA
find_via_cuda();
#endif
-#ifdef CONFIG_ADB_PMU68K
+#ifdef CONFIG_ADB_PMU
find_via_pmu();
#endif
}
diff --git a/arch/m68k/mac/misc.c b/arch/m68k/mac/misc.c
index c68054361615..28090a44fa09 100644
--- a/arch/m68k/mac/misc.c
+++ b/arch/m68k/mac/misc.c
@@ -85,7 +85,7 @@ static void cuda_write_pram(int offset, __u8 data)
}
#endif /* CONFIG_ADB_CUDA */
-#ifdef CONFIG_ADB_PMU68K
+#ifdef CONFIG_ADB_PMU
static long pmu_read_time(void)
{
struct adb_request req;
@@ -136,7 +136,7 @@ static void pmu_write_pram(int offset, __u8 data)
while (!req.complete)
pmu_poll();
}
-#endif /* CONFIG_ADB_PMU68K */
+#endif /* CONFIG_ADB_PMU */
/*
* VIA PRAM/RTC access routines
@@ -367,38 +367,6 @@ static void cuda_shutdown(void)
}
#endif /* CONFIG_ADB_CUDA */
-#ifdef CONFIG_ADB_PMU68K
-
-void pmu_restart(void)
-{
- struct adb_request req;
- if (pmu_request(, NULL,
- 2, PMU_SET_INTR_MASK, PMU_INT_ADB|PMU_INT_TICK) < 0)
- return;
- while (!req.complete)
- pmu_poll();
- if (pmu_request(, NULL, 1, PMU_RESET) < 0)
- return;
- while (!req.complete)
- pmu_poll();
-}
-
-void pmu_shutdown(void)
-{
- struct adb_request req;
- if (pmu_request(, NULL,
- 2, PMU_SET_INTR_MASK, PMU_INT_ADB|PMU_INT_TICK) < 0)
- return;
- while (!req.complete)
- pmu_poll();
- if (pmu_request(, NULL, 5, PMU_SHUTDOWN, 'M', 'A', 'T', 'T') < 0)
- return;
- while (!req.complete)
- pmu_poll();
-}
-
-#endif
-
/*
*---
* Below this point are the generic routines; they'll dispatch to the
@@ -423,7 +391,7 @@ void mac_pram_read(int offset, __u8 *buffer, int len)
func = cuda_read_pram;
break;
#endif
-#ifdef CONFIG_ADB_PMU68K
+#ifdef CONFIG_ADB_PMU
case MAC_ADB_PB2:
func = pmu_read_pram;
break;
@@ -453,7 +421,7 @@ void mac_pram_write(int offset, __u8 *buffer, int len)
func = cuda_write_pram;
break;
#endif
-#ifdef CONFIG_ADB_PMU68K
+#ifdef CONFIG_ADB_PMU
case MAC_ADB_PB2:
func = pmu_write_pram;
break;
@@ -477,9 +445,8 @@ void mac_poweroff(void)
macintosh_config->adb_type == MAC_ADB_CUDA) {
cuda_shutdown();
#endif
-#ifdef CONFIG_ADB_PMU68K
- } else if (macintosh_config->adb_type == MAC_ADB_PB1
- || macintosh_config->adb_type == MAC_ADB_PB2) {
+#ifdef CONFIG_ADB_PMU
+ } else if (macintosh_config->adb_type == MAC_ADB_PB2) {
pmu_shutdown();
#endif
}
@@ -519,9 +486,8 @@ void mac_reset(void)
macintosh_config->adb_type == MAC_ADB_CUDA) {
cuda_restart();
#endif
-#ifdef CONFIG_ADB_PMU68K
- } else if (macintosh_config->adb_type == MAC_ADB_PB1
- || macintosh_config->adb_type == MAC_ADB_PB2) {
+#ifdef
[PATCH 05/11] macintosh/via-pmu: Replace via pointer with via1 and via2 pointers
On most PowerPC Macs, the PMU driver uses the shift register and
IO port B from a single VIA chip.
On 68k and early PowerPC PowerBooks, the driver uses the shift register
from one VIA chip together with IO port B from another.
Replace via with via1 and via2 to accommodate this. For the
CONFIG_PPC_PMAC case, set via1 = via2 so there is no change.
Tested-by: Stan Johnson
Signed-off-by: Finn Thain
---
drivers/macintosh/via-pmu.c | 142 +---
1 file changed, 69 insertions(+), 73 deletions(-)
diff --git a/drivers/macintosh/via-pmu.c b/drivers/macintosh/via-pmu.c
index 7fba3c88991d..f1c190c02a9c 100644
--- a/drivers/macintosh/via-pmu.c
+++ b/drivers/macintosh/via-pmu.c
@@ -76,7 +76,6 @@
#define BATTERY_POLLING_COUNT 2
static DEFINE_MUTEX(pmu_info_proc_mutex);
-static volatile unsigned char __iomem *via;
/* VIA registers - spaced 0x200 bytes apart */
#define RS 0x200 /* skip between registers */
@@ -145,6 +144,8 @@ static struct device_node *vias;
static int pmu_kind = PMU_UNKNOWN;
static int pmu_fully_inited;
static int pmu_has_adb;
+static volatile unsigned char __iomem *via1;
+static volatile unsigned char __iomem *via2;
static struct device_node *gpio_node;
static unsigned char __iomem *gpio_reg;
static int gpio_irq = 0;
@@ -340,14 +341,14 @@ int __init find_via_pmu(void)
} else
pmu_kind = PMU_UNKNOWN;
- via = ioremap(taddr, 0x2000);
- if (via == NULL) {
+ via1 = via2 = ioremap(taddr, 0x2000);
+ if (via1 == NULL) {
printk(KERN_ERR "via-pmu: Can't map address !\n");
goto fail_via_remap;
}
- out_8([IER], IER_CLR | 0x7f); /* disable all intrs */
- out_8([IFR], 0x7f); /* clear IFR */
+ out_8([IER], IER_CLR | 0x7f); /* disable all intrs */
+ out_8([IFR], 0x7f);/* clear IFR */
pmu_state = idle;
@@ -362,8 +363,8 @@ int __init find_via_pmu(void)
return 1;
fail_init:
- iounmap(via);
- via = NULL;
+ iounmap(via1);
+ via1 = via2 = NULL;
fail_via_remap:
iounmap(gpio_reg);
gpio_reg = NULL;
@@ -437,7 +438,7 @@ static int __init via_pmu_start(void)
}
/* Enable interrupts */
- out_8([IER], IER_SET | SR_INT | CB1_INT);
+ out_8([IER], IER_SET | SR_INT | CB1_INT);
pmu_fully_inited = 1;
@@ -533,8 +534,8 @@ init_pmu(void)
struct adb_request req;
/* Negate TREQ. Set TACK to input and TREQ to output. */
- out_8([B], in_8([B]) | TREQ);
- out_8([DIRB], (in_8([DIRB]) | TREQ) & ~TACK);
+ out_8([B], in_8([B]) | TREQ);
+ out_8([DIRB], (in_8([DIRB]) | TREQ) & ~TACK);
pmu_request(, NULL, 2, PMU_SET_INTR_MASK, pmu_intr_mask);
timeout = 10;
@@ -1174,7 +1175,7 @@ wait_for_ack(void)
* reported
*/
int timeout = 4000;
- while ((in_8([B]) & TACK) == 0) {
+ while ((in_8([B]) & TACK) == 0) {
if (--timeout < 0) {
printk(KERN_ERR "PMU not responding (!ack)\n");
return;
@@ -1188,23 +1189,19 @@ wait_for_ack(void)
static inline void
send_byte(int x)
{
- volatile unsigned char __iomem *v = via;
-
- out_8([ACR], in_8([ACR]) | SR_OUT | SR_EXT);
- out_8([SR], x);
- out_8([B], in_8([B]) & ~TREQ); /* assert TREQ */
- (void)in_8([B]);
+ out_8([ACR], in_8([ACR]) | SR_OUT | SR_EXT);
+ out_8([SR], x);
+ out_8([B], in_8([B]) & ~TREQ);/* assert TREQ */
+ (void)in_8([B]);
}
static inline void
recv_byte(void)
{
- volatile unsigned char __iomem *v = via;
-
- out_8([ACR], (in_8([ACR]) & ~SR_OUT) | SR_EXT);
- in_8([SR]); /* resets SR */
- out_8([B], in_8([B]) & ~TREQ);
- (void)in_8([B]);
+ out_8([ACR], (in_8([ACR]) & ~SR_OUT) | SR_EXT);
+ in_8([SR]);/* resets SR */
+ out_8([B], in_8([B]) & ~TREQ);
+ (void)in_8([B]);
}
static inline void
@@ -1307,7 +1304,7 @@ pmu_suspend(void)
if (!adb_int_pending && pmu_state == idle &&
!req_awaiting_reply) {
if (gpio_irq >= 0)
disable_irq_nosync(gpio_irq);
- out_8([IER], CB1_INT | IER_CLR);
+ out_8([IER], CB1_INT | IER_CLR);
spin_unlock_irqrestore(_lock, flags);
break;
}
@@ -1331,7 +1328,7 @@ pmu_resume(void)
adb_int_pending = 1;
if (gpio_irq >= 0)
enable_irq(gpio_irq);
- out_8([IER], CB1_INT | IER_SET);
+ out_8([IER], CB1_INT | IER_SET);
spin_unlock_irqrestore(_lock, flags);
pmu_poll();
}
@@ -1456,20 +1453,20 @@ pmu_sr_intr(void)
struct adb_request *req;
int bite = 0;
- if (in_8([B]) &
[PATCH 11/11] macintosh/via-pmu: Disambiguate interrupt statistics
Some of the event counters are overloaded which makes it very
difficult to interpret their values.
Counter 0 is supposed to report CB1 interrupts but it can also count
PMU_INT_WAITING_CHARGER events.
Counter 1 is supposed to report GPIO interrupts but it can also count
other events (depending upon the value of the PMU_INT_ADB bit).
Disambiguate these statistics with dedicated counters for GPIO and
CB1 interrupts.
Comments in the MkLinux source code say that the type 0 and type 1
interrupts are model-specific. Label them as "unknown".
This change to the contents of /proc/pmu/interrupts is by necessity
visible in userland. However, packages which interact with the PMU
(that is, pbbuttonsd, pmac-utils and pmud) don't open this file.
AFAIK, user software has no need to poll these counters.
Tested-by: Stan Johnson
Signed-off-by: Finn Thain
---
The file now looks like this,
0: 0 (Unknown interrupt (type 0))
1: 0 (Unknown interrupt (type 1))
2: 0 (PC-Card eject button)
3: 23 (Sound/Brightness button)
4: 74 (ADB message)
5: 0 (Battery state change)
6: 0 (Environment interrupt)
7:121 (Tick timer)
8: 0 (Ghost interrupt (zero len))
9: 1 (Empty interrupt (empty mask))
10: 2 (Max irqs in a row)
11:194 (Total CB1 triggered events)
12: 0 (Total GPIO1 triggered events)
rather than this,
0:194 (Total CB1 triggered events)
1: 0 (Total GPIO1 triggered events)
2: 0 (PC-Card eject button)
3: 23 (Sound/Brightness button)
4: 74 (ADB message)
5: 0 (Battery state change)
6: 0 (Environment interrupt)
7:121 (Tick timer)
8: 0 (Ghost interrupt (zero len))
9: 1 (Empty interrupt (empty mask))
10: 2 (Max irqs in a row)
If some parser exists for this file, and if this change is problematic,
we could increment the driver version number in /proc/pmu/info, to
correspond with the format change.
---
drivers/macintosh/via-pmu.c | 20
1 file changed, 12 insertions(+), 8 deletions(-)
diff --git a/drivers/macintosh/via-pmu.c b/drivers/macintosh/via-pmu.c
index 5c5ebad4e6ae..490bbcc42ce0 100644
--- a/drivers/macintosh/via-pmu.c
+++ b/drivers/macintosh/via-pmu.c
@@ -172,7 +172,9 @@ static int drop_interrupts;
static int option_lid_wakeup = 1;
#endif /* CONFIG_SUSPEND && CONFIG_PPC32 */
static unsigned long async_req_locks;
-static unsigned int pmu_irq_stats[11];
+
+#define NUM_IRQ_STATS 13
+static unsigned int pmu_irq_stats[NUM_IRQ_STATS];
static struct proc_dir_entry *proc_pmu_root;
static struct proc_dir_entry *proc_pmu_info;
@@ -884,9 +886,9 @@ static const struct file_operations pmu_info_proc_fops = {
static int pmu_irqstats_proc_show(struct seq_file *m, void *v)
{
int i;
- static const char *irq_names[] = {
- "Total CB1 triggered events",
- "Total GPIO1 triggered events",
+ static const char *irq_names[NUM_IRQ_STATS] = {
+ "Unknown interrupt (type 0)",
+ "Unknown interrupt (type 1)",
"PC-Card eject button",
"Sound/Brightness button",
"ADB message",
@@ -895,10 +897,12 @@ static int pmu_irqstats_proc_show(struct seq_file *m,
void *v)
"Tick timer",
"Ghost interrupt (zero len)",
"Empty interrupt (empty mask)",
- "Max irqs in a row"
+ "Max irqs in a row",
+ "Total CB1 triggered events",
+ "Total GPIO1 triggered events",
};
- for (i=0; i<11; i++) {
+ for (i = 0; i < NUM_IRQ_STATS; i++) {
seq_printf(m, " %2u: %10u (%s)\n",
i, pmu_irq_stats[i], irq_names[i]);
}
@@ -1655,7 +1659,7 @@ via_pmu_interrupt(int irq, void *arg)
}
if (intr & CB1_INT) {
adb_int_pending = 1;
- pmu_irq_stats[0]++;
+ pmu_irq_stats[11]++;
}
if (intr & SR_INT) {
req = pmu_sr_intr();
@@ -1742,7 +1746,7 @@ gpio1_interrupt(int irq, void *arg)
disable_irq_nosync(gpio_irq);
gpio_irq_enabled = 0;
}
- pmu_irq_stats[1]++;
+ pmu_irq_stats[12]++;
adb_int_pending = 1;
spin_unlock_irqrestore(_lock, flags);
via_pmu_interrupt(0, NULL);
--
2.16.1
[PATCH 10/11] macintosh/via-pmu: Clean up interrupt statistics
Replace an open-coded ffs() with the function call.
Simplify an if-else cascade using a switch statement.
Correct a typo and an indentation issue.
Tested-by: Stan Johnson
Signed-off-by: Finn Thain
---
drivers/macintosh/via-pmu.c | 35 ++-
1 file changed, 18 insertions(+), 17 deletions(-)
diff --git a/drivers/macintosh/via-pmu.c b/drivers/macintosh/via-pmu.c
index 3cbccd346997..5c5ebad4e6ae 100644
--- a/drivers/macintosh/via-pmu.c
+++ b/drivers/macintosh/via-pmu.c
@@ -1392,7 +1392,8 @@ pmu_resume(void)
static void
pmu_handle_data(unsigned char *data, int len)
{
- unsigned char ints, pirq;
+ unsigned char ints;
+ int idx;
int i = 0;
asleep = 0;
@@ -1414,25 +1415,24 @@ pmu_handle_data(unsigned char *data, int len)
ints &= ~(PMU_INT_ADB_AUTO | PMU_INT_AUTO_SRQ_POLL);
next:
-
if (ints == 0) {
if (i > pmu_irq_stats[10])
pmu_irq_stats[10] = i;
return;
}
-
- for (pirq = 0; pirq < 8; pirq++)
- if (ints & (1 << pirq))
- break;
- pmu_irq_stats[pirq]++;
i++;
- ints &= ~(1 << pirq);
+
+ idx = ffs(ints) - 1;
+ ints &= ~BIT(idx);
+
+ pmu_irq_stats[idx]++;
/* Note: for some reason, we get an interrupt with len=1,
* data[0]==0 after each normal ADB interrupt, at least
* on the Pismo. Still investigating... --BenH
*/
- if ((1 << pirq) & PMU_INT_ADB) {
+ switch (BIT(idx)) {
+ case PMU_INT_ADB:
if ((data[0] & PMU_INT_ADB_AUTO) == 0) {
struct adb_request *req = req_awaiting_reply;
if (req == 0) {
@@ -1470,25 +1470,25 @@ pmu_handle_data(unsigned char *data, int len)
adb_input(data+1, len-1, 1);
#endif /* CONFIG_ADB */
}
- }
+ break;
/* Sound/brightness button pressed */
- else if ((1 << pirq) & PMU_INT_SNDBRT) {
+ case PMU_INT_SNDBRT:
#ifdef CONFIG_PMAC_BACKLIGHT
if (len == 3)
pmac_backlight_set_legacy_brightness_pmu(data[1] >> 4);
#endif
- }
+ break;
/* Tick interrupt */
- else if ((1 << pirq) & PMU_INT_TICK) {
- /* Environement or tick interrupt, query batteries */
+ case PMU_INT_TICK:
+ /* Environment or tick interrupt, query batteries */
if (pmu_battery_count) {
if ((--query_batt_timer) == 0) {
query_battery_state();
query_batt_timer = BATTERY_POLLING_COUNT;
}
}
-}
- else if ((1 << pirq) & PMU_INT_ENVIRONMENT) {
+ break;
+ case PMU_INT_ENVIRONMENT:
if (pmu_battery_count)
query_battery_state();
pmu_pass_intr(data, len);
@@ -1498,7 +1498,8 @@ pmu_handle_data(unsigned char *data, int len)
via_pmu_event(PMU_EVT_POWER, !!(data[1]&8));
via_pmu_event(PMU_EVT_LID, data[1]&1);
}
- } else {
+ break;
+ default:
pmu_pass_intr(data, len);
}
goto next;
--
2.16.1
[PATCH 06/11] macintosh/via-pmu: Add support for m68k PowerBooks
Put #ifdefs around the Open Firmware, xmon, interrupt dispatch,
battery and suspend code. Add the necessary interrupt handling to
support m68k PowerBooks.
The pmu_kind value is available to userspace using the
PMU_IOC_GET_MODEL ioctl. It is not clear yet what hardware classes
are be needed to describe m68k PowerBook models, so pmu_kind is given
the provisional value PMU_UNKNOWN.
To find out about the hardware, user programs can use /proc/bootinfo
or /proc/hardware, or send the PMU_GET_VERSION command using /dev/adb.
Tested-by: Stan Johnson
Signed-off-by: Finn Thain
---
drivers/macintosh/Kconfig | 2 +-
drivers/macintosh/via-pmu.c | 101 +++-
2 files changed, 91 insertions(+), 12 deletions(-)
diff --git a/drivers/macintosh/Kconfig b/drivers/macintosh/Kconfig
index 97a420c11eed..9c6452b38c36 100644
--- a/drivers/macintosh/Kconfig
+++ b/drivers/macintosh/Kconfig
@@ -65,7 +65,7 @@ config ADB_CUDA
If unsure say Y.
config ADB_PMU
- bool "Support for PMU based PowerMacs"
+ bool "Support for PMU based PowerMacs and PowerBooks"
depends on PPC_PMAC
help
On PowerBooks, iBooks, and recent iMacs and Power Macintoshes, the
diff --git a/drivers/macintosh/via-pmu.c b/drivers/macintosh/via-pmu.c
index f1c190c02a9c..19a27ed49721 100644
--- a/drivers/macintosh/via-pmu.c
+++ b/drivers/macintosh/via-pmu.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Device driver for the via-pmu on Apple Powermacs.
+ * Device driver for the PMU in Apple PowerBooks and PowerMacs.
*
* The VIA (versatile interface adapter) interfaces to the PMU,
* a 6805 microprocessor core whose primary function is to control
@@ -49,20 +49,26 @@
#include
#include
#include
-#include
+#include
#include
#include
#include
#include
#include
+#ifdef CONFIG_PPC_PMAC
#include
#include
#include
-#include
+#include
#include
#include
#include
#include
+#else
+#include
+#include
+#include
+#endif
#include "via-pmu-event.h"
@@ -97,8 +103,13 @@ static DEFINE_MUTEX(pmu_info_proc_mutex);
#define ANH(15*RS) /* A-side data, no handshake */
/* Bits in B data register: both active low */
+#ifdef CONFIG_PPC_PMAC
#define TACK 0x08/* Transfer acknowledge (input) */
#define TREQ 0x10/* Transfer request (output) */
+#else
+#define TACK 0x02
+#define TREQ 0x04
+#endif
/* Bits in ACR */
#define SR_CTRL0x1c/* Shift register control bits
*/
@@ -140,13 +151,15 @@ static int data_index;
static int data_len;
static volatile int adb_int_pending;
static volatile int disable_poll;
-static struct device_node *vias;
static int pmu_kind = PMU_UNKNOWN;
static int pmu_fully_inited;
static int pmu_has_adb;
+#ifdef CONFIG_PPC_PMAC
static volatile unsigned char __iomem *via1;
static volatile unsigned char __iomem *via2;
+static struct device_node *vias;
static struct device_node *gpio_node;
+#endif
static unsigned char __iomem *gpio_reg;
static int gpio_irq = 0;
static int gpio_irq_enabled = -1;
@@ -273,6 +286,7 @@ static char *pbook_type[] = {
int __init find_via_pmu(void)
{
+#ifdef CONFIG_PPC_PMAC
u64 taddr;
const u32 *reg;
@@ -355,9 +369,6 @@ int __init find_via_pmu(void)
if (!init_pmu())
goto fail_init;
- printk(KERN_INFO "PMU driver v%d initialized for %s, firmware: %02x\n",
- PMU_DRIVER_VERSION, pbook_type[pmu_kind], pmu_version);
-
sys_ctrler = SYS_CTRLER_PMU;
return 1;
@@ -373,6 +384,30 @@ int __init find_via_pmu(void)
vias = NULL;
pmu_state = uninitialized;
return 0;
+#else
+ if (macintosh_config->adb_type != MAC_ADB_PB2)
+ return 0;
+
+ pmu_kind = PMU_UNKNOWN;
+
+ spin_lock_init(_lock);
+
+ pmu_has_adb = 1;
+
+ pmu_intr_mask = PMU_INT_PCEJECT |
+ PMU_INT_SNDBRT |
+ PMU_INT_ADB |
+ PMU_INT_TICK;
+
+ pmu_state = idle;
+
+ if (!init_pmu()) {
+ pmu_state = uninitialized;
+ return 0;
+ }
+
+ return 1;
+#endif /* !CONFIG_PPC_PMAC */
}
#ifdef CONFIG_ADB
@@ -396,13 +431,14 @@ static int pmu_init(void)
*/
static int __init via_pmu_start(void)
{
- unsigned int irq;
+ unsigned int __maybe_unused irq;
if (pmu_state == uninitialized)
return -ENODEV;
batt_req.complete = 1;
+#ifdef CONFIG_PPC_PMAC
irq = irq_of_parse_and_map(vias, 0);
if (!irq) {
printk(KERN_ERR "via-pmu: can't map interrupt\n");
@@ -439,6 +475,19 @@ static int __init via_pmu_start(void)
/* Enable interrupts */
out_8([IER], IER_SET | SR_INT | CB1_INT);
+#else
+ if (request_irq(IRQ_MAC_ADB_SR, via_pmu_interrupt, IRQF_NO_SUSPEND,
+
[PATCH 09/11] macintosh: Use common code to access RTC
Now that the 68k Mac port has adopted the via-pmu driver, it must access
the PMU RTC using the appropriate command format. The same code can now
be used for both m68k and powerpc.
Replace the RTC code that's duplicated in arch/powerpc and arch/m68k
with common RTC accessors for Cuda and PMU devices.
Cc: Geert Uytterhoeven
Cc: Paul Mackerras ,
Cc: Michael Ellerman
Tested-by: Stan Johnson
Signed-off-by: Finn Thain
---
arch/m68k/mac/misc.c | 64 ++---
arch/powerpc/platforms/powermac/time.c | 74 +-
drivers/macintosh/via-cuda.c | 34
drivers/macintosh/via-pmu.c| 32 +++
include/linux/cuda.h | 3 ++
include/linux/pmu.h| 3 ++
6 files changed, 78 insertions(+), 132 deletions(-)
diff --git a/arch/m68k/mac/misc.c b/arch/m68k/mac/misc.c
index 28090a44fa09..397f9f942a9f 100644
--- a/arch/m68k/mac/misc.c
+++ b/arch/m68k/mac/misc.c
@@ -33,34 +33,6 @@
static void (*rom_reset)(void);
#ifdef CONFIG_ADB_CUDA
-static long cuda_read_time(void)
-{
- struct adb_request req;
- long time;
-
- if (cuda_request(, NULL, 2, CUDA_PACKET, CUDA_GET_TIME) < 0)
- return 0;
- while (!req.complete)
- cuda_poll();
-
- time = (req.reply[3] << 24) | (req.reply[4] << 16) |
- (req.reply[5] << 8) | req.reply[6];
- return time - RTC_OFFSET;
-}
-
-static void cuda_write_time(long data)
-{
- struct adb_request req;
-
- data += RTC_OFFSET;
- if (cuda_request(, NULL, 6, CUDA_PACKET, CUDA_SET_TIME,
-(data >> 24) & 0xFF, (data >> 16) & 0xFF,
-(data >> 8) & 0xFF, data & 0xFF) < 0)
- return;
- while (!req.complete)
- cuda_poll();
-}
-
static __u8 cuda_read_pram(int offset)
{
struct adb_request req;
@@ -86,34 +58,6 @@ static void cuda_write_pram(int offset, __u8 data)
#endif /* CONFIG_ADB_CUDA */
#ifdef CONFIG_ADB_PMU
-static long pmu_read_time(void)
-{
- struct adb_request req;
- long time;
-
- if (pmu_request(, NULL, 1, PMU_READ_RTC) < 0)
- return 0;
- while (!req.complete)
- pmu_poll();
-
- time = (req.reply[1] << 24) | (req.reply[2] << 16) |
- (req.reply[3] << 8) | req.reply[4];
- return time - RTC_OFFSET;
-}
-
-static void pmu_write_time(long data)
-{
- struct adb_request req;
-
- data += RTC_OFFSET;
- if (pmu_request(, NULL, 5, PMU_SET_RTC,
- (data >> 24) & 0xFF, (data >> 16) & 0xFF,
- (data >> 8) & 0xFF, data & 0xFF) < 0)
- return;
- while (!req.complete)
- pmu_poll();
-}
-
static __u8 pmu_read_pram(int offset)
{
struct adb_request req;
@@ -635,12 +579,12 @@ int mac_hwclk(int op, struct rtc_time *t)
#ifdef CONFIG_ADB_CUDA
case MAC_ADB_EGRET:
case MAC_ADB_CUDA:
- now = cuda_read_time();
+ now = cuda_get_time();
break;
#endif
#ifdef CONFIG_ADB_PMU
case MAC_ADB_PB2:
- now = pmu_read_time();
+ now = pmu_get_time();
break;
#endif
default:
@@ -671,12 +615,12 @@ int mac_hwclk(int op, struct rtc_time *t)
#ifdef CONFIG_ADB_CUDA
case MAC_ADB_EGRET:
case MAC_ADB_CUDA:
- cuda_write_time(now);
+ cuda_set_time(now);
break;
#endif
#ifdef CONFIG_ADB_PMU
case MAC_ADB_PB2:
- pmu_write_time(now);
+ pmu_set_time(now);
break;
#endif
default:
diff --git a/arch/powerpc/platforms/powermac/time.c
b/arch/powerpc/platforms/powermac/time.c
index 274af6fa388e..e9c1f3dafe2f 100644
--- a/arch/powerpc/platforms/powermac/time.c
+++ b/arch/powerpc/platforms/powermac/time.c
@@ -42,9 +42,6 @@
#define DBG(x...)
#endif
-/* Apparently the RTC stores seconds since 1 Jan 1904 */
-#define RTC_OFFSET 2082844800
-
/*
* Calibrate the decrementer frequency with the VIA timer 1.
*/
@@ -103,43 +100,8 @@ static unsigned long from_rtc_time(struct rtc_time *tm)
#endif
#ifdef CONFIG_ADB_CUDA
-static unsigned long cuda_get_time(void)
-{
- struct adb_request req;
- unsigned int now;
-
- if (cuda_request(, NULL, 2, CUDA_PACKET, CUDA_GET_TIME) < 0)
- return 0;
- while (!req.complete)
- cuda_poll();
- if (req.reply_len != 7)
- printk(KERN_ERR "cuda_get_time: got %d byte reply\n",
- req.reply_len);
- now = (req.reply[3] << 24) + (req.reply[4] << 16)
- + (req.reply[5] << 8) + req.reply[6];
- return ((unsigned long)now) -
[PATCH 07/11] macintosh/via-pmu: Make CONFIG_PPC_PMAC Kconfig deps explicit
At present, CONFIG_ADB_PMU depends on CONFIG_PPC_PMAC. When this gets relaxed to CONFIG_PPC_PMAC || CONFIG_MAC, those Kconfig symbols with implicit deps on PPC_PMAC will need explicit deps. Add them now. No functional change. Tested-by: Stan Johnson Signed-off-by: Finn Thain --- drivers/macintosh/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/macintosh/Kconfig b/drivers/macintosh/Kconfig index 9c6452b38c36..26abae4c899d 100644 --- a/drivers/macintosh/Kconfig +++ b/drivers/macintosh/Kconfig @@ -79,7 +79,7 @@ config ADB_PMU config ADB_PMU_LED bool "Support for the Power/iBook front LED" - depends on ADB_PMU + depends on PPC_PMAC && ADB_PMU select NEW_LEDS select LEDS_CLASS help @@ -122,7 +122,7 @@ config PMAC_MEDIABAY config PMAC_BACKLIGHT bool "Backlight control for LCD screens" - depends on ADB_PMU && FB = y && (BROKEN || !PPC64) + depends on PPC_PMAC && ADB_PMU && FB = y && (BROKEN || !PPC64) select FB_BACKLIGHT help Say Y here to enable Macintosh specific extensions of the generic -- 2.16.1
[PATCH 04/11] macintosh/via-pmu: Enhance state machine with new 'uninitialized' state
On 68k Macs, the via/vias pointer can't be used to determine whether
the PMU driver has been initialized. For portability, add a new state
to indicate that via_find_pmu() succeeded.
After via_find_pmu() executes, testing vias == NULL is equivalent to
testing via == NULL. Replace these tests with pmu_state == uninitialized
which is simpler and more consistent. No functional change.
Tested-by: Stan Johnson
Signed-off-by: Finn Thain
---
drivers/macintosh/via-pmu.c | 44 ++--
1 file changed, 22 insertions(+), 22 deletions(-)
diff --git a/drivers/macintosh/via-pmu.c b/drivers/macintosh/via-pmu.c
index 087c3aa5233a..7fba3c88991d 100644
--- a/drivers/macintosh/via-pmu.c
+++ b/drivers/macintosh/via-pmu.c
@@ -114,6 +114,7 @@ static volatile unsigned char __iomem *via;
#define CB1_INT0x10/* transition on CB1 input */
static volatile enum pmu_state {
+ uninitialized = 0,
idle,
sending,
intack,
@@ -274,7 +275,7 @@ int __init find_via_pmu(void)
u64 taddr;
const u32 *reg;
- if (via != 0)
+ if (pmu_state != uninitialized)
return 1;
vias = of_find_node_by_name(NULL, "via-pmu");
if (vias == NULL)
@@ -369,20 +370,19 @@ int __init find_via_pmu(void)
fail:
of_node_put(vias);
vias = NULL;
+ pmu_state = uninitialized;
return 0;
}
#ifdef CONFIG_ADB
static int pmu_probe(void)
{
- return vias == NULL? -ENODEV: 0;
+ return pmu_state == uninitialized ? -ENODEV : 0;
}
static int pmu_init(void)
{
- if (vias == NULL)
- return -ENODEV;
- return 0;
+ return pmu_state == uninitialized ? -ENODEV : 0;
}
#endif /* CONFIG_ADB */
@@ -397,7 +397,7 @@ static int __init via_pmu_start(void)
{
unsigned int irq;
- if (vias == NULL)
+ if (pmu_state == uninitialized)
return -ENODEV;
batt_req.complete = 1;
@@ -463,7 +463,7 @@ arch_initcall(via_pmu_start);
*/
static int __init via_pmu_dev_init(void)
{
- if (vias == NULL)
+ if (pmu_state == uninitialized)
return -ENODEV;
#ifdef CONFIG_PMAC_BACKLIGHT
@@ -966,7 +966,7 @@ static int pmu_send_request(struct adb_request *req, int
sync)
{
int i, ret;
- if ((vias == NULL) || (!pmu_fully_inited)) {
+ if (pmu_state == uninitialized || !pmu_fully_inited) {
req->complete = 1;
return -ENXIO;
}
@@ -1060,7 +1060,7 @@ static int __pmu_adb_autopoll(int devs)
static int pmu_adb_autopoll(int devs)
{
- if ((vias == NULL) || (!pmu_fully_inited) || !pmu_has_adb)
+ if (pmu_state == uninitialized || !pmu_fully_inited || !pmu_has_adb)
return -ENXIO;
adb_dev_map = devs;
@@ -1073,7 +1073,7 @@ static int pmu_adb_reset_bus(void)
struct adb_request req;
int save_autopoll = adb_dev_map;
- if ((vias == NULL) || (!pmu_fully_inited) || !pmu_has_adb)
+ if (pmu_state == uninitialized || !pmu_fully_inited || !pmu_has_adb)
return -ENXIO;
/* anyone got a better idea?? */
@@ -1109,7 +1109,7 @@ pmu_request(struct adb_request *req, void (*done)(struct
adb_request *),
va_list list;
int i;
- if (vias == NULL)
+ if (pmu_state == uninitialized)
return -ENXIO;
if (nbytes < 0 || nbytes > 32) {
@@ -1134,7 +1134,7 @@ pmu_queue_request(struct adb_request *req)
unsigned long flags;
int nsend;
- if (via == NULL) {
+ if (pmu_state == uninitialized) {
req->complete = 1;
return -ENXIO;
}
@@ -1247,7 +1247,7 @@ pmu_start(void)
void
pmu_poll(void)
{
- if (!via)
+ if (pmu_state == uninitialized)
return;
if (disable_poll)
return;
@@ -1257,7 +1257,7 @@ pmu_poll(void)
void
pmu_poll_adb(void)
{
- if (!via)
+ if (pmu_state == uninitialized)
return;
if (disable_poll)
return;
@@ -1272,7 +1272,7 @@ pmu_poll_adb(void)
void
pmu_wait_complete(struct adb_request *req)
{
- if (!via)
+ if (pmu_state == uninitialized)
return;
while((pmu_state != idle && pmu_state != locked) || !req->complete)
via_pmu_interrupt(0, NULL);
@@ -1288,7 +1288,7 @@ pmu_suspend(void)
{
unsigned long flags;
- if (!via)
+ if (pmu_state == uninitialized)
return;
spin_lock_irqsave(_lock, flags);
@@ -1319,7 +1319,7 @@ pmu_resume(void)
{
unsigned long flags;
- if (!via || (pmu_suspended < 1))
+ if (pmu_state == uninitialized || pmu_suspended < 1)
return;
spin_lock_irqsave(_lock, flags);
@@ -1681,7 +1681,7 @@ pmu_enable_irled(int on)
{
struct adb_request req;
- if (vias == NULL)
+ if (pmu_state ==
[PATCH 03/11] macintosh/via-pmu: Don't clear shift register interrupt flag twice
Clearing the interrupt flag twice in succession creates a theoretical
race condition. Fix this.
Tested-by: Stan Johnson
Signed-off-by: Finn Thain
---
drivers/macintosh/via-pmu.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/macintosh/via-pmu.c b/drivers/macintosh/via-pmu.c
index 9c94f99e80da..087c3aa5233a 100644
--- a/drivers/macintosh/via-pmu.c
+++ b/drivers/macintosh/via-pmu.c
@@ -1458,7 +1458,6 @@ pmu_sr_intr(void)
if (in_8([B]) & TREQ) {
printk(KERN_ERR "PMU: spurious SR intr (%x)\n", in_8([B]));
- out_8([IFR], SR_INT);
return NULL;
}
/* The ack may not yet be low when we get the interrupt */
--
2.16.1
[PATCH 02/11] macintosh/via-pmu: Add missing mmio accessors
Add missing in_8() accessors to init_pmu() and pmu_sr_intr().
This fixes several sparse warnings:
drivers/macintosh/via-pmu.c:536:29: warning: dereference of noderef expression
drivers/macintosh/via-pmu.c:537:33: warning: dereference of noderef expression
drivers/macintosh/via-pmu.c:1455:17: warning: dereference of noderef expression
drivers/macintosh/via-pmu.c:1456:69: warning: dereference of noderef expression
Tested-by: Stan Johnson
Signed-off-by: Finn Thain
---
drivers/macintosh/via-pmu.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/macintosh/via-pmu.c b/drivers/macintosh/via-pmu.c
index aea147bd8754..9c94f99e80da 100644
--- a/drivers/macintosh/via-pmu.c
+++ b/drivers/macintosh/via-pmu.c
@@ -532,8 +532,9 @@ init_pmu(void)
int timeout;
struct adb_request req;
- out_8([B], via[B] | TREQ); /* negate TREQ */
- out_8([DIRB], (via[DIRB] | TREQ) & ~TACK); /* TACK in, TREQ out */
+ /* Negate TREQ. Set TACK to input and TREQ to output. */
+ out_8([B], in_8([B]) | TREQ);
+ out_8([DIRB], (in_8([DIRB]) | TREQ) & ~TACK);
pmu_request(, NULL, 2, PMU_SET_INTR_MASK, pmu_intr_mask);
timeout = 10;
@@ -1455,8 +1456,8 @@ pmu_sr_intr(void)
struct adb_request *req;
int bite = 0;
- if (via[B] & TREQ) {
- printk(KERN_ERR "PMU: spurious SR intr (%x)\n", via[B]);
+ if (in_8([B]) & TREQ) {
+ printk(KERN_ERR "PMU: spurious SR intr (%x)\n", in_8([B]));
out_8([IFR], SR_INT);
return NULL;
}
--
2.16.1
[PATCH 00/11] macintosh: Resolve various PMU driver problems
This series of patches has the following aims. 1) Eliminate duplicated code. Linux presently has two drivers for the 68HC05-based PMU devices found in Macs: via-pmu and via-pmu68k. There's no value in having separate PMU drivers for each architecture. 2) Avoid further work on via-pmu68k that's not needed for via-pmu. 3) Fix some bugs in the via-pmu driver. 4) Enable the /dev/pmu and /proc/pmu/* userspace APIs on m68k Macs by adopting via-pmu. 5) Improve stability on early 100-series PowerBooks by loading no PMU driver at all. Neither via-pmu nor via-pmu68k supports the early M50753-based PMU device found in these models. 6) Eliminate duplicated RTC accessors for PMU and Cuda. Presently these can be found under both arch/m68k and arch/powerpc. 7) Assist the out-of-tree NuBus PowerMac port to support PMU designs shared with the m68k Mac port (e.g. PowerBooks 190 and 5300). This patch series has been regression tested on various PowerBooks (190, 520, 3400, Pismo G3) and PowerMacs (Beige G3, G5). These patches did not affect userland utilities. (Note that there is a userland- visible change to the contents of /proc/pmu/interrupts.) Finn Thain (11): macintosh/via-pmu: Fix section mismatch warning macintosh/via-pmu: Add missing mmio accessors macintosh/via-pmu: Don't clear shift register interrupt flag twice macintosh/via-pmu: Enhance state machine with new 'uninitialized' state macintosh/via-pmu: Replace via pointer with via1 and via2 pointers macintosh/via-pmu: Add support for m68k PowerBooks macintosh/via-pmu: Make CONFIG_PPC_PMAC Kconfig deps explicit macintosh/via-pmu: Replace via-pmu68k driver with via-pmu driver macintosh: Use common code to access RTC macintosh/via-pmu: Clean up interrupt statistics macintosh/via-pmu: Disambiguate interrupt statistics arch/m68k/configs/mac_defconfig| 2 +- arch/m68k/configs/multi_defconfig | 2 +- arch/m68k/mac/config.c | 2 +- arch/m68k/mac/misc.c | 118 + arch/powerpc/platforms/powermac/time.c | 74 +-- drivers/macintosh/Kconfig | 19 +- drivers/macintosh/Makefile | 1 - drivers/macintosh/adb.c| 2 +- drivers/macintosh/via-cuda.c | 34 ++ drivers/macintosh/via-pmu.c| 374 ++- drivers/macintosh/via-pmu68k.c | 850 - include/linux/cuda.h | 3 + include/linux/pmu.h| 3 + include/uapi/linux/pmu.h | 2 - 14 files changed, 307 insertions(+), 1179 deletions(-) delete mode 100644 drivers/macintosh/via-pmu68k.c -- 2.16.1
[PATCH 01/11] macintosh/via-pmu: Fix section mismatch warning
The pmu_init() function has the __init qualifier, but the ops struct
that holds a pointer to it does not. This causes a build warning.
The driver works fine because the pointer is only dereferenced early.
The function is so small that there's negligible benefit from using
the __init qualifier. Remove it to fix the warning, consistent with
the other ADB drivers.
Tested-by: Stan Johnson
Signed-off-by: Finn Thain
---
drivers/macintosh/via-pmu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/macintosh/via-pmu.c b/drivers/macintosh/via-pmu.c
index ff1b518e9ebe..aea147bd8754 100644
--- a/drivers/macintosh/via-pmu.c
+++ b/drivers/macintosh/via-pmu.c
@@ -378,7 +378,7 @@ static int pmu_probe(void)
return vias == NULL? -ENODEV: 0;
}
-static int __init pmu_init(void)
+static int pmu_init(void)
{
if (vias == NULL)
return -ENODEV;
--
2.16.1
Re: [PATCH] cpuidle:powernv: Make the snooze timeout dynamic.
On Fri, Jun 1, 2018 at 2:54 PM, Gautham R Shenoy
wrote:
> Hi Balbir,
>
> Thanks for reviewing the patch!
>
> On Fri, Jun 01, 2018 at 12:51:05AM +1000, Balbir Singh wrote:
>> On Thu, May 31, 2018 at 10:15 PM, Gautham R. Shenoy
>
> [..snip..]
>> >
>> > +static u64 get_snooze_timeout(struct cpuidle_device *dev,
>> > + struct cpuidle_driver *drv,
>> > + int index)
>> > +{
>> > + int i;
>> > +
>> > + if (unlikely(!snooze_timeout_en))
>> > + return default_snooze_timeout;
>> > +
>> > + for (i = index + 1; i < drv->state_count; i++) {
>> > + struct cpuidle_state *s = >states[i];
>> > + struct cpuidle_state_usage *su = >states_usage[i];
>> > +
>> > + if (s->disabled || su->disable)
>> > + continue;
>> > +
>> > + return s->target_residency * tb_ticks_per_usec;
>>
>> Can we ensure this is not prone to overflow?
>
> s->target_residency is an "unsigned int" so can take a maximum value
> of UINT_MAX. tb_ticks_per_usec is an "unsigned long" with a value in
> the range of 100-1000. The return value is a u64. The product of
> s->target_residency and tb_ticks_per_usec should be contained in u64.
>
Fair enough, looks reasonable to me
Balbir Singh.
Re: [PATCH 1/2] error-injection: Simplify arch specific helpers
On Thu, 31 May 2018 15:39:03 +0530 "Naveen N. Rao" wrote: > Masami Hiramatsu wrote: > > On Tue, 29 May 2018 18:06:02 +0530 > > "Naveen N. Rao" wrote: > > > >> We already have an arch-independent way to set the instruction pointer > >> with instruction_pointer_set(). Using this allows us to get rid of the > >> need for override_function_with_return() that each architecture has to > >> implement. > >> > >> Furthermore, just_return_func() only has to encode arch-specific > >> assembly instructions to return from a function. Introduce a macro > >> ARCH_FUNC_RET to provide the arch-specific instruction and move over > >> just_return_func() to generic code. > >> > >> With these changes, architectures that already support kprobes, only > >> just need to ensure they provide regs_set_return_value(), GET_IP() (for > >> instruction_pointer_set()), and ARCH_FUNC_RET to support error > >> injection. > > > > Nice! the code basically good to me. Just one comment, ARCH_FUNC_RET sounds > > like a function. Maybe ARCH_RETURN_INSTRUCTION will be better name, isn't > > it? :) > > Sure -- I thought of writing ARCH_FUNCTION_RETURN, but felt that was too > verbose. How about ARCH_FUNC_RET_INST? It is OK if we can recognize it is an instruction. Thank you, -- Masami Hiramatsu
Re: [PATCH] powerpc/64s: Fix compiler store ordering to SLB shadow area
On Fri, Jun 01, 2018 at 08:52:27AM +1000, Nicholas Piggin wrote:
> On Fri, 01 Jun 2018 00:22:21 +1000
> Michael Ellerman wrote:
> > Nicholas Piggin writes:
> > > - p->save_area[index].esid = 0;
> > > - p->save_area[index].vsid = cpu_to_be64(mk_vsid_data(ea, ssize, flags));
> > > - p->save_area[index].esid = cpu_to_be64(mk_esid_data(ea, ssize, index));
> > > + WRITE_ONCE(p->save_area[index].esid, 0);
> > > + WRITE_ONCE(p->save_area[index].vsid, cpu_to_be64(mk_vsid_data(ea,
> > > ssize, flags)));
> > > + WRITE_ONCE(p->save_area[index].esid, cpu_to_be64(mk_esid_data(ea,
> > > ssize, index)));
> >
> > What's the code-gen for that look like? I suspect it's terrible?
>
> Yeah it's not great.
>
> >
> > Should we just do it in inline-asm I wonder?
That is my recommendation: that will work for all compiler versions.
> There should be no fundamental correctness reason why we can't store
> to a volatile with a byteswap store.
There are may operations that are *not* correct to merge into a volatile
memory access, and which are fine is different for every arch. GCC
simply disallows combining anything into any volatile memory by default.
This is kind of fine because volatile already means "I want this to go
slow", in common cases ;-)
I'll see what I can do to make the byteswap load/stores work with volatile
(for powerpc).
> The other option we could do is
> add a compiler barrier() between each store. The reason I didn't is
> that in theory we don't need to invalidate all memory contents here,
> but in practice probably the end result code generation would be
> better.
Something like
p->save_area[index].esid = 0;
asm("" : : "m"(p->save_area[index].esid));
p->save_area[index].vsid = cpu_to_be64(mk_vsid_data(ea, ssize, flags));
asm("" : : "m"(p->save_area[index].vsid));
p->save_area[index].esid = cpu_to_be64(mk_esid_data(ea, ssize, index));
should do the trick (and once again for the second write to esid, if you
want to be sure it is not optimised away).
Segher
Re: [PATCH] crypto/nx: Initialize 842 high and normal RxFIFO control registers
On 06/01/2018 12:41 AM, Stewart Smith wrote:
> Haren Myneni writes:
>> NX increments readOffset by FIFO size in receive FIFO control register
>> when CRB is read. But the index in RxFIFO has to match with the
>> corresponding entry in FIFO maintained by VAS in kernel. Otherwise NX
>> may be processing incorrect CRBs and can cause CRB timeout.
>>
>> VAS FIFO offset is 0 when the receive window is opened during
>> initialization. When the module is reloaded or in kexec boot, readOffset
>> in FIFO control register may not match with VAS entry. This patch adds
>> nx_coproc_init OPAL call to reset readOffset and queued entries in FIFO
>> control register for both high and normal FIFOs.
>>
>> Signed-off-by: Haren Myneni
>>
>> diff --git a/arch/powerpc/include/asm/opal-api.h
>> b/arch/powerpc/include/asm/opal-api.h
>> index d886a5b..ff61e4b 100644
>> --- a/arch/powerpc/include/asm/opal-api.h
>> +++ b/arch/powerpc/include/asm/opal-api.h
>> @@ -206,7 +206,8 @@
>> #define OPAL_NPU_TL_SET 161
>> #define OPAL_PCI_GET_PBCQ_TUNNEL_BAR164
>> #define OPAL_PCI_SET_PBCQ_TUNNEL_BAR165
>> -#define OPAL_LAST 165
>> +#define OPAL_NX_COPROC_INIT 167
>> +#define OPAL_LAST 167
>>
>> /* Device tree flags */
>>
>> diff --git a/arch/powerpc/include/asm/opal.h
>> b/arch/powerpc/include/asm/opal.h
>> index 7159e1a..d79eb82 100644
>> --- a/arch/powerpc/include/asm/opal.h
>> +++ b/arch/powerpc/include/asm/opal.h
>> @@ -288,6 +288,7 @@ int64_t opal_imc_counters_init(uint32_t type, uint64_t
>> address,
>> int opal_get_power_shift_ratio(u32 handle, int token, u32 *psr);
>> int opal_set_power_shift_ratio(u32 handle, int token, u32 psr);
>> int opal_sensor_group_clear(u32 group_hndl, int token);
>> +int opal_nx_coproc_init(uint32_t chip_id, uint32_t ct);
>>
>> s64 opal_signal_system_reset(s32 cpu);
>>
>> diff --git a/arch/powerpc/platforms/powernv/opal-wrappers.S
>> b/arch/powerpc/platforms/powernv/opal-wrappers.S
>> index 3da30c2..c7541a9 100644
>> --- a/arch/powerpc/platforms/powernv/opal-wrappers.S
>> +++ b/arch/powerpc/platforms/powernv/opal-wrappers.S
>> @@ -325,3 +325,4 @@ OPAL_CALL(opal_npu_spa_clear_cache,
>> OPAL_NPU_SPA_CLEAR_CACHE);
>> OPAL_CALL(opal_npu_tl_set, OPAL_NPU_TL_SET);
>> OPAL_CALL(opal_pci_get_pbcq_tunnel_bar,
>> OPAL_PCI_GET_PBCQ_TUNNEL_BAR);
>> OPAL_CALL(opal_pci_set_pbcq_tunnel_bar,
>> OPAL_PCI_SET_PBCQ_TUNNEL_BAR);
>> +OPAL_CALL(opal_nx_coproc_init, OPAL_NX_COPROC_INIT);
>> diff --git a/arch/powerpc/platforms/powernv/opal.c
>> b/arch/powerpc/platforms/powernv/opal.c
>> index 48fbb41..5e13908 100644
>> --- a/arch/powerpc/platforms/powernv/opal.c
>> +++ b/arch/powerpc/platforms/powernv/opal.c
>> @@ -1035,3 +1035,5 @@ void powernv_set_nmmu_ptcr(unsigned long ptcr)
>> EXPORT_SYMBOL_GPL(opal_int_set_mfrr);
>> EXPORT_SYMBOL_GPL(opal_int_eoi);
>> EXPORT_SYMBOL_GPL(opal_error_code);
>> +/* Export the below symbol for NX compression */
>> +EXPORT_SYMBOL(opal_nx_coproc_init);
>> diff --git a/drivers/crypto/nx/nx-842-powernv.c
>> b/drivers/crypto/nx/nx-842-powernv.c
>> index 1e87637..6c4784d 100644
>> --- a/drivers/crypto/nx/nx-842-powernv.c
>> +++ b/drivers/crypto/nx/nx-842-powernv.c
>> @@ -24,6 +24,8 @@
>> #include
>> #include
>> #include
>> +#include
>> +#include
>>
>> MODULE_LICENSE("GPL");
>> MODULE_AUTHOR("Dan Streetman ");
>> @@ -803,9 +805,26 @@ static int __init vas_cfg_coproc_info(struct
>> device_node *dn, int chip_id,
>> if (!coproc)
>> return -ENOMEM;
>>
>> -if (!strcmp(priority, "High"))
>> +if (!strcmp(priority, "High")) {
>> +/*
>> + * (lpid, pid, tid) combination has to be unique for each
>> + * coprocessor instance in the system. So to make it
>> + * unique, skiboot uses coprocessor type such as 842 or
>> + * GZIP for pid and provides this value to kernel in pid
>> + * device-tree property.
>> + *
>> + * Initialize each NX instance for both high and normal
>> + * priority FIFOs.
>> + */
>> +ret = opal_nx_coproc_init(chip_id, pid);
>> +if (ret) {
>> +pr_err("Failed to initialize NX coproc: %d\n", ret);
>> +ret = opal_error_code(ret);
>> +goto err_out;
>> +}
>> +
>> coproc->ct = VAS_COP_TYPE_842_HIPRI;
>
> I think this should be called for all priority queues as it would be at
> least theoretically possible to only have Normal priority queues, in
> which case this patch wouldn't fix the problem.
device tree exports separate nodes for high and normal priority FIFOs per each
NX instance. But NX init OPAL function is called once per each NX instance when
high-FIFO device node is parsed to reset high and
Re: [PATCH] [SCHEME 2]powernv/cpuidle: Add support for new idle state device-tree format
Hi Akshay,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on powerpc/next]
[also build test ERROR on v4.17-rc7 next-20180531]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Akshay-Adiga/powernv-cpuidle-Add-support-for-new-idle-state-device-tree-format/20180601-202708
base: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git next
config: powerpc-allmodconfig (attached as .config)
compiler: powerpc64-linux-gnu-gcc (Debian 7.2.0-11) 7.2.0
reproduce:
wget
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O
~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=powerpc
All errors (new ones prefixed by >>):
drivers//cpuidle/cpuidle-powernv.c: In function 'powernv_add_idle_states':
>> drivers//cpuidle/cpuidle-powernv.c:403:36: error: 'versions' undeclared
>> (first use in this function)
"ibm,cpu-idle-state-versions", versions, additional_states) < 0) {
^~~~
drivers//cpuidle/cpuidle-powernv.c:403:36: note: each undeclared identifier
is reported only once for each function it appears in
>> drivers//cpuidle/cpuidle-powernv.c:436:17: error: 'version' undeclared
>> (first use in this function); did you mean 'versions'?
if (!( strcmp(version[i] , "ibm,idle-state-v1"))
^~~
versions
>> drivers//cpuidle/cpuidle-powernv.c:437:5: error: expected ')' before
>> 'continue'
continue;
^~~~
>> drivers//cpuidle/cpuidle-powernv.c:511:2: error: expected expression before
>> '}' token
}
^
drivers//cpuidle/cpuidle-powernv.c:426:8: warning: unused variable
'stops_timebase' [-Wunused-variable]
bool stops_timebase = false;
^~
drivers//cpuidle/cpuidle-powernv.c:425:30: warning: unused variable
'target_residency' [-Wunused-variable]
unsigned int exit_latency, target_residency;
^~~~
drivers//cpuidle/cpuidle-powernv.c:425:16: warning: unused variable
'exit_latency' [-Wunused-variable]
unsigned int exit_latency, target_residency;
^~~~
At top level:
drivers//cpuidle/cpuidle-powernv.c:121:12: warning: 'stop_loop' defined but
not used [-Wunused-function]
static int stop_loop(struct cpuidle_device *dev,
^
drivers//cpuidle/cpuidle-powernv.c:95:12: warning: 'fastsleep_loop' defined
but not used [-Wunused-function]
static int fastsleep_loop(struct cpuidle_device *dev,
^~
drivers//cpuidle/cpuidle-powernv.c:84:12: warning: 'nap_loop' defined but
not used [-Wunused-function]
static int nap_loop(struct cpuidle_device *dev,
^~~~
vim +/versions +403 drivers//cpuidle/cpuidle-powernv.c
240
241 extern u32 pnv_get_supported_cpuidle_states(void);
242 static int powernv_add_idle_states(void)
243 {
244 struct device_node *power_mgt,*np_new;
245 int nr_idle_states = 1; /* Snooze */
246 int dt_idle_states, count, additional_states;
247 u32 latency_ns[CPUIDLE_STATE_MAX];
248 u32 residency_ns[CPUIDLE_STATE_MAX];
249 u32 flags[CPUIDLE_STATE_MAX];
250 u64 psscr_val[CPUIDLE_STATE_MAX];
251 u64 psscr_mask[CPUIDLE_STATE_MAX];
252 const char *names[CPUIDLE_STATE_MAX];
253 u32 has_stop_states = 0;
254 int i, rc;
255 u32 supported_flags = pnv_get_supported_cpuidle_states();
256
257
258 /* Currently we have snooze statically defined */
259
260 power_mgt = of_find_node_by_path("/ibm,opal/power-mgt");
261 if (!power_mgt) {
262 pr_warn("opal: PowerMgmt Node not found\n");
263 goto out;
264 }
265
266 /* Read values of any property to determine the num of idle
states */
267 dt_idle_states = of_property_count_u32_elems(power_mgt,
"ibm,cpu-idle-state-flags");
268 if (dt_idle_states < 0) {
269 pr_warn("cpuidle-powernv: no idle states found in the
DT\n");
270 goto out;
271 }
272
273 count = of_property_count_u32_elems(power_mgt,
274
"ibm,cpu-idle-state-latencies-ns");
275
276 if (validate_dt_prop_sizes("ibm,cpu-idle-state-flags",
dt_idle_states,
277 "ibm,cpu-idle-state-latencies-ns",
278 count) != 0)
279
Re: powerpc/mm: Fix kernel crash on page table free
On Wed, 2018-05-30 at 12:32:25 UTC, "Aneesh Kumar K.V" wrote:
> Fix the below crash on BookE 64. pgtable_page_dtor expects struct page *arg.
>
> Also call the destructor on non book3s platforms correctly. This free up the
> split ptl locks correctly if we had allocated them before.
>
> Call Trace:
> [c000f30c7520] [c021eeec] .kmem_cache_free+0x9c/0x44c (unreliable)
> [c000f30c75c0] [c01ee07c] .ptlock_free+0x1c/0x30
> [c000f30c7630] [c01ee260] .tlb_remove_table+0xdc/0x224
> [c000f30c76c0] [c01ee640] .free_pgd_range+0x298/0x500
> [c000f30c77d0] [c0232afc] .shift_arg_pages+0x10c/0x1e0
> [c000f30c7910] [c0232dd0] .setup_arg_pages+0x200/0x25c
> [c000f30c79c0] [c02ad4fc] .load_elf_binary+0x450/0x16c8
> [c000f30c7b10] [c0234914]
> .search_binary_handler.part.11+0x9c/0x248
> [c000f30c7bb0] [c023595c] .do_execveat_common.isra.13+0x868/0xc18
> [c000f30c7cb0] [c000184c] .run_init_process+0x34/0x4c
> [c000f30c7d30] [c0001880] .try_to_run_init_process+0x1c/0x68
> [c000f30c7db0] [c0002bd8] .kernel_init+0xdc/0x130
> [c000f30c7e30] [c9dc] .ret_from_kernel_thread+0x58/0x7c
>
> Fixes: 702346768 ("powerpc/mm/nohash: Remove pte fragment dependency from
> nohash")
> Signed-off-by: Aneesh Kumar K.V
Applied to powerpc next, thanks.
https://git.kernel.org/powerpc/c/667416f38554eef94485496f3a27b9
cheers
Re: powerpc/prom: Fix %u/%llx usage since prom_printf() change
On Tue, 2018-05-29 at 19:20:01 UTC, Mathieu Malaterre wrote:
> In commit eae5f709a4d7 ("powerpc: Add __printf verification to
> prom_printf") __printf attribute was added to prom_printf(), which
> means GCC started warning about type/format mismatches. As part of that
> commit we changed some "%lx" formats to "%llx" where the type is
> actually unsigned long long.
>
> Unfortunately prom_printf() doesn't know how to print "%llx", it just
> prints a literal "lx", eg:
>
> reserved memory map:
> lx - lx
> lx - lx
>
> prom_printf() also doesn't know how to print "%u" (only "%lu"), it just
> print a literal "u", eg:
>
> Max number of cores passed to firmware: u (NR_CPUS = 2048)
>
> instead of:
>
> Max number of cores passed to firmware: 2048 (NR_CPUS = 2048)
>
> This commit adds support for the missing formatters.
>
> Fixes: eae5f709a4d7 ("powerpc: Add __printf verification to prom_printf")
> Reported-by: Michael Ellerman
> Reported-by: Stephen Rothwell
> Signed-off-by: Mathieu Malaterre
Applied to powerpc next, thanks.
https://git.kernel.org/powerpc/c/8af1da40669609707303eecdb857f4
cheers
Re: powerpc/modules: remove unused mod_arch_specific.toc field
On Fri, 2018-05-25 at 03:48:34 UTC, Josh Poimboeuf wrote: > The toc field in the mod_arch_specific struct isn't actually used > anywhere, so remove it. > > Also the ftrace-specific fields are now common between 32-bit and > 64-bit, so simplify the struct definition a bit by moving them out of > the __powerpc64__ #ifdef. > > Signed-off-by: Josh Poimboeuf > Reviewed-by: Kamalesh Babulal Applied to powerpc next, thanks. https://git.kernel.org/powerpc/c/8ce621e1d946b1d1d7717337ab8dc3 cheers
Re: [v2, 2/2] selftests/powerpc: Add core file test for Protection Key registers
On Fri, 2018-05-25 at 02:11:45 UTC, Thiago Jung Bauermann wrote: > This test verifies that the AMR, IAMR and UAMOR are being written to a > process' core file. > > Signed-off-by: Thiago Jung Bauermann Applied to powerpc next, thanks. https://git.kernel.org/powerpc/c/39b91dd625f15438859204a489ab62 cheers
Re: [v2, 1/2] selftests/powerpc: Add ptrace tests for Protection Key registers
On Fri, 2018-05-25 at 02:11:44 UTC, Thiago Jung Bauermann wrote: > This test exercises read and write access to the AMR, IAMR and UAMOR. > > Signed-off-by: Thiago Jung Bauermann Applied to powerpc next, thanks. https://git.kernel.org/powerpc/c/1f7256e7dddef49acf9f6c9fe3f935 cheers
Re: [PATCH-RESEND] cxl: Disable prefault_mode in Radix mode
On Fri, 2018-05-18 at 09:42:23 UTC, Vaibhav Jain wrote:
> From: Vaibhav Jain
>
> Currently we see a kernel-oops reported on Power-9 while attaching a
> context to an AFU, with radix-mode and sysfs attr 'prefault_mode' set
> to anything other than 'none'. The backtrace of the oops is of this
> form:
>
> Unable to handle kernel paging request for data at address 0x0080
> Faulting instruction address: 0xc0080bcf3b20
> cpu 0x1: Vector: 300 (Data Access) at [c0037f003800]
> pc: c0080bcf3b20: cxl_load_segment+0x178/0x290 [cxl]
> lr: c0080bcf39f0: cxl_load_segment+0x48/0x290 [cxl]
> sp: c0037f003a80
>msr: 90009033
>dar: 80
> dsisr: 4000
> current = 0xc0037f28
> paca= 0xc003e600 softe: 3irq_happened: 0x01
> pid = 3529, comm = afp_no_int
>
> [c0037f003af0] c0080bcf4424 cxl_prefault+0xfc/0x248 [cxl]
> [c0037f003b50] c0080bcf8a40 process_element_entry_psl9+0xd8/0x1a0
> [cxl]
> [c0037f003b90] c0080bcf944c
> cxl_attach_dedicated_process_psl9+0x44/0x130 [cxl]
> [c0037f003bd0] c0080bcf5448 native_attach_process+0xc0/0x130 [cxl]
> [c0037f003c50] c0080bcf16cc afu_ioctl+0x3f4/0x5e0 [cxl]
> [c0037f003d00] c039d98c do_vfs_ioctl+0xdc/0x890
> [c0037f003da0] c039e1a8 ksys_ioctl+0x68/0xf0
> [c0037f003df0] c039e270 sys_ioctl+0x40/0xa0
> [c0037f003e30] c000b320 system_call+0x58/0x6c
> --- Exception: c01 (System Call) at 10053bb0
>
> The issue is caused as on Power-8 the AFU attr 'prefault_mode' was
> used to improve initial storage fault performance by prefaulting
> process segments. However on Power-9 with radix mode we don't have
> Storage-Segments that we can prefault. Also prefaulting process Pages
> will be too costly and fine-grained.
>
> Hence, since the prefaulting mechanism doesn't makes sense of
> radix-mode, this patch updates prefault_mode_store() to not allow any
> other value apart from CXL_PREFAULT_NONE when radix mode is enabled.
>
> Cc:
> Fixes: f24be42aab37 ("cxl: Add psl9 specific code")
> Signed-off-by: Vaibhav Jain
> Acked-by: Frederic Barrat
> Acked-by: Andrew Donnellan
Applied to powerpc next, thanks.
https://git.kernel.org/powerpc/c/b6c84ba22ff3a198eb8d5552cf9b8f
cheers
Re: powerpc/kprobes: Fix build error with kprobes disabled.
On Tue, 2018-05-22 at 09:08:20 UTC, "Aneesh Kumar K.V" wrote: > arch/powerpc/kernel/stacktrace.c: In function > ‘save_stack_trace_tsk_reliable’: > arch/powerpc/kernel/stacktrace.c:176:28: error: ‘kretprobe_trampoline’ > undeclared (first use in this function); did you mean > ‘is_ftrace_trampoline’? >if (ip == (unsigned long)kretprobe_trampoline) > ^~~~ > is_ftrace_trampoline > arch/powerpc/kernel/stacktrace.c:176:28: note: each undeclared identifier is > reported only once for each function it appears in > > Signed-off-by: Aneesh Kumar K.V Applied to powerpc next, thanks. https://git.kernel.org/powerpc/c/5e3f0d15ae5f95bdde8d092a0884d2 cheers
Re: cpuidle/powernv : init all present cpus for deep states
On Wed, 2018-05-16 at 12:02:14 UTC, Akshay Adiga wrote: > Init all present cpus for deep states instead of "all possible" cpus. > Init fails if the possible cpu is gaurded. Resulting in making only > non-deep states available for cpuidle/hotplug. > > Signed-off-by: Akshay Adiga Applied to powerpc next, thanks. https://git.kernel.org/powerpc/c/ac9816dcbab53c57bcf1d7b15370b0 cheers
Re: powerpc/perf: Update raw-event code encoding comment for power8
On Tue, 2018-05-08 at 05:00:24 UTC, Madhavan Srinivasan wrote:
> Comment explanning the raw event code encoding for Power8 was
> moved to isa207_common.h file when re-factoring the code to
> support power9. But then Power9 pmu branched out due to changes
> specific to power9. So move the encoding comment back to power8-pmu.c
> Just comment movement and no logic change.
>
> Fixes: 4d3576b20716 ('powerpc/perf: factor out power8 pmu macros and defines')
> Signed-off-by: Madhavan Srinivasan
Applied to powerpc next, thanks.
https://git.kernel.org/powerpc/c/458c70173d823faeb5b4031bf8
cheers
Re: cxl: Configure PSL to not use APC virtual machines
On Tue, 2018-04-17 at 05:11:02 UTC, Vaibhav Jain wrote: > APC virtual machines arent used on POWER-9 chips and are already > disabled in on-chip CAPP. They also need to be disabled on the PSL via > 'PSL Data Send Control Register' by setting bit(47). This forces the > PSL to send commands to CAPP with queue.id == 0. > > Signed-off-by: Vaibhav Jain > Acked-by: Andrew Donnellan > Reviewed-by: Alastair D'Silva > Reviewed-by: Christophe Lombard Applied to powerpc next, thanks. https://git.kernel.org/powerpc/c/9a6d2022bacd8fca0be6297459a02d cheers
[RFC PATCH v2 14/14] powerpc: Split synch.h in two parts
move feature-fixups related stuff from synch.h to synch-ftr.h
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/atomic.h | 1 +
arch/powerpc/include/asm/barrier.h| 1 +
arch/powerpc/include/asm/bitops.h | 1 +
arch/powerpc/include/asm/cmpxchg.h| 1 +
arch/powerpc/include/asm/spinlock.h | 1 +
arch/powerpc/include/asm/{synch.h => synch-ftr.h} | 22 +++--
arch/powerpc/include/asm/synch.h | 30 ---
arch/powerpc/lib/feature-fixups-test.S| 1 +
8 files changed, 9 insertions(+), 49 deletions(-)
copy arch/powerpc/include/asm/{synch.h => synch-ftr.h} (66%)
diff --git a/arch/powerpc/include/asm/atomic.h
b/arch/powerpc/include/asm/atomic.h
index cbdb0b7e60a3..49a929ec5435 100644
--- a/arch/powerpc/include/asm/atomic.h
+++ b/arch/powerpc/include/asm/atomic.h
@@ -11,6 +11,7 @@
#include
#include
#include
+#include
#define ATOMIC_INIT(i) { (i) }
diff --git a/arch/powerpc/include/asm/barrier.h
b/arch/powerpc/include/asm/barrier.h
index 117d09df869f..6a2da24a2219 100644
--- a/arch/powerpc/include/asm/barrier.h
+++ b/arch/powerpc/include/asm/barrier.h
@@ -6,6 +6,7 @@
#define _ASM_POWERPC_BARRIER_H
#include
+#include
/*
* Memory barrier.
diff --git a/arch/powerpc/include/asm/bitops.h
b/arch/powerpc/include/asm/bitops.h
index ff71566dadee..b8bf2f5b75ce 100644
--- a/arch/powerpc/include/asm/bitops.h
+++ b/arch/powerpc/include/asm/bitops.h
@@ -44,6 +44,7 @@
#include
#include
+#include
#include
#include
diff --git a/arch/powerpc/include/asm/cmpxchg.h
b/arch/powerpc/include/asm/cmpxchg.h
index 27183871eb3b..d94a67a1a574 100644
--- a/arch/powerpc/include/asm/cmpxchg.h
+++ b/arch/powerpc/include/asm/cmpxchg.h
@@ -4,6 +4,7 @@
#ifdef __KERNEL__
#include
+#include
#include
#include
#include
diff --git a/arch/powerpc/include/asm/spinlock.h
b/arch/powerpc/include/asm/spinlock.h
index 685c72310f5d..182f950a4c5d 100644
--- a/arch/powerpc/include/asm/spinlock.h
+++ b/arch/powerpc/include/asm/spinlock.h
@@ -24,6 +24,7 @@
#include
#include
#endif
+#include
#include
#include
#include
diff --git a/arch/powerpc/include/asm/synch.h
b/arch/powerpc/include/asm/synch-ftr.h
similarity index 66%
copy from arch/powerpc/include/asm/synch.h
copy to arch/powerpc/include/asm/synch-ftr.h
index aca70fb43147..f86c536bd351 100644
--- a/arch/powerpc/include/asm/synch.h
+++ b/arch/powerpc/include/asm/synch-ftr.h
@@ -1,27 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_POWERPC_SYNCH_H
-#define _ASM_POWERPC_SYNCH_H
+#ifndef _ASM_POWERPC_SYNCH_FTR_H
+#define _ASM_POWERPC_SYNCH_FTR_H
#ifdef __KERNEL__
#include
#include
-#ifndef __ASSEMBLY__
-extern unsigned int __start___lwsync_fixup, __stop___lwsync_fixup;
-extern void do_lwsync_fixups(unsigned long value, void *fixup_start,
-void *fixup_end);
-
-static inline void eieio(void)
-{
- __asm__ __volatile__ ("eieio" : : : "memory");
-}
-
-static inline void isync(void)
-{
- __asm__ __volatile__ ("isync" : : : "memory");
-}
-#endif /* __ASSEMBLY__ */
-
#if defined(__powerpc64__)
#define LWSYNC lwsync
#elif defined(CONFIG_E500)
@@ -50,4 +34,4 @@ static inline void isync(void)
#endif
#endif /* __KERNEL__ */
-#endif /* _ASM_POWERPC_SYNCH_H */
+#endif /* _ASM_POWERPC_SYNCH_FTR_H */
diff --git a/arch/powerpc/include/asm/synch.h b/arch/powerpc/include/asm/synch.h
index aca70fb43147..48b23168ea9e 100644
--- a/arch/powerpc/include/asm/synch.h
+++ b/arch/powerpc/include/asm/synch.h
@@ -3,9 +3,6 @@
#define _ASM_POWERPC_SYNCH_H
#ifdef __KERNEL__
-#include
-#include
-
#ifndef __ASSEMBLY__
extern unsigned int __start___lwsync_fixup, __stop___lwsync_fixup;
extern void do_lwsync_fixups(unsigned long value, void *fixup_start,
@@ -22,32 +19,5 @@ static inline void isync(void)
}
#endif /* __ASSEMBLY__ */
-#if defined(__powerpc64__)
-#define LWSYNC lwsync
-#elif defined(CONFIG_E500)
-#define LWSYNC \
- START_LWSYNC_SECTION(96); \
- sync; \
- MAKE_LWSYNC_SECTION_ENTRY(96, __lwsync_fixup);
-#else
-#define LWSYNC sync
-#endif
-
-#ifdef CONFIG_SMP
-#define __PPC_ACQUIRE_BARRIER \
- START_LWSYNC_SECTION(97); \
- isync; \
- MAKE_LWSYNC_SECTION_ENTRY(97, __lwsync_fixup);
-#define PPC_ACQUIRE_BARRIER "\n" stringify_in_c(__PPC_ACQUIRE_BARRIER)
-#define PPC_RELEASE_BARRIER stringify_in_c(LWSYNC) "\n"
-#define PPC_ATOMIC_ENTRY_BARRIER "\n" stringify_in_c(sync) "\n"
-#define PPC_ATOMIC_EXIT_BARRIER "\n" stringify_in_c(sync) "\n"
-#else
-#define PPC_ACQUIRE_BARRIER
-#define PPC_RELEASE_BARRIER
-#define PPC_ATOMIC_ENTRY_BARRIER
-#define PPC_ATOMIC_EXIT_BARRIER
-#endif
-
[RFC PATCH v2 13/14] powerpc: split reg.h in two parts
Move all macros involving feature-fixups in a new file reg-ftr.h Signed-off-by: Christophe Leroy --- arch/powerpc/include/asm/exception-64s.h | 1 + arch/powerpc/include/asm/reg-ftr.h | 63 arch/powerpc/include/asm/reg.h | 36 -- arch/powerpc/kernel/entry_64.S | 1 + arch/powerpc/kernel/exceptions-64s.S | 1 + arch/powerpc/kernel/head_64.S| 1 + arch/powerpc/kernel/idle_book3s.S| 1 + arch/powerpc/kernel/paca.c | 1 + arch/powerpc/kernel/tm.S | 1 + arch/powerpc/kvm/book3s_hv_rmhandlers.S | 1 + arch/powerpc/kvm/book3s_rmhandlers.S | 1 + arch/powerpc/kvm/book3s_segment.S| 1 + 12 files changed, 73 insertions(+), 36 deletions(-) create mode 100644 arch/powerpc/include/asm/reg-ftr.h diff --git a/arch/powerpc/include/asm/exception-64s.h b/arch/powerpc/include/asm/exception-64s.h index 1f2efc1a9769..9d748eaeb9ec 100644 --- a/arch/powerpc/include/asm/exception-64s.h +++ b/arch/powerpc/include/asm/exception-64s.h @@ -36,6 +36,7 @@ */ #include #include +#include /* PACA save area offsets (exgen, exmc, etc) */ #define EX_R9 0 diff --git a/arch/powerpc/include/asm/reg-ftr.h b/arch/powerpc/include/asm/reg-ftr.h new file mode 100644 index ..ec2e53c500c2 --- /dev/null +++ b/arch/powerpc/include/asm/reg-ftr.h @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Contains the definition of registers common to all PowerPC variants. + * If a register definition has been changed in a different PowerPC + * variant, we will case it in #ifndef XXX ... #endif, and have the + * number used in the Programming Environments Manual For 32-Bit + * Implementations of the PowerPC Architecture (a.k.a. Green Book) here. + */ + +#ifndef _ASM_POWERPC_REG_FTR_H +#define _ASM_POWERPC_REG_FTR_H +#ifdef __KERNEL__ + +#include +#include +#include +#include + +#ifdef CONFIG_PPC_BOOK3S_64 + +#define GET_PACA(rX) \ + BEGIN_FTR_SECTION_NESTED(66); \ + mfspr rX,SPRN_SPRG_PACA; \ + FTR_SECTION_ELSE_NESTED(66);\ + mfspr rX,SPRN_SPRG_HPACA; \ + ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE, 66) + +#define SET_PACA(rX) \ + BEGIN_FTR_SECTION_NESTED(66); \ + mtspr SPRN_SPRG_PACA,rX; \ + FTR_SECTION_ELSE_NESTED(66);\ + mtspr SPRN_SPRG_HPACA,rX; \ + ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE, 66) + +#define GET_SCRATCH0(rX) \ + BEGIN_FTR_SECTION_NESTED(66); \ + mfspr rX,SPRN_SPRG_SCRATCH0; \ + FTR_SECTION_ELSE_NESTED(66);\ + mfspr rX,SPRN_SPRG_HSCRATCH0; \ + ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE, 66) + +#define SET_SCRATCH0(rX) \ + BEGIN_FTR_SECTION_NESTED(66); \ + mtspr SPRN_SPRG_SCRATCH0,rX; \ + FTR_SECTION_ELSE_NESTED(66);\ + mtspr SPRN_SPRG_HSCRATCH0,rX; \ + ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE, 66) + +#else /* CONFIG_PPC_BOOK3S_64 */ +#define GET_SCRATCH0(rX) mfspr rX,SPRN_SPRG_SCRATCH0 +#define SET_SCRATCH0(rX) mtspr SPRN_SPRG_SCRATCH0,rX + +#endif + +#ifdef CONFIG_PPC_BOOK3E_64 + +#define SET_PACA(rX) mtspr SPRN_SPRG_PACA,rX +#define GET_PACA(rX) mfspr rX,SPRN_SPRG_PACA + +#endif + +#endif /* __KERNEL__ */ +#endif /* _ASM_POWERPC_REG_FTR_H */ diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h index b59a633dc349..69dcf26a02a8 100644 --- a/arch/powerpc/include/asm/reg.h +++ b/arch/powerpc/include/asm/reg.h @@ -14,7 +14,6 @@ #include #include #include -#include /* Pickup Book E specific registers. */ #if defined(CONFIG_BOOKE) || defined(CONFIG_40x) @@ -1084,38 +1083,6 @@ #define SPRN_SPRG_VDSO_READSPRN_USPRG3 #define SPRN_SPRG_VDSO_WRITE SPRN_SPRG3 -#define GET_PACA(rX) \ - BEGIN_FTR_SECTION_NESTED(66); \ - mfspr rX,SPRN_SPRG_PACA; \ - FTR_SECTION_ELSE_NESTED(66);\ - mfspr rX,SPRN_SPRG_HPACA; \ - ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE, 66) - -#define SET_PACA(rX) \ - BEGIN_FTR_SECTION_NESTED(66); \ - mtspr SPRN_SPRG_PACA,rX; \ - FTR_SECTION_ELSE_NESTED(66);\ - mtspr SPRN_SPRG_HPACA,rX; \ - ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE, 66) - -#define GET_SCRATCH0(rX) \
[RFC PATCH v2 12/14] powerpc/44x: remove page.h from mmu-44x.h
mmu-44x.h doesn't need asm/page.h if PAGE_SHIFT are replaced by
CONFIG_PPC_XX_PAGES
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/mmu-44x.h | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/include/asm/mmu-44x.h
b/arch/powerpc/include/asm/mmu-44x.h
index 9bdbe1d1c9b9..b2b8274037ea 100644
--- a/arch/powerpc/include/asm/mmu-44x.h
+++ b/arch/powerpc/include/asm/mmu-44x.h
@@ -5,7 +5,7 @@
* PPC440 support
*/
-#include
+#include
#include
#define PPC44x_MMUCR_TID 0x00ff
@@ -125,19 +125,19 @@ typedef struct {
/* Size of the TLBs used for pinning in lowmem */
#define PPC_PIN_SIZE (1 << 28) /* 256M */
-#if (PAGE_SHIFT == 12)
+#if defined(CONFIG_PPC_4K_PAGES)
#define PPC44x_TLBE_SIZE PPC44x_TLB_4K
#define PPC47x_TLBE_SIZE PPC47x_TLB0_4K
#define mmu_virtual_psize MMU_PAGE_4K
-#elif (PAGE_SHIFT == 14)
+#elif defined(CONFIG_PPC_16K_PAGES)
#define PPC44x_TLBE_SIZE PPC44x_TLB_16K
#define PPC47x_TLBE_SIZE PPC47x_TLB0_16K
#define mmu_virtual_psize MMU_PAGE_16K
-#elif (PAGE_SHIFT == 16)
+#elif defined(CONFIG_PPC_64K_PAGES)
#define PPC44x_TLBE_SIZE PPC44x_TLB_64K
#define PPC47x_TLBE_SIZE PPC47x_TLB0_64K
#define mmu_virtual_psize MMU_PAGE_64K
-#elif (PAGE_SHIFT == 18)
+#elif defined(CONFIG_PPC_256K_PAGES)
#define PPC44x_TLBE_SIZE PPC44x_TLB_256K
#define mmu_virtual_psize MMU_PAGE_256K
#else
--
2.13.3
[RFC PATCH v2 11/14] powerpc/nohash: fix hash related comments in pgtable.h
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/nohash/32/pgtable.h | 4
arch/powerpc/include/asm/nohash/64/pgtable.h | 18 --
2 files changed, 4 insertions(+), 18 deletions(-)
diff --git a/arch/powerpc/include/asm/nohash/32/pgtable.h
b/arch/powerpc/include/asm/nohash/32/pgtable.h
index b2d0f3d0b097..a70f7bf2248f 100644
--- a/arch/powerpc/include/asm/nohash/32/pgtable.h
+++ b/arch/powerpc/include/asm/nohash/32/pgtable.h
@@ -223,10 +223,6 @@ static inline unsigned long long pte_update(pte_t *p,
}
#endif /* CONFIG_PTE_64BIT */
-/*
- * 2.6 calls this without flushing the TLB entry; this is wrong
- * for our hash-based implementation, we fix that up here.
- */
#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
static inline int __ptep_test_and_clear_young(unsigned int context, unsigned
long addr, pte_t *ptep)
{
diff --git a/arch/powerpc/include/asm/nohash/64/pgtable.h
b/arch/powerpc/include/asm/nohash/64/pgtable.h
index b90256f74cc8..bf04176dbef1 100644
--- a/arch/powerpc/include/asm/nohash/64/pgtable.h
+++ b/arch/powerpc/include/asm/nohash/64/pgtable.h
@@ -3,7 +3,7 @@
#define _ASM_POWERPC_NOHASH_64_PGTABLE_H
/*
* This file contains the functions and defines necessary to modify and use
- * the ppc64 hashed page table.
+ * the ppc64 non-hashed page table.
*/
#include
@@ -38,7 +38,7 @@
/*
* The vmalloc space starts at the beginning of that region, and
- * occupies half of it on hash CPUs and a quarter of it on Book3E
+ * occupies a quarter of it on Book3E
* (we keep a quarter for the virtual memmap)
*/
#define VMALLOC_START KERN_VIRT_START
@@ -78,7 +78,7 @@
/*
* Defines the address of the vmemap area, in its own region on
- * hash table CPUs and after the vmalloc space on Book3E
+ * after the vmalloc space on Book3E
*/
#define VMEMMAP_BASE VMALLOC_END
#define VMEMMAP_ENDKERN_IO_START
@@ -248,14 +248,6 @@ static inline void huge_ptep_set_wrprotect(struct
mm_struct *mm,
pte_update(mm, addr, ptep, _PAGE_RW, 0, 1);
}
-/*
- * We currently remove entries from the hashtable regardless of whether
- * the entry was young or dirty. The generic routines only flush if the
- * entry was young or dirty which is not good enough.
- *
- * We should be more intelligent about this but for the moment we override
- * these functions and force a tlb flush unconditionally
- */
#define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
#define ptep_clear_flush_young(__vma, __address, __ptep) \
({ \
@@ -279,9 +271,7 @@ static inline void pte_clear(struct mm_struct *mm, unsigned
long addr,
}
-/* Set the dirty and/or accessed bits atomically in a linux PTE, this
- * function doesn't need to flush the hash entry
- */
+/* Set the dirty and/or accessed bits atomically in a linux PTE */
static inline void __ptep_set_access_flags(struct mm_struct *mm,
pte_t *ptep, pte_t entry,
unsigned long address)
--
2.13.3
[RFC PATCH v2 10/14] powerpc: fix includes in asm/processor.h
Remove superflous includes and add missing ones
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/hw_breakpoint.h | 1 +
arch/powerpc/include/asm/processor.h | 5 ++---
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/include/asm/hw_breakpoint.h
b/arch/powerpc/include/asm/hw_breakpoint.h
index 8e7b09703ca4..3637588d3f6d 100644
--- a/arch/powerpc/include/asm/hw_breakpoint.h
+++ b/arch/powerpc/include/asm/hw_breakpoint.h
@@ -55,6 +55,7 @@ struct arch_hw_breakpoint {
struct perf_event;
struct pmu;
struct perf_sample_data;
+struct task_struct;
#define HW_BREAKPOINT_ALIGN 0x7
diff --git a/arch/powerpc/include/asm/processor.h
b/arch/powerpc/include/asm/processor.h
index c4b36a494a63..74ed654928f0 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -39,10 +39,9 @@
#endif /* CONFIG_PPC64 */
#ifndef __ASSEMBLY__
-#include
-#include
+#include
+#include
#include
-#include
#include
/* We do _not_ want to define new machine types at all, those must die
--
2.13.3
[RFC PATCH v2 09/14] powerpc/book3s: Remove PPC_PIN_SIZE
PPC_PIN_SIZE is specific to the 44x and is defined in mmu.h Signed-off-by: Christophe Leroy --- arch/powerpc/include/asm/book3s/32/pgtable.h | 5 - arch/powerpc/include/asm/nohash/32/pgtable.h | 2 +- 2 files changed, 1 insertion(+), 6 deletions(-) diff --git a/arch/powerpc/include/asm/book3s/32/pgtable.h b/arch/powerpc/include/asm/book3s/32/pgtable.h index 231699ef6ebe..b3a538dc227a 100644 --- a/arch/powerpc/include/asm/book3s/32/pgtable.h +++ b/arch/powerpc/include/asm/book3s/32/pgtable.h @@ -84,17 +84,12 @@ * of RAM. -- Cort */ #define VMALLOC_OFFSET (0x100) /* 16M */ -#ifdef PPC_PIN_SIZE -#define VMALLOC_START (((_ALIGN((long)high_memory, PPC_PIN_SIZE) + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))) -#else #define VMALLOC_START long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))) -#endif #define VMALLOC_ENDioremap_bot #ifndef __ASSEMBLY__ #include #include -#include /* For sub-arch specific PPC_PIN_SIZE */ extern unsigned long ioremap_bot; diff --git a/arch/powerpc/include/asm/nohash/32/pgtable.h b/arch/powerpc/include/asm/nohash/32/pgtable.h index 62e48ecb9dcc..b2d0f3d0b097 100644 --- a/arch/powerpc/include/asm/nohash/32/pgtable.h +++ b/arch/powerpc/include/asm/nohash/32/pgtable.h @@ -8,7 +8,7 @@ #ifndef __ASSEMBLY__ #include #include -#include /* For sub-arch specific PPC_PIN_SIZE */ +#include/* For sub-arch specific PPC_PIN_SIZE */ #include extern unsigned long ioremap_bot; -- 2.13.3
[RFC PATCH v2 08/14] powerpc: declare set_breakpoint() static
set_breakpoint() is only used in process.c so make it static
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/debug.h | 1 -
arch/powerpc/kernel/process.c| 14 +++---
2 files changed, 7 insertions(+), 8 deletions(-)
diff --git a/arch/powerpc/include/asm/debug.h b/arch/powerpc/include/asm/debug.h
index ce5da214ffe5..7756026b95ca 100644
--- a/arch/powerpc/include/asm/debug.h
+++ b/arch/powerpc/include/asm/debug.h
@@ -45,7 +45,6 @@ static inline int debugger_break_match(struct pt_regs *regs)
{ return 0; }
static inline int debugger_fault_handler(struct pt_regs *regs) { return 0; }
#endif
-void set_breakpoint(struct arch_hw_breakpoint *brk);
void __set_breakpoint(struct arch_hw_breakpoint *brk);
bool ppc_breakpoint_available(void);
#ifdef CONFIG_PPC_ADV_DEBUG_REGS
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index 1237f13fed51..3e66cf6f7f95 100644
--- a/arch/powerpc/kernel/process.c
+++ b/arch/powerpc/kernel/process.c
@@ -714,6 +714,13 @@ void switch_booke_debug_regs(struct debug_reg *new_debug)
EXPORT_SYMBOL_GPL(switch_booke_debug_regs);
#else /* !CONFIG_PPC_ADV_DEBUG_REGS */
#ifndef CONFIG_HAVE_HW_BREAKPOINT
+static void set_breakpoint(struct arch_hw_breakpoint *brk)
+{
+ preempt_disable();
+ __set_breakpoint(brk);
+ preempt_enable();
+}
+
static void set_debug_reg_defaults(struct thread_struct *thread)
{
thread->hw_brk.address = 0;
@@ -826,13 +833,6 @@ void __set_breakpoint(struct arch_hw_breakpoint *brk)
WARN_ON_ONCE(1);
}
-void set_breakpoint(struct arch_hw_breakpoint *brk)
-{
- preempt_disable();
- __set_breakpoint(brk);
- preempt_enable();
-}
-
/* Check if we have DAWR or DABR hardware */
bool ppc_breakpoint_available(void)
{
--
2.13.3
[RFC PATCH v2 07/14] powerpc: remove superflous inclusions of asm/fixmap.h
Files not using fixmap consts or functions don't need asm/fixmap.h Signed-off-by: Christophe Leroy --- arch/powerpc/include/asm/fixmap.h| 2 -- arch/powerpc/kernel/head_8xx.S | 1 - arch/powerpc/mm/dump_hashpagetable.c | 1 - arch/powerpc/sysdev/cpm_common.c | 1 - 4 files changed, 5 deletions(-) diff --git a/arch/powerpc/include/asm/fixmap.h b/arch/powerpc/include/asm/fixmap.h index 6c40dfda5912..40efdf1d2d6e 100644 --- a/arch/powerpc/include/asm/fixmap.h +++ b/arch/powerpc/include/asm/fixmap.h @@ -15,9 +15,7 @@ #define _ASM_FIXMAP_H #ifndef __ASSEMBLY__ -#include #include -#include #ifdef CONFIG_HIGHMEM #include #include diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S index 6cab07e76732..95f6bdc0718f 100644 --- a/arch/powerpc/kernel/head_8xx.S +++ b/arch/powerpc/kernel/head_8xx.S @@ -30,7 +30,6 @@ #include #include #include -#include #include #if CONFIG_TASK_SIZE <= 0x8000 && CONFIG_PAGE_OFFSET >= 0x8000 diff --git a/arch/powerpc/mm/dump_hashpagetable.c b/arch/powerpc/mm/dump_hashpagetable.c index 14cfb11b09d0..ddffb1513ddc 100644 --- a/arch/powerpc/mm/dump_hashpagetable.c +++ b/arch/powerpc/mm/dump_hashpagetable.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/powerpc/sysdev/cpm_common.c b/arch/powerpc/sysdev/cpm_common.c index b74508175b67..010975c3422f 100644 --- a/arch/powerpc/sysdev/cpm_common.c +++ b/arch/powerpc/sysdev/cpm_common.c @@ -28,7 +28,6 @@ #include #include #include -#include #include #include -- 2.13.3
[RFC PATCH v2 06/14] powerpc: clean inclusions of asm/feature-fixups.h
files not using feature fixup don't need asm/feature-fixups.h files using feature fixup need asm/feature-fixups.h Signed-off-by: Christophe Leroy --- arch/powerpc/include/asm/cputable.h| 1 - arch/powerpc/include/asm/dbell.h | 1 + arch/powerpc/include/asm/dt_cpu_ftrs.h | 1 - arch/powerpc/include/asm/exception-64s.h | 1 + arch/powerpc/include/asm/firmware.h| 1 - arch/powerpc/include/asm/kvm_booke_hv_asm.h| 2 ++ arch/powerpc/include/asm/mmu.h | 1 - arch/powerpc/include/asm/ppc_asm.h | 1 + arch/powerpc/include/asm/reg.h | 1 + arch/powerpc/kernel/cpu_setup_6xx.S| 1 + arch/powerpc/kernel/entry_32.S | 1 + arch/powerpc/kernel/entry_64.S | 1 + arch/powerpc/kernel/exceptions-64e.S | 1 + arch/powerpc/kernel/exceptions-64s.S | 1 + arch/powerpc/kernel/fpu.S | 1 + arch/powerpc/kernel/head_32.S | 1 + arch/powerpc/kernel/head_64.S | 1 + arch/powerpc/kernel/head_fsl_booke.S | 1 + arch/powerpc/kernel/idle_6xx.S | 1 + arch/powerpc/kernel/idle_book3s.S | 1 + arch/powerpc/kernel/idle_e500.S| 1 + arch/powerpc/kernel/idle_power4.S | 1 + arch/powerpc/kernel/l2cr_6xx.S | 1 + arch/powerpc/kernel/misc_32.S | 1 + arch/powerpc/kernel/misc_64.S | 1 + arch/powerpc/kernel/setup_32.c | 1 + arch/powerpc/kernel/setup_64.c | 1 + arch/powerpc/kernel/swsusp_32.S| 1 + arch/powerpc/kernel/swsusp_asm64.S | 1 + arch/powerpc/kernel/tm.S | 1 + arch/powerpc/kvm/book3s_64_slb.S | 1 + arch/powerpc/kvm/book3s_hv_interrupts.S| 1 + arch/powerpc/kvm/book3s_hv_rmhandlers.S| 1 + arch/powerpc/kvm/book3s_segment.S | 1 + arch/powerpc/lib/copypage_64.S | 1 + arch/powerpc/lib/copyuser_64.S | 1 + arch/powerpc/lib/hweight_64.S | 1 + arch/powerpc/lib/memcpy_64.S | 1 + arch/powerpc/mm/hash_low_32.S | 1 + arch/powerpc/mm/hash_native_64.c | 1 + arch/powerpc/mm/slb_low.S | 1 + arch/powerpc/mm/tlb_low_64e.S | 1 + arch/powerpc/mm/tlb_nohash_low.S | 1 + arch/powerpc/platforms/powermac/cache.S| 1 + arch/powerpc/platforms/powermac/sleep.S| 1 + arch/powerpc/platforms/powernv/opal-wrappers.S | 1 + arch/powerpc/platforms/pseries/hvCall.S| 1 + 47 files changed, 44 insertions(+), 4 deletions(-) diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h index 5e29b8a2106a..c36360be2491 100644 --- a/arch/powerpc/include/asm/cputable.h +++ b/arch/powerpc/include/asm/cputable.h @@ -4,7 +4,6 @@ #include -#include #include #include diff --git a/arch/powerpc/include/asm/dbell.h b/arch/powerpc/include/asm/dbell.h index 998c42ff1caa..99b84db23e8c 100644 --- a/arch/powerpc/include/asm/dbell.h +++ b/arch/powerpc/include/asm/dbell.h @@ -16,6 +16,7 @@ #include #include +#include #define PPC_DBELL_MSG_BRDCAST (0x0400) #define PPC_DBELL_TYPE(x) (((x) & 0xf) << (63-36)) diff --git a/arch/powerpc/include/asm/dt_cpu_ftrs.h b/arch/powerpc/include/asm/dt_cpu_ftrs.h index 55113432fc91..0c729e2d0e8a 100644 --- a/arch/powerpc/include/asm/dt_cpu_ftrs.h +++ b/arch/powerpc/include/asm/dt_cpu_ftrs.h @@ -10,7 +10,6 @@ */ #include -#include #include #ifdef CONFIG_PPC_DT_CPU_FTRS diff --git a/arch/powerpc/include/asm/exception-64s.h b/arch/powerpc/include/asm/exception-64s.h index c40b4380951c..1f2efc1a9769 100644 --- a/arch/powerpc/include/asm/exception-64s.h +++ b/arch/powerpc/include/asm/exception-64s.h @@ -35,6 +35,7 @@ * implementations as possible. */ #include +#include /* PACA save area offsets (exgen, exmc, etc) */ #define EX_R9 0 diff --git a/arch/powerpc/include/asm/firmware.h b/arch/powerpc/include/asm/firmware.h index ce8aab72c21b..7a051bd21f87 100644 --- a/arch/powerpc/include/asm/firmware.h +++ b/arch/powerpc/include/asm/firmware.h @@ -14,7 +14,6 @@ #ifdef __KERNEL__ -#include #include /* firmware feature bitmask values */ diff --git a/arch/powerpc/include/asm/kvm_booke_hv_asm.h b/arch/powerpc/include/asm/kvm_booke_hv_asm.h index e5f048bbcb7c..931260b59ac6 100644 --- a/arch/powerpc/include/asm/kvm_booke_hv_asm.h +++ b/arch/powerpc/include/asm/kvm_booke_hv_asm.h @@ -9,6 +9,8 @@ #ifndef ASM_KVM_BOOKE_HV_ASM_H #define ASM_KVM_BOOKE_HV_ASM_H +#include + #ifdef __ASSEMBLY__ /* diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h index 8418d83b5eb0..13ea441ac531 100644 --- a/arch/powerpc/include/asm/mmu.h +++ b/arch/powerpc/include/asm/mmu.h @@ -5,7 +5,6 @@ #include -#include
[RFC PATCH v2 05/14] powerpc: clean the inclusion of stringify.h
Only include linux/stringify.h is files using __stringify()
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/dcr-native.h| 1 +
arch/powerpc/include/asm/ppc-opcode.h| 1 -
arch/powerpc/include/asm/reg_fsl_emb.h | 2 ++
arch/powerpc/include/asm/synch.h | 1 -
arch/powerpc/include/asm/thread_info.h | 1 -
arch/powerpc/kernel/prom.c | 1 -
arch/powerpc/kernel/prom_init.c | 1 -
arch/powerpc/kvm/book3s_64_vio_hv.c | 1 +
arch/powerpc/lib/locks.c | 1 -
arch/powerpc/perf/req-gen/_begin.h | 2 ++
arch/powerpc/perf/req-gen/perf.h | 1 +
arch/powerpc/platforms/cell/cbe_thermal.c| 1 +
arch/powerpc/platforms/cell/spufs/sputrace.h | 1 +
arch/powerpc/platforms/powernv/vas.h | 1 +
arch/powerpc/platforms/pseries/mobility.c| 1 +
15 files changed, 11 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/include/asm/dcr-native.h
b/arch/powerpc/include/asm/dcr-native.h
index 4a2beef74277..151dff555f50 100644
--- a/arch/powerpc/include/asm/dcr-native.h
+++ b/arch/powerpc/include/asm/dcr-native.h
@@ -25,6 +25,7 @@
#include
#include
#include
+#include
typedef struct {
unsigned int base;
diff --git a/arch/powerpc/include/asm/ppc-opcode.h
b/arch/powerpc/include/asm/ppc-opcode.h
index 68d916ae1986..04a03da18602 100644
--- a/arch/powerpc/include/asm/ppc-opcode.h
+++ b/arch/powerpc/include/asm/ppc-opcode.h
@@ -12,7 +12,6 @@
#ifndef _ASM_POWERPC_PPC_OPCODE_H
#define _ASM_POWERPC_PPC_OPCODE_H
-#include
#include
#define__REG_R00
diff --git a/arch/powerpc/include/asm/reg_fsl_emb.h
b/arch/powerpc/include/asm/reg_fsl_emb.h
index d7ccf93e6279..a21f529c43d9 100644
--- a/arch/powerpc/include/asm/reg_fsl_emb.h
+++ b/arch/powerpc/include/asm/reg_fsl_emb.h
@@ -7,6 +7,8 @@
#ifndef __ASM_POWERPC_REG_FSL_EMB_H__
#define __ASM_POWERPC_REG_FSL_EMB_H__
+#include
+
#ifndef __ASSEMBLY__
/* Performance Monitor Registers */
#define mfpmr(rn) ({unsigned int rval; \
diff --git a/arch/powerpc/include/asm/synch.h b/arch/powerpc/include/asm/synch.h
index f6f8c75bbb24..aca70fb43147 100644
--- a/arch/powerpc/include/asm/synch.h
+++ b/arch/powerpc/include/asm/synch.h
@@ -3,7 +3,6 @@
#define _ASM_POWERPC_SYNCH_H
#ifdef __KERNEL__
-#include
#include
#include
diff --git a/arch/powerpc/include/asm/thread_info.h
b/arch/powerpc/include/asm/thread_info.h
index 7b464fcbdb35..60c78b9af82e 100644
--- a/arch/powerpc/include/asm/thread_info.h
+++ b/arch/powerpc/include/asm/thread_info.h
@@ -27,7 +27,6 @@
#include
#include
#include
-#include
#include
/*
diff --git a/arch/powerpc/kernel/prom.c b/arch/powerpc/kernel/prom.c
index 05e7fb47a7a4..60ccf08d3a08 100644
--- a/arch/powerpc/kernel/prom.c
+++ b/arch/powerpc/kernel/prom.c
@@ -23,7 +23,6 @@
#include
#include
#include
-#include
#include
#include
#include
diff --git a/arch/powerpc/kernel/prom_init.c b/arch/powerpc/kernel/prom_init.c
index 425992e393bc..59cc00414721 100644
--- a/arch/powerpc/kernel/prom_init.c
+++ b/arch/powerpc/kernel/prom_init.c
@@ -27,7 +27,6 @@
#include
#include
#include
-#include
#include
#include
#include
diff --git a/arch/powerpc/kvm/book3s_64_vio_hv.c
b/arch/powerpc/kvm/book3s_64_vio_hv.c
index 6651f736a0b1..76cb20ffc201 100644
--- a/arch/powerpc/kvm/book3s_64_vio_hv.c
+++ b/arch/powerpc/kvm/book3s_64_vio_hv.c
@@ -26,6 +26,7 @@
#include
#include
#include
+#include
#include
#include
diff --git a/arch/powerpc/lib/locks.c b/arch/powerpc/lib/locks.c
index b7b1237d4aa6..35a0ef932e1a 100644
--- a/arch/powerpc/lib/locks.c
+++ b/arch/powerpc/lib/locks.c
@@ -15,7 +15,6 @@
#include
#include
#include
-#include
#include
/* waiting for a spinlock... */
diff --git a/arch/powerpc/perf/req-gen/_begin.h
b/arch/powerpc/perf/req-gen/_begin.h
index 549f8782c52d..a200b86eba3b 100644
--- a/arch/powerpc/perf/req-gen/_begin.h
+++ b/arch/powerpc/perf/req-gen/_begin.h
@@ -3,6 +3,8 @@
#ifndef POWERPC_PERF_REQ_GEN_H_
#define POWERPC_PERF_REQ_GEN_H_
+#include
+
#define CAT2_STR_(t, s) __stringify(t/s)
#define CAT2_STR(t, s) CAT2_STR_(t, s)
#define I(...) __VA_ARGS__
diff --git a/arch/powerpc/perf/req-gen/perf.h b/arch/powerpc/perf/req-gen/perf.h
index 871a9a1766c2..fa9bc804e67a 100644
--- a/arch/powerpc/perf/req-gen/perf.h
+++ b/arch/powerpc/perf/req-gen/perf.h
@@ -3,6 +3,7 @@
#define LINUX_POWERPC_PERF_REQ_GEN_PERF_H_
#include
+#include
#ifndef REQUEST_FILE
#error "REQUEST_FILE must be defined before including"
diff --git a/arch/powerpc/platforms/cell/cbe_thermal.c
b/arch/powerpc/platforms/cell/cbe_thermal.c
index 2c15ff094483..55aac74e1cb9 100644
--- a/arch/powerpc/platforms/cell/cbe_thermal.c
+++ b/arch/powerpc/platforms/cell/cbe_thermal.c
@@ -49,6 +49,7 @@
#include
#include
#include
+#include
#include
#include
#include
diff --git a/arch/powerpc/platforms/cell/spufs/sputrace.h
[RFC PATCH v2 04/14] powerpc: move ASM_CONST and stringify_in_c() into asm-const.h
This patch moves ASM_CONST() and stringify_in_c() into dedicated asm-const.h, then cleans all related inclusions. Signed-off-by: Christophe Leroy --- arch/powerpc/crypto/md5-asm.S | 1 + arch/powerpc/crypto/sha1-powerpc-asm.S | 1 + arch/powerpc/include/asm/asm-compat.h | 13 + arch/powerpc/include/asm/asm-const.h | 14 ++ arch/powerpc/include/asm/barrier.h | 2 ++ arch/powerpc/include/asm/book3s/64/hash.h | 2 ++ arch/powerpc/include/asm/book3s/64/mmu-hash.h | 2 +- arch/powerpc/include/asm/book3s/64/radix.h | 2 ++ arch/powerpc/include/asm/cmpxchg.h | 1 - arch/powerpc/include/asm/code-patching.h | 1 + arch/powerpc/include/asm/cputable.h| 2 +- arch/powerpc/include/asm/dt_cpu_ftrs.h | 1 - arch/powerpc/include/asm/feature-fixups.h | 2 ++ arch/powerpc/include/asm/firmware.h| 2 +- arch/powerpc/include/asm/futex.h | 1 - arch/powerpc/include/asm/iommu.h | 1 + arch/powerpc/include/asm/jump_label.h | 2 +- arch/powerpc/include/asm/mmu-44x.h | 1 + arch/powerpc/include/asm/mmu.h | 2 +- arch/powerpc/include/asm/nohash/64/pgtable.h | 1 + arch/powerpc/include/asm/page.h| 2 +- arch/powerpc/include/asm/page_64.h | 2 ++ arch/powerpc/include/asm/ppc-opcode.h | 2 +- arch/powerpc/include/asm/ptrace.h | 1 + arch/powerpc/include/asm/reg.h | 1 + arch/powerpc/include/asm/reg_a2.h | 2 ++ arch/powerpc/include/asm/spinlock.h| 1 - arch/powerpc/include/asm/synch.h | 1 + arch/powerpc/include/asm/thread_info.h | 2 ++ arch/powerpc/include/asm/uaccess.h | 1 - arch/powerpc/kernel/entry_64.S | 1 + arch/powerpc/kernel/fpu.S | 1 + arch/powerpc/kernel/idle_book3s.S | 1 + arch/powerpc/kernel/kvm_emul.S | 1 + arch/powerpc/kernel/ppc_save_regs.S| 1 + arch/powerpc/kernel/vector.S | 1 + arch/powerpc/kvm/book3s_64_slb.S | 2 ++ arch/powerpc/kvm/book3s_hv_interrupts.S| 1 + arch/powerpc/kvm/book3s_hv_rmhandlers.S| 1 + arch/powerpc/kvm/book3s_interrupts.S | 1 + arch/powerpc/kvm/book3s_rmhandlers.S | 1 + arch/powerpc/kvm/book3s_segment.S | 2 ++ arch/powerpc/lib/copyuser_64.S | 1 + arch/powerpc/lib/feature-fixups-test.S | 1 + arch/powerpc/lib/ldstfp.S | 1 + arch/powerpc/lib/memcpy_64.S | 1 + arch/powerpc/lib/string.S | 1 + arch/powerpc/mm/tlb_nohash_low.S | 1 + arch/powerpc/net/bpf_jit32.h | 1 + arch/powerpc/net/bpf_jit_asm.S | 1 + arch/powerpc/net/bpf_jit_asm64.S | 1 + arch/powerpc/net/bpf_jit_comp.c| 1 + arch/powerpc/net/bpf_jit_comp64.c | 1 + arch/powerpc/platforms/powernv/opal-wrappers.S | 1 + arch/powerpc/platforms/pseries/setup.c | 1 + arch/powerpc/purgatory/trampoline.S| 10 +- arch/powerpc/xmon/spr_access.S | 1 + 57 files changed, 74 insertions(+), 33 deletions(-) create mode 100644 arch/powerpc/include/asm/asm-const.h diff --git a/arch/powerpc/crypto/md5-asm.S b/arch/powerpc/crypto/md5-asm.S index 10cdf5bceebb..1834065362c7 100644 --- a/arch/powerpc/crypto/md5-asm.S +++ b/arch/powerpc/crypto/md5-asm.S @@ -11,6 +11,7 @@ */ #include #include +#include #define rHPr3 #define rWPr4 diff --git a/arch/powerpc/crypto/sha1-powerpc-asm.S b/arch/powerpc/crypto/sha1-powerpc-asm.S index c8951ce0dcc4..23e248beff71 100644 --- a/arch/powerpc/crypto/sha1-powerpc-asm.S +++ b/arch/powerpc/crypto/sha1-powerpc-asm.S @@ -7,6 +7,7 @@ #include #include +#include #ifdef __BIG_ENDIAN__ #define LWZ(rt, d, ra) \ diff --git a/arch/powerpc/include/asm/asm-compat.h b/arch/powerpc/include/asm/asm-compat.h index d2cf3593e987..09f8dd4da883 100644 --- a/arch/powerpc/include/asm/asm-compat.h +++ b/arch/powerpc/include/asm/asm-compat.h @@ -1,21 +1,10 @@ #ifndef _ASM_POWERPC_ASM_COMPAT_H #define _ASM_POWERPC_ASM_COMPAT_H +#include #include #include -#ifdef __ASSEMBLY__ -# define stringify_in_c(...) __VA_ARGS__ -# define ASM_CONST(x) x -#else -/* This version of stringify will deal with commas... */ -# define __stringify_in_c(...)#__VA_ARGS__ -# define stringify_in_c(...) __stringify_in_c(__VA_ARGS__) " " -# define __ASM_CONST(x) x##UL -# define ASM_CONST(x) __ASM_CONST(x) -#endif - - #ifdef __powerpc64__ /* operations for longs and pointers */ diff --git a/arch/powerpc/include/asm/asm-const.h b/arch/powerpc/include/asm/asm-const.h new file mode 100644 index ..082c1538c562 ---
[RFC PATCH v2 03/14] powerpc/405: move PPC405_ERR77 in asm-405.h
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/asm-405.h | 19 +++
arch/powerpc/include/asm/asm-compat.h| 13 -
arch/powerpc/include/asm/atomic.h| 1 +
arch/powerpc/include/asm/bitops.h| 1 +
arch/powerpc/include/asm/book3s/32/pgtable.h | 2 --
arch/powerpc/include/asm/cmpxchg.h | 1 +
arch/powerpc/include/asm/futex.h | 1 +
arch/powerpc/include/asm/nohash/32/pgtable.h | 1 +
arch/powerpc/include/asm/spinlock.h | 1 +
arch/powerpc/kernel/entry_32.S | 1 +
arch/powerpc/kernel/head_40x.S | 1 +
11 files changed, 27 insertions(+), 15 deletions(-)
create mode 100644 arch/powerpc/include/asm/asm-405.h
diff --git a/arch/powerpc/include/asm/asm-405.h
b/arch/powerpc/include/asm/asm-405.h
new file mode 100644
index ..7270d3ae7c8e
--- /dev/null
+++ b/arch/powerpc/include/asm/asm-405.h
@@ -0,0 +1,19 @@
+#ifndef _ASM_POWERPC_ASM_405_H
+#define _ASM_POWERPC_ASM_405_H
+
+#include
+
+#ifdef __KERNEL__
+#ifdef CONFIG_IBM405_ERR77
+/* Erratum #77 on the 405 means we need a sync or dcbt before every
+ * stwcx. The old ATOMIC_SYNC_FIX covered some but not all of this.
+ */
+#define PPC405_ERR77(ra,rb)stringify_in_c(dcbt ra, rb;)
+#definePPC405_ERR77_SYNC stringify_in_c(sync;)
+#else
+#define PPC405_ERR77(ra,rb)
+#define PPC405_ERR77_SYNC
+#endif
+#endif
+
+#endif /* _ASM_POWERPC_ASM_405_H */
diff --git a/arch/powerpc/include/asm/asm-compat.h
b/arch/powerpc/include/asm/asm-compat.h
index 7f2a7702596c..d2cf3593e987 100644
--- a/arch/powerpc/include/asm/asm-compat.h
+++ b/arch/powerpc/include/asm/asm-compat.h
@@ -70,17 +70,4 @@
#endif
-#ifdef __KERNEL__
-#ifdef CONFIG_IBM405_ERR77
-/* Erratum #77 on the 405 means we need a sync or dcbt before every
- * stwcx. The old ATOMIC_SYNC_FIX covered some but not all of this.
- */
-#define PPC405_ERR77(ra,rb)stringify_in_c(dcbt ra, rb;)
-#definePPC405_ERR77_SYNC stringify_in_c(sync;)
-#else
-#define PPC405_ERR77(ra,rb)
-#define PPC405_ERR77_SYNC
-#endif
-#endif
-
#endif /* _ASM_POWERPC_ASM_COMPAT_H */
diff --git a/arch/powerpc/include/asm/atomic.h
b/arch/powerpc/include/asm/atomic.h
index 682b3e6a1e21..cbdb0b7e60a3 100644
--- a/arch/powerpc/include/asm/atomic.h
+++ b/arch/powerpc/include/asm/atomic.h
@@ -10,6 +10,7 @@
#include
#include
#include
+#include
#define ATOMIC_INIT(i) { (i) }
diff --git a/arch/powerpc/include/asm/bitops.h
b/arch/powerpc/include/asm/bitops.h
index b750ffef83c7..ff71566dadee 100644
--- a/arch/powerpc/include/asm/bitops.h
+++ b/arch/powerpc/include/asm/bitops.h
@@ -45,6 +45,7 @@
#include
#include
#include
+#include
/* PPC bit number conversion */
#define PPC_BITLSHIFT(be) (BITS_PER_LONG - 1 - (be))
diff --git a/arch/powerpc/include/asm/book3s/32/pgtable.h
b/arch/powerpc/include/asm/book3s/32/pgtable.h
index c615abdce119..231699ef6ebe 100644
--- a/arch/powerpc/include/asm/book3s/32/pgtable.h
+++ b/arch/powerpc/include/asm/book3s/32/pgtable.h
@@ -164,7 +164,6 @@ static inline unsigned long pte_update(pte_t *p,
1: lwarx %0,0,%3\n\
andc%1,%0,%4\n\
or %1,%1,%5\n"
- PPC405_ERR77(0,%3)
" stwcx. %1,0,%3\n\
bne-1b"
: "=" (old), "=" (tmp), "=m" (*p)
@@ -186,7 +185,6 @@ static inline unsigned long long pte_update(pte_t *p,
lwzx%0,0,%3\n\
andc%1,%L0,%5\n\
or %1,%1,%6\n"
- PPC405_ERR77(0,%3)
" stwcx. %1,0,%4\n\
bne-1b"
: "=" (old), "=" (tmp), "=m" (*p)
diff --git a/arch/powerpc/include/asm/cmpxchg.h
b/arch/powerpc/include/asm/cmpxchg.h
index 9b001f1f6b32..67ec1073ac97 100644
--- a/arch/powerpc/include/asm/cmpxchg.h
+++ b/arch/powerpc/include/asm/cmpxchg.h
@@ -7,6 +7,7 @@
#include
#include
#include
+#include
#ifdef __BIG_ENDIAN
#define BITOFF_CAL(size, off) ((sizeof(u32) - size - off) * BITS_PER_BYTE)
diff --git a/arch/powerpc/include/asm/futex.h b/arch/powerpc/include/asm/futex.h
index 1a944c18c539..76c8648d0fa8 100644
--- a/arch/powerpc/include/asm/futex.h
+++ b/arch/powerpc/include/asm/futex.h
@@ -9,6 +9,7 @@
#include
#include
#include
+#include
#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \
__asm__ __volatile ( \
diff --git a/arch/powerpc/include/asm/nohash/32/pgtable.h
b/arch/powerpc/include/asm/nohash/32/pgtable.h
index 987a658b18e1..62e48ecb9dcc 100644
--- a/arch/powerpc/include/asm/nohash/32/pgtable.h
+++ b/arch/powerpc/include/asm/nohash/32/pgtable.h
@@ -9,6 +9,7 @@
#include
#include
#include /* For sub-arch specific PPC_PIN_SIZE */
+#include
extern unsigned long ioremap_bot;
diff --git a/arch/powerpc/include/asm/spinlock.h
b/arch/powerpc/include/asm/spinlock.h
index 72dc4ddc2972..7ec38f4ee927 100644
--- a/arch/powerpc/include/asm/spinlock.h
+++ b/arch/powerpc/include/asm/spinlock.h
@@ -27,6 +27,7 @@
[RFC PATCH v2 02/14] powerpc: remove unneeded inclusions of cpu_has_feature.h
Files not using cpu_has_feature() don't need cpu_has_feature.h Signed-off-by: Christophe Leroy --- arch/powerpc/include/asm/cacheflush.h | 1 - arch/powerpc/include/asm/cputime.h| 1 - arch/powerpc/include/asm/dbell.h | 1 - arch/powerpc/kernel/vdso.c| 1 - 4 files changed, 4 deletions(-) diff --git a/arch/powerpc/include/asm/cacheflush.h b/arch/powerpc/include/asm/cacheflush.h index 11843e37d9cf..cfe3a98349c4 100644 --- a/arch/powerpc/include/asm/cacheflush.h +++ b/arch/powerpc/include/asm/cacheflush.h @@ -11,7 +11,6 @@ #include #include -#include /* * No cache flushing is required when address mappings are changed, diff --git a/arch/powerpc/include/asm/cputime.h b/arch/powerpc/include/asm/cputime.h index 99b541865d8d..d78fee0cdbf0 100644 --- a/arch/powerpc/include/asm/cputime.h +++ b/arch/powerpc/include/asm/cputime.h @@ -23,7 +23,6 @@ #include #include #include -#include typedef u64 __nocast cputime_t; typedef u64 __nocast cputime64_t; diff --git a/arch/powerpc/include/asm/dbell.h b/arch/powerpc/include/asm/dbell.h index 9f2ae0d25e15..998c42ff1caa 100644 --- a/arch/powerpc/include/asm/dbell.h +++ b/arch/powerpc/include/asm/dbell.h @@ -16,7 +16,6 @@ #include #include -#include #define PPC_DBELL_MSG_BRDCAST (0x0400) #define PPC_DBELL_TYPE(x) (((x) & 0xf) << (63-36)) diff --git a/arch/powerpc/kernel/vdso.c b/arch/powerpc/kernel/vdso.c index b44ec104a5a1..63b4e4485b00 100644 --- a/arch/powerpc/kernel/vdso.c +++ b/arch/powerpc/kernel/vdso.c @@ -22,7 +22,6 @@ #include #include -#include #include #include #include -- 2.13.3
[RFC PATCH v2 01/14] powerpc: remove kdump.h from page.h
page.h doesn't need kdump.h Signed-off-by: Christophe Leroy --- arch/powerpc/include/asm/page.h | 1 - arch/powerpc/kernel/crash.c | 1 - arch/powerpc/kernel/machine_kexec.c | 1 + arch/powerpc/kernel/setup_32.c | 1 + 4 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/include/asm/page.h b/arch/powerpc/include/asm/page.h index db7be0779d55..a9fbefaacf10 100644 --- a/arch/powerpc/include/asm/page.h +++ b/arch/powerpc/include/asm/page.h @@ -17,7 +17,6 @@ #include #endif #include -#include /* * On regular PPC32 page size is 4K (but we support 4K/16K/64K/256K pages diff --git a/arch/powerpc/kernel/crash.c b/arch/powerpc/kernel/crash.c index 17c8b99680f2..43a3ce2301e8 100644 --- a/arch/powerpc/kernel/crash.c +++ b/arch/powerpc/kernel/crash.c @@ -23,7 +23,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/powerpc/kernel/machine_kexec.c b/arch/powerpc/kernel/machine_kexec.c index 936c7e2d421e..e530cbd48995 100644 --- a/arch/powerpc/kernel/machine_kexec.c +++ b/arch/powerpc/kernel/machine_kexec.c @@ -17,6 +17,7 @@ #include #include +#include #include #include #include diff --git a/arch/powerpc/kernel/setup_32.c b/arch/powerpc/kernel/setup_32.c index 74457485574b..ef747a5a30b9 100644 --- a/arch/powerpc/kernel/setup_32.c +++ b/arch/powerpc/kernel/setup_32.c @@ -40,6 +40,7 @@ #include #include #include +#include #define DBG(fmt...) -- 2.13.3
[RFC PATCH v2 00/14] Remove unneccessary included headers
The purpose of this serie is to limit the number of includes to
only the necessary ones in order to reduce the number of files
recompiled everytime a header file is modified.
This is the start of the work, please provide feedback if any so
that I don't go in the wrong direction.
Handled inclusion changes more carrefully after Michael feedback.
Started splitting some headers in order to reduce their coverage.
Christophe Leroy (14):
powerpc: remove kdump.h from page.h
powerpc: remove unneeded inclusions of cpu_has_feature.h
powerpc/405: move PPC405_ERR77 in asm-405.h
powerpc: move ASM_CONST and stringify_in_c() into asm-const.h
powerpc: clean the inclusion of stringify.h
powerpc: clean inclusions of asm/feature-fixups.h
powerpc: remove superflous inclusions of asm/fixmap.h
powerpc: declare set_breakpoint() static
powerpc/book3s: Remove PPC_PIN_SIZE
powerpc: fix includes in asm/processor.h
powerpc/nohash: fix hash related comments in pgtable.h
powerpc/44x: remove page.h from mmu-44x.h
powerpc: split reg.h in two parts
powerpc: Split synch.h in two parts
arch/powerpc/crypto/md5-asm.S | 1 +
arch/powerpc/crypto/sha1-powerpc-asm.S| 1 +
arch/powerpc/include/asm/asm-405.h| 19 +++
arch/powerpc/include/asm/asm-compat.h | 26 +-
arch/powerpc/include/asm/asm-const.h | 14 +
arch/powerpc/include/asm/atomic.h | 2 +
arch/powerpc/include/asm/barrier.h| 3 ++
arch/powerpc/include/asm/bitops.h | 2 +
arch/powerpc/include/asm/book3s/32/pgtable.h | 7 ---
arch/powerpc/include/asm/book3s/64/hash.h | 2 +
arch/powerpc/include/asm/book3s/64/mmu-hash.h | 2 +-
arch/powerpc/include/asm/book3s/64/radix.h| 2 +
arch/powerpc/include/asm/cacheflush.h | 1 -
arch/powerpc/include/asm/cmpxchg.h| 3 +-
arch/powerpc/include/asm/code-patching.h | 1 +
arch/powerpc/include/asm/cputable.h | 3 +-
arch/powerpc/include/asm/cputime.h| 1 -
arch/powerpc/include/asm/dbell.h | 2 +-
arch/powerpc/include/asm/dcr-native.h | 1 +
arch/powerpc/include/asm/debug.h | 1 -
arch/powerpc/include/asm/dt_cpu_ftrs.h| 2 -
arch/powerpc/include/asm/exception-64s.h | 2 +
arch/powerpc/include/asm/feature-fixups.h | 2 +
arch/powerpc/include/asm/firmware.h | 3 +-
arch/powerpc/include/asm/fixmap.h | 2 -
arch/powerpc/include/asm/futex.h | 2 +-
arch/powerpc/include/asm/hw_breakpoint.h | 1 +
arch/powerpc/include/asm/iommu.h | 1 +
arch/powerpc/include/asm/jump_label.h | 2 +-
arch/powerpc/include/asm/kvm_booke_hv_asm.h | 2 +
arch/powerpc/include/asm/mmu-44x.h| 11 ++--
arch/powerpc/include/asm/mmu.h| 3 +-
arch/powerpc/include/asm/nohash/32/pgtable.h | 7 +--
arch/powerpc/include/asm/nohash/64/pgtable.h | 19 ++-
arch/powerpc/include/asm/page.h | 3 +-
arch/powerpc/include/asm/page_64.h| 2 +
arch/powerpc/include/asm/ppc-opcode.h | 3 +-
arch/powerpc/include/asm/ppc_asm.h| 1 +
arch/powerpc/include/asm/processor.h | 5 +-
arch/powerpc/include/asm/ptrace.h | 1 +
arch/powerpc/include/asm/reg-ftr.h| 63 +++
arch/powerpc/include/asm/reg.h| 36 +
arch/powerpc/include/asm/reg_a2.h | 2 +
arch/powerpc/include/asm/reg_fsl_emb.h| 2 +
arch/powerpc/include/asm/spinlock.h | 3 +-
arch/powerpc/include/asm/{synch.h => synch-ftr.h} | 24 ++---
arch/powerpc/include/asm/synch.h | 30 ---
arch/powerpc/include/asm/thread_info.h| 3 +-
arch/powerpc/include/asm/uaccess.h| 1 -
arch/powerpc/kernel/cpu_setup_6xx.S | 1 +
arch/powerpc/kernel/crash.c | 1 -
arch/powerpc/kernel/entry_32.S| 2 +
arch/powerpc/kernel/entry_64.S| 3 ++
arch/powerpc/kernel/exceptions-64e.S | 1 +
arch/powerpc/kernel/exceptions-64s.S | 2 +
arch/powerpc/kernel/fpu.S | 2 +
arch/powerpc/kernel/head_32.S | 1 +
arch/powerpc/kernel/head_40x.S| 1 +
arch/powerpc/kernel/head_64.S | 2 +
arch/powerpc/kernel/head_8xx.S| 1 -
arch/powerpc/kernel/head_fsl_booke.S | 1 +
arch/powerpc/kernel/idle_6xx.S| 1 +
arch/powerpc/kernel/idle_book3s.S | 3 ++
arch/powerpc/kernel/idle_e500.S | 1 +
arch/powerpc/kernel/idle_power4.S | 1 +
[PATCH v4] powerpc: fix build failure by disabling attribute-alias warning
Latest GCC version emit the following warnings
As arch/powerpc code is built with -Werror, this breaks build with
GCC 8.1
This patch inhibits those warnings
CC arch/powerpc/kernel/syscalls.o
In file included from arch/powerpc/kernel/syscalls.c:24:
./include/linux/syscalls.h:233:18: error: 'sys_mmap2' alias between functions
of incompatible types 'long int(long unsigned int, size_t, long unsigned int,
long unsigned int, long unsigned int, long unsigned int)' {aka 'long
int(long unsigned int, long unsigned int, long unsigned int, long unsigned
int, long unsigned int, long unsigned int)'} and 'long int(long int, long
int, long int, long int, long int, long int)' [-Werror=attribute-alias]
asmlinkage long sys##name(__MAP(x,__SC_DECL,__VA_ARGS__)) \
^~~
./include/linux/syscalls.h:222:2: note: in expansion of macro
'__SYSCALL_DEFINEx'
__SYSCALL_DEFINEx(x, sname, __VA_ARGS__)
^
./include/linux/syscalls.h:216:36: note: in expansion of macro 'SYSCALL_DEFINEx'
#define SYSCALL_DEFINE6(name, ...) SYSCALL_DEFINEx(6, _##name, __VA_ARGS__)
^~~
arch/powerpc/kernel/syscalls.c:65:1: note: in expansion of macro
'SYSCALL_DEFINE6'
SYSCALL_DEFINE6(mmap2, unsigned long, addr, size_t, len,
^~~
./include/linux/syscalls.h:238:18: note: aliased declaration here
asmlinkage long __se_sys##name(__MAP(x,__SC_LONG,__VA_ARGS__)) \
^~~~
./include/linux/syscalls.h:222:2: note: in expansion of macro
'__SYSCALL_DEFINEx'
__SYSCALL_DEFINEx(x, sname, __VA_ARGS__)
^
./include/linux/syscalls.h:216:36: note: in expansion of macro 'SYSCALL_DEFINEx'
#define SYSCALL_DEFINE6(name, ...) SYSCALL_DEFINEx(6, _##name, __VA_ARGS__)
^~~
arch/powerpc/kernel/syscalls.c:65:1: note: in expansion of macro
'SYSCALL_DEFINE6'
SYSCALL_DEFINE6(mmap2, unsigned long, addr, size_t, len,
^~~
./include/linux/syscalls.h:233:18: error: 'sys_mmap' alias between functions of
incompatible types 'long int(long unsigned int, size_t, long unsigned int,
long unsigned int, long unsigned int, off_t)' {aka 'long int(long unsigned
int, long unsigned int, long unsigned int, long unsigned int, long unsigned
int, long int)'} and 'long int(long int, long int, long int, long int,
long int, long int)' [-Werror=attribute-alias]
asmlinkage long sys##name(__MAP(x,__SC_DECL,__VA_ARGS__)) \
^~~
./include/linux/syscalls.h:222:2: note: in expansion of macro
'__SYSCALL_DEFINEx'
__SYSCALL_DEFINEx(x, sname, __VA_ARGS__)
^
./include/linux/syscalls.h:216:36: note: in expansion of macro 'SYSCALL_DEFINEx'
#define SYSCALL_DEFINE6(name, ...) SYSCALL_DEFINEx(6, _##name, __VA_ARGS__)
^~~
arch/powerpc/kernel/syscalls.c:72:1: note: in expansion of macro
'SYSCALL_DEFINE6'
SYSCALL_DEFINE6(mmap, unsigned long, addr, size_t, len,
^~~
./include/linux/syscalls.h:238:18: note: aliased declaration here
asmlinkage long __se_sys##name(__MAP(x,__SC_LONG,__VA_ARGS__)) \
^~~~
./include/linux/syscalls.h:222:2: note: in expansion of macro
'__SYSCALL_DEFINEx'
__SYSCALL_DEFINEx(x, sname, __VA_ARGS__)
^
./include/linux/syscalls.h:216:36: note: in expansion of macro 'SYSCALL_DEFINEx'
#define SYSCALL_DEFINE6(name, ...) SYSCALL_DEFINEx(6, _##name, __VA_ARGS__)
^~~
arch/powerpc/kernel/syscalls.c:72:1: note: in expansion of macro
'SYSCALL_DEFINE6'
SYSCALL_DEFINE6(mmap, unsigned long, addr, size_t, len,
^~~
CC arch/powerpc/kernel/signal_32.o
In file included from arch/powerpc/kernel/signal_32.c:31:
./include/linux/compat.h:74:18: error: 'compat_sys_swapcontext' alias between
functions of incompatible types 'long int(struct ucontext32 *, struct
ucontext32 *, int)' and 'long int(long int, long int, long int)'
[-Werror=attribute-alias]
asmlinkage long compat_sys##name(__MAP(x,__SC_DECL,__VA_ARGS__)) \
^~
./include/linux/compat.h:58:2: note: in expansion of macro
'COMPAT_SYSCALL_DEFINEx'
COMPAT_SYSCALL_DEFINEx(3, _##name, __VA_ARGS__)
^~
arch/powerpc/kernel/signal_32.c:1041:1: note: in expansion of macro
'COMPAT_SYSCALL_DEFINE3'
COMPAT_SYSCALL_DEFINE3(swapcontext, struct ucontext __user *, old_ctx,
^~
./include/linux/compat.h:79:18: note: aliased declaration here
asmlinkage long __se_compat_sys##name(__MAP(x,__SC_LONG,__VA_ARGS__)) \
^~~
./include/linux/compat.h:58:2: note: in expansion of macro
'COMPAT_SYSCALL_DEFINEx'
COMPAT_SYSCALL_DEFINEx(3, _##name, __VA_ARGS__)
^~
arch/powerpc/kernel/signal_32.c:1041:1: note: in expansion of macro
'COMPAT_SYSCALL_DEFINE3'
COMPAT_SYSCALL_DEFINE3(swapcontext, struct ucontext __user *,
Re: [PATCH v2 07/13] powerpc/eeh: Clean up pci_ers_result handling
Sam Bobroff writes:
> As EEH event handling progresses, a cumulative result of type
> pci_ers_result is built up by (some of) the eeh_report_*() functions
> using either:
> if (rc == PCI_ERS_RESULT_NEED_RESET) *res = rc;
> if (*res == PCI_ERS_RESULT_NONE) *res = rc;
> or:
> if ((*res == PCI_ERS_RESULT_NONE) ||
> (*res == PCI_ERS_RESULT_RECOVERED)) *res = rc;
> if (*res == PCI_ERS_RESULT_DISCONNECT &&
> rc == PCI_ERS_RESULT_NEED_RESET) *res = rc;
> (Where *res is the accumulator.)
>
> However, the intent is not immediately clear and the result in some
> situations is order dependent.
>
> Address this by assigning a priority to each result value, and always
> merging to the highest priority. This renders the intent clear, and
> provides a stable value for all orderings.
>
> Signed-off-by: Sam Bobroff
> ---
> == v1 -> v2: ==
>
> * Added the value, and missing newline, to some WARN()s.
> * Improved name of merge_result() to pci_ers_merge_result().
> * Adjusted the result priorities so that unknown doesn't overlap with _NONE.
These === markers seem to have confused patchwork, they ended up in the
patch, and then git put them in the changelog.
http://patchwork.ozlabs.org/patch/920194/
The usual format is just something like:
v2 - Added the value, and missing newline, to some WARN()s.
- Improved name of merge_result() to pci_ers_merge_result().
- Adjusted the result priorities so that unknown doesn't overlap with _NONE.
cheers
> arch/powerpc/kernel/eeh_driver.c | 36 ++--
> 1 file changed, 26 insertions(+), 10 deletions(-)
>
> diff --git a/arch/powerpc/kernel/eeh_driver.c
> b/arch/powerpc/kernel/eeh_driver.c
> index 188d15c4fe3a..2d3cac584899 100644
> --- a/arch/powerpc/kernel/eeh_driver.c
> +++ b/arch/powerpc/kernel/eeh_driver.c
> @@ -39,6 +39,29 @@ struct eeh_rmv_data {
> int removed;
> };
>
> +static int eeh_result_priority(enum pci_ers_result result)
> +{
> + switch (result) {
> + case PCI_ERS_RESULT_NONE: return 1;
> + case PCI_ERS_RESULT_NO_AER_DRIVER: return 2;
> + case PCI_ERS_RESULT_RECOVERED: return 3;
> + case PCI_ERS_RESULT_CAN_RECOVER: return 4;
> + case PCI_ERS_RESULT_DISCONNECT: return 5;
> + case PCI_ERS_RESULT_NEED_RESET: return 6;
> + default:
> + WARN_ONCE(1, "Unknown pci_ers_result value: %d\n", (int)result);
> + return 0;
> + }
> +};
> +
> +static enum pci_ers_result pci_ers_merge_result(enum pci_ers_result old,
> + enum pci_ers_result new)
> +{
> + if (eeh_result_priority(new) > eeh_result_priority(old))
> + return new;
> + return old;
> +}
> +
> /**
> * eeh_pcid_get - Get the PCI device driver
> * @pdev: PCI device
> @@ -206,9 +229,7 @@ static void *eeh_report_error(struct eeh_dev *edev, void
> *userdata)
>
> rc = driver->err_handler->error_detected(dev, pci_channel_io_frozen);
>
> - /* A driver that needs a reset trumps all others */
> - if (rc == PCI_ERS_RESULT_NEED_RESET) *res = rc;
> - if (*res == PCI_ERS_RESULT_NONE) *res = rc;
> + *res = pci_ers_merge_result(*res, rc);
>
> edev->in_error = true;
> pci_uevent_ers(dev, PCI_ERS_RESULT_NONE);
> @@ -249,9 +270,7 @@ static void *eeh_report_mmio_enabled(struct eeh_dev
> *edev, void *userdata)
>
> rc = driver->err_handler->mmio_enabled(dev);
>
> - /* A driver that needs a reset trumps all others */
> - if (rc == PCI_ERS_RESULT_NEED_RESET) *res = rc;
> - if (*res == PCI_ERS_RESULT_NONE) *res = rc;
> + *res = pci_ers_merge_result(*res, rc);
>
> out:
> eeh_pcid_put(dev);
> @@ -294,10 +313,7 @@ static void *eeh_report_reset(struct eeh_dev *edev, void
> *userdata)
> goto out;
>
> rc = driver->err_handler->slot_reset(dev);
> - if ((*res == PCI_ERS_RESULT_NONE) ||
> - (*res == PCI_ERS_RESULT_RECOVERED)) *res = rc;
> - if (*res == PCI_ERS_RESULT_DISCONNECT &&
> - rc == PCI_ERS_RESULT_NEED_RESET) *res = rc;
> + *res = pci_ers_merge_result(*res, rc);
>
> out:
> eeh_pcid_put(dev);
> --
> 2.16.1.74.g9b0b1f47b
Re: [RFC PATCH] powerpc/fsl: Add barrier_nospec implementation for NXP PowerPC Book E
On 6/1/2018 1:40 PM, Michael Ellerman wrote: > Scott Wood writes: > >> On Thu, 2018-05-31 at 14:35 +, Diana Madalina Craciun wrote: >>> On 5/31/2018 5:21 PM, Michael Ellerman wrote: We can add a nospectre_v1 command line option if necessary. >>> What about nobarrier_nospec (or similar) instead of nospectre_v1 command >>> line? We are not disabling all the v1 mitigations, the masking part will >>> remain unchanged. >> I think nospectre_v1 makes more sense as it's about the user's intentions >> rather than the implementation. The user is giving the kernel permission to >> not defend against spectre v1, and it's up to the implementation which >> mitigations (if any) to disable in response to that, same as any other >> optimization. > Yeah I agree. We also have `nospectre_v2` on x86/s390 so I think keeping > consistency with that is a must. > > cheers > OK Diana
Re: [PATCH v5 0/4] powerpc patches for new Kconfig language
Masahiro Yamada writes:
> 2018-06-01 19:34 GMT+09:00 Michael Ellerman :
...
>
> Could you update your branch, please?
Done.
I've only pushed the first three patches this time, to avoid any
confusion. Hopefully :)
The top commit is:
1421dc6d4829 ("powerpc/kbuild: Use flags variables rather than overriding
LD/CC/AS")
For the fourth one you're welcome to add my ack when you apply it:
Acked-by: Michael Ellerman
> Then, I will re-pull the new one.
Thanks! Sorry this took a while to get right, next time we'll be much
better at it ;)
cheers
Re: [PATCH] powerpc/64s: Fix compiler store ordering to SLB shadow area
Nicholas Piggin writes: > On Fri, 01 Jun 2018 00:22:21 +1000 > Michael Ellerman wrote: >> Nicholas Piggin writes: >> > The stores to update the SLB shadow area must be made as they appear >> > in the C code, so that the hypervisor does not see an entry with >> > mismatched vsid and esid. Use WRITE_ONCE for this. >> > >> > GCC has been observed to elide the first store to esid in the update, >> > which means that if the hypervisor interrupts the guest after storing >> > to vsid, it could see an entry with old esid and new vsid, which may >> > possibly result in memory corruption. >> > >> > Signed-off-by: Nicholas Piggin >> > --- >> > arch/powerpc/mm/slb.c | 8 >> > 1 file changed, 4 insertions(+), 4 deletions(-) >> > >> > diff --git a/arch/powerpc/mm/slb.c b/arch/powerpc/mm/slb.c >> > index 66577cc66dc9..2f4b33b24b3b 100644 >> > --- a/arch/powerpc/mm/slb.c >> > +++ b/arch/powerpc/mm/slb.c >> > @@ -63,14 +63,14 @@ static inline void slb_shadow_update(unsigned long ea, >> > int ssize, >> > * updating it. No write barriers are needed here, provided >> > * we only update the current CPU's SLB shadow buffer. >> > */ >> > - p->save_area[index].esid = 0; >> > - p->save_area[index].vsid = cpu_to_be64(mk_vsid_data(ea, ssize, flags)); >> > - p->save_area[index].esid = cpu_to_be64(mk_esid_data(ea, ssize, index)); >> > + WRITE_ONCE(p->save_area[index].esid, 0); >> > + WRITE_ONCE(p->save_area[index].vsid, cpu_to_be64(mk_vsid_data(ea, >> > ssize, flags))); >> > + WRITE_ONCE(p->save_area[index].esid, cpu_to_be64(mk_esid_data(ea, >> > ssize, index))); >> >> What's the code-gen for that look like? I suspect it's terrible? > > Yeah it's not great. Actually with GCC 7 the WRITE_ONCE() doesn't make it any worse. Which is a little suspicious. But it is doing the first store: li r10,0 # r10 = 0 ld r29,56(r13) # r29 = paca->slb_shadow_ptr rldicr r8,r31,4,59 # r8 = index rldicr r9,r9,32,31 add r29,r29,r8 # r29 = r29 + index orisr9,r9,65535 std r10,16(r29) # esid = r10 = 0 So I'll just merge this as-is. cheers
Re: [PATCH v5 0/4] powerpc patches for new Kconfig language
Hi. 2018-06-01 19:34 GMT+09:00 Michael Ellerman : > Hi Masahiro, > > Masahiro Yamada writes: > ... >> >> Also, the change logs could be dropped. >> >> I see >> >> Since v1: reworded changelog to explain the cause of the problem (thanks >> Segher) and moved the flags into the 64-32 cross compile case. >> >> or >> >> Since v1: removed extra -EB in the recordmcount script (thanks mpe) >> >> >> above your signed-off-by. >> >> >> Of course, this is your call, >> and you do not need to disturb the git history if it is too late. > > You're right, sorry those are bit messy. > > I'm happy to update them, I haven't merged them yet, but I see you have > them in your tree. > > So I won't change them unless you confirm you're OK with it. Let me > know. Could you update your branch, please? Then, I will re-pull the new one. Thanks! -- Best Regards Masahiro Yamada
Re: [RFC PATCH] powerpc/fsl: Add barrier_nospec implementation for NXP PowerPC Book E
Scott Wood writes: > On Thu, 2018-05-31 at 14:35 +, Diana Madalina Craciun wrote: >> On 5/31/2018 5:21 PM, Michael Ellerman wrote: >> > >> > We can add a nospectre_v1 command line option if necessary. >> >> What about nobarrier_nospec (or similar) instead of nospectre_v1 command >> line? We are not disabling all the v1 mitigations, the masking part will >> remain unchanged. > > I think nospectre_v1 makes more sense as it's about the user's intentions > rather than the implementation. The user is giving the kernel permission to > not defend against spectre v1, and it's up to the implementation which > mitigations (if any) to disable in response to that, same as any other > optimization. Yeah I agree. We also have `nospectre_v2` on x86/s390 so I think keeping consistency with that is a must. cheers
Re: [PATCH v5 0/4] powerpc patches for new Kconfig language
Hi Masahiro, Masahiro Yamada writes: ... > > Also, the change logs could be dropped. > > I see > > Since v1: reworded changelog to explain the cause of the problem (thanks > Segher) and moved the flags into the 64-32 cross compile case. > > or > > Since v1: removed extra -EB in the recordmcount script (thanks mpe) > > > above your signed-off-by. > > > Of course, this is your call, > and you do not need to disturb the git history if it is too late. You're right, sorry those are bit messy. I'm happy to update them, I haven't merged them yet, but I see you have them in your tree. So I won't change them unless you confirm you're OK with it. Let me know. cheers
[PATCH v4 7/7] powerpc/64s/radix: flush remote CPUs out of single-threaded mm_cpumask
When a single-threaded process has a non-local mm_cpumask, try to use
that point to flush the TLBs out of other CPUs in the cpumask.
An IPI is used for clearing remote CPUs for a few reasons:
- An IPI can end lazy TLB use of the mm, which is required to prevent
TLB entries being created on the remote CPU. The alternative is to
drop lazy TLB switching completely, which costs 7.5% in a context
switch ping-pong test betwee a process and kernel idle thread.
- An IPI can have remote CPUs flush the entire PID, but the local CPU
can flush a specific VA. tlbie would require over-flushing of the
local CPU (where the process is running).
- A single threaded process that is migrated to a different CPU is
likely to have a relatively small mm_cpumask, so IPI is reasonable.
No other thread can concurrently switch to this mm, because it must
have been given a reference to mm_users by the current thread before it
can use_mm. mm_users can be asynchronously incremented (by
mm_activate or mmget_not_zero), but those users must use remote mm
access and can't use_mm or access user address space. Existing code
makes the this assumption already, for example sparc64 has reset
mm_cpumask using this condition since the start of history, see
arch/sparc/kernel/smp_64.c.
This reduces tlbies for a kernel compile workload from 0.90M to 0.12M,
tlbiels are increased significantly due to the PID flushing for the
cleaning up remote CPUs, and increased local flushes (PID flushes take
128 tlbiels vs 1 tlbie).
Signed-off-by: Nicholas Piggin
---
arch/powerpc/include/asm/tlb.h | 13 +++
arch/powerpc/mm/tlb-radix.c| 148 +++--
2 files changed, 134 insertions(+), 27 deletions(-)
diff --git a/arch/powerpc/include/asm/tlb.h b/arch/powerpc/include/asm/tlb.h
index a7eabff27a0f..9138baccebb0 100644
--- a/arch/powerpc/include/asm/tlb.h
+++ b/arch/powerpc/include/asm/tlb.h
@@ -76,6 +76,19 @@ static inline int mm_is_thread_local(struct mm_struct *mm)
return false;
return cpumask_test_cpu(smp_processor_id(), mm_cpumask(mm));
}
+static inline void mm_reset_thread_local(struct mm_struct *mm)
+{
+ WARN_ON(atomic_read(>context.copros) > 0);
+ /*
+* It's possible for mm_access to take a reference on mm_users to
+* access the remote mm from another thread, but it's not allowed
+* to set mm_cpumask, so mm_users may be > 1 here.
+*/
+ WARN_ON(current->mm != mm);
+ atomic_set(>context.active_cpus, 1);
+ cpumask_clear(mm_cpumask(mm));
+ cpumask_set_cpu(smp_processor_id(), mm_cpumask(mm));
+}
#else /* CONFIG_PPC_BOOK3S_64 */
static inline int mm_is_thread_local(struct mm_struct *mm)
{
diff --git a/arch/powerpc/mm/tlb-radix.c b/arch/powerpc/mm/tlb-radix.c
index cdc50398fd60..67a6e86d3e7e 100644
--- a/arch/powerpc/mm/tlb-radix.c
+++ b/arch/powerpc/mm/tlb-radix.c
@@ -12,6 +12,8 @@
#include
#include
#include
+#include
+#include
#include
#include
@@ -504,6 +506,15 @@ void radix__local_flush_tlb_page(struct vm_area_struct
*vma, unsigned long vmadd
}
EXPORT_SYMBOL(radix__local_flush_tlb_page);
+static bool mm_is_singlethreaded(struct mm_struct *mm)
+{
+ if (atomic_read(>context.copros) > 0)
+ return false;
+ if (atomic_read(>mm_users) <= 1 && current->mm == mm)
+ return true;
+ return false;
+}
+
static bool mm_needs_flush_escalation(struct mm_struct *mm)
{
/*
@@ -511,10 +522,47 @@ static bool mm_needs_flush_escalation(struct mm_struct
*mm)
* caching PTEs and not flushing them properly when
* RIC = 0 for a PID/LPID invalidate
*/
- return atomic_read(>context.copros) != 0;
+ if (atomic_read(>context.copros) > 0)
+ return true;
+ return false;
}
#ifdef CONFIG_SMP
+static void do_exit_flush_lazy_tlb(void *arg)
+{
+ struct mm_struct *mm = arg;
+ unsigned long pid = mm->context.id;
+
+ if (current->mm == mm)
+ return; /* Local CPU */
+
+ if (current->active_mm == mm) {
+ /*
+* Must be a kernel thread because sender is single-threaded.
+*/
+ BUG_ON(current->mm);
+ mmgrab(_mm);
+ switch_mm(mm, _mm, current);
+ current->active_mm = _mm;
+ mmdrop(mm);
+ }
+ _tlbiel_pid(pid, RIC_FLUSH_ALL);
+}
+
+static void exit_flush_lazy_tlbs(struct mm_struct *mm)
+{
+ /*
+* Would be nice if this was async so it could be run in
+* parallel with our local flush, but generic code does not
+* give a good API for it. Could extend the generic code or
+* make a special powerpc IPI for flushing TLBs.
+* For now it's not too performance critical.
+*/
+ smp_call_function_many(mm_cpumask(mm), do_exit_flush_lazy_tlb,
+ (void *)mm, 1);
+ mm_reset_thread_local(mm);
+}
+
[PATCH v4 6/7] powerpc/64s/radix: optimise pte_update
Implementing pte_update with pte_xchg (which uses cmpxchg) is
inefficient. A single larx/stcx. works fine, no need for the less
efficient cmpxchg sequence.
Then remove the memory barriers from the operation. There is a
requirement for TLB flushing to load mm_cpumask after the store
that reduces pte permissions, which is moved into the TLB flush
code.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/include/asm/book3s/64/radix.h | 25 +++---
arch/powerpc/mm/mmu_context.c | 6 --
arch/powerpc/mm/tlb-radix.c| 11 +-
3 files changed, 27 insertions(+), 15 deletions(-)
diff --git a/arch/powerpc/include/asm/book3s/64/radix.h
b/arch/powerpc/include/asm/book3s/64/radix.h
index 9c567d243f61..ef9f96742ce1 100644
--- a/arch/powerpc/include/asm/book3s/64/radix.h
+++ b/arch/powerpc/include/asm/book3s/64/radix.h
@@ -131,20 +131,21 @@ extern void radix__ptep_set_access_flags(struct
vm_area_struct *vma, pte_t *ptep
static inline unsigned long __radix_pte_update(pte_t *ptep, unsigned long clr,
unsigned long set)
{
- pte_t pte;
- unsigned long old_pte, new_pte;
-
- do {
- pte = READ_ONCE(*ptep);
- old_pte = pte_val(pte);
- new_pte = (old_pte | set) & ~clr;
-
- } while (!pte_xchg(ptep, __pte(old_pte), __pte(new_pte)));
-
- return old_pte;
+ __be64 old_be, tmp_be;
+
+ __asm__ __volatile__(
+ "1: ldarx %0,0,%3 # pte_update\n"
+ " andc%1,%0,%5\n"
+ " or %1,%1,%4\n"
+ " stdcx. %1,0,%3 \n"
+ " bne-1b"
+ : "=" (old_be), "=" (tmp_be), "=m" (*ptep)
+ : "r" (ptep), "r" (cpu_to_be64(set)), "r" (cpu_to_be64(clr))
+ : "cc" );
+
+ return be64_to_cpu(old_be);
}
-
static inline unsigned long radix__pte_update(struct mm_struct *mm,
unsigned long addr,
pte_t *ptep, unsigned long clr,
diff --git a/arch/powerpc/mm/mmu_context.c b/arch/powerpc/mm/mmu_context.c
index 0ab297c4cfad..f84e14f23e50 100644
--- a/arch/powerpc/mm/mmu_context.c
+++ b/arch/powerpc/mm/mmu_context.c
@@ -57,8 +57,10 @@ void switch_mm_irqs_off(struct mm_struct *prev, struct
mm_struct *next,
* in switch_slb(), and/or the store of paca->mm_ctx_id in
* copy_mm_to_paca().
*
-* On the read side the barrier is in pte_xchg(), which orders
-* the store to the PTE vs the load of mm_cpumask.
+* On the other side, the barrier is in mm/tlb-radix.c for
+* radix which orders earlier stores to clear the PTEs vs
+* the load of mm_cpumask. And pte_xchg which does the same
+* thing for hash.
*
* This full barrier is needed by membarrier when switching
* between processes after store to rq->curr, before user-space
diff --git a/arch/powerpc/mm/tlb-radix.c b/arch/powerpc/mm/tlb-radix.c
index 5ac3206c51cc..cdc50398fd60 100644
--- a/arch/powerpc/mm/tlb-radix.c
+++ b/arch/powerpc/mm/tlb-radix.c
@@ -524,6 +524,11 @@ void radix__flush_tlb_mm(struct mm_struct *mm)
return;
preempt_disable();
+ /*
+* Order loads of mm_cpumask vs previous stores to clear ptes before
+* the invalidate. See barrier in switch_mm_irqs_off
+*/
+ smp_mb();
if (!mm_is_thread_local(mm)) {
if (mm_needs_flush_escalation(mm))
_tlbie_pid(pid, RIC_FLUSH_ALL);
@@ -544,6 +549,7 @@ void radix__flush_all_mm(struct mm_struct *mm)
return;
preempt_disable();
+ smp_mb(); /* see radix__flush_tlb_mm */
if (!mm_is_thread_local(mm))
_tlbie_pid(pid, RIC_FLUSH_ALL);
else
@@ -568,6 +574,7 @@ void radix__flush_tlb_page_psize(struct mm_struct *mm,
unsigned long vmaddr,
return;
preempt_disable();
+ smp_mb(); /* see radix__flush_tlb_mm */
if (!mm_is_thread_local(mm))
_tlbie_va(vmaddr, pid, psize, RIC_FLUSH_TLB);
else
@@ -630,6 +637,7 @@ void radix__flush_tlb_range(struct vm_area_struct *vma,
unsigned long start,
return;
preempt_disable();
+ smp_mb(); /* see radix__flush_tlb_mm */
if (mm_is_thread_local(mm)) {
local = true;
full = (end == TLB_FLUSH_ALL ||
@@ -791,6 +799,7 @@ static inline void __radix__flush_tlb_range_psize(struct
mm_struct *mm,
return;
preempt_disable();
+ smp_mb(); /* see radix__flush_tlb_mm */
if (mm_is_thread_local(mm)) {
local = true;
full = (end == TLB_FLUSH_ALL ||
@@ -849,7 +858,7 @@ void radix__flush_tlb_collapsed_pmd(struct mm_struct *mm,
unsigned long
[PATCH v4 5/7] powerpc/64s/radix: avoid ptesync after set_pte and ptep_set_access_flags
The ISA suggests ptesync after setting a pte, to prevent a table walk
initiated by a subsequent access from missing that store and causing a
spurious fault. This is an architectual allowance that allows an
implementation's page table walker to be incoherent with the store
queue.
However there is no correctness problem in taking a spurious fault in
userspace -- the kernel copes with these at any time, so the updated
pte will be found eventually. Spurious kernel faults on vmap memory
must be avoided, so a ptesync is put into flush_cache_vmap.
On POWER9 so far I have not found a measurable window where this can
result in more minor faults, so as an optimisation, remove the costly
ptesync from pte updates. If an implementation benefits from ptesync,
it would be better to add it back in update_mmu_cache, so it's not
done for things like fork(2).
fork --fork --exec benchmark improved 5.2% (12400->13100).
Signed-off-by: Nicholas Piggin
---
arch/powerpc/include/asm/book3s/64/radix.h | 19 ++-
arch/powerpc/include/asm/cacheflush.h | 13 +
arch/powerpc/mm/pgtable-radix.c| 2 +-
3 files changed, 32 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/include/asm/book3s/64/radix.h
b/arch/powerpc/include/asm/book3s/64/radix.h
index 01f6c2ca7ecd..9c567d243f61 100644
--- a/arch/powerpc/include/asm/book3s/64/radix.h
+++ b/arch/powerpc/include/asm/book3s/64/radix.h
@@ -202,7 +202,24 @@ static inline void radix__set_pte_at(struct mm_struct *mm,
unsigned long addr,
pte_t *ptep, pte_t pte, int percpu)
{
*ptep = pte;
- asm volatile("ptesync" : : : "memory");
+
+ /*
+* The architecture suggests a ptesync after setting the pte, which
+* orders the store that updates the pte with subsequent page table
+* walk accesses which may load the pte. Without this it may be
+* possible for a subsequent access to result in spurious fault.
+*
+* This is not necessary for correctness, because a spurious fault
+* is tolerated by the page fault handler, and this store will
+* eventually be seen. In testing, there was no noticable increase
+* in user faults on POWER9. Avoiding ptesync here is a significant
+* win for things like fork. If a future microarchitecture benefits
+* from ptesync, it should probably go into update_mmu_cache, rather
+* than set_pte_at (which is used to set ptes unrelated to faults).
+*
+* Spurious faults to vmalloc region are not tolerated, so there is
+* a ptesync in flush_cache_vmap.
+*/
}
static inline int radix__pmd_bad(pmd_t pmd)
diff --git a/arch/powerpc/include/asm/cacheflush.h
b/arch/powerpc/include/asm/cacheflush.h
index 11843e37d9cf..e9662648e72d 100644
--- a/arch/powerpc/include/asm/cacheflush.h
+++ b/arch/powerpc/include/asm/cacheflush.h
@@ -26,6 +26,19 @@
#define flush_cache_vmap(start, end) do { } while (0)
#define flush_cache_vunmap(start, end) do { } while (0)
+#ifdef CONFIG_BOOK3S_64
+/*
+ * Book3s has no ptesync after setting a pte, so without this ptesync it's
+ * possible for a kernel virtual mapping access to return a spurious fault
+ * if it's accessed right after the pte is set. The page fault handler does
+ * not expect this type of fault. flush_cache_vmap is not exactly the right
+ * place to put this, but it seems to work well enough.
+ */
+#define flush_cache_vmap(start, end) do { asm volatile("ptesync"); }
while (0)
+#else
+#define flush_cache_vmap(start, end) do { } while (0)
+#endif
+
#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
extern void flush_dcache_page(struct page *page);
#define flush_dcache_mmap_lock(mapping)do { } while (0)
diff --git a/arch/powerpc/mm/pgtable-radix.c b/arch/powerpc/mm/pgtable-radix.c
index d6f74cbf0fed..96f68c5aa1f5 100644
--- a/arch/powerpc/mm/pgtable-radix.c
+++ b/arch/powerpc/mm/pgtable-radix.c
@@ -1115,5 +1115,5 @@ void radix__ptep_set_access_flags(struct vm_area_struct
*vma, pte_t *ptep,
* an access fault, which is defined by the architectue.
*/
}
- asm volatile("ptesync" : : : "memory");
+ /* See ptesync comment in radix__set_pte_at */
}
--
2.17.0
[PATCH v4 4/7] powerpc/64s/radix: prefetch user address in update_mmu_cache
Prefetch the faulting address in update_mmu_cache to give the page
table walker perhaps 100 cycles head start as locks are dropped and
the interrupt completed.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/mm/mem.c | 4 +++-
arch/powerpc/mm/pgtable-book3s64.c | 3 ++-
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/mm/mem.c b/arch/powerpc/mm/mem.c
index c3c39b02b2ba..8cecda4bd66a 100644
--- a/arch/powerpc/mm/mem.c
+++ b/arch/powerpc/mm/mem.c
@@ -509,8 +509,10 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned
long address,
*/
unsigned long access, trap;
- if (radix_enabled())
+ if (radix_enabled()) {
+ prefetch((void *)address);
return;
+ }
/* We only want HPTEs for linux PTEs that have _PAGE_ACCESSED set */
if (!pte_young(*ptep) || address >= TASK_SIZE)
diff --git a/arch/powerpc/mm/pgtable-book3s64.c
b/arch/powerpc/mm/pgtable-book3s64.c
index 82fed87289de..c1f4ca45c93a 100644
--- a/arch/powerpc/mm/pgtable-book3s64.c
+++ b/arch/powerpc/mm/pgtable-book3s64.c
@@ -152,7 +152,8 @@ pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr,
pmd_t *pmd)
{
- return;
+ if (radix_enabled())
+ prefetch((void *)addr);
}
#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
--
2.17.0
[PATCH v4 3/7] powerpc/64s/radix: make ptep_get_and_clear_full non-atomic for the full case
This matches other architectures, when we know there will be no
further accesses to the address (e.g., for teardown), page table
entries can be cleared non-atomically.
The comments about NMMU are bogus: all MMU notifiers (including NMMU)
are released at this point, with their TLBs flushed. An NMMU access at
this point would be a bug.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/include/asm/book3s/64/radix.h | 10 ++
1 file changed, 2 insertions(+), 8 deletions(-)
diff --git a/arch/powerpc/include/asm/book3s/64/radix.h
b/arch/powerpc/include/asm/book3s/64/radix.h
index 62a73a7a78a4..01f6c2ca7ecd 100644
--- a/arch/powerpc/include/asm/book3s/64/radix.h
+++ b/arch/powerpc/include/asm/book3s/64/radix.h
@@ -180,14 +180,8 @@ static inline pte_t radix__ptep_get_and_clear_full(struct
mm_struct *mm,
unsigned long old_pte;
if (full) {
- /*
-* If we are trying to clear the pte, we can skip
-* the DD1 pte update sequence and batch the tlb flush. The
-* tlb flush batching is done by mmu gather code. We
-* still keep the cmp_xchg update to make sure we get
-* correct R/C bit which might be updated via Nest MMU.
-*/
- old_pte = __radix_pte_update(ptep, ~0ul, 0);
+ old_pte = pte_val(*ptep);
+ *ptep = __pte(0);
} else
old_pte = radix__pte_update(mm, addr, ptep, ~0ul, 0, 0);
--
2.17.0
[PATCH v4 2/7] powerpc/64s/radix: do not flush TLB on spurious fault
In the case of a spurious fault (which can happen due to a race with
another thread that changes the page table), the default Linux mm code
calls flush_tlb_page for that address. This is not required because
the pte will be re-fetched. Hash does not wire this up to a hardware
TLB flush for this reason. This patch avoids the flush for radix.
>From Power ISA v3.0B, p.1090:
Setting a Reference or Change Bit or Upgrading Access Authority
(PTE Subject to Atomic Hardware Updates)
If the only change being made to a valid PTE that is subject to
atomic hardware updates is to set the Refer- ence or Change bit to
1 or to add access authorities, a simpler sequence suffices
because the translation hardware will refetch the PTE if an access
is attempted for which the only problems were reference and/or
change bits needing to be set or insufficient access authority.
The nest MMU on POWER9 does not re-fetch the PTE after such an access
attempt before faulting, so address spaces with a coprocessor
attached will continue to flush in these cases.
This reduces tlbies for a kernel compile workload from 0.95M to 0.90M.
fork --fork --exec benchmark improved 0.5% (12300->12400).
Reviewed-by: Aneesh Kumar K.V
Signed-off-by: Nicholas Piggin
---
arch/powerpc/include/asm/book3s/64/tlbflush.h | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/include/asm/book3s/64/tlbflush.h
b/arch/powerpc/include/asm/book3s/64/tlbflush.h
index 0cac17253513..ebf572ea621e 100644
--- a/arch/powerpc/include/asm/book3s/64/tlbflush.h
+++ b/arch/powerpc/include/asm/book3s/64/tlbflush.h
@@ -4,7 +4,7 @@
#define MMU_NO_CONTEXT ~0UL
-
+#include
#include
#include
@@ -137,6 +137,16 @@ static inline void flush_all_mm(struct mm_struct *mm)
#define flush_tlb_page(vma, addr) local_flush_tlb_page(vma, addr)
#define flush_all_mm(mm) local_flush_all_mm(mm)
#endif /* CONFIG_SMP */
+
+#define flush_tlb_fix_spurious_fault flush_tlb_fix_spurious_fault
+static inline void flush_tlb_fix_spurious_fault(struct vm_area_struct *vma,
+ unsigned long address)
+{
+ /* See ptep_set_access_flags comment */
+ if (atomic_read(>vm_mm->context.copros) > 0)
+ flush_tlb_page(vma, address);
+}
+
/*
* flush the page walk cache for the address
*/
--
2.17.0
[PATCH v4 1/7] powerpc/64s/radix: do not flush TLB when relaxing access
Radix flushes the TLB when updating ptes to increase permissiveness
of protection (increase access authority). Book3S does not require
TLB flushing in this case, and it is not done on hash. This patch
avoids the flush for radix.
>From Power ISA v3.0B, p.1090:
Setting a Reference or Change Bit or Upgrading Access Authority
(PTE Subject to Atomic Hardware Updates)
If the only change being made to a valid PTE that is subject to
atomic hardware updates is to set the Reference or Change bit to 1
or to add access authorities, a simpler sequence suffices because
the translation hardware will refetch the PTE if an access is
attempted for which the only problems were reference and/or change
bits needing to be set or insufficient access authority.
The nest MMU on POWER9 does not re-fetch the PTE after such an access
attempt before faulting, so address spaces with a coprocessor
attached will continue to flush in these cases.
This reduces tlbies for a kernel compile workload from 1.28M to 0.95M,
tlbiels from 20.17M 19.68M.
fork --fork --exec benchmark improved 2.77% (12000->12300).
Reviewed-by: Aneesh Kumar K.V
Signed-off-by: Nicholas Piggin
---
arch/powerpc/mm/pgtable-radix.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/mm/pgtable-radix.c b/arch/powerpc/mm/pgtable-radix.c
index 0ddfe591cd24..d6f74cbf0fed 100644
--- a/arch/powerpc/mm/pgtable-radix.c
+++ b/arch/powerpc/mm/pgtable-radix.c
@@ -1108,7 +1108,12 @@ void radix__ptep_set_access_flags(struct vm_area_struct
*vma, pte_t *ptep,
__radix_pte_update(ptep, 0, new_pte);
} else {
__radix_pte_update(ptep, 0, set);
- radix__flush_tlb_page_psize(mm, address, psize);
+ /*
+* Book3S does not require a TLB flush when relaxing access
+* restrictions when the address space is not attached to a
+* NMMU, because the core MMU will reload the pte after taking
+* an access fault, which is defined by the architectue.
+*/
}
asm volatile("ptesync" : : : "memory");
}
--
2.17.0
[PATCH v4 0/7] Various TLB and PTE improvements
Since last time: - Rebased on top of Aneesh's series "[PATCH V2 1/4] powerpc/mm/hugetlb: Update huge_ptep_set_access_flags to call __ptep_set_access_flags" Thanks, Nick Nicholas Piggin (7): powerpc/64s/radix: do not flush TLB when relaxing access powerpc/64s/radix: do not flush TLB on spurious fault powerpc/64s/radix: make ptep_get_and_clear_full non-atomic for the full case powerpc/64s/radix: prefetch user address in update_mmu_cache powerpc/64s/radix: avoid ptesync after set_pte and ptep_set_access_flags powerpc/64s/radix: optimise pte_update powerpc/64s/radix: flush remote CPUs out of single-threaded mm_cpumask arch/powerpc/include/asm/book3s/64/radix.h| 54 +++--- arch/powerpc/include/asm/book3s/64/tlbflush.h | 12 +- arch/powerpc/include/asm/cacheflush.h | 13 ++ arch/powerpc/include/asm/tlb.h| 13 ++ arch/powerpc/mm/mem.c | 4 +- arch/powerpc/mm/mmu_context.c | 6 +- arch/powerpc/mm/pgtable-book3s64.c| 3 +- arch/powerpc/mm/pgtable-radix.c | 9 +- arch/powerpc/mm/tlb-radix.c | 159 +++--- 9 files changed, 217 insertions(+), 56 deletions(-) -- 2.17.0
[PATCH] powerpc/mm/hugetlb: Update hugetlb related locks
With split pmd page table lock enabled, we don't use mm->page_table_lock when
updating pmd entries. This patch update hugetlb path to use the right lock
when inserting huge page directory entries into page table.
ex: if we are using hugepd and inserting hugepd entry at the pmd level, we
use pmd_lockptr, which based on config can be split pmd lock.
For update huge page directory entries itself we use mm->page_table_lock. We
do have a helper huge_pte_lockptr() for that.
Fixes: 675d99529 ("powerpc/book3s64: Enable split pmd ptlock")
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/mm/hugetlbpage.c | 33 +++--
arch/powerpc/mm/pgtable.c | 12 +++-
2 files changed, 30 insertions(+), 15 deletions(-)
diff --git a/arch/powerpc/mm/hugetlbpage.c b/arch/powerpc/mm/hugetlbpage.c
index 2a4b1bf8bde6..7c5f479c5c00 100644
--- a/arch/powerpc/mm/hugetlbpage.c
+++ b/arch/powerpc/mm/hugetlbpage.c
@@ -52,7 +52,8 @@ pte_t *huge_pte_offset(struct mm_struct *mm, unsigned long
addr, unsigned long s
}
static int __hugepte_alloc(struct mm_struct *mm, hugepd_t *hpdp,
- unsigned long address, unsigned pdshift, unsigned
pshift)
+ unsigned long address, unsigned int pdshift,
+ unsigned int pshift, spinlock_t *ptl)
{
struct kmem_cache *cachep;
pte_t *new;
@@ -82,8 +83,7 @@ static int __hugepte_alloc(struct mm_struct *mm, hugepd_t
*hpdp,
*/
smp_wmb();
- spin_lock(>page_table_lock);
-
+ spin_lock(ptl);
/*
* We have multiple higher-level entries that point to the same
* actual pte location. Fill in each as we go and backtrack on error.
@@ -113,7 +113,7 @@ static int __hugepte_alloc(struct mm_struct *mm, hugepd_t
*hpdp,
*hpdp = __hugepd(0);
kmem_cache_free(cachep, new);
}
- spin_unlock(>page_table_lock);
+ spin_unlock(ptl);
return 0;
}
@@ -138,6 +138,7 @@ pte_t *huge_pte_alloc(struct mm_struct *mm, unsigned long
addr, unsigned long sz
hugepd_t *hpdp = NULL;
unsigned pshift = __ffs(sz);
unsigned pdshift = PGDIR_SHIFT;
+ spinlock_t *ptl;
addr &= ~(sz-1);
pg = pgd_offset(mm, addr);
@@ -146,39 +147,46 @@ pte_t *huge_pte_alloc(struct mm_struct *mm, unsigned long
addr, unsigned long sz
if (pshift == PGDIR_SHIFT)
/* 16GB huge page */
return (pte_t *) pg;
- else if (pshift > PUD_SHIFT)
+ else if (pshift > PUD_SHIFT) {
/*
* We need to use hugepd table
*/
+ ptl = >page_table_lock;
hpdp = (hugepd_t *)pg;
- else {
+ } else {
pdshift = PUD_SHIFT;
pu = pud_alloc(mm, pg, addr);
if (pshift == PUD_SHIFT)
return (pte_t *)pu;
- else if (pshift > PMD_SHIFT)
+ else if (pshift > PMD_SHIFT) {
+ ptl = pud_lockptr(mm, pu);
hpdp = (hugepd_t *)pu;
- else {
+ } else {
pdshift = PMD_SHIFT;
pm = pmd_alloc(mm, pu, addr);
if (pshift == PMD_SHIFT)
/* 16MB hugepage */
return (pte_t *)pm;
- else
+ else {
+ ptl = pmd_lockptr(mm, pm);
hpdp = (hugepd_t *)pm;
+ }
}
}
#else
if (pshift >= HUGEPD_PGD_SHIFT) {
+ ptl = >page_table_lock;
hpdp = (hugepd_t *)pg;
} else {
pdshift = PUD_SHIFT;
pu = pud_alloc(mm, pg, addr);
if (pshift >= HUGEPD_PUD_SHIFT) {
+ ptl = pud_lockptr(mm, pu);
hpdp = (hugepd_t *)pu;
} else {
pdshift = PMD_SHIFT;
pm = pmd_alloc(mm, pu, addr);
+ ptl = pmd_lockptr(mm, pm);
hpdp = (hugepd_t *)pm;
}
}
@@ -188,7 +196,8 @@ pte_t *huge_pte_alloc(struct mm_struct *mm, unsigned long
addr, unsigned long sz
BUG_ON(!hugepd_none(*hpdp) && !hugepd_ok(*hpdp));
- if (hugepd_none(*hpdp) && __hugepte_alloc(mm, hpdp, addr, pdshift,
pshift))
+ if (hugepd_none(*hpdp) && __hugepte_alloc(mm, hpdp, addr,
+ pdshift, pshift, ptl))
return NULL;
return hugepte_offset(*hpdp, addr, pdshift);
@@ -499,6 +508,10 @@ struct page *follow_huge_pd(struct vm_area_struct *vma,
struct mm_struct *mm = vma->vm_mm;
retry:
+ /*
+* hugepage directory entries are protected by mm->page_table_lock
+*
[PATCH] powerpc/mm/hash: hard disable irq in the SLB insert path
When inserting SLB entries for EA above 512TB, we need to hard disable irq.
This will make sure we don't take a PMU interrupt that can possibly touch
user space address via a stack dump. To prevent this, we need to hard disable
the interrupt.
Also add a comment explaining why we don't need context synchronizing isync
with slbmte.
Fixes: f384796c4 ("powerpc/mm: Add support for handling > 512TB address in SLB
miss")
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/mm/slb.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/powerpc/mm/slb.c b/arch/powerpc/mm/slb.c
index 66577cc66dc9..27f5b81c372a 100644
--- a/arch/powerpc/mm/slb.c
+++ b/arch/powerpc/mm/slb.c
@@ -352,6 +352,14 @@ static void insert_slb_entry(unsigned long vsid, unsigned
long ea,
/*
* We are irq disabled, hence should be safe to access PACA.
*/
+ VM_WARN_ON(!irqs_disabled());
+
+ /*
+* We can't take a PMU exception in the following code, so hard
+* disable interrupts.
+*/
+ hard_irq_disable();
+
index = get_paca()->stab_rr;
/*
@@ -369,6 +377,11 @@ static void insert_slb_entry(unsigned long vsid, unsigned
long ea,
((unsigned long) ssize << SLB_VSID_SSIZE_SHIFT);
esid_data = mk_esid_data(ea, ssize, index);
+ /*
+* No need for an isync before or after this slbmte. The exception
+* we enter with and the rfid we exit with are context synchronizing.
+* Also we only handle user segments here.
+*/
asm volatile("slbmte %0, %1" : : "r" (vsid_data), "r" (esid_data)
: "memory");
--
2.17.0
[PATCH kernel 2/2] powerpc/powernv: Define PHB4 type and enable sketchy bypass on POWER9
These are found in POWER9 chips. Right now these PHBs have unknown type
so changing it to PHB4 won't make much of a difference except enabling
sketchy bypass for POWER9 as this does below.
Signed-off-by: Alexey Kardashevskiy
---
arch/powerpc/platforms/powernv/pci.h | 1 +
arch/powerpc/platforms/powernv/pci-ioda.c | 5 -
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/platforms/powernv/pci.h
b/arch/powerpc/platforms/powernv/pci.h
index eada4b6..1408247 100644
--- a/arch/powerpc/platforms/powernv/pci.h
+++ b/arch/powerpc/platforms/powernv/pci.h
@@ -23,6 +23,7 @@ enum pnv_phb_model {
PNV_PHB_MODEL_UNKNOWN,
PNV_PHB_MODEL_P7IOC,
PNV_PHB_MODEL_PHB3,
+ PNV_PHB_MODEL_PHB4,
PNV_PHB_MODEL_NPU,
PNV_PHB_MODEL_NPU2,
};
diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c
b/arch/powerpc/platforms/powernv/pci-ioda.c
index 9239142..66c2804 100644
--- a/arch/powerpc/platforms/powernv/pci-ioda.c
+++ b/arch/powerpc/platforms/powernv/pci-ioda.c
@@ -1882,7 +1882,8 @@ static int pnv_pci_ioda_dma_set_mask(struct pci_dev
*pdev, u64 dma_mask)
if (dma_mask >> 32 &&
dma_mask > (memory_hotplug_max() + (1ULL << 32)) &&
pnv_pci_ioda_pe_single_vendor(pe) &&
- phb->model == PNV_PHB_MODEL_PHB3) {
+ (phb->model == PNV_PHB_MODEL_PHB3 ||
+phb->model == PNV_PHB_MODEL_PHB4)) {
/* Configure the bypass mode */
rc = pnv_pci_ioda_dma_64bit_bypass(pe);
if (rc)
@@ -3930,6 +3931,8 @@ static void __init pnv_pci_init_ioda_phb(struct
device_node *np,
phb->model = PNV_PHB_MODEL_P7IOC;
else if (of_device_is_compatible(np, "ibm,power8-pciex"))
phb->model = PNV_PHB_MODEL_PHB3;
+ else if (of_device_is_compatible(np, "ibm,power9-pciex"))
+ phb->model = PNV_PHB_MODEL_PHB4;
else if (of_device_is_compatible(np, "ibm,power8-npu-pciex"))
phb->model = PNV_PHB_MODEL_NPU;
else if (of_device_is_compatible(np, "ibm,power9-npu-pciex"))
--
2.11.0
[PATCH kernel 1/2] powerpc/powernv: Reuse existing TCE code for sketchy bypass
The existing sketchy bypass ignores the existing default 32bit TCE table
(created by default for every PE at boot time or after being used by
VFIO) and it allocates another table instead without updating PE DMA
config (pe->table_group). So if we decide to use such device for VFIO
later, this new table will also leak memory.
This replaces adhoc table allocation and programming with the existing
API which handles memory leaks.
This programs the default 32bit table back to TVE#0 if configuring
the new table failed for some reason.
While we are at it, switch from the hardcoded 256MB TCEs to the biggest
size supported by the hardware and reported by the firmware. This allows
the sketchy bypass (originally made for POWER8 only) to work on POWER9
too assuming that PHB4 type is defined and pnv_pci_ioda_dma_64bit_bypass()
is called (coming next).
This does not call iommu_init_table() for the new table as the caller
will use _nommu_ops and therefore ::it_map is not needed.
Signed-off-by: Alexey Kardashevskiy
---
Tested with:
if (pe->tce_bypass_enabled) {
top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1;
- bypass = (dma_mask >= top);
+ bypass = false;//(dma_mask >= top);
}
---
arch/powerpc/platforms/powernv/pci-ioda.c | 71 +--
1 file changed, 39 insertions(+), 32 deletions(-)
diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c
b/arch/powerpc/platforms/powernv/pci-ioda.c
index ceb7e64..9239142 100644
--- a/arch/powerpc/platforms/powernv/pci-ioda.c
+++ b/arch/powerpc/platforms/powernv/pci-ioda.c
@@ -1791,54 +1791,61 @@ static bool pnv_pci_ioda_pe_single_vendor(struct
pnv_ioda_pe *pe)
*
* Currently this will only work on PHB3 (POWER8).
*/
+static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group,
+ int num, __u32 page_shift, __u64 window_size, __u32 levels,
+ struct iommu_table **ptbl);
+
+static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group,
+ int num, struct iommu_table *tbl);
+
+static unsigned long pnv_ioda_parse_tce_sizes(struct pnv_phb *phb);
+
static int pnv_pci_ioda_dma_64bit_bypass(struct pnv_ioda_pe *pe)
{
- u64 window_size, table_size, tce_count, addr;
- struct page *table_pages;
- u64 tce_order = 28; /* 256MB TCEs */
- __be64 *tces;
+ u64 window_size;
s64 rc;
+ struct iommu_table *tbl, *oldtbl = NULL;
+ unsigned long shift, offset;
/*
* Window size needs to be a power of two, but needs to account for
* shifting memory by the 4GB offset required to skip 32bit space.
*/
- window_size = roundup_pow_of_two(memory_hotplug_max() + (1ULL << 32));
- tce_count = window_size >> tce_order;
- table_size = tce_count << 3;
-
- if (table_size < PAGE_SIZE)
- table_size = PAGE_SIZE;
+ window_size = roundup_pow_of_two(memory_hotplug_max() + SZ_4G);
+ shift = ilog2(pnv_ioda_parse_tce_sizes(pe->phb));
+ rc = pnv_pci_ioda2_create_table(>table_group, 0, shift, window_size,
+ POWERNV_IOMMU_DEFAULT_LEVELS, );
+ if (rc) {
+ pe_err(pe, "Failed to create 64-bypass TCE table, err %ld", rc);
+ return rc;
+ }
- table_pages = alloc_pages_node(pe->phb->hose->node, GFP_KERNEL,
- get_order(table_size));
- if (!table_pages)
+ offset = SZ_4G >> shift;
+ rc = tbl->it_ops->set(tbl, offset, tbl->it_size - offset,
+ 0 /* uaddr */, DMA_BIDIRECTIONAL, 0 /* attrs */);
+ if (rc)
goto err;
- tces = page_address(table_pages);
- if (!tces)
+ if (pe->table_group.tables[0]) {
+ oldtbl = pe->table_group.tables[0];
+ pnv_pci_ioda2_unset_window(>table_group, 0);
+ }
+
+ rc = pnv_pci_ioda2_set_window(>table_group, 0, tbl);
+ if (rc != OPAL_SUCCESS) {
+ rc = pnv_pci_ioda2_set_window(>table_group, 0, oldtbl);
goto err;
+ }
- memset(tces, 0, table_size);
+ if (oldtbl)
+ iommu_tce_table_put(oldtbl);
- for (addr = 0; addr < memory_hotplug_max(); addr += (1 << tce_order)) {
- tces[(addr + (1ULL << 32)) >> tce_order] =
- cpu_to_be64(addr | TCE_PCI_READ | TCE_PCI_WRITE);
- }
+ pe_info(pe, "Using 64-bit DMA iommu bypass (through TVE#0)\n");
+ return 0;
- rc = opal_pci_map_pe_dma_window(pe->phb->opal_id,
- pe->pe_number,
- /* reconfigure window 0 */
- (pe->pe_number << 1) + 0,
- 1,
- __pa(tces),
- table_size,
-
[PATCH kernel 0/2] powerpc/powernv: Rework sketchy bypass
I came across this adhoc implementation and thought it could use some polishing. This fixes memory leaks and add P9 support. Based on the current upstream. Please comment. Thanks. Alexey Kardashevskiy (2): powerpc/powernv: Reuse existing TCE code for sketchy bypass powerpc/powernv: Define PHB4 type and enable sketchy bypass on POWER9 arch/powerpc/platforms/powernv/pci.h | 1 + arch/powerpc/platforms/powernv/pci-ioda.c | 76 +-- 2 files changed, 44 insertions(+), 33 deletions(-) -- 2.11.0
[PATCH kernel] powerpc/powernv/ioda2: Reduce upper limit for DMA window size
We use PHB in mode1 which uses bit 59 to select a correct DMA window. However there is mode2 which uses bits 59:55 and allows up to 32 DMA windows per a PE. Even though documentation does not clearly specify that, it seems that the actual hardware does not support bits 59:55 even in mode1, in other words we can create a window as big as 1<<58 but DMA simply won't work. This reduces the upper limit from 59 to 55 bits to let the userspace know about the hardware limits. Fixes: 7aafac11e3 "powerpc/powernv/ioda2: Gracefully fail if too many TCE levels requested" Signed-off-by: Alexey Kardashevskiy --- arch/powerpc/platforms/powernv/pci-ioda.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c b/arch/powerpc/platforms/powernv/pci-ioda.c index 92ca662..50e21d7 100644 --- a/arch/powerpc/platforms/powernv/pci-ioda.c +++ b/arch/powerpc/platforms/powernv/pci-ioda.c @@ -2839,7 +2839,7 @@ static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset, level_shift = entries_shift + 3; level_shift = max_t(unsigned, level_shift, PAGE_SHIFT); - if ((level_shift - 3) * levels + page_shift >= 60) + if ((level_shift - 3) * levels + page_shift >= 55) return -EINVAL; /* Allocate TCE table */ -- 2.11.0
Re: [PATCH] crypto/nx: Initialize 842 high and normal RxFIFO control registers
Haren Myneni writes:
> NX increments readOffset by FIFO size in receive FIFO control register
> when CRB is read. But the index in RxFIFO has to match with the
> corresponding entry in FIFO maintained by VAS in kernel. Otherwise NX
> may be processing incorrect CRBs and can cause CRB timeout.
>
> VAS FIFO offset is 0 when the receive window is opened during
> initialization. When the module is reloaded or in kexec boot, readOffset
> in FIFO control register may not match with VAS entry. This patch adds
> nx_coproc_init OPAL call to reset readOffset and queued entries in FIFO
> control register for both high and normal FIFOs.
>
> Signed-off-by: Haren Myneni
>
> diff --git a/arch/powerpc/include/asm/opal-api.h
> b/arch/powerpc/include/asm/opal-api.h
> index d886a5b..ff61e4b 100644
> --- a/arch/powerpc/include/asm/opal-api.h
> +++ b/arch/powerpc/include/asm/opal-api.h
> @@ -206,7 +206,8 @@
> #define OPAL_NPU_TL_SET 161
> #define OPAL_PCI_GET_PBCQ_TUNNEL_BAR 164
> #define OPAL_PCI_SET_PBCQ_TUNNEL_BAR 165
> -#define OPAL_LAST165
> +#define OPAL_NX_COPROC_INIT 167
> +#define OPAL_LAST167
>
> /* Device tree flags */
>
> diff --git a/arch/powerpc/include/asm/opal.h b/arch/powerpc/include/asm/opal.h
> index 7159e1a..d79eb82 100644
> --- a/arch/powerpc/include/asm/opal.h
> +++ b/arch/powerpc/include/asm/opal.h
> @@ -288,6 +288,7 @@ int64_t opal_imc_counters_init(uint32_t type, uint64_t
> address,
> int opal_get_power_shift_ratio(u32 handle, int token, u32 *psr);
> int opal_set_power_shift_ratio(u32 handle, int token, u32 psr);
> int opal_sensor_group_clear(u32 group_hndl, int token);
> +int opal_nx_coproc_init(uint32_t chip_id, uint32_t ct);
>
> s64 opal_signal_system_reset(s32 cpu);
>
> diff --git a/arch/powerpc/platforms/powernv/opal-wrappers.S
> b/arch/powerpc/platforms/powernv/opal-wrappers.S
> index 3da30c2..c7541a9 100644
> --- a/arch/powerpc/platforms/powernv/opal-wrappers.S
> +++ b/arch/powerpc/platforms/powernv/opal-wrappers.S
> @@ -325,3 +325,4 @@ OPAL_CALL(opal_npu_spa_clear_cache,
> OPAL_NPU_SPA_CLEAR_CACHE);
> OPAL_CALL(opal_npu_tl_set, OPAL_NPU_TL_SET);
> OPAL_CALL(opal_pci_get_pbcq_tunnel_bar,
> OPAL_PCI_GET_PBCQ_TUNNEL_BAR);
> OPAL_CALL(opal_pci_set_pbcq_tunnel_bar,
> OPAL_PCI_SET_PBCQ_TUNNEL_BAR);
> +OPAL_CALL(opal_nx_coproc_init, OPAL_NX_COPROC_INIT);
> diff --git a/arch/powerpc/platforms/powernv/opal.c
> b/arch/powerpc/platforms/powernv/opal.c
> index 48fbb41..5e13908 100644
> --- a/arch/powerpc/platforms/powernv/opal.c
> +++ b/arch/powerpc/platforms/powernv/opal.c
> @@ -1035,3 +1035,5 @@ void powernv_set_nmmu_ptcr(unsigned long ptcr)
> EXPORT_SYMBOL_GPL(opal_int_set_mfrr);
> EXPORT_SYMBOL_GPL(opal_int_eoi);
> EXPORT_SYMBOL_GPL(opal_error_code);
> +/* Export the below symbol for NX compression */
> +EXPORT_SYMBOL(opal_nx_coproc_init);
> diff --git a/drivers/crypto/nx/nx-842-powernv.c
> b/drivers/crypto/nx/nx-842-powernv.c
> index 1e87637..6c4784d 100644
> --- a/drivers/crypto/nx/nx-842-powernv.c
> +++ b/drivers/crypto/nx/nx-842-powernv.c
> @@ -24,6 +24,8 @@
> #include
> #include
> #include
> +#include
> +#include
>
> MODULE_LICENSE("GPL");
> MODULE_AUTHOR("Dan Streetman ");
> @@ -803,9 +805,26 @@ static int __init vas_cfg_coproc_info(struct device_node
> *dn, int chip_id,
> if (!coproc)
> return -ENOMEM;
>
> - if (!strcmp(priority, "High"))
> + if (!strcmp(priority, "High")) {
> + /*
> + * (lpid, pid, tid) combination has to be unique for each
> + * coprocessor instance in the system. So to make it
> + * unique, skiboot uses coprocessor type such as 842 or
> + * GZIP for pid and provides this value to kernel in pid
> + * device-tree property.
> + *
> + * Initialize each NX instance for both high and normal
> + * priority FIFOs.
> + */
> + ret = opal_nx_coproc_init(chip_id, pid);
> + if (ret) {
> + pr_err("Failed to initialize NX coproc: %d\n", ret);
> + ret = opal_error_code(ret);
> + goto err_out;
> + }
> +
> coproc->ct = VAS_COP_TYPE_842_HIPRI;
I think this should be called for all priority queues as it would be at
least theoretically possible to only have Normal priority queues, in
which case this patch wouldn't fix the problem.
--
Stewart Smith
OPAL Architect, IBM.
Re: [PATCH] crypto/nx: Initialize 842 high and normal RxFIFO control registers
On 05/31/2018 08:52 PM, Stewart Smith wrote: > Haren Myneni writes: >> NX increments readOffset by FIFO size in receive FIFO control register >> when CRB is read. But the index in RxFIFO has to match with the >> corresponding entry in FIFO maintained by VAS in kernel. Otherwise NX >> may be processing incorrect CRBs and can cause CRB timeout. >> >> VAS FIFO offset is 0 when the receive window is opened during >> initialization. When the module is reloaded or in kexec boot, readOffset >> in FIFO control register may not match with VAS entry. This patch adds >> nx_coproc_init OPAL call to reset readOffset and queued entries in FIFO >> control register for both high and normal FIFOs. >> >> Signed-off-by: Haren Myneni > > I've yet to go and check out the skiboot patch properly, but should this > be both: > Fixes: b0d6c9bab crypto/nx: Add P9 NX support for 842 compression engine > CC: stable # v4.14+ > > as otherwise "rmmod ; insmod" will crash, and possibly even issues over kexec? > Correct, P9 NX support is included in 4.14. We also need fix in stable trees (4.14+). But this patch will not apply cleanly. I will post different patch for 4.14 and 4.16 stable trees. Thanks Haren
