Pull request: scottwood/linux.git next
Highlights include elimination of legacy clock bindings use from dts files, an 83xx watchdog handler, fixes to old dts interrupt errors, and some minor cleanup. The following changes since commit 8c6c942d33f2a79439e86f8f406afae40a5bc767: powerpc/eeh: Fix debugfs_simple_attr.cocci warnings (2018-12-20 22:59:03 +1100) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/scottwood/linux.git next for you to fetch changes up to 5f470b3638a4ed03df79b993ece819cac2f4ca7e: powerpc/configs/85xx: Enable CONFIG_DEBUG_KERNEL (2018-12-21 22:07:54 -0600) Alexandre Belloni (1): powerpc/fsl-rio: fix spelling mistake "reserverd" -> "reserved" Christoph Hellwig (1): powerpc/fsl_pci: simplify fsl_pci_dma_set_mask Christophe Leroy (1): powerpc/83xx: handle machine check caused by watchdog timer Sabyasachi Gupta (1): arch/powerpc/fsl_rmu: Use dma_zalloc_coherent Scott Wood (3): powerpc/fsl: Use new clockgen binding powerpc/dts/fsl: Fix dtc-flagged interrupt errors powerpc/configs/85xx: Enable CONFIG_DEBUG_KERNEL Yuantian Tang (1): clk: qoriq: add more compatibles strings .../devicetree/bindings/clock/qoriq-clock.txt | 6 + arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi | 4 +- arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi | 8 +- arch/powerpc/boot/dts/fsl/b4si-post.dtsi | 15 --- arch/powerpc/boot/dts/fsl/mpc8641_hpcn.dts | 128 ++--- arch/powerpc/boot/dts/fsl/mpc8641_hpcn_36b.dts | 128 ++--- arch/powerpc/boot/dts/fsl/mpc8641si-post.dtsi | 2 + arch/powerpc/boot/dts/fsl/p1020rdb-pc.dtsi | 4 +- arch/powerpc/boot/dts/fsl/p2041si-post.dtsi| 18 --- arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi | 8 +- arch/powerpc/boot/dts/fsl/p3041si-post.dtsi| 18 --- arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi | 8 +- arch/powerpc/boot/dts/fsl/p4080si-post.dtsi| 70 --- arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi | 16 +-- arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi | 4 +- arch/powerpc/boot/dts/fsl/p5040si-post.dtsi| 18 --- arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi | 8 +- arch/powerpc/boot/dts/fsl/qoriq-clockgen1.dtsi | 47 arch/powerpc/boot/dts/fsl/qoriq-clockgen2.dtsi | 30 - arch/powerpc/boot/dts/fsl/t1023si-post.dtsi| 16 --- arch/powerpc/boot/dts/fsl/t102xsi-pre.dtsi | 4 +- arch/powerpc/boot/dts/fsl/t1040si-post.dtsi| 44 --- arch/powerpc/boot/dts/fsl/t104xsi-pre.dtsi | 8 +- arch/powerpc/boot/dts/fsl/t2081si-post.dtsi| 22 arch/powerpc/boot/dts/fsl/t208xsi-pre.dtsi | 8 +- arch/powerpc/boot/dts/fsl/t4240si-post.dtsi| 61 -- arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi | 24 ++-- arch/powerpc/boot/dts/mpc832x_rdb.dts | 4 - arch/powerpc/configs/fsl-emb-nonhw.config | 1 + arch/powerpc/include/asm/cputable.h| 1 + arch/powerpc/include/asm/reg.h | 2 + arch/powerpc/kernel/cputable.c | 10 +- arch/powerpc/platforms/83xx/misc.c | 17 +++ arch/powerpc/sysdev/fsl_pci.c | 6 +- arch/powerpc/sysdev/fsl_rio.h | 2 +- arch/powerpc/sysdev/fsl_rmu.c | 4 +- 36 files changed, 218 insertions(+), 556 deletions(-)
Re: [PATCH 1/2 v3] powerpc/fsl: Use new clockgen binding
On Wed, 2018-12-12 at 01:57 +, Andy Tang wrote:
> > -Original Message-
> > From: Scott Wood
> > Sent: 2018年11月26日 9:19
> > To: Andy Tang
> > Cc: mturque...@baylibre.com; sb...@kernel.org; robh...@kernel.org;
> > mark.rutl...@arm.com; b...@kernel.crashing.org; pau...@samba.org;
> > m...@ellerman.id.au; linux-...@vger.kernel.org;
> > devicet...@vger.kernel.org; linux-ker...@vger.kernel.org;
> > linuxppc-dev@lists.ozlabs.org
> > Subject: Re: [PATCH 1/2 v3] powerpc/fsl: Use new clockgen binding
> >
> > On Wed, 2018-10-31 at 14:57 +0800, Yuantian Tang wrote:
> > > From: Scott Wood
> > >
> > > The driver retains compatibility with old device trees, but we don't
> > > want the old nodes lying around to be copied, or used as a reference
> > > (some of the mux options are incorrect), or even just being clutter.
> > >
> > >
> > > +sysclk: sysclk {
> > > + compatible = "fixed-clock";
> > > + #clock-cells = <0>;
> > > + clock-frequency = <1>;
> > > + clock-output-names = "sysclk";
> > > +};
> > > +
> > > clockgen: global-utilities@e1000 {
> >
> > The U-Boot fixup won't work with this. U-Boot patches the frequency
> > directly into the clockgen node (BTW, this is another reason to preserve
> > the generic
> > 1.0/2.0 compatible string). The new binding does not require an input
> > clock node when it is provided as clock-frequency directly in the clockgen
> > node -- and the sysclk node was not in my original patch (nor did you note
> > that you made changes from that original). Why did you add it?
> >
> > I would just remove it when applying, but I'm concerned that this
> > indicates
> > a lack of testing (and I don't have the hardware access to test it myself,
> > except on t4240) -- unless the 100 MHz sysclk just happened to be correct
> > on the machines you tested (which would also be a test coverage
> > problem)?
>
> [Andy] You are right. Sysclk may not be useful anymore.
> Uboot will fixup the clockgen node correctly. Please apply this patch
> without sysclk. We will
> test it and catch the error if the clock is not fixed correctly.
OK.
> BTW, which git tree are you going to apply it on? This one?
>
https://git.kernel.org/pub/scm/linux/kernel/git/scottwood/linux.git/log/?h=next
That will be the branch I use to send the patches to Michael, but it's not a
branch that is kept constantly updated. If you're asking what tree to base
future patches on, that would generally be the next branch of
powerpc/linux.git (unless you depend on something else that isn't there yet).
-Scott
[PATCH] dmaengine: fsldma: Add 64-bit I/O accessors for powerpc64
Otherwise 64-bit PPC builds fail with undefined references
to these accessors.
Cc: Peng Ma
Cc: Wen He
Fixes: 68997fff94afa (" dmaengine: fsldma: Adding macro FSL_DMA_IN/OUT
implement for ARM platform")
Signed-off-by: Scott Wood
---
Is there any reason why ioreadXXbe() etc can't be used on PPC as well?
drivers/dma/fsldma.h | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/dma/fsldma.h b/drivers/dma/fsldma.h
index 88db939c04a1..a9b12f82b5c3 100644
--- a/drivers/dma/fsldma.h
+++ b/drivers/dma/fsldma.h
@@ -202,7 +202,12 @@ struct fsldma_chan {
#define fsl_iowrite32(v, p)out_le32(p, v)
#define fsl_iowrite32be(v, p) out_be32(p, v)
-#ifndef __powerpc64__
+#ifdef __powerpc64__
+#define fsl_ioread64(p)in_le64(p)
+#define fsl_ioread64be(p) in_be64(p)
+#define fsl_iowrite64(v, p)out_le64(p, v)
+#define fsl_iowrite64be(v, p) out_be64(p, v)
+#else
static u64 fsl_ioread64(const u64 __iomem *addr)
{
u32 fsl_addr = lower_32_bits(addr);
--
2.17.1
[PATCH] powerpc/configs/85xx: Enable CONFIG_DEBUG_KERNEL
This is required for CONFIG_DEBUG_INFO to work. Signed-off-by: Scott Wood --- arch/powerpc/configs/fsl-emb-nonhw.config | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/powerpc/configs/fsl-emb-nonhw.config b/arch/powerpc/configs/fsl-emb-nonhw.config index e0567dc41968..d592ba27b122 100644 --- a/arch/powerpc/configs/fsl-emb-nonhw.config +++ b/arch/powerpc/configs/fsl-emb-nonhw.config @@ -25,6 +25,7 @@ CONFIG_CRYPTO_SHA256=y CONFIG_CRYPTO_SHA512=y CONFIG_DEBUG_FS=y CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_KERNEL=y CONFIG_DEBUG_SHIRQ=y CONFIG_DETECT_HUNG_TASK=y CONFIG_DEVTMPFS_MOUNT=y -- 2.17.1
Re: [PATCH 2/3] powerpc/dts/fsl: t4240rdb: use the Cortina PHY driver compatible
On Wed, 2018-07-18 at 14:46 +0300, Camelia Groza wrote:
> The Cortina PHY requires the use of the dedicated Cortina PHY driver
> instead of the generic one.
>
> Signed-off-by: Camelia Groza
> ---
> arch/powerpc/boot/dts/fsl/t4240rdb.dts | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/arch/powerpc/boot/dts/fsl/t4240rdb.dts
> b/arch/powerpc/boot/dts/fsl/t4240rdb.dts
> index 15eb0a3..a56a705 100644
> --- a/arch/powerpc/boot/dts/fsl/t4240rdb.dts
> +++ b/arch/powerpc/boot/dts/fsl/t4240rdb.dts
> @@ -267,22 +267,22 @@
>
> mdio@fd000 {
> xfiphy1: ethernet-phy@10 {
> - compatible = "ethernet-phy-ieee802.3-
> c45";
> + compatible = "ethernet-phy-
> id13e5.1002";
> reg = <0x10>;
> };
>
> xfiphy2: ethernet-phy@11 {
> - compatible = "ethernet-phy-ieee802.3-
> c45";
> + compatible = "ethernet-phy-
> id13e5.1002";
> reg = <0x11>;
> };
>
> xfiphy3: ethernet-phy@13 {
> - compatible = "ethernet-phy-ieee802.3-
> c45";
> + compatible = "ethernet-phy-
> id13e5.1002";
> reg = <0x13>;
> };
>
> xfiphy4: ethernet-phy@12 {
> - compatible = "ethernet-phy-ieee802.3-
> c45";
> + compatible = "ethernet-phy-
> id13e5.1002";
> reg = <0x12>;
> };
> };
I get crashes on boot when using a dtb with this change:
libphy: Fixed MDIO Bus: probed
iommu: Adding device ffe488000.port to group 61
libphy: Freescale XGMAC MDIO Bus: probed
mdio_bus ffe4e1000: Error while reading PHY0 reg at 3.3
iommu: Adding device ffe489000.port to group 63
libphy: Freescale XGMAC MDIO Bus: probed
mdio_bus ffe4e3000: Error while reading PHY0 reg at 3.3
iommu: Adding device ffe48a000.port to group 64
libphy: Freescale XGMAC MDIO Bus: probed
mdio_bus ffe4e5000: Error while reading PHY0 reg at 3.3
iommu: Adding device ffe48b000.port to group 65
libphy: Freescale XGMAC MDIO Bus: probed
mdio_bus ffe4e7000: Error while reading PHY0 reg at 3.3
iommu: Adding device ffe48c000.port to group 66
libphy: Freescale XGMAC MDIO Bus: probed
mdio_bus ffe4e9000: Error while reading PHY0 reg at 3.3
iommu: Adding device ffe48d000.port to group 67
libphy: Freescale XGMAC MDIO Bus: probed
mdio_bus ffe4eb000: Error while reading PHY0 reg at 3.3
iommu: Adding device ffe49.port to group 68
libphy: Freescale XGMAC MDIO Bus: probed
iommu: Adding device ffe491000.port to group 69
libphy: Freescale XGMAC MDIO Bus: probed
libphy: Freescale XGMAC MDIO Bus: probed
libphy: Freescale XGMAC MDIO Bus: probed
BUG: Kernel NULL pointer dereference at 0x
Faulting instruction address: 0xc0842c1c
Oops: Kernel access of bad area, sig: 11 [#1]
BE SMP NR_CPUS=24 CoreNet Generic
Modules linked in:
CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.20.0-rc2+ #25
NIP: c0842c1c LR: c063426c CTR: c06341e8
REGS: c002ef1626b0 TRAP: 0300 Not tainted (4.20.0-rc2+)
MSR: 80029000 CR: 24008482 XER: 2000
DEAR: ESR: IRQMASK: 0
GPR00: c054810c c002ef162940 c0f73a00 c002ef1629b4
GPR04: c002ed64d128 c002ed64d128
GPR08: c002ef158000 0001
GPR12: 84008488 c10f3000 c0002464
GPR16: 0010
GPR20: c0cad9c0 c0c8c5e0 f000 c0c8c600
GPR24: c0a38db8 c002ec4ab748
GPR28: c10e3b70 c0e81540 c002ec4ab400
NIP [c0842c1c] .ethtool_convert_link_mode_to_legacy_u32+0x0/0x10
LR [c063426c] .phy_probe+0x84/0x320
Call Trace:
[c002ef162940] [c002ec4ab410] 0xc002ec4ab410 (unreliable)
[c002ef1629f0] [c054810c] .really_probe+0x268/0x3d0
[c002ef162a90] [c0545798] .bus_for_each_drv+0x7c/0xdc
[c002ef162b30] [c0547e58] .__device_attach+0x108/0x14c
[c002ef162bd0] [c0546db4] .bus_probe_device+0xcc/0xd8
[c002ef162c60] [c0543ffc] .device_add+0x4f8/0x6f8
[c002ef162d30] [c0633894] .phy_device_register+0x68/0xc8
[c002ef162db0] [c07be7a0] .of_mdiobus_register_phy+0x150/0x1dc
[c002ef162e50] [c07beea8] .of_mdiobus_register+0x14c/0x37c
[c002ef162f40]
[PATCH] powerpc/dts/fsl: Fix dtc-flagged interrupt errors
mpc8641_hpcn was updated to 4-cell interrupt specifiers, but PCI interrupt-map was not updated. It was also missing #interrupt-cells on the outer PCI buses. p1020rdb-pc was updated to 4-cell interrupt specifiers, but the ethernet-phy nodes weren't updated. mpc832x_rdb had an invalid "interrupts = <0>" on the ethernet-phy nodes. Besides being the wrong number of cells, 0 is not a valid IPIC interrupt according to ipic.c. Presumably it was meant to indicate that these PHYs are not connected to an interrupt. Signed-off-by: Scott Wood --- arch/powerpc/boot/dts/fsl/mpc8641_hpcn.dts| 128 +- .../powerpc/boot/dts/fsl/mpc8641_hpcn_36b.dts | 128 +- arch/powerpc/boot/dts/fsl/mpc8641si-post.dtsi | 2 + arch/powerpc/boot/dts/fsl/p1020rdb-pc.dtsi| 4 +- arch/powerpc/boot/dts/mpc832x_rdb.dts | 4 - 5 files changed, 132 insertions(+), 134 deletions(-) diff --git a/arch/powerpc/boot/dts/fsl/mpc8641_hpcn.dts b/arch/powerpc/boot/dts/fsl/mpc8641_hpcn.dts index 11bea3e6a43f..58ac17496c89 100644 --- a/arch/powerpc/boot/dts/fsl/mpc8641_hpcn.dts +++ b/arch/powerpc/boot/dts/fsl/mpc8641_hpcn.dts @@ -169,100 +169,100 @@ interrupt-map-mask = <0xff00 0 0 7>; interrupt-map = < /* IDSEL 0x11 func 0 - PCI slot 1 */ - 0x8800 0 0 1 2 1 - 0x8800 0 0 2 3 1 - 0x8800 0 0 3 4 1 - 0x8800 0 0 4 1 1 + 0x8800 0 0 1 2 1 0 0 + 0x8800 0 0 2 3 1 0 0 + 0x8800 0 0 3 4 1 0 0 + 0x8800 0 0 4 1 1 0 0 /* IDSEL 0x11 func 1 - PCI slot 1 */ - 0x8900 0 0 1 2 1 - 0x8900 0 0 2 3 1 - 0x8900 0 0 3 4 1 - 0x8900 0 0 4 1 1 + 0x8900 0 0 1 2 1 0 0 + 0x8900 0 0 2 3 1 0 0 + 0x8900 0 0 3 4 1 0 0 + 0x8900 0 0 4 1 1 0 0 /* IDSEL 0x11 func 2 - PCI slot 1 */ - 0x8a00 0 0 1 2 1 - 0x8a00 0 0 2 3 1 - 0x8a00 0 0 3 4 1 - 0x8a00 0 0 4 1 1 + 0x8a00 0 0 1 2 1 0 0 + 0x8a00 0 0 2 3 1 0 0 + 0x8a00 0 0 3 4 1 0 0 + 0x8a00 0 0 4 1 1 0 0 /* IDSEL 0x11 func 3 - PCI slot 1 */ - 0x8b00 0 0 1 2 1 - 0x8b00 0 0 2 3 1 - 0x8b00 0 0 3 4 1 - 0x8b00 0 0 4 1 1 + 0x8b00 0 0 1 2 1 0 0 + 0x8b00 0 0 2 3 1 0 0 + 0x8b00 0 0 3 4 1 0 0 + 0x8b00 0 0 4 1 1 0 0 /* IDSEL 0x11 func 4 - PCI slot 1 */ - 0x8c00 0 0 1 2 1 - 0x8c00 0 0 2 3 1 - 0x8c00 0 0 3 4 1 - 0x8c00 0 0 4 1 1 + 0x8c00 0 0 1 2 1 0 0 + 0x8c00 0 0 2 3 1 0 0 + 0x8c00 0 0 3 4 1 0 0 + 0x8c00 0 0 4 1 1 0 0 /* IDSEL 0x11 func 5 - PCI slot 1 */ - 0x8d00 0 0 1 2 1 - 0x8d00 0 0 2 3 1 - 0x8d00 0 0 3 4 1 - 0x8d00 0 0 4 1 1 + 0x8d00 0 0 1 2 1 0 0 + 0x8d00 0 0 2 3 1 0 0 + 0x8d00 0 0 3 4 1 0 0 + 0x8d00 0 0 4 1 1 0 0 /* IDSEL 0x11 func 6 - PCI slot 1 */ - 0x8e00 0 0 1 2 1 - 0x8e00 0 0 2 3 1 - 0x8e00 0 0 3 4 1 - 0x8e00 0 0 4 1 1 + 0x8e00 0 0 1 2 1 0 0 + 0x8e00 0 0 2 3 1 0 0 + 0x8e00 0 0 3 4 1 0 0 + 0x8e00 0 0 4 1 1 0 0 /* IDSEL 0x11 func 7 - PCI slot 1 */ - 0x8f00 0 0 1 2 1 - 0x8f00 0 0 2 3 1 - 0x8f00 0 0 3 4 1 - 0x8f00 0 0 4 1 1 + 0x8f00 0 0 1 2 1 0 0 + 0x8f00 0 0 2 3 1 0 0 + 0x8f00 0 0 3 4 1 0 0 + 0x8f00 0 0 4 1 1 0 0 /* IDSEL 0x12 func 0 - PCI slot 2 */ - 0x9000 0 0 1 3 1 - 0x9000 0 0 2 4 1 - 0x9000 0 0 3 1 1 - 0x9000 0 0 4 2 1 + 0x9000 0 0 1 3 1 0 0 + 0x9000 0 0 2 4 1 0 0 + 0x9000 0 0 3 1 1 0 0 + 0x9000 0 0 4 2 1 0 0
Re: [PATCH] soc: fsl: guts: us devm_kstrdup_const() for RO data
On Fri, 2018-12-07 at 09:22 +0100, Nicholas Mc Guire wrote: > devm_kstrdup() may return NULL if internal allocation failed, but > as machine is from the device tree, and thus RO, devm_kstrdup_const() > can be used here, which will only copy the reference. Is it really going to only copy the reference? That would require that is_kernel_rodata(machine) be true, which it shouldn't be since it's not part of the kernel image. -Scott
Re: [PATCH] arch/powerpc: Use dma_zalloc_coherent
On Thu, 2018-11-15 at 23:26 +0530, Sabyasachi Gupta wrote: > On Mon, Nov 5, 2018 at 7:52 AM Sabyasachi Gupta > wrote: > > > > Replaced dma_alloc_coherent + memset with dma_zalloc_coherent > > > > Signed-off-by: Sabyasachi Gupta > > Any comment on this patch? Just that FSL patches should be CCed to me, and the subject line is too broad (and duplicates another patch posted around the same time). I'm applying with the subject changed to "arch/powerpc/fsl_rmu: Use dma_zalloc_coherent". -Scott
Re: trace_hardirqs_on/off vs. extra stack frames
On Thu, 2018-12-20 at 21:02 -0500, Steven Rostedt wrote: > On Fri, 21 Dec 2018 12:11:35 +1100 > Benjamin Herrenschmidt wrote: > > > Hi Steven ! > > > > I'm trying to untangle something, and I need your help :-) > > > > In commit 3cb5f1a3e58c0bd70d47d9907cc5c65192281dee, you added a summy > > stack frame around the assembly calls to trace_hardirqs_on/off on the > > ground that when using the latency tracer (irqsoff), you might poke at > > CALLER_ADDR1 and that could blow up if there's only one frame at hand. > > > > However, I can't see where it would be doing that. lockdep.c only uses > > CALLER_ADDR0 and irqsoff uses the values passed by it. In fact, that > > was already the case when the above commit was merged. > > > > I tried on a 32-bit kernel to remove the dummy stack frame with no > > issue so far (though I do get stupid values reported with or > > without a stack frame, but I think that's normal, looking into it). > > BTW, I only had a 64 bit PPC working, so I would have been testing that. > > > The reason I'm asking is that we have other code path, on return > > from interrupts for example, at least on 32-bits where we call the > > tracing without the extra stack frame, and I yet to see it crash. > > Have you tried enabling the irqsoff tracer and running it for a while? > > echo irqsoff > /sys/kernel/debug/tracing/current_tracer > > The problem is that when we come from user space, and we disable > interrupts in the entry code, it calls into the irqsoff tracer: > > [ in userspace ] > > [ in kernel ] > bl .trace_hardirqs_off > > kernel/trace/trace_preemptirq.c: > >trace_hardirqs_off(CALLER_ADDR_0, CALLER_ADDR1) > > IIRC, without the stack frame, that CALLER_ADDR1 can end up having the > kernel read garbage. You're right, I was looking at a too old tree where trace_hardirqs_* is implemented in kernel/locking/lockdep.c and only uses CALLER_ADDR0. > > -- Steve > > > > I wonder if the commit and bug fix above relates to some older code > > that no longer existed even at the point where the commit was > merged...
[for-next][PATCH 05/24] powerpc/frace: Use ftrace_graph_get_ret_stack() instead of curr_ret_stack
From: "Steven Rostedt (VMware)"
The structure of the ret_stack array on the task struct is going to
change, and accessing it directly via the curr_ret_stack index will no
longer give the ret_stack entry that holds the return address. To access
that, architectures must now use ftrace_graph_get_ret_stack() to get the
associated ret_stack that matches the saved return address.
Cc: Benjamin Herrenschmidt
Cc: Paul Mackerras
Cc: Michael Ellerman
Cc: linuxppc-dev@lists.ozlabs.org
Signed-off-by: Steven Rostedt (VMware)
---
arch/powerpc/kernel/process.c | 13 +
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index 96f34730010f..ce393df243aa 100644
--- a/arch/powerpc/kernel/process.c
+++ b/arch/powerpc/kernel/process.c
@@ -2061,9 +2061,10 @@ void show_stack(struct task_struct *tsk, unsigned long
*stack)
int count = 0;
int firstframe = 1;
#ifdef CONFIG_FUNCTION_GRAPH_TRACER
- int curr_frame = current->curr_ret_stack;
+ struct ftrace_ret_stack *ret_stack;
extern void return_to_handler(void);
unsigned long rth = (unsigned long)return_to_handler;
+ int curr_frame = 0;
#endif
sp = (unsigned long) stack;
@@ -2089,9 +2090,13 @@ void show_stack(struct task_struct *tsk, unsigned long
*stack)
printk("["REG"] ["REG"] %pS", sp, ip, (void *)ip);
#ifdef CONFIG_FUNCTION_GRAPH_TRACER
if ((ip == rth) && curr_frame >= 0) {
- pr_cont(" (%pS)",
- (void
*)current->ret_stack[curr_frame].ret);
- curr_frame--;
+ ret_stack = ftrace_graph_get_ret_stack(current,
+ curr_frame++);
+ if (ret_stack)
+ pr_cont(" (%pS)",
+ (void *)ret_stack->ret);
+ else
+ curr_frame = -1;
}
#endif
if (firstframe)
--
2.19.2
[PATCH 11/11 v2] powerpc/fsl: Add FSL_PPC_BOOK3E as supported arch for nospectre_v2 boot arg
Signed-off-by: Diana Craciun --- v1-->v2 - no changes Documentation/admin-guide/kernel-parameters.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index aefd358..cf6b4c5 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -2827,7 +2827,7 @@ check bypass). With this option data leaks are possible in the system. - nospectre_v2[X86] Disable all mitigations for the Spectre variant 2 + nospectre_v2[X86,PPC_FSL_BOOK3E] Disable all mitigations for the Spectre variant 2 (indirect branch prediction) vulnerability. System may allow data leaks with this option, which is equivalent to spectre_v2=off. -- 2.5.5
[PATCH 09/11 v2] powerpc/fsl: Enable runtime patching if nospectre_v2 boot arg is used
If the user choses not to use the mitigations, replace the code sequence with nops. Signed-off-by: Diana Craciun --- v1-->v2 - no changes arch/powerpc/kernel/setup-common.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/powerpc/kernel/setup-common.c b/arch/powerpc/kernel/setup-common.c index 93ee370..f27eeda 100644 --- a/arch/powerpc/kernel/setup-common.c +++ b/arch/powerpc/kernel/setup-common.c @@ -974,6 +974,7 @@ void __init setup_arch(char **cmdline_p) ppc_md.setup_arch(); setup_barrier_nospec(); + setup_spectre_v2(); paging_init(); -- 2.5.5
[PATCH 06/11 v2] powerpc/fsl: Flush the branch predictor at each kernel entry (64bit)
In order to protect against speculation attacks on indirect branches, the branch predictor is flushed at kernel entry to protect for the following situations: - userspace process attacking another userspace process - userspace process attacking the kernel Basically when the privillege level change (i.e. the kernel is entered), the branch predictor state is flushed. Signed-off-by: Diana Craciun --- v1-->v2 - no change arch/powerpc/kernel/entry_64.S | 5 + arch/powerpc/kernel/exceptions-64e.S | 26 +- arch/powerpc/mm/tlb_low_64e.S| 7 +++ 3 files changed, 37 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S index 7b1693a..7c2032e 100644 --- a/arch/powerpc/kernel/entry_64.S +++ b/arch/powerpc/kernel/entry_64.S @@ -80,6 +80,11 @@ END_FTR_SECTION_IFSET(CPU_FTR_TM) std r0,GPR0(r1) std r10,GPR1(r1) beq 2f /* if from kernel mode */ +#ifdef CONFIG_PPC_FSL_BOOK3E +START_BTB_FLUSH_SECTION + BTB_FLUSH(r10) +END_BTB_FLUSH_SECTION +#endif ACCOUNT_CPU_USER_ENTRY(r13, r10, r11) 2: std r2,GPR2(r1) std r3,GPR3(r1) diff --git a/arch/powerpc/kernel/exceptions-64e.S b/arch/powerpc/kernel/exceptions-64e.S index 6d6e144..afb6387 100644 --- a/arch/powerpc/kernel/exceptions-64e.S +++ b/arch/powerpc/kernel/exceptions-64e.S @@ -296,7 +296,8 @@ ret_from_mc_except: andi. r10,r11,MSR_PR; /* save stack pointer */\ beq 1f; /* branch around if supervisor */ \ ld r1,PACAKSAVE(r13); /* get kernel stack coming from usr */\ -1: cmpdi cr1,r1,0; /* check if SP makes sense */ \ +1: type##_BTB_FLUSH\ + cmpdi cr1,r1,0; /* check if SP makes sense */ \ bge-cr1,exc_##n##_bad_stack;/* bad stack (TODO: out of line) */ \ mfspr r10,SPRN_##type##_SRR0; /* read SRR0 before touching stack */ @@ -328,6 +329,29 @@ ret_from_mc_except: #define SPRN_MC_SRR0 SPRN_MCSRR0 #define SPRN_MC_SRR1 SPRN_MCSRR1 +#ifdef CONFIG_PPC_FSL_BOOK3E +#define GEN_BTB_FLUSH \ + START_BTB_FLUSH_SECTION \ + beq 1f; \ + BTB_FLUSH(r10) \ + 1: \ + END_BTB_FLUSH_SECTION + +#define CRIT_BTB_FLUSH \ + START_BTB_FLUSH_SECTION \ + BTB_FLUSH(r10) \ + END_BTB_FLUSH_SECTION + +#define DBG_BTB_FLUSH CRIT_BTB_FLUSH +#define MC_BTB_FLUSH CRIT_BTB_FLUSH +#define GDBELL_BTB_FLUSH GEN_BTB_FLUSH +#else +#define GEN_BTB_FLUSH +#define CRIT_BTB_FLUSH +#define DBG_BTB_FLUSH +#define GDBELL_BTB_FLUSH +#endif + #define NORMAL_EXCEPTION_PROLOG(n, intnum, addition) \ EXCEPTION_PROLOG(n, intnum, GEN, addition##_GEN(n)) diff --git a/arch/powerpc/mm/tlb_low_64e.S b/arch/powerpc/mm/tlb_low_64e.S index 7fd20c5..9ed9006 100644 --- a/arch/powerpc/mm/tlb_low_64e.S +++ b/arch/powerpc/mm/tlb_low_64e.S @@ -70,6 +70,13 @@ END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV) std r15,EX_TLB_R15(r12) std r10,EX_TLB_CR(r12) #ifdef CONFIG_PPC_FSL_BOOK3E +START_BTB_FLUSH_SECTION + mfspr r11, SPRN_SRR1 + andi. r10,r11,MSR_PR + beq 1f + BTB_FLUSH(r10) +1: +END_BTB_FLUSH_SECTION std r7,EX_TLB_R7(r12) #endif TLB_MISS_PROLOG_STATS -- 2.5.5
[PATCH 10/11 v2] powerpc/fsl: Update Spectre v2 reporting
Report branch predictor state flush as a mitigation for
Spectre variant 2.
Signed-off-by: Diana Craciun
---
v1-->v2
- no changes
arch/powerpc/kernel/security.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/kernel/security.c b/arch/powerpc/kernel/security.c
index 4393a38..861fab3 100644
--- a/arch/powerpc/kernel/security.c
+++ b/arch/powerpc/kernel/security.c
@@ -212,8 +212,11 @@ ssize_t cpu_show_spectre_v2(struct device *dev, struct
device_attribute *attr, c
if (count_cache_flush_type == COUNT_CACHE_FLUSH_HW)
seq_buf_printf(, "(hardware accelerated)");
- } else
+ } else if (btb_flush_enabled) {
+ seq_buf_printf(, "Mitigation: Branch predictor state flush");
+ } else {
seq_buf_printf(, "Vulnerable");
+ }
seq_buf_printf(, "\n");
--
2.5.5
[PATCH 07/11 v2] powerpc/fsl: Flush the branch predictor at each kernel entry (32 bit)
In order to protect against speculation attacks on indirect branches, the branch predictor is flushed at kernel entry to protect for the following situations: - userspace process attacking another userspace process - userspace process attacking the kernel Basically when the privillege level change (i.e.the kernel is entered), the branch predictor state is flushed. Signed-off-by: Diana Craciun --- v1-->v2 - fixed warnings reported by the automated build system arch/powerpc/kernel/head_booke.h | 11 +++ arch/powerpc/kernel/head_fsl_booke.S | 15 +++ 2 files changed, 26 insertions(+) diff --git a/arch/powerpc/kernel/head_booke.h b/arch/powerpc/kernel/head_booke.h index d0862a1..27f5249 100644 --- a/arch/powerpc/kernel/head_booke.h +++ b/arch/powerpc/kernel/head_booke.h @@ -32,6 +32,15 @@ */ #define THREAD_NORMSAVE(offset)(THREAD_NORMSAVES + (offset * 4)) +#ifdef CONFIG_PPC_FSL_BOOK3E +#define BOOKE_CLEAR_BTB(reg) \ +START_BTB_FLUSH_SECTION \ + BTB_FLUSH(reg) \ +END_BTB_FLUSH_SECTION +#else +#define BOOKE_CLEAR_BTB(reg) +#endif + #define NORMAL_EXCEPTION_PROLOG(intno) \ mtspr SPRN_SPRG_WSCRATCH0, r10; /* save one register */ \ mfspr r10, SPRN_SPRG_THREAD; \ @@ -43,6 +52,7 @@ andi. r11, r11, MSR_PR; /* check whether user or kernel*/\ mr r11, r1; \ beq 1f; \ + BOOKE_CLEAR_BTB(r11)\ /* if from user, start at top of this thread's kernel stack */ \ lwz r11, THREAD_INFO-THREAD(r10);\ ALLOC_STACK_FRAME(r11, THREAD_SIZE); \ @@ -128,6 +138,7 @@ stw r9,_CCR(r8);/* save CR on stack*/\ mfspr r11,exc_level_srr1; /* check whether user or kernel*/\ DO_KVM BOOKE_INTERRUPT_##intno exc_level_srr1; \ + BOOKE_CLEAR_BTB(r10)\ andi. r11,r11,MSR_PR; \ mfspr r11,SPRN_SPRG_THREAD; /* if from user, start at top of */\ lwz r11,THREAD_INFO-THREAD(r11); /* this thread's kernel stack */\ diff --git a/arch/powerpc/kernel/head_fsl_booke.S b/arch/powerpc/kernel/head_fsl_booke.S index e2750b8..2386ce2 100644 --- a/arch/powerpc/kernel/head_fsl_booke.S +++ b/arch/powerpc/kernel/head_fsl_booke.S @@ -453,6 +453,13 @@ END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV) mfcrr13 stw r13, THREAD_NORMSAVE(3)(r10) DO_KVM BOOKE_INTERRUPT_DTLB_MISS SPRN_SRR1 +START_BTB_FLUSH_SECTION + mfspr r11, SPRN_SRR1 + andi. r10,r11,MSR_PR + beq 1f + BTB_FLUSH(r10) +1: +END_BTB_FLUSH_SECTION mfspr r10, SPRN_DEAR /* Get faulting address */ /* If we are faulting a kernel address, we have to use the @@ -547,6 +554,14 @@ END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV) mfcrr13 stw r13, THREAD_NORMSAVE(3)(r10) DO_KVM BOOKE_INTERRUPT_ITLB_MISS SPRN_SRR1 +START_BTB_FLUSH_SECTION + mfspr r11, SPRN_SRR1 + andi. r10,r11,MSR_PR + beq 1f + BTB_FLUSH(r10) +1: +END_BTB_FLUSH_SECTION + mfspr r10, SPRN_SRR0 /* Get faulting address */ /* If we are faulting a kernel address, we have to use the -- 2.5.5
[PATCH 01/11 v2] powerpc/fsl: Add infrastructure to fixup branch predictor flush
In order to protect against speculation attacks (Spectre
variant 2) on NXP PowerPC platforms, the branch predictor
should be flushed when the privillege level is changed.
This patch is adding the infrastructure to fixup at runtime
the code sections that are performing the branch predictor flush
depending on a boot arg parameter which is added later in a
separate patch.
Signed-off-by: Diana Craciun
---
v1-->v2
- no change
arch/powerpc/include/asm/feature-fixups.h | 12
arch/powerpc/include/asm/setup.h | 2 ++
arch/powerpc/kernel/vmlinux.lds.S | 8
arch/powerpc/lib/feature-fixups.c | 21 +
4 files changed, 43 insertions(+)
diff --git a/arch/powerpc/include/asm/feature-fixups.h
b/arch/powerpc/include/asm/feature-fixups.h
index 33b6f9c..40a6c926 100644
--- a/arch/powerpc/include/asm/feature-fixups.h
+++ b/arch/powerpc/include/asm/feature-fixups.h
@@ -221,6 +221,17 @@ label##3: \
FTR_ENTRY_OFFSET 953b-954b; \
.popsection;
+#define START_BTB_FLUSH_SECTION\
+955: \
+
+#define END_BTB_FLUSH_SECTION \
+956: \
+ .pushsection __btb_flush_fixup,"a"; \
+ .align 2; \
+957: \
+ FTR_ENTRY_OFFSET 955b-957b; \
+ FTR_ENTRY_OFFSET 956b-957b; \
+ .popsection;
#ifndef __ASSEMBLY__
#include
@@ -230,6 +241,7 @@ extern long __start___stf_entry_barrier_fixup,
__stop___stf_entry_barrier_fixup;
extern long __start___stf_exit_barrier_fixup, __stop___stf_exit_barrier_fixup;
extern long __start___rfi_flush_fixup, __stop___rfi_flush_fixup;
extern long __start___barrier_nospec_fixup, __stop___barrier_nospec_fixup;
+extern long __start__btb_flush_fixup, __stop__btb_flush_fixup;
void apply_feature_fixups(void);
void setup_feature_keys(void);
diff --git a/arch/powerpc/include/asm/setup.h b/arch/powerpc/include/asm/setup.h
index 1fffbba..c941c8c 100644
--- a/arch/powerpc/include/asm/setup.h
+++ b/arch/powerpc/include/asm/setup.h
@@ -67,6 +67,8 @@ void do_barrier_nospec_fixups_range(bool enable, void *start,
void *end);
static inline void do_barrier_nospec_fixups_range(bool enable, void *start,
void *end) { };
#endif
+void do_btb_flush_fixups(void);
+
#endif /* !__ASSEMBLY__ */
#endif /* _ASM_POWERPC_SETUP_H */
diff --git a/arch/powerpc/kernel/vmlinux.lds.S
b/arch/powerpc/kernel/vmlinux.lds.S
index 434581b..254b757 100644
--- a/arch/powerpc/kernel/vmlinux.lds.S
+++ b/arch/powerpc/kernel/vmlinux.lds.S
@@ -170,6 +170,14 @@ SECTIONS
}
#endif /* CONFIG_PPC_BARRIER_NOSPEC */
+#ifdef CONFIG_PPC_FSL_BOOK3E
+ . = ALIGN(8);
+ __spec_btb_flush_fixup : AT(ADDR(__spec_btb_flush_fixup) - LOAD_OFFSET)
{
+ __start__btb_flush_fixup = .;
+ *(__btb_flush_fixup)
+ __stop__btb_flush_fixup = .;
+ }
+#endif
EXCEPTION_TABLE(0)
NOTES :kernel :notes
diff --git a/arch/powerpc/lib/feature-fixups.c
b/arch/powerpc/lib/feature-fixups.c
index e613b02..02a213c 100644
--- a/arch/powerpc/lib/feature-fixups.c
+++ b/arch/powerpc/lib/feature-fixups.c
@@ -347,6 +347,27 @@ void do_barrier_nospec_fixups_range(bool enable, void
*fixup_start, void *fixup_
printk(KERN_DEBUG "barrier-nospec: patched %d locations\n", i);
}
+static void patch_btb_flush_section(long *curr)
+{
+ unsigned int *start, *end;
+
+ start = (void *)curr + *curr;
+ end = (void *)curr + *(curr + 1);
+ for (; start < end; start++) {
+ pr_devel("patching dest %lx\n", (unsigned long)start);
+ patch_instruction(start, PPC_INST_NOP);
+ }
+}
+void do_btb_flush_fixups(void)
+{
+ long *start, *end;
+
+ start = PTRRELOC(&__start__btb_flush_fixup);
+ end = PTRRELOC(&__stop__btb_flush_fixup);
+
+ for (; start < end; start += 2)
+ patch_btb_flush_section(start);
+}
#endif /* CONFIG_PPC_FSL_BOOK3E */
void do_lwsync_fixups(unsigned long value, void *fixup_start, void *fixup_end)
--
2.5.5
[PATCH 00/11 v2] powerpc/fsl: NXP PowerPC Spectre variant 2 workarounds
Implement Spectre variant 2 workarounds for NXP PowerPC Book3E processors. Diana Craciun (11): Add infrastructure to fixup branch predictor flush Add macro to flush the branch predictor Fix spectre_v2 mitigations reporting Emulate SPRN_BUCSR register Add nospectre_v2 command line argument Flush the branch predictor at each kernel entry (64bit) Flush the branch predictor at each kernel entry (32 bit) Flush branch predictor when entering KVM Enable runtime patching if nospectre_v2 boot arg is used Update Spectre v2 reporting Add FSL_PPC_BOOK3E as supported arch for nospectre_v2 boot arg Documentation/admin-guide/kernel-parameters.txt | 2 +- arch/powerpc/include/asm/feature-fixups.h | 12 +++ arch/powerpc/include/asm/ppc_asm.h | 10 + arch/powerpc/include/asm/setup.h| 7 +++ arch/powerpc/kernel/entry_64.S | 5 + arch/powerpc/kernel/exceptions-64e.S| 26 ++- arch/powerpc/kernel/head_booke.h| 11 ++ arch/powerpc/kernel/head_fsl_booke.S| 15 + arch/powerpc/kernel/security.c | 28 +++-- arch/powerpc/kernel/setup-common.c | 1 + arch/powerpc/kernel/vmlinux.lds.S | 8 +++ arch/powerpc/kvm/bookehv_interrupts.S | 4 arch/powerpc/kvm/e500_emulate.c | 5 + arch/powerpc/lib/feature-fixups.c | 21 +++ arch/powerpc/mm/tlb_low_64e.S | 7 +++ 15 files changed, 158 insertions(+), 4 deletions(-) -- 2.5.5
[PATCH 02/11 v2] powerpc/fsl: Add macro to flush the branch predictor
The BUCSR register can be used to invalidate the entries in the branch prediction mechanisms. Signed-off-by: Diana Craciun --- v1-->v2 - no change arch/powerpc/include/asm/ppc_asm.h | 10 ++ 1 file changed, 10 insertions(+) diff --git a/arch/powerpc/include/asm/ppc_asm.h b/arch/powerpc/include/asm/ppc_asm.h index b5d0236..5c901bf 100644 --- a/arch/powerpc/include/asm/ppc_asm.h +++ b/arch/powerpc/include/asm/ppc_asm.h @@ -821,4 +821,14 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601) stringify_in_c(.long (_target) - . ;) \ stringify_in_c(.previous) +#ifdef CONFIG_PPC_FSL_BOOK3E +#define BTB_FLUSH(reg) \ + lis reg,BUCSR_INIT@h; \ + ori reg,reg,BUCSR_INIT@l; \ + mtspr SPRN_BUCSR,reg; \ + isync; +#else +#define BTB_FLUSH(reg) +#endif /* CONFIG_PPC_FSL_BOOK3E */ + #endif /* _ASM_POWERPC_PPC_ASM_H */ -- 2.5.5
[PATCH 08/11 v2] powerpc/fsl: Flush branch predictor when entering KVM
Switching from the guest to host is another place where the speculative accesses can be exploited. Flush the branch predictor when entering KVM. Signed-off-by: Diana Craciun --- v1-->v2 - no changes arch/powerpc/kvm/bookehv_interrupts.S | 4 1 file changed, 4 insertions(+) diff --git a/arch/powerpc/kvm/bookehv_interrupts.S b/arch/powerpc/kvm/bookehv_interrupts.S index 051af7d..4e5081e 100644 --- a/arch/powerpc/kvm/bookehv_interrupts.S +++ b/arch/powerpc/kvm/bookehv_interrupts.S @@ -75,6 +75,10 @@ PPC_LL r1, VCPU_HOST_STACK(r4) PPC_LL r2, HOST_R2(r1) +START_BTB_FLUSH_SECTION + BTB_FLUSH(r10) +END_BTB_FLUSH_SECTION + mfspr r10, SPRN_PID lwz r8, VCPU_HOST_PID(r4) PPC_LL r11, VCPU_SHARED(r4) -- 2.5.5
[PATCH 04/11 v2] powerpc/fsl: Emulate SPRN_BUCSR register
In order to flush the branch predictor the guest kernel performs writes to the BUCSR register which is hypervisor privilleged. However, the branch predictor is flushed at each KVM entry, so the branch predictor has been already flushed, so just return as soon as possible to guest. Signed-off-by: Diana Craciun --- v1-->v2 - no change arch/powerpc/kvm/e500_emulate.c | 5 + 1 file changed, 5 insertions(+) diff --git a/arch/powerpc/kvm/e500_emulate.c b/arch/powerpc/kvm/e500_emulate.c index 3f8189e..d0eb670 100644 --- a/arch/powerpc/kvm/e500_emulate.c +++ b/arch/powerpc/kvm/e500_emulate.c @@ -276,6 +276,11 @@ int kvmppc_core_emulate_mtspr_e500(struct kvm_vcpu *vcpu, int sprn, ulong spr_va */ vcpu->arch.pwrmgtcr0 = spr_val; break; + /* if we are here, it means that we have already flushed the +* branch predictor, so just return to guest +*/ + case SPRN_BUCSR: + break; /* extra exceptions */ #ifdef CONFIG_SPE_POSSIBLE -- 2.5.5
[PATCH 03/11 v2] powerpc/fsl: Fix spectre_v2 mitigations reporting
Currently for CONFIG_PPC_FSL_BOOK3E
cat /sys/devices/system/cpu/vulnerabilities/spectre_v2 reports:
"Mitigation: Software count cache flush" which is wrong. Fix it
to report vulnerable for now.
Signed-off-by: Diana Craciun
---
v1->v2
- no change
arch/powerpc/kernel/security.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/kernel/security.c b/arch/powerpc/kernel/security.c
index f6f469f..1b395b8 100644
--- a/arch/powerpc/kernel/security.c
+++ b/arch/powerpc/kernel/security.c
@@ -22,7 +22,7 @@ enum count_cache_flush_type {
COUNT_CACHE_FLUSH_SW= 0x2,
COUNT_CACHE_FLUSH_HW= 0x4,
};
-static enum count_cache_flush_type count_cache_flush_type;
+static enum count_cache_flush_type count_cache_flush_type =
COUNT_CACHE_FLUSH_NONE;
bool barrier_nospec_enabled;
static bool no_nospec;
--
2.5.5
[PATCH 05/11 v2] powerpc/fsl: Add nospectre_v2 command line argument
When the command line argument is present, the Spectre variant 2
mitigations are disabled.
Signed-off-by: Diana Craciun
---
v1-->v2
- no changes
arch/powerpc/include/asm/setup.h | 5 +
arch/powerpc/kernel/security.c | 21 +
2 files changed, 26 insertions(+)
diff --git a/arch/powerpc/include/asm/setup.h b/arch/powerpc/include/asm/setup.h
index c941c8c..65676e2 100644
--- a/arch/powerpc/include/asm/setup.h
+++ b/arch/powerpc/include/asm/setup.h
@@ -67,6 +67,11 @@ void do_barrier_nospec_fixups_range(bool enable, void
*start, void *end);
static inline void do_barrier_nospec_fixups_range(bool enable, void *start,
void *end) { };
#endif
+#ifdef CONFIG_PPC_FSL_BOOK3E
+void setup_spectre_v2(void);
+#else
+static inline void setup_spectre_v2(void) {};
+#endif
void do_btb_flush_fixups(void);
#endif /* !__ASSEMBLY__ */
diff --git a/arch/powerpc/kernel/security.c b/arch/powerpc/kernel/security.c
index 1b395b8..4393a38 100644
--- a/arch/powerpc/kernel/security.c
+++ b/arch/powerpc/kernel/security.c
@@ -26,6 +26,10 @@ static enum count_cache_flush_type count_cache_flush_type =
COUNT_CACHE_FLUSH_NO
bool barrier_nospec_enabled;
static bool no_nospec;
+static bool btb_flush_enabled;
+#ifdef CONFIG_PPC_FSL_BOOK3E
+static bool no_spectrev2;
+#endif
static void enable_barrier_nospec(bool enable)
{
@@ -101,6 +105,23 @@ static __init int barrier_nospec_debugfs_init(void)
device_initcall(barrier_nospec_debugfs_init);
#endif /* CONFIG_DEBUG_FS */
+#ifdef CONFIG_PPC_FSL_BOOK3E
+static int __init handle_nospectre_v2(char *p)
+{
+ no_spectrev2 = true;
+
+ return 0;
+}
+early_param("nospectre_v2", handle_nospectre_v2);
+void setup_spectre_v2(void)
+{
+ if (no_spectrev2)
+ do_btb_flush_fixups();
+ else
+ btb_flush_enabled = true;
+}
+#endif /* CONFIG_PPC_FSL_BOOK3E */
+
#ifdef CONFIG_PPC_BOOK3S_64
ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr,
char *buf)
{
--
2.5.5
[RFC PATCH] powerpc/powernv: move OPAL call wrapper tracing and interrupt handling to C
The OPAL call wrapper gets interrupt disabling wrong. It disables interrupts just by clearing MSR[EE], which has two problems: - It doesn't call into the IRQ tracing subsystem, which means tracing across OPAL calls does not always notice IRQs have been disabled. - It doesn't go through the IRQ soft-mask code, which causes a minor bug. MSR[EE] can not be restored by saving the MSR then clearing MSR[EE], because a racing interrupt while soft-masked because a masked interrupt could race and clear MSR[EE] between the two steps. This can cause MSR[EE] to be incorrectly enabled when the OPAL call returns. Fortunately that should just take an interrupt and re-run the masked handler to fix things, but it's sloppy. The wapper also saves MSR to PACA, which is not re-entrant if the nested MSRs does not match, which could be a problem if a SRESET interrupts a real-mode call, for example. To fix this, move the tracing and IRQ handling code to C, and call into asm when everything is ready to go. Save MSR on stack. Performance cost is kept to a minimum with a few optimisations, - The endian switch upon return is combined with the MSR restore, which avoids an expensive context synchronizing operation for LE kernels. This makes up for the additional mtmsrd to enable interrupts with local_irq_enable(). - The bl/blr branches are balanced to avoid link stack corruption and reduce mispredicts. This requires a skiboot link stack fix as well. Even so, a NULL call goes from 410ns to 430ns (POWER9) after this. I would have expected it to come out much closer or even a little ahead, can't see why it's ~70 cycles slower. Might have to do some trace analysis. --- arch/powerpc/include/asm/asm-prototypes.h | 10 +- arch/powerpc/platforms/powernv/Makefile | 5 +- arch/powerpc/platforms/powernv/opal-call.c| 277 ++ .../platforms/powernv/opal-tracepoints.c | 88 - .../powerpc/platforms/powernv/opal-wrappers.S | 344 ++ 5 files changed, 322 insertions(+), 402 deletions(-) create mode 100644 arch/powerpc/platforms/powernv/opal-call.c delete mode 100644 arch/powerpc/platforms/powernv/opal-tracepoints.c diff --git a/arch/powerpc/include/asm/asm-prototypes.h b/arch/powerpc/include/asm/asm-prototypes.h index ec691d489656..4c0599e5bfaf 100644 --- a/arch/powerpc/include/asm/asm-prototypes.h +++ b/arch/powerpc/include/asm/asm-prototypes.h @@ -37,13 +37,11 @@ void kexec_copy_flush(struct kimage *image); extern struct static_key hcall_tracepoint_key; void __trace_hcall_entry(unsigned long opcode, unsigned long *args); void __trace_hcall_exit(long opcode, long retval, unsigned long *retbuf); -/* OPAL tracing */ -#ifdef HAVE_JUMP_LABEL -extern struct static_key opal_tracepoint_key; -#endif -void __trace_opal_entry(unsigned long opcode, unsigned long *args); -void __trace_opal_exit(long opcode, unsigned long retval); +/* OPAL */ +int64_t __opal_call(int64_t a0, int64_t a1, int64_t a2, int64_t a3, + int64_t a4, int64_t a5, int64_t a6, int64_t a7, + int64_t opcode, uint64_t msr); /* VMX copying */ int enter_vmx_usercopy(void); diff --git a/arch/powerpc/platforms/powernv/Makefile b/arch/powerpc/platforms/powernv/Makefile index b540ce8eec55..da2e99efbd04 100644 --- a/arch/powerpc/platforms/powernv/Makefile +++ b/arch/powerpc/platforms/powernv/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 -obj-y += setup.o opal-wrappers.o opal.o opal-async.o idle.o -obj-y += opal-rtc.o opal-nvram.o opal-lpc.o opal-flash.o +obj-y += setup.o opal-call.o opal-wrappers.o opal.o opal-async.o +obj-y += idle.o opal-rtc.o opal-nvram.o opal-lpc.o opal-flash.o obj-y += rng.o opal-elog.o opal-dump.o opal-sysparam.o opal-sensor.o obj-y += opal-msglog.o opal-hmi.o opal-power.o opal-irqchip.o obj-y += opal-kmsg.o opal-powercap.o opal-psr.o opal-sensor-groups.o @@ -11,7 +11,6 @@ obj-$(CONFIG_CXL_BASE)+= pci-cxl.o obj-$(CONFIG_EEH) += eeh-powernv.o obj-$(CONFIG_PPC_SCOM) += opal-xscom.o obj-$(CONFIG_MEMORY_FAILURE) += opal-memory-errors.o -obj-$(CONFIG_TRACEPOINTS) += opal-tracepoints.o obj-$(CONFIG_OPAL_PRD) += opal-prd.o obj-$(CONFIG_PERF_EVENTS) += opal-imc.o obj-$(CONFIG_PPC_MEMTRACE) += memtrace.o diff --git a/arch/powerpc/platforms/powernv/opal-call.c b/arch/powerpc/platforms/powernv/opal-call.c new file mode 100644 index ..172fea114a92 --- /dev/null +++ b/arch/powerpc/platforms/powernv/opal-call.c @@ -0,0 +1,277 @@ +// SPDX-License-Identifier: GPL-2.0 +#include +#include +#include +#include +#include + +#ifdef CONFIG_TRACEPOINTS +/* + * Since the tracing code might execute OPAL calls we need to guard against + * recursion. + */ +static DEFINE_PER_CPU(unsigned int, opal_trace_depth); + +static void __trace_opal_entry(s64 a0, s64 a1, s64 a2, s64 a3, +
[PATCH] soc: fsl: qbman: avoid race in clearing QMan interrupt
By clearing all interrupt sources, not only those that
already occurred, the existing code may acknowledge by
mistake interrupts that occurred after the code checks
for them.
Signed-off-by: Madalin Bucur
Signed-off-by: Roy Pledge
---
drivers/soc/fsl/qbman/qman.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/soc/fsl/qbman/qman.c b/drivers/soc/fsl/qbman/qman.c
index 52c153cd795a..636f83f781f5 100644
--- a/drivers/soc/fsl/qbman/qman.c
+++ b/drivers/soc/fsl/qbman/qman.c
@@ -1143,18 +1143,19 @@ static void qm_mr_process_task(struct work_struct
*work);
static irqreturn_t portal_isr(int irq, void *ptr)
{
struct qman_portal *p = ptr;
-
- u32 clear = QM_DQAVAIL_MASK | p->irq_sources;
u32 is = qm_in(>p, QM_REG_ISR) & p->irq_sources;
+ u32 clear = 0;
if (unlikely(!is))
return IRQ_NONE;
/* DQRR-handling if it's interrupt-driven */
- if (is & QM_PIRQ_DQRI)
+ if (is & QM_PIRQ_DQRI) {
__poll_portal_fast(p, QMAN_POLL_LIMIT);
+ clear = QM_DQAVAIL_MASK | QM_PIRQ_DQRI;
+ }
/* Handling of anything else that's interrupt-driven */
- clear |= __poll_portal_slow(p, is);
+ clear |= __poll_portal_slow(p, is) & QM_PIRQ_SLOW;
qm_out(>p, QM_REG_ISR, clear);
return IRQ_HANDLED;
}
--
2.1.0
Re: [PATCH 1/2] PCI/IOV: provide flag to skip VF scanning
Hello Bjorn, On Thu, 20 Dec 2018, Bjorn Helgaas wrote: > I think the strategy is fine, but can you restructure the patches > like this: > > 1) Factor out sriov_add_vfs() and sriov_dev_vfs(). This makes no > functional change at all. > > 2) Add dev->no_vf_scan, set it in the s390 pcibios_add_device(), and > test it in sriov_add_vfs(), and sriov_del_vfs(). > > I think both pieces will be easier to review that way. Done. I took the liberty to add Christoph's R-b to the first two patches since it's just a split of the patch he gave the R-b to. Thanks! Sebastian
[PATCH 3/3] s390/pci: skip VF scanning
Set the flag to skip scanning for VFs after SRIOV enablement. VF creation will be triggered by the hotplug code. Signed-off-by: Sebastian Ott Reviewed-by: Christoph Hellwig --- arch/s390/pci/pci.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/s390/pci/pci.c b/arch/s390/pci/pci.c index 9f6f392a4461..4266a4de3160 100644 --- a/arch/s390/pci/pci.c +++ b/arch/s390/pci/pci.c @@ -651,6 +651,9 @@ int pcibios_add_device(struct pci_dev *pdev) struct resource *res; int i; + if (pdev->is_physfn) + pdev->no_vf_scan = 1; + pdev->dev.groups = zpci_attr_groups; pdev->dev.dma_ops = _pci_dma_ops; zpci_map_resources(pdev); -- 2.13.4
[PATCH 2/3] PCI/IOV: provide flag to skip VF scanning
Provide a flag to skip scanning for new VFs after SRIOV enablement.
This can be set by implementations for which the VFs are already
reported by other means.
Signed-off-by: Sebastian Ott
Reviewed-by: Christoph Hellwig
---
drivers/pci/iov.c | 6 ++
include/linux/pci.h | 1 +
2 files changed, 7 insertions(+)
diff --git a/drivers/pci/iov.c b/drivers/pci/iov.c
index 408db232a328..3aa115ed3a65 100644
--- a/drivers/pci/iov.c
+++ b/drivers/pci/iov.c
@@ -257,6 +257,9 @@ static int sriov_add_vfs(struct pci_dev *dev, u16 num_vfs)
unsigned int i;
int rc;
+ if (dev->no_vf_scan)
+ return 0;
+
for (i = 0; i < num_vfs; i++) {
rc = pci_iov_add_virtfn(dev, i);
if (rc)
@@ -385,6 +388,9 @@ static void sriov_del_vfs(struct pci_dev *dev)
struct pci_sriov *iov = dev->sriov;
int i;
+ if (dev->no_vf_scan)
+ return;
+
for (i = 0; i < iov->num_VFs; i++)
pci_iov_remove_virtfn(dev, i);
}
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 11c71c4ecf75..f9bc7651c406 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -405,6 +405,7 @@ struct pci_dev {
unsigned intnon_compliant_bars:1; /* Broken BARs; ignore them */
unsigned intis_probed:1;/* Device probing in progress */
unsigned intlink_active_reporting:1;/* Device capable of reporting
link active */
+ unsigned intno_vf_scan:1; /* Don't scan for VFs after IOV
enablement */
pci_dev_flags_t dev_flags;
atomic_tenable_cnt; /* pci_enable_device has been called */
--
2.13.4
[PATCH 1/3] PCI/IOV: factor out sriov_add_vfs
Provide sriov_add_vfs as a wrapper to scan for VFs that cleans up
after itself. This is just a code simplification. No functional change.
Signed-off-by: Sebastian Ott
Reviewed-by: Christoph Hellwig
---
drivers/pci/iov.c | 44 +++-
1 file changed, 31 insertions(+), 13 deletions(-)
diff --git a/drivers/pci/iov.c b/drivers/pci/iov.c
index 9616eca3182f..408db232a328 100644
--- a/drivers/pci/iov.c
+++ b/drivers/pci/iov.c
@@ -252,6 +252,24 @@ int __weak pcibios_sriov_disable(struct pci_dev *pdev)
return 0;
}
+static int sriov_add_vfs(struct pci_dev *dev, u16 num_vfs)
+{
+ unsigned int i;
+ int rc;
+
+ for (i = 0; i < num_vfs; i++) {
+ rc = pci_iov_add_virtfn(dev, i);
+ if (rc)
+ goto failed;
+ }
+ return 0;
+failed:
+ while (i--)
+ pci_iov_remove_virtfn(dev, i);
+
+ return rc;
+}
+
static int sriov_enable(struct pci_dev *dev, int nr_virtfn)
{
int rc;
@@ -337,21 +355,15 @@ static int sriov_enable(struct pci_dev *dev, int
nr_virtfn)
msleep(100);
pci_cfg_access_unlock(dev);
- for (i = 0; i < initial; i++) {
- rc = pci_iov_add_virtfn(dev, i);
- if (rc)
- goto failed;
- }
+ rc = sriov_add_vfs(dev, initial);
+ if (rc)
+ goto err_pcibios;
kobject_uevent(>dev.kobj, KOBJ_CHANGE);
iov->num_VFs = nr_virtfn;
return 0;
-failed:
- while (i--)
- pci_iov_remove_virtfn(dev, i);
-
err_pcibios:
iov->ctrl &= ~(PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE);
pci_cfg_access_lock(dev);
@@ -368,17 +380,23 @@ static int sriov_enable(struct pci_dev *dev, int
nr_virtfn)
return rc;
}
-static void sriov_disable(struct pci_dev *dev)
+static void sriov_del_vfs(struct pci_dev *dev)
{
+ struct pci_sriov *iov = dev->sriov;
int i;
+
+ for (i = 0; i < iov->num_VFs; i++)
+ pci_iov_remove_virtfn(dev, i);
+}
+
+static void sriov_disable(struct pci_dev *dev)
+{
struct pci_sriov *iov = dev->sriov;
if (!iov->num_VFs)
return;
- for (i = 0; i < iov->num_VFs; i++)
- pci_iov_remove_virtfn(dev, i);
-
+ sriov_del_vfs(dev);
iov->ctrl &= ~(PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE);
pci_cfg_access_lock(dev);
pci_write_config_word(dev, iov->pos + PCI_SRIOV_CTRL, iov->ctrl);
--
2.13.4
Re: [PATCH 01/33] powerpc: use mm zones more sensibly
On Tue, 2018-10-09 at 15:24 +0200, Christoph Hellwig wrote: > * Find the least restrictive zone that is entirely below the > @@ -324,11 +305,14 @@ void __init paging_init(void) > printk(KERN_DEBUG "Memory hole size: %ldMB\n", >(long int)((top_of_ram - total_ram) >> 20)); > > +#ifdef CONFIG_ZONE_DMA > + max_zone_pfns[ZONE_DMA] = min(max_low_pfn, 0x7fffUL >> > PAGE_SHIFT); > +#endif > + max_zone_pfns[ZONE_NORMAL] = max_low_pfn; > #ifdef CONFIG_HIGHMEM > - limit_zone_pfn(ZONE_NORMAL, lowmem_end_addr >> PAGE_SHIFT); > + max_zone_pfns[ZONE_HIGHMEM] = max_pfn ^ Missing a ";" here --| Sorry ... works with that fix on an old laptop with highmem. > #endif > - limit_zone_pfn(TOP_ZONE, top_of_ram >> PAGE_SHIFT); > - zone_limits_final = true; > + > free_area_init_nodes(max_zone_pfns); >
Re: [Resend PATCH V5 2/10] x86/hyper-v: Add HvFlushGuestAddressList hypercall support
On 06/12/18 14:21, lantianyu1...@gmail.com wrote:
> static inline int hyperv_flush_guest_mapping(u64 as) { return -1; }
> +static inline int hyperv_flush_guest_mapping_range(u64 as,
> + hyperv_fill_flush_list_func fill_func, void *data);
> +{
> + return -1;
This part for !IS_ENABLED(CONFIG_HYPERV) does not compile.
No big deal, but please add that to your testing procedures.
Paolo
Re: [Resend PATCH V5 0/10] x86/KVM/Hyper-v: Add HV ept tlb range flush hypercall support in KVM
On 06/12/18 14:21, lantianyu1...@gmail.com wrote: > From: Lan Tianyu > > For nested memory virtualization, Hyper-v doesn't set write-protect > L1 hypervisor EPT page directory and page table node to track changes > while it relies on guest to tell it changes via HvFlushGuestAddressLlist > hypercall. HvFlushGuestAddressLlist hypercall provides a way to flush > EPT page table with ranges which are specified by L1 hypervisor. > > If L1 hypervisor uses INVEPT or HvFlushGuestAddressSpace hypercall to > flush EPT tlb, Hyper-V will invalidate associated EPT shadow page table > and sync L1's EPT table when next EPT page fault is triggered. > HvFlushGuestAddressLlist hypercall helps to avoid such redundant EPT > page fault and synchronization of shadow page table. > > This patchset is based on the Patch "KVM/VMX: Check ept_pointer before > flushing ept tlb"(https://marc.info/?l=kvm=154408169705686=2). > > Change since v4: >1) Split flush address and flush list patches. This patchset only > contains >flush address patches. Will post flush list patches later. >2) Expose function hyperv_fill_flush_guest_mapping_list() >out of hyperv file >3) Adjust parameter of hyperv_flush_guest_mapping_range() >4) Reorder patchset and move Hyper-V and VMX changes ahead. > > Change since v3: > 1) Remove code of updating "tlbs_dirty" in > kvm_flush_remote_tlbs_with_range() > 2) Remove directly tlb flush in the kvm_handle_hva_range() > 3) Move tlb flush in kvm_set_pte_rmapp() to > kvm_mmu_notifier_change_pte() > 4) Combine Vitaly's "don't pass EPT configuration info to > vmx_hv_remote_flush_tlb()" fix > > Change since v2: >1) Fix comment in the kvm_flush_remote_tlbs_with_range() >2) Move HV_MAX_FLUSH_PAGES and HV_MAX_FLUSH_REP_COUNT to > hyperv-tlfs.h. >3) Calculate HV_MAX_FLUSH_REP_COUNT in the macro definition >4) Use HV_MAX_FLUSH_REP_COUNT to define length of gpa_list in > struct hv_guest_mapping_flush_list. > > Change since v1: >1) Convert "end_gfn" of struct kvm_tlb_range to "pages" in order > to avoid confusion as to whether "end_gfn" is inclusive or exlusive. >2) Add hyperv tlb range struct and replace kvm tlb range struct > with new struct in order to avoid using kvm struct in the hyperv > code directly. > > > > Lan Tianyu (10): > KVM: Add tlb_remote_flush_with_range callback in kvm_x86_ops > x86/hyper-v: Add HvFlushGuestAddressList hypercall support > x86/Hyper-v: Add trace in the > hyperv_nested_flush_guest_mapping_range() > KVM/VMX: Add hv tlb range flush support > KVM/MMU: Add tlb flush with range helper function > KVM: Replace old tlb flush function with new one to flush a specified > range. > KVM: Make kvm_set_spte_hva() return int > KVM/MMU: Move tlb flush in kvm_set_pte_rmapp() to > kvm_mmu_notifier_change_pte() > KVM/MMU: Flush tlb directly in the kvm_set_pte_rmapp() > KVM/MMU: Flush tlb directly in the kvm_zap_gfn_range() > > arch/arm/include/asm/kvm_host.h | 2 +- > arch/arm64/include/asm/kvm_host.h | 2 +- > arch/mips/include/asm/kvm_host.h| 2 +- > arch/mips/kvm/mmu.c | 3 +- > arch/powerpc/include/asm/kvm_host.h | 2 +- > arch/powerpc/kvm/book3s.c | 3 +- > arch/powerpc/kvm/e500_mmu_host.c| 3 +- > arch/x86/hyperv/nested.c| 80 +++ > arch/x86/include/asm/hyperv-tlfs.h | 32 + > arch/x86/include/asm/kvm_host.h | 9 +++- > arch/x86/include/asm/mshyperv.h | 15 ++ > arch/x86/include/asm/trace/hyperv.h | 14 ++ > arch/x86/kvm/mmu.c | 96 > + > arch/x86/kvm/paging_tmpl.h | 3 +- > arch/x86/kvm/vmx.c | 63 +--- > virt/kvm/arm/mmu.c | 6 ++- > virt/kvm/kvm_main.c | 5 +- > 17 files changed, 292 insertions(+), 48 deletions(-) > Queued, thanks. Paolo
[PATCH v3] crypto: talitos - fix ablkcipher for CONFIG_VMAP_STACK
[2.364486] WARNING: CPU: 0 PID: 60 at ./arch/powerpc/include/asm/io.h:837
dma_nommu_map_page+0x44/0xd4
[2.373579] CPU: 0 PID: 60 Comm: cryptomgr_test Tainted: GW
4.20.0-rc5-00560-g6bfb52e23a00-dirty #531
[2.384740] NIP: c000c540 LR: c000c584 CTR:
[2.389743] REGS: c95abab0 TRAP: 0700 Tainted: GW
(4.20.0-rc5-00560-g6bfb52e23a00-dirty)
[2.400042] MSR: 00029032 CR: 24042204 XER:
[2.406669]
[2.406669] GPR00: c02f2244 c95abb60 c6262990 c95abd80 256a 0001
0001 0001
[2.406669] GPR08: 2000 0010 0010 24042202
0100 c95abd88
[2.406669] GPR16: c05569d4 0001 0010 c95abc88 c0615664
0004
[2.406669] GPR24: 0010 c95abc88 c95abc88 c61ae210 c7ff6d40
c61ae210 3d68
[2.441559] NIP [c000c540] dma_nommu_map_page+0x44/0xd4
[2.446720] LR [c000c584] dma_nommu_map_page+0x88/0xd4
[2.451762] Call Trace:
[2.454195] [c95abb60] [82000808] 0x82000808 (unreliable)
[2.459572] [c95abb80] [c02f2244] talitos_edesc_alloc+0xbc/0x3c8
[2.465493] [c95abbb0] [c02f2600] ablkcipher_edesc_alloc+0x4c/0x5c
[2.471606] [c95abbd0] [c02f4ed0] ablkcipher_encrypt+0x20/0x64
[2.477389] [c95abbe0] [c02023b0] __test_skcipher+0x4bc/0xa08
[2.483049] [c95abe00] [c0204b60] test_skcipher+0x2c/0xcc
[2.488385] [c95abe20] [c0204c48] alg_test_skcipher+0x48/0xbc
[2.494064] [c95abe40] [c0205cec] alg_test+0x164/0x2e8
[2.499142] [c95abf00] [c0200dec] cryptomgr_test+0x48/0x50
[2.504558] [c95abf10] [c0039ff4] kthread+0xe4/0x110
[2.509471] [c95abf40] [c000e1d0] ret_from_kernel_thread+0x14/0x1c
[2.515532] Instruction dump:
[2.518468] 7c7e1b78 7c9d2378 7cbf2b78 41820054 3d20c076 8089c200 3d20c076
7c84e850
[2.526127] 8129c204 7c842e70 7f844840 419c0008 <0fe0> 2f9e 54847022
7c84fa14
[2.533960] ---[ end trace bf78d94af73fe3b8 ]---
[2.539123] talitos ff02.crypto: master data transfer error
[2.544775] talitos ff02.crypto: TEA error: ISR 0x2000_0040
[2.551625] alg: skcipher: encryption failed on test 1 for ecb-aes-talitos:
ret=22
IV cannot be on stack when CONFIG_VMAP_STACK is selected because the stack
cannot be DMA mapped anymore.
This patch copies the IV into the extended descriptor when iv is not
a valid linear address.
Fixes: 4de9d0b547b9 ("crypto: talitos - Add ablkcipher algorithms")
Cc: sta...@vger.kernel.org
Signed-off-by: Christophe Leroy
---
v3: Using struct edesc buffer.
v2: Using per-request context.
drivers/crypto/talitos.c | 35 +++
1 file changed, 15 insertions(+), 20 deletions(-)
diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos.c
index 6988012deca4..160702b119bb 100644
--- a/drivers/crypto/talitos.c
+++ b/drivers/crypto/talitos.c
@@ -1355,29 +1355,23 @@ static struct talitos_edesc *talitos_edesc_alloc(struct
device *dev,
{
struct talitos_edesc *edesc;
int src_nents, dst_nents, alloc_len, dma_len, src_len, dst_len;
- dma_addr_t iv_dma = 0;
gfp_t flags = cryptoflags & CRYPTO_TFM_REQ_MAY_SLEEP ? GFP_KERNEL :
GFP_ATOMIC;
struct talitos_private *priv = dev_get_drvdata(dev);
bool is_sec1 = has_ftr_sec1(priv);
int max_len = is_sec1 ? TALITOS1_MAX_DATA_LEN : TALITOS2_MAX_DATA_LEN;
- void *err;
if (cryptlen + authsize > max_len) {
dev_err(dev, "length exceeds h/w max limit\n");
return ERR_PTR(-EINVAL);
}
- if (ivsize)
- iv_dma = dma_map_single(dev, iv, ivsize, DMA_TO_DEVICE);
-
if (!dst || dst == src) {
src_len = assoclen + cryptlen + authsize;
src_nents = sg_nents_for_len(src, src_len);
if (src_nents < 0) {
dev_err(dev, "Invalid number of src SG.\n");
- err = ERR_PTR(-EINVAL);
- goto error_sg;
+ return ERR_PTR(-EINVAL);
}
src_nents = (src_nents == 1) ? 0 : src_nents;
dst_nents = dst ? src_nents : 0;
@@ -1387,16 +1381,14 @@ static struct talitos_edesc *talitos_edesc_alloc(struct
device *dev,
src_nents = sg_nents_for_len(src, src_len);
if (src_nents < 0) {
dev_err(dev, "Invalid number of src SG.\n");
- err = ERR_PTR(-EINVAL);
- goto error_sg;
+ return ERR_PTR(-EINVAL);
}
src_nents = (src_nents == 1) ? 0 : src_nents;
dst_len = assoclen + cryptlen + (encrypt ? authsize : 0);
dst_nents = sg_nents_for_len(dst, dst_len);
if (dst_nents < 0) {
dev_err(dev, "Invalid number of dst SG.\n");
- err = ERR_PTR(-EINVAL);
-
