Re: [PATCH 03/18] powerpc: bad_page_fault, do_break get registers from regs

2020-11-10 Thread Nicholas Piggin 
Excerpts from Nicholas Piggin's message of November 11, 2020 2:46 pm:
> Excerpts from Christophe Leroy's message of November 10, 2020 9:19 pm:
>> 
>> 
>> Le 10/11/2020 à 09:34, Nicholas Piggin a écrit :
>>> Excerpts from Christophe Leroy's message of November 6, 2020 6:14 pm:


 Le 05/11/2020 à 15:34, Nicholas Piggin a écrit :
> This also moves the 32s DABR match to C.

 Is there a real benefit doing this ?
>>> 
>>> Oh I missed doing it, but yes I think bad_page_fault and do_break should
>>> probably be implemented with the DEFINE_INTERRUT_HANDLER wrappers.
>>> 
>> 
>> Yes, anyway, do we need to do that change ? Can't the dispatch between 
>> do_break() and page fault 
>> handling remain in handle_page_fault() ? What's the benefit of going into 
>> do_page_fault() and coming 
>> back ?
> 
> You might be right, I'll take another look at it.

For 32-bit, we need to come back to save NV GPRs. Certainly the 64s code 
stays in do_page_fault because it always saves them.

Now I don't think that's the nicest thing to go in and out of the 
interrupt wrappers twice in these cases, but for a first pass I think 
it's okay. Either we could add another type of error-case wrapper that
does some adjustment if it becomes necessary, or we find a nice way to
save NVGPRs from C code.

If we could somehow parse unwind data to find where the NVGPRs are saved 
by the compiler and generate a little code stub to load them out, would
be the ultimate :) Maybe one day...

Thanks,
Nick

[PATCH] powerpc/powernv/memtrace: Fake non-memblock aligned sized traces

2020-11-10 Thread Jordan Niethe 
The hardware trace macros which use the memory provided by memtrace are
able to use trace sizes as small as 16MB. Only memblock aligned values
can be removed from each NUMA node by writing that value to
memtrace/enable in debugfs.  This means setting up, say, a 16MB trace is
not possible.  To allow such a trace size, instead align whatever value
is written to memtrace/enable to the memblock size for the purpose of
removing it from each NUMA node but report the written value from
memtrace/enable and memtrace/x/size in debugfs.

Signed-off-by: Jordan Niethe 
---
 arch/powerpc/platforms/powernv/memtrace.c | 20 ++--
 1 file changed, 6 insertions(+), 14 deletions(-)

diff --git a/arch/powerpc/platforms/powernv/memtrace.c 
b/arch/powerpc/platforms/powernv/memtrace.c
index 6828108486f8..1188bc8fd090 100644
--- a/arch/powerpc/platforms/powernv/memtrace.c
+++ b/arch/powerpc/platforms/powernv/memtrace.c
@@ -191,7 +191,7 @@ static int memtrace_init_debugfs(void)
ent->dir = dir;
debugfs_create_file("trace", 0400, dir, ent, _fops);
debugfs_create_x64("start", 0400, dir, >start);
-   debugfs_create_x64("size", 0400, dir, >size);
+   debugfs_create_x64("size", 0400, dir, _size);
}
 
return ret;
@@ -259,33 +259,25 @@ static int memtrace_enable_set(void *data, u64 val)
 {
u64 bytes;
 
-   /*
-* Don't attempt to do anything if size isn't aligned to a memory
-* block or equal to zero.
-*/
-   bytes = memory_block_size_bytes();
-   if (val & (bytes - 1)) {
-   pr_err("Value must be aligned with 0x%llx\n", bytes);
-   return -EINVAL;
-   }
-
/* Re-add/online previously removed/offlined memory */
if (memtrace_size) {
if (memtrace_online())
return -EAGAIN;
}
 
+   memtrace_size = val;
+
if (!val)
return 0;
 
-   /* Offline and remove memory */
-   if (memtrace_init_regions_runtime(val))
+   /* Offline and remove memory aligned to memory blocks */
+   bytes = memory_block_size_bytes();
+   if (memtrace_init_regions_runtime(ALIGN(val, bytes)))
return -EINVAL;
 
if (memtrace_init_debugfs())
return -EINVAL;
 
-   memtrace_size = val;
 
return 0;
 }
-- 
2.17.1

[PATCH 2/4] powerpc/perf: Update the PMU group constraints for l2l3 and threshold events in power10

2020-11-10 Thread Athira Rajeev 
In Power9, L2/L3 bus events are always available as a
"bank" of 4 events. To obtain the counts for any of the
l2/l3 bus events in a given bank, the user will have to
program PMC4 with corresponding l2/l3 bus event for that
bank.

Commit 59029136d750 ("powerpc/perf: Add constraints for power9 l2/l3 bus 
events")
enforced this rule in Power9. But this is not valid for
Power10, since in Power10 Monitor Mode Control Register2
(MMCR2) has bits to configure l2/l3 event bits. Hence remove
this PMC4 constraint check from power10.

Since the l2/l3 bits in MMCR2 are not per-pmc, patch handles
group constrints checks for l2/l3 bits in MMCR2.
Patch also updates constraints for threshold events in power10.

Fixes: a64e697cef23 ("powerpc/perf: power10 Performance Monitoring support")
Signed-off-by: Athira Rajeev 
---
 arch/powerpc/perf/isa207-common.c | 15 +++
 arch/powerpc/perf/isa207-common.h |  3 +++
 2 files changed, 14 insertions(+), 4 deletions(-)

diff --git a/arch/powerpc/perf/isa207-common.c 
b/arch/powerpc/perf/isa207-common.c
index f57f54f..0f4983e 100644
--- a/arch/powerpc/perf/isa207-common.c
+++ b/arch/powerpc/perf/isa207-common.c
@@ -311,9 +311,11 @@ int isa207_get_constraint(u64 event, unsigned long *maskp, 
unsigned long *valp)
}
 
if (unit >= 6 && unit <= 9) {
-   if (cpu_has_feature(CPU_FTR_ARCH_31) && (unit == 6)) {
-   mask |= CNST_L2L3_GROUP_MASK;
-   value |= CNST_L2L3_GROUP_VAL(event >> 
p10_L2L3_EVENT_SHIFT);
+   if (cpu_has_feature(CPU_FTR_ARCH_31)) {
+   if (unit == 6) {
+   mask |= CNST_L2L3_GROUP_MASK;
+   value |= CNST_L2L3_GROUP_VAL(event >> 
p10_L2L3_EVENT_SHIFT);
+   }
} else if (cpu_has_feature(CPU_FTR_ARCH_300)) {
mask  |= CNST_CACHE_GROUP_MASK;
value |= CNST_CACHE_GROUP_VAL(event & 0xff);
@@ -349,7 +351,12 @@ int isa207_get_constraint(u64 event, unsigned long *maskp, 
unsigned long *valp)
value |= CNST_SAMPLE_VAL(event >> EVENT_SAMPLE_SHIFT);
}
 
-   if (cpu_has_feature(CPU_FTR_ARCH_300))  {
+   if (cpu_has_feature(CPU_FTR_ARCH_31)) {
+   if (event_is_threshold(event)) {
+   mask  |= CNST_THRESH_CTL_SEL_MASK;
+   value |= CNST_THRESH_CTL_SEL_VAL(event >> 
EVENT_THRESH_SHIFT);
+   }
+   } else if (cpu_has_feature(CPU_FTR_ARCH_300))  {
if (event_is_threshold(event) && is_thresh_cmp_valid(event)) {
mask  |= CNST_THRESH_MASK;
value |= CNST_THRESH_VAL(event >> EVENT_THRESH_SHIFT);
diff --git a/arch/powerpc/perf/isa207-common.h 
b/arch/powerpc/perf/isa207-common.h
index dc9c3d2..4208764 100644
--- a/arch/powerpc/perf/isa207-common.h
+++ b/arch/powerpc/perf/isa207-common.h
@@ -149,6 +149,9 @@
 #define CNST_THRESH_VAL(v) (((v) & EVENT_THRESH_MASK) << 32)
 #define CNST_THRESH_MASK   CNST_THRESH_VAL(EVENT_THRESH_MASK)
 
+#define CNST_THRESH_CTL_SEL_VAL(v) (((v) & 0x7ffull) << 32)
+#define CNST_THRESH_CTL_SEL_MASK   CNST_THRESH_CTL_SEL_VAL(0x7ff)
+
 #define CNST_EBB_VAL(v)(((v) & EVENT_EBB_MASK) << 24)
 #define CNST_EBB_MASK  CNST_EBB_VAL(EVENT_EBB_MASK)
 
-- 
1.8.3.1

Re: [PATCH 00/25] Rid W=1 warnings in SoC

2020-11-10 Thread Bjorn Andersson 
On Tue 03 Nov 09:28 CST 2020, Lee Jones wrote:

> This set is part of a larger effort attempting to clean-up W=1
> kernel builds, which are currently overwhelmingly riddled with
> niggly little warnings.
> 

For patches 2, 3, 12, 15, 16, 17, 18, 19, 20, 21, 22 (i.e. the soc/qcom
patches):

Reviewed-by: Bjorn Andersson 
and applied towards 5.11

Regards,
Bjorn

> Lee Jones (25):
>   soc: bcm: brcmstb: pm: pm-arm: Provide prototype for
> brcmstb_pm_s3_finish()
>   soc: qcom: qcom_aoss: Remove set but unused variable 'tlen'
>   soc: qcom: qcom_aoss: Add missing description for 'cooling_devs'
>   soc: fsl: dpio: qbman-portal: Fix a bunch of kernel-doc misdemeanours
>   soc: rockchip: io-domain: Remove incorrect and incomplete comment
> header
>   soc: ti: knav_qmss_queue: Remove set but unchecked variable 'ret'
>   soc: ti: knav_qmss_queue: Fix a whole host of function documentation
> issues
>   soc: ti: knav_dma: Fix a kernel function doc formatting issue
>   soc: ti: pm33xx: Remove set but unused variable 'ret'
>   soc: ti: wkup_m3_ipc: Document 'm3_ipc' parameter throughout
>   soc: fsl: qe: qe_common: Fix misnamed function attribute 'addr'
>   soc: qcom: qcom-geni-se: Fix misnamed function parameter 'rx_rfr'
>   soc: tegra: fuse: speedo-tegra124: Remove some set but unused
> variables
>   soc: samsung: s3c-pm-check: Fix incorrectly named variable 'val'
>   soc: qcom: rpmh: Fix possible doc-rot in rpmh_write()'s header
>   soc: qcom: smem: Fix formatting and missing documentation issues
>   soc: qcom: smsm: Fix some kernel-doc formatting and naming problems
>   soc: qcom: wcnss_ctrl: Demote non-conformant struct header and fix
> function headers
>   soc: qcom: smp2p: Remove unused struct attribute provide another
>   soc: qcom: llcc-qcom: Fix expected kernel-doc formatting
>   soc: qcom: rpmhpd: Provide some missing struct member descriptions
>   soc: qcom: kryo-l2-accessors: Fix misnaming of 'val'
>   soc: ti: k3-ringacc: Provide documentation for 'k3_ring's 'state'
>   soc: tegra: fuse: speedo-tegra210: Remove a group of set but unused
> variables
>   soc: fsl: qbman: qman: Remove unused variable 'dequeue_wq'
> 
>  drivers/soc/bcm/brcmstb/pm/pm-arm.c  |  2 +
>  drivers/soc/fsl/dpio/qbman-portal.c  | 18 +--
>  drivers/soc/fsl/qbman/qman.c |  8 +--
>  drivers/soc/fsl/qe/qe_common.c   |  2 +-
>  drivers/soc/qcom/kryo-l2-accessors.c |  2 +-
>  drivers/soc/qcom/llcc-qcom.c |  2 +-
>  drivers/soc/qcom/qcom-geni-se.c  |  5 +-
>  drivers/soc/qcom/qcom_aoss.c |  4 +-
>  drivers/soc/qcom/rpmh.c  |  2 +-
>  drivers/soc/qcom/rpmhpd.c|  3 ++
>  drivers/soc/qcom/smem.c  |  3 +-
>  drivers/soc/qcom/smp2p.c |  3 +-
>  drivers/soc/qcom/smsm.c  |  4 +-
>  drivers/soc/qcom/wcnss_ctrl.c|  8 +--
>  drivers/soc/rockchip/io-domain.c |  3 --
>  drivers/soc/samsung/s3c-pm-check.c   |  2 +-
>  drivers/soc/tegra/fuse/speedo-tegra124.c |  7 ++-
>  drivers/soc/tegra/fuse/speedo-tegra210.c |  8 +--
>  drivers/soc/ti/k3-ringacc.c  |  1 +
>  drivers/soc/ti/knav_dma.c|  2 +-
>  drivers/soc/ti/knav_qmss_queue.c | 62 
>  drivers/soc/ti/pm33xx.c  |  4 +-
>  drivers/soc/ti/wkup_m3_ipc.c |  8 ++-
>  23 files changed, 86 insertions(+), 77 deletions(-)
> 
> Cc: act 
> Cc: Andy Gross 
> Cc: bcm-kernel-feedback-l...@broadcom.com
> Cc: Ben Dooks 
> Cc: Bjorn Andersson 
> Cc: Cyril Chemparathy 
> Cc: Dan Malek 
> Cc: Dave Gerlach 
> Cc: Doug Anderson 
> Cc: Florian Fainelli 
> Cc: Heiko Stuebner 
> Cc: Jonathan Hunter 
> Cc: Krzysztof Kozlowski 
> Cc: Liam Girdwood 
> Cc: linux-arm-...@vger.kernel.org
> Cc: linuxppc-dev@lists.ozlabs.org
> Cc: linux-rockc...@lists.infradead.org
> Cc: linux-samsung-...@vger.kernel.org
> Cc: linux-te...@vger.kernel.org
> Cc: Li Yang 
> Cc: Mark Brown 
> Cc: Qiang Zhao 
> Cc: "Rafael J. Wysocki" 
> Cc: Roy Pledge 
> Cc: Sandeep Nair 
> Cc: Santosh Shilimkar 
> Cc: Scott Wood 
> Cc: "Software, Inc" 
> Cc: Thierry Reding 
> Cc: Vitaly Bordug 
> Cc: YueHaibing 
> 
> -- 
> 2.25.1
>

[PATCH 3/4] powerpc/perf: Fix to update l2l3 events and generic event codes for power10

2020-11-10 Thread Athira Rajeev 
Fix the event code for events: branch-instructions (to PM_BR_FIN),
branch-misses (to PM_BR_MPRED_FIN) and cache-misses (to
PM_LD_DEMAND_MISS_L1_FIN) for power10 PMU. Update the
list of generic events with this modified event code.
Export l2l3 events (PM_L2_ST_MISS and PM_L2_ST) and LLC-prefetches
(PM_L3_PF_MISS_L3) via sysfs, and also add these to cache_events.

To maintain the current event code work with DD1, rename
existing array of generic_events, cache_events and pmu_attr_groups
with suffix _dd1. Update the power10 pmu init code to pick the
dd1 list while registering the power PMU, based on the pvr
(Processor Version Register) value.

Signed-off-by: Athira Rajeev 
---
 arch/powerpc/perf/power10-events-list.h |   9 ++
 arch/powerpc/perf/power10-pmu.c | 166 +++-
 2 files changed, 173 insertions(+), 2 deletions(-)

diff --git a/arch/powerpc/perf/power10-events-list.h 
b/arch/powerpc/perf/power10-events-list.h
index 60c1b81..9e0b3c9 100644
--- a/arch/powerpc/perf/power10-events-list.h
+++ b/arch/powerpc/perf/power10-events-list.h
@@ -15,6 +15,9 @@
 EVENT(PM_RUN_INST_CMPL,0x500fa);
 EVENT(PM_BR_CMPL,   0x4d05e);
 EVENT(PM_BR_MPRED_CMPL, 0x400f6);
+EVENT(PM_BR_FIN,   0x2f04a);
+EVENT(PM_BR_MPRED_FIN, 0x35884);
+EVENT(PM_LD_DEMAND_MISS_L1_FIN,0x400f0);
 
 /* All L1 D cache load references counted at finish, gated by reject */
 EVENT(PM_LD_REF_L1,0x100fc);
@@ -36,6 +39,12 @@
 EVENT(PM_DATA_FROM_L3, 0x0134001c040);
 /* Demand LD - L3 Miss (not L2 hit and not L3 hit) */
 EVENT(PM_DATA_FROM_L3MISS, 0x300fe);
+/* All successful D-side store dispatches for this thread */
+EVENT(PM_L2_ST,0x01046080);
+/* All successful D-side store dispatches for this thread that were L2 Miss */
+EVENT(PM_L2_ST_MISS,   0x26880);
+/* Total HW L3 prefetches(Load+store) */
+EVENT(PM_L3_PF_MISS_L3,0x10016080);
 /* Data PTEG reload */
 EVENT(PM_DTLB_MISS,0x300fc);
 /* ITLB Reloaded */
diff --git a/arch/powerpc/perf/power10-pmu.c b/arch/powerpc/perf/power10-pmu.c
index cf44fb7..86665ad 100644
--- a/arch/powerpc/perf/power10-pmu.c
+++ b/arch/powerpc/perf/power10-pmu.c
@@ -114,6 +114,9 @@ static int power10_get_alternatives(u64 event, unsigned int 
flags, u64 alt[])
 GENERIC_EVENT_ATTR(cache-misses,   PM_LD_MISS_L1);
 GENERIC_EVENT_ATTR(mem-loads,  MEM_LOADS);
 GENERIC_EVENT_ATTR(mem-stores, MEM_STORES);
+GENERIC_EVENT_ATTR(branch-instructions, PM_BR_FIN);
+GENERIC_EVENT_ATTR(branch-misses,   PM_BR_MPRED_FIN);
+GENERIC_EVENT_ATTR(cache-misses,   PM_LD_DEMAND_MISS_L1_FIN);
 
 CACHE_EVENT_ATTR(L1-dcache-load-misses,PM_LD_MISS_L1);
 CACHE_EVENT_ATTR(L1-dcache-loads,  PM_LD_REF_L1);
@@ -124,12 +127,15 @@ static int power10_get_alternatives(u64 event, unsigned 
int flags, u64 alt[])
 CACHE_EVENT_ATTR(L1-icache-prefetches, PM_IC_PREF_REQ);
 CACHE_EVENT_ATTR(LLC-load-misses,  PM_DATA_FROM_L3MISS);
 CACHE_EVENT_ATTR(LLC-loads,PM_DATA_FROM_L3);
+CACHE_EVENT_ATTR(LLC-prefetches,   PM_L3_PF_MISS_L3);
+CACHE_EVENT_ATTR(LLC-store-misses, PM_L2_ST_MISS);
+CACHE_EVENT_ATTR(LLC-stores,   PM_L2_ST);
 CACHE_EVENT_ATTR(branch-load-misses,   PM_BR_MPRED_CMPL);
 CACHE_EVENT_ATTR(branch-loads, PM_BR_CMPL);
 CACHE_EVENT_ATTR(dTLB-load-misses, PM_DTLB_MISS);
 CACHE_EVENT_ATTR(iTLB-load-misses, PM_ITLB_MISS);
 
-static struct attribute *power10_events_attr[] = {
+static struct attribute *power10_events_attr_dd1[] = {
GENERIC_EVENT_PTR(PM_RUN_CYC),
GENERIC_EVENT_PTR(PM_RUN_INST_CMPL),
GENERIC_EVENT_PTR(PM_BR_CMPL),
@@ -154,11 +160,44 @@ static int power10_get_alternatives(u64 event, unsigned 
int flags, u64 alt[])
NULL
 };
 
+static struct attribute *power10_events_attr[] = {
+   GENERIC_EVENT_PTR(PM_RUN_CYC),
+   GENERIC_EVENT_PTR(PM_RUN_INST_CMPL),
+   GENERIC_EVENT_PTR(PM_BR_FIN),
+   GENERIC_EVENT_PTR(PM_BR_MPRED_FIN),
+   GENERIC_EVENT_PTR(PM_LD_REF_L1),
+   GENERIC_EVENT_PTR(PM_LD_DEMAND_MISS_L1_FIN),
+   GENERIC_EVENT_PTR(MEM_LOADS),
+   GENERIC_EVENT_PTR(MEM_STORES),
+   CACHE_EVENT_PTR(PM_LD_MISS_L1),
+   CACHE_EVENT_PTR(PM_LD_REF_L1),
+   CACHE_EVENT_PTR(PM_LD_PREFETCH_CACHE_LINE_MISS),
+   CACHE_EVENT_PTR(PM_ST_MISS_L1),
+   CACHE_EVENT_PTR(PM_L1_ICACHE_MISS),
+   CACHE_EVENT_PTR(PM_INST_FROM_L1),
+   CACHE_EVENT_PTR(PM_IC_PREF_REQ),
+   CACHE_EVENT_PTR(PM_DATA_FROM_L3MISS),
+   CACHE_EVENT_PTR(PM_DATA_FROM_L3),
+

[PATCH 1/4] powerpc/perf: Fix to update radix_scope_qual in power10

2020-11-10 Thread Athira Rajeev 
power10 uses bit 9 of the raw event code as RADIX_SCOPE_QUAL.
This bit is used for enabling the radix process events.
Patch fixes the PMU counter support functions to program bit
18 of MMCR1 ( Monitor Mode Control Register1 ) with the
RADIX_SCOPE_QUAL bit value. Since this field is not per-pmc,
add this to PMU group constraints to make sure events in a
group will have same bit value for this field. Use bit 21 as
constraint bit field for radix_scope_qual. Patch also updates
the power10 raw event encoding layout information, format field
and constraints bit layout to include the radix_scope_qual bit.

Fixes: a64e697cef23 ("powerpc/perf: power10 Performance Monitoring support")
Signed-off-by: Athira Rajeev 
---
 arch/powerpc/perf/isa207-common.c | 12 
 arch/powerpc/perf/isa207-common.h | 13 ++---
 arch/powerpc/perf/power10-pmu.c   | 11 +++
 3 files changed, 29 insertions(+), 7 deletions(-)

diff --git a/arch/powerpc/perf/isa207-common.c 
b/arch/powerpc/perf/isa207-common.c
index 2848904..f57f54f 100644
--- a/arch/powerpc/perf/isa207-common.c
+++ b/arch/powerpc/perf/isa207-common.c
@@ -339,6 +339,11 @@ int isa207_get_constraint(u64 event, unsigned long *maskp, 
unsigned long *valp)
value |= CNST_L1_QUAL_VAL(cache);
}
 
+   if (cpu_has_feature(CPU_FTR_ARCH_31)) {
+   mask |= CNST_RADIX_SCOPE_GROUP_MASK;
+   value |= CNST_RADIX_SCOPE_GROUP_VAL(event >> 
p10_EVENT_RADIX_SCOPE_QUAL_SHIFT);
+   }
+
if (is_event_marked(event)) {
mask  |= CNST_SAMPLE_MASK;
value |= CNST_SAMPLE_VAL(event >> EVENT_SAMPLE_SHIFT);
@@ -456,6 +461,13 @@ int isa207_compute_mmcr(u64 event[], int n_ev,
}
}
 
+   /* Set RADIX_SCOPE_QUAL bit */
+   if (cpu_has_feature(CPU_FTR_ARCH_31)) {
+   val = (event[i] >> p10_EVENT_RADIX_SCOPE_QUAL_SHIFT) &
+   p10_EVENT_RADIX_SCOPE_QUAL_MASK;
+   mmcr1 |= val << p10_MMCR1_RADIX_SCOPE_QUAL_SHIFT;
+   }
+
if (is_event_marked(event[i])) {
mmcra |= MMCRA_SAMPLE_ENABLE;
 
diff --git a/arch/powerpc/perf/isa207-common.h 
b/arch/powerpc/perf/isa207-common.h
index 7025de5..dc9c3d2 100644
--- a/arch/powerpc/perf/isa207-common.h
+++ b/arch/powerpc/perf/isa207-common.h
@@ -101,6 +101,9 @@
 #define p10_EVENT_CACHE_SEL_MASK   0x3ull
 #define p10_EVENT_MMCR3_MASK   0x7fffull
 #define p10_EVENT_MMCR3_SHIFT  45
+#define p10_EVENT_RADIX_SCOPE_QUAL_SHIFT   9
+#define p10_EVENT_RADIX_SCOPE_QUAL_MASK0x1
+#define p10_MMCR1_RADIX_SCOPE_QUAL_SHIFT   45
 
 #define p10_EVENT_VALID_MASK   \
((p10_SDAR_MODE_MASK   << p10_SDAR_MODE_SHIFT   |   \
@@ -112,6 +115,7 @@
(p9_EVENT_COMBINE_MASK << p9_EVENT_COMBINE_SHIFT)   |   \
(p10_EVENT_MMCR3_MASK  << p10_EVENT_MMCR3_SHIFT)|   \
(EVENT_MARKED_MASK << EVENT_MARKED_SHIFT)   |   \
+   (p10_EVENT_RADIX_SCOPE_QUAL_MASK << p10_EVENT_RADIX_SCOPE_QUAL_SHIFT)   
|   \
 EVENT_LINUX_MASK   |   \
EVENT_PSEL_MASK))
 /*
@@ -125,9 +129,9 @@
  *
  *2824201612 8 4   
  0
  * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - 
- - |
- *   [ ] |   [ ]   [  sample ]   [ ]   [6] [5]   [4] [3]   [2] 
[1]
- *|  || |
- *  BHRB IFM -*  || |  Count of events for 
each PMC.
+ *   [ ] |   [ ] |  [  sample ]   [ ]   [6] [5]   [4] [3]   
[2] [1]
+ *|  ||  |  |
+ *  BHRB IFM -*  ||  |*radix_scope  |  Count of events for 
each PMC.
  *  EBB -*| |p1, p2, p3, p4, p5, 
p6.
  *  L1 I/D qualifier -* |
  * nc - number of counters -*
@@ -165,6 +169,9 @@
 #define CNST_L2L3_GROUP_VAL(v) (((v) & 0x1full) << 55)
 #define CNST_L2L3_GROUP_MASK   CNST_L2L3_GROUP_VAL(0x1f)
 
+#define CNST_RADIX_SCOPE_GROUP_VAL(v)  (((v) & 0x1ull) << 21)
+#define CNST_RADIX_SCOPE_GROUP_MASKCNST_RADIX_SCOPE_GROUP_VAL(1)
+
 /*
  * For NC we are counting up to 4 events. This requires three bits, and we need
  * the fifth event to overflow and set the 4th bit. To achieve that we bias the
diff --git a/arch/powerpc/perf/power10-pmu.c b/arch/powerpc/perf/power10-pmu.c
index 9dbe8f9..cf44fb7 100644
--- a/arch/powerpc/perf/power10-pmu.c
+++ b/arch/powerpc/perf/power10-pmu.c
@@ -23,10 +23,10 @@
  *
  *2824201612 8 4   
  0
  * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - 
- - |
- *   [   ] [  sample ]   [ ] [ ]   [ pmc ]   [unit ]   [ ]   m   [pmcxsel

Re: [RFC PATCH 0/9] powerpc/64s: fast interrupt exit

2020-11-10 Thread Nicholas Piggin 
Excerpts from Christophe Leroy's message of November 10, 2020 9:31 pm:
> 
> 
> Le 10/11/2020 à 09:49, Nicholas Piggin a écrit :
>> Excerpts from Christophe Leroy's message of November 7, 2020 8:35 pm:
>>>
>>>
>>> Le 06/11/2020 à 16:59, Nicholas Piggin a écrit :
 This series attempts to improve the speed of interrupts and system calls
 in two major ways.

 Firstly, the SRR/HSRR registers do not need to be reloaded if they were
 not used or clobbered fur the duration of the interrupt.

 Secondly, an alternate return location facility is added for soft-masked
 asynchronous interrupts and then that's used to set everything up for
 return without having to disable MSR RI or EE.

 After this series, the entire system call / interrupt handler fast path
 executes no mtsprs and one mtmsrd to enable interrupts initially, and
 the system call vectored path doesn't even need to do that.
>>>
>>> Interesting series.
>>>
>>> Unfortunately, can't be done on PPC32 (at least on non bookE), because it 
>>> would mean mapping kernel
>>> at 0 instead of 0xC000. Not sure libc would like it, and anyway it 
>>> would be an issue for
>>> catching NULL pointer dereferencing, unless we use page tables instead of 
>>> BATs to map kernel mem,
>>> which would be serious performance cut.
>> 
>> Hmm, why would you have to map at 0?
> 
> In real mode, physical mem is at 0. If we want to switch from real to virtual 
> mode by just writing 
> to MSR, then we need virtuel addresses match with real addresses ?

Ah that's what I missed.

64s real mode masks out the top 2 bits of the address which is how that 
works. But I don't usually think about that path anyway because most
iterrupts arrive with MMU on.

> We could play with chip selects to put RAM at 0xc000, but then we'd have 
> a problem with 
> exception as they have to be at 0. Or we could play with MSR[IP] and get the 
> exceptions at 
> 0xfff0, but that would not be so easy I guess.
> 
>> 
>> PPC32 doesn't have soft mask interrupts, but you could still test all
>> MSR[PR]=0 interrupts to see if they land inside some region to see if
>> they hit in the restart table I think?
> 
> Yes and this is already what is done at exit for the ones that handle MSR[RI] 
> I think.

Interesting, I'll have to check that out.

>> 
>> Could PPC32 skip the SRR reload at least? That's simpler.
> 
> I think that would only be possible if real addresses where matching virtual 
> addresses, or am I 
> missing something ?

No you're right, I was missing something.

Thanks,
Nick

[PATCH 4/4] powerpc/perf: MMCR0 control for PMU registers under PMCC=00

2020-11-10 Thread Athira Rajeev 
PowerISA v3.1 introduces new control bit (PMCCEXT) for enabling
secure access to group B PMU registers in problem state when
MMCR0 PMCC=0b00. This patch adds support for MMCR0 PMCCEXT bit
in power10 by enabling this bit during boot and during the PMU
event enable/disable operations when MMCR0 PMCC=0b00

Signed-off-by: Athira Rajeev 
---
 arch/powerpc/include/asm/reg.h|  1 +
 arch/powerpc/kernel/cpu_setup_power.S |  2 ++
 arch/powerpc/kernel/dt_cpu_ftrs.c |  1 +
 arch/powerpc/perf/core-book3s.c   | 16 
 4 files changed, 20 insertions(+)

diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index f877a57..cba9965 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -864,6 +864,7 @@
 #define   MMCR0_BHRBA  0x0020UL /* BHRB Access allowed in userspace */
 #define   MMCR0_EBE0x0010UL /* Event based branch enable */
 #define   MMCR0_PMCC   0x000cUL /* PMC control */
+#define   MMCR0_PMCCEXTASM_CONST(0x0200) /* PMCCEXT control */
 #define   MMCR0_PMCC_U60x0008UL /* PMC1-6 are R/W by user (PR) */
 #define   MMCR0_PMC1CE 0x8000UL /* PMC1 count enable*/
 #define   MMCR0_PMCjCE ASM_CONST(0x4000) /* PMCj count enable*/
diff --git a/arch/powerpc/kernel/cpu_setup_power.S 
b/arch/powerpc/kernel/cpu_setup_power.S
index 704e8b9..8fc8b72 100644
--- a/arch/powerpc/kernel/cpu_setup_power.S
+++ b/arch/powerpc/kernel/cpu_setup_power.S
@@ -249,4 +249,6 @@ __init_PMU_ISA31:
mtspr   SPRN_MMCR3,r5
LOAD_REG_IMMEDIATE(r5, MMCRA_BHRB_DISABLE)
mtspr   SPRN_MMCRA,r5
+   LOAD_REG_IMMEDIATE(r5, MMCR0_PMCCEXT)
+   mtspr   SPRN_MMCR0,r5
blr
diff --git a/arch/powerpc/kernel/dt_cpu_ftrs.c 
b/arch/powerpc/kernel/dt_cpu_ftrs.c
index 1098863..9d07965 100644
--- a/arch/powerpc/kernel/dt_cpu_ftrs.c
+++ b/arch/powerpc/kernel/dt_cpu_ftrs.c
@@ -454,6 +454,7 @@ static void init_pmu_power10(void)
 
mtspr(SPRN_MMCR3, 0);
mtspr(SPRN_MMCRA, MMCRA_BHRB_DISABLE);
+   mtspr(SPRN_MMCR0, MMCR0_PMCCEXT);
 }
 
 static int __init feat_enable_pmu_power10(struct dt_cpu_feature *f)
diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c
index 08643cb..f328bc0 100644
--- a/arch/powerpc/perf/core-book3s.c
+++ b/arch/powerpc/perf/core-book3s.c
@@ -95,6 +95,7 @@ struct cpu_hw_events {
 #define SPRN_SIER3 0
 #define MMCRA_SAMPLE_ENABLE0
 #define MMCRA_BHRB_DISABLE 0
+#define MMCR0_PMCCEXT  0
 
 static inline unsigned long perf_ip_adjust(struct pt_regs *regs)
 {
@@ -1242,6 +1243,9 @@ static void power_pmu_disable(struct pmu *pmu)
val |= MMCR0_FC;
val &= ~(MMCR0_EBE | MMCR0_BHRBA | MMCR0_PMCC | MMCR0_PMAO |
 MMCR0_FC56);
+   /* Set mmcr0 PMCCEXT for p10 */
+   if (ppmu->flags & PPMU_ARCH_31)
+   val |= MMCR0_PMCCEXT;
 
/*
 * The barrier is to make sure the mtspr has been
@@ -1449,6 +1453,18 @@ static void power_pmu_enable(struct pmu *pmu)
 
mmcr0 = ebb_switch_in(ebb, cpuhw);
 
+   /*
+* Set mmcr0 (PMCCEXT) for p10
+* if mmcr0 PMCC=0b00 to allow secure
+* mode of access to group B registers.
+*/
+   if (ppmu->flags & PPMU_ARCH_31) {
+   if (!(mmcr0 & MMCR0_PMCC)) {
+   cpuhw->mmcr.mmcr0 |= MMCR0_PMCCEXT;
+   mmcr0 |= MMCR0_PMCCEXT;
+   }
+   }
+
mb();
if (cpuhw->bhrb_users)
ppmu->config_bhrb(cpuhw->bhrb_filter);
-- 
1.8.3.1

[PATCH 0/4] powerpc/perf: Fixes for power10 PMU

2020-11-10 Thread Athira Rajeev 
Patchset contains PMU fixes for power10.

This patchset contains 4 patches.
Patch1 includes fix to update event code with radix_scope_qual
bit in power10.
Patch2 updates the event group constraints for L2/L3 and threshold
events in power10.
Patch3 includes the event code changes for l2/l3 events and
some of the generic events.
Patch4 adds fixes for PMCCEXT bit in power10.

Athira Rajeev (4):
  powerpc/perf: Fix to update radix_scope_qual in power10
  powerpc/perf: Update the PMU group constraints for l2l3 and threshold
events in power10
  powerpc/perf: Fix to update l2l3 events and generic event codes for
power10
  powerpc/perf: MMCR0 control for PMU registers under PMCC=00

 arch/powerpc/include/asm/reg.h  |   1 +
 arch/powerpc/kernel/cpu_setup_power.S   |   2 +
 arch/powerpc/kernel/dt_cpu_ftrs.c   |   1 +
 arch/powerpc/perf/core-book3s.c |  16 +++
 arch/powerpc/perf/isa207-common.c   |  27 -
 arch/powerpc/perf/isa207-common.h   |  16 ++-
 arch/powerpc/perf/power10-events-list.h |   9 ++
 arch/powerpc/perf/power10-pmu.c | 177 ++--
 8 files changed, 236 insertions(+), 13 deletions(-)

-- 
1.8.3.1

Re: [PATCH 03/18] powerpc: bad_page_fault, do_break get registers from regs

2020-11-10 Thread Nicholas Piggin 
Excerpts from Christophe Leroy's message of November 10, 2020 9:19 pm:
> 
> 
> Le 10/11/2020 à 09:34, Nicholas Piggin a écrit :
>> Excerpts from Christophe Leroy's message of November 6, 2020 6:14 pm:
>>>
>>>
>>> Le 05/11/2020 à 15:34, Nicholas Piggin a écrit :
 This also moves the 32s DABR match to C.
>>>
>>> Is there a real benefit doing this ?
>> 
>> Oh I missed doing it, but yes I think bad_page_fault and do_break should
>> probably be implemented with the DEFINE_INTERRUT_HANDLER wrappers.
>> 
> 
> Yes, anyway, do we need to do that change ? Can't the dispatch between 
> do_break() and page fault 
> handling remain in handle_page_fault() ? What's the benefit of going into 
> do_page_fault() and coming 
> back ?

You might be right, I'll take another look at it.

Thanks,
Nick

Re: [PATCH 02/18] powerpc: remove arguments from fault handler functions

2020-11-10 Thread Nicholas Piggin 
Excerpts from Christophe Leroy's message of November 10, 2020 9:15 pm:
> 
> 
> Le 10/11/2020 à 09:29, Nicholas Piggin a écrit :
>> Excerpts from Christophe Leroy's message of November 6, 2020 5:59 pm:
>>>
>>>
>>> Le 05/11/2020 à 15:34, Nicholas Piggin a écrit :
 Make mm fault handlers all just take the pt_regs * argument and load
 DAR/DSISR from that. Make those that return a value return long.

 This is done to make the function signatures match other handlers, which
 will help with a future patch to add wrappers. Explicit arguments could
 be added for performance but that would require more wrapper macro
 variants.

 Signed-off-by: Nicholas Piggin 
 ---
> 
> [...]
> 
>> 
 diff --git a/arch/powerpc/mm/fault.c b/arch/powerpc/mm/fault.c
 index e65a49f246ef..390a296b16a3 100644
 --- a/arch/powerpc/mm/fault.c
 +++ b/arch/powerpc/mm/fault.c
 @@ -549,11 +549,12 @@ static int __do_page_fault(struct pt_regs *regs, 
 unsigned long address,
}
NOKPROBE_SYMBOL(__do_page_fault);

 -int do_page_fault(struct pt_regs *regs, unsigned long address,
 -unsigned long error_code)
 +long do_page_fault(struct pt_regs *regs)
{
enum ctx_state prev_state = exception_enter();
 -  int err;
 +  unsigned long address = regs->dar;
 +  unsigned long error_code = regs->dsisr;
 +  long err;
>>>
>>> By doing something more or less like this (need to be tuned for bookE as 
>>> well):
>>>
>>> +   int is_exec = TRAP(regs) == 0x400;
>>> +   unsigned long address = is_exec ? regs->ssr0 : regs->dar;
>>> +   unsigned long error_code = is_exec ? (regs->ssr1 & 
>>> DSISR_SRR1_MATCH_32S) : regs->dsisr;
>> 
>> Ah, I didn't see that you saved these in srr0/1 already. Hmm, not in
>> pt_regs though. thread_struct (VMAP_STACK only)? exception_regs (booke
>> only)? Doesn't seem so easy.
> 
> Oops yes you are right, SRR0/SRR1 are not in pt_regs. And their validity in 
> thread struct is rather 
> short ... So forget my comment.

So, are you happy to go with this for now? I guess things can
later be cleaned up to avoid double saving on cases like VMAP.

Thanks,
Nick

[PATCH] Revert "powerpc/pseries/hotplug-cpu: Remove double free in error path"

2020-11-10 Thread Zhang Xiaoxu 
This reverts commit a0ff72f9f5a780341e7ff5e9ba50a0dad5fa1980.

Since the commit b015f6bc9547 ("powerpc/pseries: Add cpu DLPAR
support for drc-info property"), the 'cpu_drcs' wouldn't be double
freed when the 'cpus' node not found.

So we needn't apply this patch, otherwise, the memory will be leak.

Fixes: a0ff72f9f5a7 ("powerpc/pseries/hotplug-cpu: Remove double free in error 
path")
Reported-by: Hulk Robot 
Signed-off-by: Zhang Xiaoxu 
---
 arch/powerpc/platforms/pseries/hotplug-cpu.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/powerpc/platforms/pseries/hotplug-cpu.c 
b/arch/powerpc/platforms/pseries/hotplug-cpu.c
index f2837e33bf5d..4bb1c9f2bb11 100644
--- a/arch/powerpc/platforms/pseries/hotplug-cpu.c
+++ b/arch/powerpc/platforms/pseries/hotplug-cpu.c
@@ -743,6 +743,7 @@ static int dlpar_cpu_add_by_count(u32 cpus_to_add)
parent = of_find_node_by_path("/cpus");
if (!parent) {
pr_warn("Could not find CPU root node in device tree\n");
+   kfree(cpu_drcs);
return -1;
}
 
-- 
2.25.4

Re: [PATCH] KVM: PPC: Book3S HV: XIVE: Fix possible oops when accessing ESB page

2020-11-10 Thread Cédric Le Goater 
On 11/6/20 4:19 AM, Michael Ellerman wrote:
> Cédric Le Goater  writes:
>> When accessing the ESB page of a source interrupt, the fault handler
>> will retrieve the page address from the XIVE interrupt 'xive_irq_data'
>> structure. If the associated KVM XIVE interrupt is not valid, that is
>> not allocated at the HW level for some reason, the fault handler will
>> dereference a NULL pointer leading to the oops below :
>>
>> WARNING: CPU: 40 PID: 59101 at arch/powerpc/kvm/book3s_xive_native.c:259 
>> xive_native_esb_fault+0xe4/0x240 [kvm]
>> CPU: 40 PID: 59101 Comm: qemu-system-ppc Kdump: loaded Tainted: G
>> W- -  - 4.18.0-240.el8.ppc64le #1
>> NIP:  c0080e949fac LR: c044b164 CTR: c0080e949ec8
>> REGS: c01f69617840 TRAP: 0700   Tainted: GW- 
>> -  -  (4.18.0-240.el8.ppc64le)
>> MSR:  90029033   CR: 44044282  XER: 
>> 
>> CFAR: c044b160 IRQMASK: 0
>> GPR00: c044b164 c01f69617ac0 c0080e96e000 
>> c01f69617c10
>> GPR04: 05faa2b21e80  0005 
>> 
>> GPR08:  0001  
>> 0001
>> GPR12: c0080e949ec8 c01d3400  
>> 
>> GPR16:    
>> 
>> GPR20:   c01f5c065160 
>> c1c76f90
>> GPR24: c01f06f2 c01f5c065100 0008 
>> c01f0eb98c78
>> GPR28: c01dcab4 c01dcab403d8 c01f69617c10 
>> 0011
>> NIP [c0080e949fac] xive_native_esb_fault+0xe4/0x240 [kvm]
>> LR [c044b164] __do_fault+0x64/0x220
>> Call Trace:
>> [c01f69617ac0] [000137a5dc20] 0x137a5dc20 (unreliable)
>> [c01f69617b50] [c044b164] __do_fault+0x64/0x220
>> [c01f69617b90] [c0453838] do_fault+0x218/0x930
>> [c01f69617bf0] [c0456f50] __handle_mm_fault+0x350/0xdf0
>> [c01f69617cd0] [c0457b1c] handle_mm_fault+0x12c/0x310
>> [c01f69617d10] [c007ef44] __do_page_fault+0x264/0xbb0
>> [c01f69617df0] [c007f8c8] do_page_fault+0x38/0xd0
>> [c01f69617e30] [c000a714] handle_page_fault+0x18/0x38
>> Instruction dump:
>> 40c2fff0 7c2004ac 2fa9 409e0118 73e90001 41820080 e8bd0008 7c2004ac
>> 7ca90074 3940 915c 7929d182 <0b09> 2fa5 419e0080 e89e0018
>> ---[ end trace 66c6ff034c53f64f ]---
>> xive-kvm: xive_native_esb_fault: accessing invalid ESB page for source 8 
>> !
>>
>> Fix that by checking the validity of the KVM XIVE interrupt structure.
>>
>> Reported-by: Greg Kurz 
>> Signed-off-by: Cédric Le Goater 
> 
> Fixes ?

Ah yes :/  

Cc: sta...@vger.kernel.org # v5.2+
Fixes: 6520ca64cde7 ("KVM: PPC: Book3S HV: XIVE: Add a mapping for the source 
ESB pages")

Since my provider changed its imap servers, my email filters are really screwed 
up and I miss emails. 

Sorry about that,

C.

Re: [PATCH] ASoC: fsl_xcvr: fix break condition

2020-11-10 Thread Mark Brown 
On Mon, 2 Nov 2020 18:18:10 +0200, Viorel Suman (OSS) wrote:
> The break condition copied by mistake as same
> as loop condition in the previous version, but must
> be the opposite. So fix it.

Applied to

   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-next

Thanks!

[1/1] ASoC: fsl_xcvr: fix break condition
  commit: 048751de568816de52dedf0fa967cceada7885f1

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark

Re: Duplicated ABI entries - Was: Re: [PATCH v2 20/39] docs: ABI: testing: make the files compatible with ReST output

2020-11-10 Thread Randy Dunlap 
On 11/9/20 11:26 PM, Mauro Carvalho Chehab wrote:
> Hi Jonathan,
> 
> Let's view ABI from the PoV of a system admin that doesn't know
> yet about a certain ABI symbol.
> 
> He'll try to seek for the symbol, more likely using the HTML 
> documentation. Only very senior system admins might try to take
> a look at the Kernel.

FWIW, I think that the likely search methods are $search_engine
and 'grep'.

Have a good few days off.

-- 
~Randy

[PATCH] powerpc/pseries/hotplug-cpu: Fix memleak when cpus node not exist

2020-11-10 Thread Zhang Xiaoxu 
From: zhangxiaoxu 

If the cpus nodes not exist, we lost to free the 'cpu_drcs', which
will leak memory.

Fixes: a0ff72f9f5a7 ("powerpc/pseries/hotplug-cpu: Remove double free in error 
path")
Reported-by: Hulk Robot 
Signed-off-by: zhangxiaoxu 
---
 arch/powerpc/platforms/pseries/hotplug-cpu.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/powerpc/platforms/pseries/hotplug-cpu.c 
b/arch/powerpc/platforms/pseries/hotplug-cpu.c
index f2837e33bf5d..4bb1c9f2bb11 100644
--- a/arch/powerpc/platforms/pseries/hotplug-cpu.c
+++ b/arch/powerpc/platforms/pseries/hotplug-cpu.c
@@ -743,6 +743,7 @@ static int dlpar_cpu_add_by_count(u32 cpus_to_add)
parent = of_find_node_by_path("/cpus");
if (!parent) {
pr_warn("Could not find CPU root node in device tree\n");
+   kfree(cpu_drcs);
return -1;
}
 
-- 
2.25.4

Re: [PATCH] powerpc/pseries/hotplug-cpu: Fix memleak when cpus node not exist

2020-11-10 Thread Tyrel Datwyler 
On 11/10/20 6:08 AM, Nathan Lynch wrote:
> Zhang Xiaoxu  writes:
>> From: zhangxiaoxu 
>>
>> If the cpus nodes not exist, we lost to free the 'cpu_drcs', which
>> will leak memory.
>>
>> Fixes: a0ff72f9f5a7 ("powerpc/pseries/hotplug-cpu: Remove double free in 
>> error path")
>> Reported-by: Hulk Robot 
>> Signed-off-by: zhangxiaoxu 
>> ---
>>  arch/powerpc/platforms/pseries/hotplug-cpu.c | 1 +
>>  1 file changed, 1 insertion(+)
>>
>> diff --git a/arch/powerpc/platforms/pseries/hotplug-cpu.c 
>> b/arch/powerpc/platforms/pseries/hotplug-cpu.c
>> index f2837e33bf5d..4bb1c9f2bb11 100644
>> --- a/arch/powerpc/platforms/pseries/hotplug-cpu.c
>> +++ b/arch/powerpc/platforms/pseries/hotplug-cpu.c
>> @@ -743,6 +743,7 @@ static int dlpar_cpu_add_by_count(u32 cpus_to_add)
>>  parent = of_find_node_by_path("/cpus");
>>  if (!parent) {
>>  pr_warn("Could not find CPU root node in device tree\n");
>> +kfree(cpu_drcs);
>>  return -1;
>>  }
> 
> Thanks for finding this.
> 
> a0ff72f9f5a7 ("powerpc/pseries/hotplug-cpu: Remove double free in error
> path") was posted in Sept 2019 but was not applied until July 2020:
> 
> https://lore.kernel.org/linuxppc-dev/20190919231633.1344-1-nath...@linux.ibm.com/
> 
> Here is that change as posted; note the function context is
> find_dlpar_cpus_to_add(), not dlpar_cpu_add_by_count():
> 
> --- a/arch/powerpc/platforms/pseries/hotplug-cpu.c
> +++ b/arch/powerpc/platforms/pseries/hotplug-cpu.c
> @@ -726,7 +726,6 @@ static int find_dlpar_cpus_to_add(u32 *cpu_drcs, u32 
> cpus_to_add)
>   parent = of_find_node_by_path("/cpus");
>   if (!parent) {
>   pr_warn("Could not find CPU root node in device tree\n");
> - kfree(cpu_drcs);
>   return -1;
>   }
> 
> Meanwhile b015f6bc9547dbc056edde7177c7868ca8629c4c ("powerpc/pseries: Add
> cpu DLPAR support for drc-info property") was posted in Nov 2019 and
> committed a few days later:
> 
> https://lore.kernel.org/linux-pci/1573449697-5448-4-git-send-email-tyr...@linux.ibm.com/
> 
> This change reorganized the same code, removing
> find_dlpar_cpus_to_add(), and it had the effect of fixing the same
> issue.
> 
> However git apparently allowed the older change to still apply on top of
> this (changing a function different from the one in the original
> patch!), leading to a real bug.

Yikes, not sure how that happened without either the committer massaging the
patch to apply, or the line location and context matching exactly.

> 
> Your patch is correct but it should be framed as a revert of
> a0ff72f9f5a7 with this context in the commit message.
> 

Agreed, in reality we want to revert a patch that shouldn't have been applied.

-Tyrel

Re: [PATCH v2 2/2] dt-bindings: misc: convert fsl, qoriq-mc from txt to YAML

2020-11-10 Thread Laurentiu Tudor 



On 11/10/2020 7:20 PM, Rob Herring wrote:
> On Mon, Nov 9, 2020 at 4:11 PM Rob Herring  wrote:
>>
>> On Mon, 09 Nov 2020 12:46:35 +0200, Laurentiu Tudor wrote:
>>> From: Ionut-robert Aron 
>>>
>>> Convert fsl,qoriq-mc to YAML in order to automate the verification
>>> process of dts files. In addition, update MAINTAINERS accordingly
>>> and, while at it, add some missing files.
>>>
>>> Signed-off-by: Ionut-robert Aron 
>>> [laurentiu.tu...@nxp.com: update MINTAINERS, updates & fixes in schema]
>>> Signed-off-by: Laurentiu Tudor 
>>> ---
>>> Changes in v2:
>>>  - fixed errors reported by yamllint
>>>  - dropped multiple unnecessary quotes
>>>  - used schema instead of text in description
>>>  - added constraints on dpmac reg property
>>>
>>>  .../devicetree/bindings/misc/fsl,qoriq-mc.txt | 196 
>>>  .../bindings/misc/fsl,qoriq-mc.yaml   | 210 ++
>>>  .../ethernet/freescale/dpaa2/overview.rst |   5 +-
>>>  MAINTAINERS   |   4 +-
>>>  4 files changed, 217 insertions(+), 198 deletions(-)
>>>  delete mode 100644 Documentation/devicetree/bindings/misc/fsl,qoriq-mc.txt
>>>  create mode 100644 Documentation/devicetree/bindings/misc/fsl,qoriq-mc.yaml
>>>
>>
>> Applied, thanks!
> 
> And now dropped. This duplicates what's in commit 0dbcd4991719
> ("dt-bindings: net: add the DPAA2 MAC DTS definition") and has
> warnings from it:
> 
> /builds/robherring/linux-dt-bindings/Documentation/devicetree/bindings/misc/fsl,qoriq-mc.example.dt.yaml:
> dpmac@1: $nodename:0: 'dpmac@1' does not match '^ethernet(@.*)?$'
>  From schema: 
> /builds/robherring/linux-dt-bindings/Documentation/devicetree/bindings/net/fsl,qoriq-mc-dpmac.yaml
> 

My patch converts the .txt devicetree/bindings/misc/fsl,qoriq-mc.yaml
while the commit you mention creates
devicetree/bindings/net/fsl,qoriq-mc-dpmac.yaml, but at a first sight
there seems to be some duplication. Will sync internally with my
colleagues and return with a resolution. Thanks and sorry for the trouble.

---
Best Regards, Laurentiu

Re: [PATCH v2 2/2] dt-bindings: misc: convert fsl, qoriq-mc from txt to YAML

2020-11-10 Thread Rob Herring 
On Mon, Nov 9, 2020 at 4:11 PM Rob Herring  wrote:
>
> On Mon, 09 Nov 2020 12:46:35 +0200, Laurentiu Tudor wrote:
> > From: Ionut-robert Aron 
> >
> > Convert fsl,qoriq-mc to YAML in order to automate the verification
> > process of dts files. In addition, update MAINTAINERS accordingly
> > and, while at it, add some missing files.
> >
> > Signed-off-by: Ionut-robert Aron 
> > [laurentiu.tu...@nxp.com: update MINTAINERS, updates & fixes in schema]
> > Signed-off-by: Laurentiu Tudor 
> > ---
> > Changes in v2:
> >  - fixed errors reported by yamllint
> >  - dropped multiple unnecessary quotes
> >  - used schema instead of text in description
> >  - added constraints on dpmac reg property
> >
> >  .../devicetree/bindings/misc/fsl,qoriq-mc.txt | 196 
> >  .../bindings/misc/fsl,qoriq-mc.yaml   | 210 ++
> >  .../ethernet/freescale/dpaa2/overview.rst |   5 +-
> >  MAINTAINERS   |   4 +-
> >  4 files changed, 217 insertions(+), 198 deletions(-)
> >  delete mode 100644 Documentation/devicetree/bindings/misc/fsl,qoriq-mc.txt
> >  create mode 100644 Documentation/devicetree/bindings/misc/fsl,qoriq-mc.yaml
> >
>
> Applied, thanks!

And now dropped. This duplicates what's in commit 0dbcd4991719
("dt-bindings: net: add the DPAA2 MAC DTS definition") and has
warnings from it:

/builds/robherring/linux-dt-bindings/Documentation/devicetree/bindings/misc/fsl,qoriq-mc.example.dt.yaml:
dpmac@1: $nodename:0: 'dpmac@1' does not match '^ethernet(@.*)?$'
 From schema: 
/builds/robherring/linux-dt-bindings/Documentation/devicetree/bindings/net/fsl,qoriq-mc-dpmac.yaml

Rob

Re: [PATCH v3 01/16] dt-bindings: usb: usb-hcd: Convert generic USB properties to DT schema

2020-11-10 Thread Serge Semin 
It seems noone is going to get involved in the discussion. Therefore I'll
fix the patch in the way I suggested in my previous message. Alas I'll
have to remove the reviewed-by tags of Rob from some patches.

-Sergey

On Mon, Oct 26, 2020 at 07:46:49PM +0300, Serge Semin wrote:
> Folks, any comment on my previous message below?
> 
> On Wed, Oct 21, 2020 at 06:46:21PM +0300, Serge Semin wrote:
> > On Wed, Oct 21, 2020 at 11:00:36AM +0800, Chunfeng Yun wrote:
> > > On Tue, 2020-10-20 at 14:20 +0300, Serge Semin wrote:
> > > > The generic USB HCD properties have been described in the legacy 
> > > > bindings
> > > > text file: Documentation/devicetree/bindings/usb/generic.txt . Let's
> > > > convert it' content into the USB HCD DT schema properties so all USB DT
> > >   ^ its?
> > > > nodes would be validated to have them properly utilized.
> > > > 
> > > > Signed-off-by: Serge Semin 
> > > > Reviewed-by: Rob Herring 
> > > > 
> > > > ---
> > > > 
> > > > Changelog v2:
> > > > - Discard '|' in all the new properties, since we don't need to preserve
> > > >   the text formatting.
> > > > - Convert abbreviated form of the "maximum-speed" enum restriction into
> > > >   the multi-lined version of the list.
> > > > - Drop quotes from around the string constants.
> > > > ---
> > > >  .../devicetree/bindings/usb/generic.txt   | 57 
> > > >  .../devicetree/bindings/usb/usb-hcd.yaml  | 88 +++
> > 
> > > Do we need change the file name or modify it's title?
> > > the title is "Generic USB Host Controller Device Tree Bindings", but
> > > some generic properties, such as, dr_mode, usb-role-switch, otg related
> > > ones, are usually used by DRD controller, this may cause some confusion.
> > 
> > Hm, good question. A problem of the naming and the properties inclusion do
> > exist here. I haven't thought that through when moved all the generic
> > properties into the usb-hcd.yaml bindings file. But I don't think it's a 
> > good
> > idea to rename the file. Most likely the best solution would be to split the
> > functionality up as follows:
> > 
> > 1) usb.yaml - common USB controller with generic properties for all USB 
> > modes (host, peripheral, otg):
> >+ $nodename
> >+ phys
> >+ phy-names
> >+ usb-phy
> >+ maximum-speed
> >+ phy_type
> > 2) usb-hcd.yaml - DT schema for USB host controllers (EHCI/OHCI/UHCI):
> >+ allOf: [usb.yaml#]
> >+ companion
> > 3) usb-xhci.yaml - DT schema for USB host controllers (xHCI):
> >+ allOf: [usb-hcd.yaml#]
> >+ usb2-lpm-disable
> >+ usb3-lpm-capable
> >+ quirk-broken-port-ped
> >+ imod-interval-ns
> > 4) usb-drd.yaml - DT schema for USB OTG controllers:
> >+ otg-rev
> >+ hnp-disable
> >+ srp-disable
> >+ adp-disable
> >+ usb-role-switch
> >+ role-switch-default-mode
> >+ tpl-support
> >+ dr_mode: [host, peripheral, otg]
> > 
> > So in case if an USB controller is DRD with EHCI host, then it will need
> > to pass evaluation of allOf: [usb-hcd.yaml#, usb-drd.yaml#]. If an USB
> > controller is DRD with xHCI host, then the next schema can be applied:
> > [usb-xhci.yaml#, usb-drd.yaml#]. A conditional schema is also applicable
> > here, like this:
> > allOf:
> >   - $ref: usb-drd.yaml#
> >   - if:
> >   properties:
> > dr_mode:
> >   const: host
> > then:
> >   $ref: usb-hcd.yaml# (or usb-xhci.yaml#)
> > else:
> >   #ref: usb.yaml#
> > 
> > What do you think? @Rob, @Greg, we need your opinion here.
> > 
> > -Sergey
> > 
> > > 
> > > >  2 files changed, 88 insertions(+), 57 deletions(-)
> > > >  delete mode 100644 Documentation/devicetree/bindings/usb/generic.txt
> > > > 
> > > > diff --git a/Documentation/devicetree/bindings/usb/generic.txt 
> > > > b/Documentation/devicetree/bindings/usb/generic.txt
> > > > deleted file mode 100644
> > > > index ba472e7aefc9..
> > > > --- a/Documentation/devicetree/bindings/usb/generic.txt
> > > > +++ /dev/null
> > > > @@ -1,57 +0,0 @@
> > > > -Generic USB Properties
> > > > -
> > > > -Optional properties:
> > > > - - maximum-speed: tells USB controllers we want to work up to a certain
> > > > -   speed. Valid arguments are "super-speed-plus",
> > > > -   "super-speed", "high-speed", "full-speed" and
> > > > -   "low-speed". In case this isn't passed via DT, 
> > > > USB
> > > > -   controllers should default to their maximum HW
> > > > -   capability.
> > > > - - dr_mode: tells Dual-Role USB controllers that we want to work on a
> > > > -   particular mode. Valid arguments are "host",
> > > > -   "peripheral" and "otg". In case this attribute 
> > > > isn't
> > > > -   passed via DT, USB DRD controllers should 
> > > > default to
> > > > -   OTG.
> > > > - - phy_type: tells USB controllers that we want

Re: [PATCH] powerpc/pseries/hotplug-cpu: Fix memleak when cpus node not exist

2020-11-10 Thread Nathan Lynch 
Zhang Xiaoxu  writes:
> From: zhangxiaoxu 
>
> If the cpus nodes not exist, we lost to free the 'cpu_drcs', which
> will leak memory.
>
> Fixes: a0ff72f9f5a7 ("powerpc/pseries/hotplug-cpu: Remove double free in 
> error path")
> Reported-by: Hulk Robot 
> Signed-off-by: zhangxiaoxu 
> ---
>  arch/powerpc/platforms/pseries/hotplug-cpu.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/arch/powerpc/platforms/pseries/hotplug-cpu.c 
> b/arch/powerpc/platforms/pseries/hotplug-cpu.c
> index f2837e33bf5d..4bb1c9f2bb11 100644
> --- a/arch/powerpc/platforms/pseries/hotplug-cpu.c
> +++ b/arch/powerpc/platforms/pseries/hotplug-cpu.c
> @@ -743,6 +743,7 @@ static int dlpar_cpu_add_by_count(u32 cpus_to_add)
>   parent = of_find_node_by_path("/cpus");
>   if (!parent) {
>   pr_warn("Could not find CPU root node in device tree\n");
> + kfree(cpu_drcs);
>   return -1;
>   }

Thanks for finding this.

a0ff72f9f5a7 ("powerpc/pseries/hotplug-cpu: Remove double free in error
path") was posted in Sept 2019 but was not applied until July 2020:

https://lore.kernel.org/linuxppc-dev/20190919231633.1344-1-nath...@linux.ibm.com/

Here is that change as posted; note the function context is
find_dlpar_cpus_to_add(), not dlpar_cpu_add_by_count():

--- a/arch/powerpc/platforms/pseries/hotplug-cpu.c
+++ b/arch/powerpc/platforms/pseries/hotplug-cpu.c
@@ -726,7 +726,6 @@ static int find_dlpar_cpus_to_add(u32 *cpu_drcs, u32 
cpus_to_add)
parent = of_find_node_by_path("/cpus");
if (!parent) {
pr_warn("Could not find CPU root node in device tree\n");
-   kfree(cpu_drcs);
return -1;
}

Meanwhile b015f6bc9547dbc056edde7177c7868ca8629c4c ("powerpc/pseries: Add
cpu DLPAR support for drc-info property") was posted in Nov 2019 and
committed a few days later:

https://lore.kernel.org/linux-pci/1573449697-5448-4-git-send-email-tyr...@linux.ibm.com/

This change reorganized the same code, removing
find_dlpar_cpus_to_add(), and it had the effect of fixing the same
issue.

However git apparently allowed the older change to still apply on top of
this (changing a function different from the one in the original
patch!), leading to a real bug.

Your patch is correct but it should be framed as a revert of
a0ff72f9f5a7 with this context in the commit message.

Re: [PATCH] powerpc/powernv/sriov: fix unsigned int win compared to less than zero

2020-11-10 Thread Andrew Donnellan 

On 10/11/20 10:19 pm, xiakaixu1...@gmail.com wrote:

From: Kaixu Xia 

Fix coccicheck warning:

./arch/powerpc/platforms/powernv/pci-sriov.c:443:7-10: WARNING: Unsigned 
expression compared with zero: win < 0
./arch/powerpc/platforms/powernv/pci-sriov.c:462:7-10: WARNING: Unsigned 
expression compared with zero: win < 0

Reported-by: Tosk Robot 
Signed-off-by: Kaixu Xia 


This seems like the right fix, the value assigned to win can indeed be 
-1 so it should be signed. Thanks for sending the patch.


Reviewed-by: Andrew Donnellan 


---
  arch/powerpc/platforms/powernv/pci-sriov.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/powerpc/platforms/powernv/pci-sriov.c 
b/arch/powerpc/platforms/powernv/pci-sriov.c
index c4434f20f42f..92fc861c528f 100644
--- a/arch/powerpc/platforms/powernv/pci-sriov.c
+++ b/arch/powerpc/platforms/powernv/pci-sriov.c
@@ -422,7 +422,7 @@ static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 
num_vfs)
  {
struct pnv_iov_data   *iov;
struct pnv_phb*phb;
-   unsigned int   win;
+   intwin;
struct resource   *res;
inti, j;
int64_trc;



--
Andrew Donnellan  OzLabs, ADL Canberra
a...@linux.ibm.com IBM Australia Limited

Re: [RFC PATCH 0/9] powerpc/64s: fast interrupt exit

2020-11-10 Thread Christophe Leroy 




Le 10/11/2020 à 09:49, Nicholas Piggin a écrit :

Excerpts from Christophe Leroy's message of November 7, 2020 8:35 pm:



Le 06/11/2020 à 16:59, Nicholas Piggin a écrit :

This series attempts to improve the speed of interrupts and system calls
in two major ways.

Firstly, the SRR/HSRR registers do not need to be reloaded if they were
not used or clobbered fur the duration of the interrupt.

Secondly, an alternate return location facility is added for soft-masked
asynchronous interrupts and then that's used to set everything up for
return without having to disable MSR RI or EE.

After this series, the entire system call / interrupt handler fast path
executes no mtsprs and one mtmsrd to enable interrupts initially, and
the system call vectored path doesn't even need to do that.


Interesting series.

Unfortunately, can't be done on PPC32 (at least on non bookE), because it would 
mean mapping kernel
at 0 instead of 0xC000. Not sure libc would like it, and anyway it would be 
an issue for
catching NULL pointer dereferencing, unless we use page tables instead of BATs 
to map kernel mem,
which would be serious performance cut.


Hmm, why would you have to map at 0?


In real mode, physical mem is at 0. If we want to switch from real to virtual mode by just writing 
to MSR, then we need virtuel addresses match with real addresses ?
We could play with chip selects to put RAM at 0xc000, but then we'd have a problem with 
exception as they have to be at 0. Or we could play with MSR[IP] and get the exceptions at 
0xfff0, but that would not be so easy I guess.




PPC32 doesn't have soft mask interrupts, but you could still test all
MSR[PR]=0 interrupts to see if they land inside some region to see if
they hit in the restart table I think?


Yes and this is already what is done at exit for the ones that handle MSR[RI] I 
think.



Could PPC32 skip the SRR reload at least? That's simpler.


I think that would only be possible if real addresses where matching virtual addresses, or am I 
missing something ?


Christophe

[PATCH] powerpc/powernv/sriov: fix unsigned int win compared to less than zero

2020-11-10 Thread xiakaixu1987 
From: Kaixu Xia 

Fix coccicheck warning:

./arch/powerpc/platforms/powernv/pci-sriov.c:443:7-10: WARNING: Unsigned 
expression compared with zero: win < 0
./arch/powerpc/platforms/powernv/pci-sriov.c:462:7-10: WARNING: Unsigned 
expression compared with zero: win < 0

Reported-by: Tosk Robot 
Signed-off-by: Kaixu Xia 
---
 arch/powerpc/platforms/powernv/pci-sriov.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/powerpc/platforms/powernv/pci-sriov.c 
b/arch/powerpc/platforms/powernv/pci-sriov.c
index c4434f20f42f..92fc861c528f 100644
--- a/arch/powerpc/platforms/powernv/pci-sriov.c
+++ b/arch/powerpc/platforms/powernv/pci-sriov.c
@@ -422,7 +422,7 @@ static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 
num_vfs)
 {
struct pnv_iov_data   *iov;
struct pnv_phb*phb;
-   unsigned int   win;
+   intwin;
struct resource   *res;
inti, j;
int64_trc;
-- 
2.20.0

Re: [PATCH 03/18] powerpc: bad_page_fault, do_break get registers from regs

2020-11-10 Thread Christophe Leroy 




Le 10/11/2020 à 09:34, Nicholas Piggin a écrit :

Excerpts from Christophe Leroy's message of November 6, 2020 6:14 pm:



Le 05/11/2020 à 15:34, Nicholas Piggin a écrit :

This also moves the 32s DABR match to C.


Is there a real benefit doing this ?


Oh I missed doing it, but yes I think bad_page_fault and do_break should
probably be implemented with the DEFINE_INTERRUT_HANDLER wrappers.



Yes, anyway, do we need to do that change ? Can't the dispatch between do_break() and page fault 
handling remain in handle_page_fault() ? What's the benefit of going into do_page_fault() and coming 
back ?


Christophe

Re: [PATCH 02/18] powerpc: remove arguments from fault handler functions

2020-11-10 Thread Christophe Leroy 




Le 10/11/2020 à 09:29, Nicholas Piggin a écrit :

Excerpts from Christophe Leroy's message of November 6, 2020 5:59 pm:



Le 05/11/2020 à 15:34, Nicholas Piggin a écrit :

Make mm fault handlers all just take the pt_regs * argument and load
DAR/DSISR from that. Make those that return a value return long.

This is done to make the function signatures match other handlers, which
will help with a future patch to add wrappers. Explicit arguments could
be added for performance but that would require more wrapper macro
variants.

Signed-off-by: Nicholas Piggin 
---


[...]




diff --git a/arch/powerpc/mm/fault.c b/arch/powerpc/mm/fault.c
index e65a49f246ef..390a296b16a3 100644
--- a/arch/powerpc/mm/fault.c
+++ b/arch/powerpc/mm/fault.c
@@ -549,11 +549,12 @@ static int __do_page_fault(struct pt_regs *regs, unsigned 
long address,
   }
   NOKPROBE_SYMBOL(__do_page_fault);
   
-int do_page_fault(struct pt_regs *regs, unsigned long address,

- unsigned long error_code)
+long do_page_fault(struct pt_regs *regs)
   {
enum ctx_state prev_state = exception_enter();
-   int err;
+   unsigned long address = regs->dar;
+   unsigned long error_code = regs->dsisr;
+   long err;


By doing something more or less like this (need to be tuned for bookE as well):

+   int is_exec = TRAP(regs) == 0x400;
+   unsigned long address = is_exec ? regs->ssr0 : regs->dar;
+   unsigned long error_code = is_exec ? (regs->ssr1 & DSISR_SRR1_MATCH_32S) : 
regs->dsisr;


Ah, I didn't see that you saved these in srr0/1 already. Hmm, not in
pt_regs though. thread_struct (VMAP_STACK only)? exception_regs (booke
only)? Doesn't seem so easy.


Oops yes you are right, SRR0/SRR1 are not in pt_regs. And their validity in thread struct is rather 
short ... So forget my comment.


Christophe

Re: [PATCH V3] sched/rt, powerpc: Prepare for PREEMPT_RT

2020-11-10 Thread Christophe Leroy 




Le 10/11/2020 à 09:53, Wang Qing a écrit :

PREEMPT_RT is a separate preemption model, CONFIG_PREEMPT will
  be disabled when CONFIG_PREEMPT_RT is enabled,  so we need
to add CONFIG_PREEMPT_RT output to __die().

Signed-off-by: Wang Qing 


Reviewed-by: Christophe Leroy 



Changes in v3:
  - Fix typo issue.

Changes in v2:
  - Modify as Christophe suggested.
---
  arch/powerpc/kernel/traps.c | 3 ++-
  1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
index 5006dcb..dec7b81
--- a/arch/powerpc/kernel/traps.c
+++ b/arch/powerpc/kernel/traps.c
@@ -262,10 +262,11 @@ static int __die(const char *str, struct pt_regs *regs, 
long err)
  {
printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter);
  
-	printk("%s PAGE_SIZE=%luK%s%s%s%s%s%s %s\n",

+   printk("%s PAGE_SIZE=%luK%s%s%s%s%s%s%s %s\n",
   IS_ENABLED(CONFIG_CPU_LITTLE_ENDIAN) ? "LE" : "BE",
   PAGE_SIZE / 1024, get_mmu_str(),
   IS_ENABLED(CONFIG_PREEMPT) ? " PREEMPT" : "",
+  IS_ENABLED(CONFIG_PREEMPT_RT) ? " PREEMPT_RT" : "",
   IS_ENABLED(CONFIG_SMP) ? " SMP" : "",
   IS_ENABLED(CONFIG_SMP) ? (" NR_CPUS=" __stringify(NR_CPUS)) : "",
   debug_pagealloc_enabled() ? " DEBUG_PAGEALLOC" : "",

Re: [PATCH v7 4/4] arch, mm: make kernel_page_present() always available

2020-11-10 Thread David Hildenbrand 

On 09.11.20 20:21, Mike Rapoport wrote:

From: Mike Rapoport 

For architectures that enable ARCH_HAS_SET_MEMORY having the ability to
verify that a page is mapped in the kernel direct map can be useful
regardless of hibernation.

Add RISC-V implementation of kernel_page_present(), update its forward
declarations and stubs to be a part of set_memory API and remove ugly
ifdefery in inlcude/linux/mm.h around current declarations of
kernel_page_present().

Signed-off-by: Mike Rapoport 
Acked-by: Kirill A. Shutemov 



Acked-by: David Hildenbrand 

--
Thanks,

David / dhildenb

[PATCH V3] sched/rt, powerpc: Prepare for PREEMPT_RT

2020-11-10 Thread Wang Qing 
PREEMPT_RT is a separate preemption model, CONFIG_PREEMPT will
 be disabled when CONFIG_PREEMPT_RT is enabled,  so we need
to add CONFIG_PREEMPT_RT output to __die().

Signed-off-by: Wang Qing 

Changes in v3:
 - Fix typo issue.

Changes in v2:
 - Modify as Christophe suggested.
---
 arch/powerpc/kernel/traps.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
index 5006dcb..dec7b81
--- a/arch/powerpc/kernel/traps.c
+++ b/arch/powerpc/kernel/traps.c
@@ -262,10 +262,11 @@ static int __die(const char *str, struct pt_regs *regs, 
long err)
 {
printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter);
 
-   printk("%s PAGE_SIZE=%luK%s%s%s%s%s%s %s\n",
+   printk("%s PAGE_SIZE=%luK%s%s%s%s%s%s%s %s\n",
   IS_ENABLED(CONFIG_CPU_LITTLE_ENDIAN) ? "LE" : "BE",
   PAGE_SIZE / 1024, get_mmu_str(),
   IS_ENABLED(CONFIG_PREEMPT) ? " PREEMPT" : "",
+  IS_ENABLED(CONFIG_PREEMPT_RT) ? " PREEMPT_RT" : "",
   IS_ENABLED(CONFIG_SMP) ? " SMP" : "",
   IS_ENABLED(CONFIG_SMP) ? (" NR_CPUS=" __stringify(NR_CPUS)) : "",
   debug_pagealloc_enabled() ? " DEBUG_PAGEALLOC" : "",
-- 
2.7.4

Re: [RFC PATCH 0/9] powerpc/64s: fast interrupt exit

2020-11-10 Thread Nicholas Piggin 
Excerpts from Christophe Leroy's message of November 7, 2020 8:35 pm:
> 
> 
> Le 06/11/2020 à 16:59, Nicholas Piggin a écrit :
>> This series attempts to improve the speed of interrupts and system calls
>> in two major ways.
>> 
>> Firstly, the SRR/HSRR registers do not need to be reloaded if they were
>> not used or clobbered fur the duration of the interrupt.
>> 
>> Secondly, an alternate return location facility is added for soft-masked
>> asynchronous interrupts and then that's used to set everything up for
>> return without having to disable MSR RI or EE.
>> 
>> After this series, the entire system call / interrupt handler fast path
>> executes no mtsprs and one mtmsrd to enable interrupts initially, and
>> the system call vectored path doesn't even need to do that.
> 
> Interesting series.
> 
> Unfortunately, can't be done on PPC32 (at least on non bookE), because it 
> would mean mapping kernel 
> at 0 instead of 0xC000. Not sure libc would like it, and anyway it would 
> be an issue for 
> catching NULL pointer dereferencing, unless we use page tables instead of 
> BATs to map kernel mem, 
> which would be serious performance cut.

Hmm, why would you have to map at 0?

PPC32 doesn't have soft mask interrupts, but you could still test all 
MSR[PR]=0 interrupts to see if they land inside some region to see if
they hit in the restart table I think?

Could PPC32 skip the SRR reload at least? That's simpler.

Thanks,
Nick

Re: [PATCH RFC PKS/PMEM 05/58] kmap: Introduce k[un]map_thread

2020-11-10 Thread Thomas Gleixner 
On Mon, Nov 09 2020 at 20:59, Ira Weiny wrote:
> On Tue, Nov 10, 2020 at 02:13:56AM +0100, Thomas Gleixner wrote:
> Also, we can convert the new memcpy_*_page() calls to kmap_local() as well.
> [For now my patch just uses kmap_atomic().]
>
> I've not looked at all of the patches in your latest version.  Have you
> included converting any of the kmap() call sites?  I thought you were more
> focused on converting the kmap_atomic() to kmap_local()?

I did not touch any of those yet, but it's a logical consequence to
convert all kmap() instances which are _not_ creating a global mapping
over to it.

Thanks,

tglx

Re: [PATCH v2 1/3] powerpc/64s: Replace RFI by RFI_TO_KERNEL and remove RFI

2020-11-10 Thread Nicholas Piggin 
Excerpts from Christophe Leroy's message of November 9, 2020 2:57 am:
> In head_64.S, we have two places using RFI to return to
> kernel. Use RFI_TO_KERNEL instead.
> 
> They are the two only places using RFI on book3s/64, so
> the RFI macro can go away.

Looks good to me.

Acked-by: Nicholas Piggin 

> 
> Signed-off-by: Christophe Leroy 
> ---
>  arch/powerpc/include/asm/ppc_asm.h | 1 -
>  arch/powerpc/kernel/head_64.S  | 9 +++--
>  2 files changed, 7 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/powerpc/include/asm/ppc_asm.h 
> b/arch/powerpc/include/asm/ppc_asm.h
> index 511786f0e40d..bedf3eb52ebc 100644
> --- a/arch/powerpc/include/asm/ppc_asm.h
> +++ b/arch/powerpc/include/asm/ppc_asm.h
> @@ -495,7 +495,6 @@ END_FTR_SECTION_NESTED(CPU_FTR_CELL_TB_BUG, 
> CPU_FTR_CELL_TB_BUG, 96)
>  #endif
>  
>  #ifdef CONFIG_PPC_BOOK3S_64
> -#define RFI  rfid
>  #define MTMSRD(r)mtmsrd  r
>  #define MTMSR_EERI(reg)  mtmsrd  reg,1
>  #else
> diff --git a/arch/powerpc/kernel/head_64.S b/arch/powerpc/kernel/head_64.S
> index 1510b2a56669..ecf9a88988ff 100644
> --- a/arch/powerpc/kernel/head_64.S
> +++ b/arch/powerpc/kernel/head_64.S
> @@ -41,6 +41,11 @@
>  #include 
>  #include 
>  #include 
> +#ifdef CONFIG_PPC_BOOK3S
> +#include 
> +#else
> +#include 
> +#endif
>  
>  /* The physical memory is laid out such that the secondary processor
>   * spin code sits at 0x...0x00ff. On server, the vectors follow
> @@ -829,7 +834,7 @@ __secondary_start:
>  
>   mtspr   SPRN_SRR0,r3
>   mtspr   SPRN_SRR1,r4
> - RFI
> + RFI_TO_KERNEL
>   b   .   /* prevent speculative execution */
>  
>  /* 
> @@ -966,7 +971,7 @@ start_here_multiplatform:
>   ld  r4,PACAKMSR(r13)
>   mtspr   SPRN_SRR0,r3
>   mtspr   SPRN_SRR1,r4
> - RFI
> + RFI_TO_KERNEL
>   b   .   /* prevent speculative execution */
>  
>   /* This is where all platforms converge execution */
> -- 
> 2.25.0
> 
>

Re: [PATCH 18/18] powerpc/64s: move power4 idle entirely to C

2020-11-10 Thread Nicholas Piggin 
Excerpts from Christophe Leroy's message of November 7, 2020 7:43 pm:
> 
> 
> Le 05/11/2020 à 15:34, Nicholas Piggin a écrit :
>> Christophe asked about doing this, most of the code is still in
>> asm but maybe it's slightly nicer? I don't know if it's worthwhile.
> 
> Heu... I don't think I was asking for that, but why not, see later comments.
> 
> At first I was just asking to write the following in C:
> 
> +
> + .globl power4_idle_nap_return
> +power4_idle_nap_return:
> + blr
> 
> 
> In extenso, instead of the above do somewhere something like:
> 
> void power4_idle_nap_return(void)
> {
> }

Ah! Well either was a good question. I don't mind attempting it :)

>> ---
>>   arch/powerpc/kernel/idle.c| 25 -
>>   arch/powerpc/kernel/idle_book3s.S | 22 --
>>   2 files changed, 20 insertions(+), 27 deletions(-)
>> 
>> diff --git a/arch/powerpc/kernel/idle.c b/arch/powerpc/kernel/idle.c
>> index ae0e2632393d..849e77a45915 100644
>> --- a/arch/powerpc/kernel/idle.c
>> +++ b/arch/powerpc/kernel/idle.c
>> @@ -72,6 +72,9 @@ int powersave_nap;
>>   #ifdef CONFIG_PPC_970_NAP
>>   void power4_idle(void)
>>   {
>> +unsigned long msr_idle = MSR_KERNEL|MSR_EE|MSR_POW;
>> +unsigned long tmp1, tmp2;
>> +
>>  if (!cpu_has_feature(CPU_FTR_CAN_NAP))
>>  return;
>>   
>> @@ -84,13 +87,25 @@ void power4_idle(void)
>>  if (cpu_has_feature(CPU_FTR_ALTIVEC))
>>  asm volatile("DSSALL ; sync" ::: "memory");
>>   
>> -power4_idle_nap();
>> -
>> +asm volatile(
>> +"   ld  %0,PACA_THREAD_INFO(r13)\n"
>> +"   ld  %1,TI_LOCAL_FLAGS(%0)   \n"
>> +"   ori %1,%1,_TLF_NAPPING  \n"
>> +"   std %1,TI_LOCAL_FLAGS(%0)   \n"
> 
> Can't this just be:
> 
>   current_thread_info()->local_flags |= _TLF_NAPPING;
> 
>>  /*
>> - * power4_idle_nap returns with interrupts enabled (soft and hard).
>> - * to our caller with interrupts enabled (soft and hard). Our caller
>> - * can cope with either interrupts disabled or enabled upon return.
>> + * NAPPING bit is set, from this point onward nap_adjust_return()
>> + * will cause interrupts to return to power4_idle_nap_return.
>>   */
>> +"1: sync\n"
>> +"   isync   \n"
>> +"   mtmsrd  %2  \n"
>> +"   isync   \n"
>> +"   b   1b  \n"
> 
> And this:
> 
>   for (;;) {
>   mb();
>   isync();
>   mtmsr(MSR_KERNEL|MSR_EE|MSR_POW);
>   isync();
>   }

I was hoping something nicer like this but I think not because as soon 
as we set _TLF_NAPPING, we might take an interrupt which returns 
somewhere else, and you aren't allowed to do that in C code (mainly 
because the stack and register state would be unknown). Even going 
immediately to blr or end of function might miss restoring NVGPRs etc.

There might be some tricks we could play with soft-masking interrupts, 
using MSR[EE]=0, and then doing all this and returning to right after 
the mtmsr POW with a flag set...  But it's a bit of tricky churn for an 
old CPU that works okay.

Thanks,
Nick

> 
> 
>> +"   .globl power4_idle_nap_return   \n"
>> +"power4_idle_nap_return:\n"
>> +: "=r"(tmp1), "=r"(tmp2)
>> +: "r"(msr_idle)
>> +);
>>   }
>>   #endif
>>   
> 
> Christophe
>

Re: [PATCH 03/18] powerpc: bad_page_fault, do_break get registers from regs

2020-11-10 Thread Nicholas Piggin 
Excerpts from Christophe Leroy's message of November 6, 2020 6:14 pm:
> 
> 
> Le 05/11/2020 à 15:34, Nicholas Piggin a écrit :
>> This also moves the 32s DABR match to C.
> 
> Is there a real benefit doing this ?

Oh I missed doing it, but yes I think bad_page_fault and do_break should
probably be implemented with the DEFINE_INTERRUT_HANDLER wrappers.

Thanks,
Nick

Re: [PATCH 02/18] powerpc: remove arguments from fault handler functions

2020-11-10 Thread Nicholas Piggin 
Excerpts from Christophe Leroy's message of November 6, 2020 5:59 pm:
> 
> 
> Le 05/11/2020 à 15:34, Nicholas Piggin a écrit :
>> Make mm fault handlers all just take the pt_regs * argument and load
>> DAR/DSISR from that. Make those that return a value return long.
>> 
>> This is done to make the function signatures match other handlers, which
>> will help with a future patch to add wrappers. Explicit arguments could
>> be added for performance but that would require more wrapper macro
>> variants.
>> 
>> Signed-off-by: Nicholas Piggin 
>> ---
>>   arch/powerpc/include/asm/asm-prototypes.h |  4 ++--
>>   arch/powerpc/include/asm/bug.h|  4 ++--
>>   arch/powerpc/kernel/exceptions-64e.S  |  2 --
>>   arch/powerpc/kernel/exceptions-64s.S  | 14 ++
>>   arch/powerpc/kernel/head_40x.S| 10 +-
>>   arch/powerpc/kernel/head_8xx.S|  6 +++---
>>   arch/powerpc/kernel/head_book3s_32.S  |  6 ++
>>   arch/powerpc/kernel/head_booke.h  |  4 +---
>>   arch/powerpc/mm/book3s64/hash_utils.c |  8 +---
>>   arch/powerpc/mm/book3s64/slb.c| 11 +++
>>   arch/powerpc/mm/fault.c   | 16 +---
>>   11 files changed, 38 insertions(+), 47 deletions(-)
>> 
>> diff --git a/arch/powerpc/include/asm/asm-prototypes.h 
>> b/arch/powerpc/include/asm/asm-prototypes.h
>> index d0b832cbbec8..22c9d08fa3a4 100644
>> --- a/arch/powerpc/include/asm/asm-prototypes.h
>> +++ b/arch/powerpc/include/asm/asm-prototypes.h
>> @@ -82,8 +82,8 @@ void kernel_bad_stack(struct pt_regs *regs);
>>   void system_reset_exception(struct pt_regs *regs);
>>   void machine_check_exception(struct pt_regs *regs);
>>   void emulation_assist_interrupt(struct pt_regs *regs);
>> -long do_slb_fault(struct pt_regs *regs, unsigned long ea);
>> -void do_bad_slb_fault(struct pt_regs *regs, unsigned long ea, long err);
>> +long do_slb_fault(struct pt_regs *regs);
>> +void do_bad_slb_fault(struct pt_regs *regs);
>>   
>>   /* signals, syscalls and interrupts */
>>   long sys_swapcontext(struct ucontext __user *old_ctx,
>> diff --git a/arch/powerpc/include/asm/bug.h b/arch/powerpc/include/asm/bug.h
>> index d714d83bbc7c..2fa0cf6c6011 100644
>> --- a/arch/powerpc/include/asm/bug.h
>> +++ b/arch/powerpc/include/asm/bug.h
>> @@ -111,8 +111,8 @@
>>   #ifndef __ASSEMBLY__
>>   
>>   struct pt_regs;
>> -extern int do_page_fault(struct pt_regs *, unsigned long, unsigned long);
>> -extern int hash__do_page_fault(struct pt_regs *, unsigned long, unsigned 
>> long);
>> +extern long do_page_fault(struct pt_regs *);
>> +extern long hash__do_page_fault(struct pt_regs *);
> 
> extern is pointless

Thanks. Sorry I'll get it right one day.

>> @@ -191,9 +191,9 @@ _ENTRY(saved_ksp_limit)
>>*/
>>  START_EXCEPTION(0x0400, InstructionAccess)
>>  EXCEPTION_PROLOG
>> -mr  r4,r12  /* Pass SRR0 as arg2 */
>> -stw r4, _DEAR(r11)
>> -li  r5,0/* Pass zero as arg3 */
>> +li  r5,0
>> +stw r5, _ESR(r11)   /* Zero ESR */
>> +stw r12, _DEAR(r11) /* SRR0 as DEAR */
> 
> I think we should avoid this, see below
> 
>> @@ -356,14 +356,14 @@ DataStoreTLBMiss:
>>  . = 0x1300
>>   InstructionTLBError:
>>  EXCEPTION_PROLOG
>> -mr  r4,r12
>>  andis.  r5,r9,DSISR_SRR1_MATCH_32S@h /* Filter relevant SRR1 bits */
> 
> Could avoid this, see below
> 
>>  andis.  r10,r9,SRR1_ISI_NOPT@h
>>  beq+.Litlbie
>> -tlbie   r4
>> +tlbie   r12
>>  /* 0x400 is InstructionAccess exception, needed by bad_page_fault() */
>>   .Litlbie:
>> -stw r4, _DAR(r11)
>> +stw r12, _DAR(r11)
>> +stw r5, _DSISR(r11)
> 
> And this

>> @@ -369,9 +369,9 @@ BEGIN_MMU_FTR_SECTION
>>  bl  hash_page
>>   END_MMU_FTR_SECTION_IFSET(MMU_FTR_HPTE_TABLE)
>>   #endif /* CONFIG_VMAP_STACK */
>> -1:  mr  r4,r12
>>  andis.  r5,r9,DSISR_SRR1_MATCH_32S@h /* Filter relevant SRR1 bits */
>> -stw r4, _DAR(r11)
>> +stw r5, _DSISR(r11)
>> +stw r12, _DAR(r11)
> 
> And this including the andis.
> 

>> @@ -477,9 +477,7 @@ ALT_FTR_SECTION_END_IFSET(CPU_FTR_EMB_HV)
>>  NORMAL_EXCEPTION_PROLOG(INST_STORAGE);\
>>  mfspr   r5,SPRN_ESR;/* Grab the ESR and save it */\
>>  stw r5,_ESR(r11); \
>> -mr  r4,r12; /* Pass SRR0 as arg2 */   \
>> -stw r4, _DEAR(r11);   \
>> -li  r5,0;   /* Pass zero as arg3 */   \
>> +stw r12, _DEAR(r11);/* Pass SRR0 as arg2 */   \
> 
> And this
> 

[...]

>> diff --git a/arch/powerpc/mm/fault.c b/arch/powerpc/mm/fault.c
>> index e65a49f246ef..390a296b16a3 100644
>> --- a/arch/powerpc/mm/fault.c
>> +++ b/arch/powerpc/mm/fault.c
>> @@ -549,11 +549,12 @@ static int

Re: [PATCH] powerpc: add compile-time support for lbarx, lwarx

2020-11-10 Thread Nicholas Piggin 
Excerpts from Christophe Leroy's message of November 7, 2020 6:15 pm:
> 
> 
> Le 07/11/2020 à 04:23, Nicholas Piggin a écrit :
>> ISA v2.06 (POWER7 and up) as well as e6500 support lbarx and lwarx.
>> Add a compile option that allows code to use it, and add support in
>> cmpxchg and xchg 8 and 16 bit values.
> 
> Do you mean lharx ? Because lwarx exists on all powerpcs I think.

Thanks all who pointed out mistakes :) Yes lharx.

> 
>> 
>> Signed-off-by: Nicholas Piggin 
>> ---
>>   arch/powerpc/Kconfig   |   3 +
>>   arch/powerpc/include/asm/cmpxchg.h | 236 -
>>   arch/powerpc/platforms/Kconfig.cputype |   5 +
>>   3 files changed, 243 insertions(+), 1 deletion(-)
>> 
>> diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
>> index e9f13fe08492..d231af06f75a 100644
>> --- a/arch/powerpc/Kconfig
>> +++ b/arch/powerpc/Kconfig
>> @@ -266,6 +266,9 @@ config PPC_BARRIER_NOSPEC
>>  default y
>>  depends on PPC_BOOK3S_64 || PPC_FSL_BOOK3E
>>   
>> +config PPC_LBARX_LWARX
>> +bool
> 
> s/LWARX/LHARX/ ?
> 
> And maybe better with PPC_HAS_LBARX_LWARX ?

Yes you're right, PPC_HAS_ fits better.

[...]

>> +#endif
> 
> That's a lot of code duplication. Could we use some macro, in the same spirit 
> as what is done in 
> arch/powerpc/include/asm/io.h for in_be16(), in_be32(), in_be64() and friends 
> ?

For now I don't get too fancy. It's a bit ugly but I'm working through a 
generic atomics conversion patch and trying to also work out a nice form
for larx/stcx operation generation macros, I'll look at tidying up this
some time after then.

Thanks,
Nick

Re: [PATCH V2] sched/rt, powerpc: Prepare for PREEMPT_RT

2020-11-10 Thread Greg Kroah-Hartman 
On Tue, Nov 10, 2020 at 04:02:47PM +0800, Wang Qing wrote:
> PREEMPT_RT is a separate preemption model, CONFIG_PRTTMPT will

Minor typo on this line with your config option :(

[PATCH V2] sched/rt, powerpc: Prepare for PREEMPT_RT

2020-11-10 Thread Wang Qing 
PREEMPT_RT is a separate preemption model, CONFIG_PRTTMPT will
 be disabled when CONFIG_PREEMPT_RT is enabled,  so you need
to add CONFIG_PREEMPT_RT judgments to __die().

Signed-off-by: Wang Qing 

Changes in v2:
 - Modify as Christophe suggested.
---
 arch/powerpc/kernel/traps.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
index 5006dcb..dec7b81
--- a/arch/powerpc/kernel/traps.c
+++ b/arch/powerpc/kernel/traps.c
@@ -262,10 +262,11 @@ static int __die(const char *str, struct pt_regs *regs, 
long err)
 {
printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter);
 
-   printk("%s PAGE_SIZE=%luK%s%s%s%s%s%s %s\n",
+   printk("%s PAGE_SIZE=%luK%s%s%s%s%s%s%s %s\n",
   IS_ENABLED(CONFIG_CPU_LITTLE_ENDIAN) ? "LE" : "BE",
   PAGE_SIZE / 1024, get_mmu_str(),
   IS_ENABLED(CONFIG_PREEMPT) ? " PREEMPT" : "",
+  IS_ENABLED(CONFIG_PREEMPT_RT) ? " PREEMPT_RT" : "",
   IS_ENABLED(CONFIG_SMP) ? " SMP" : "",
   IS_ENABLED(CONFIG_SMP) ? (" NR_CPUS=" __stringify(NR_CPUS)) : "",
   debug_pagealloc_enabled() ? " DEBUG_PAGEALLOC" : "",
-- 
2.7.4

Re: [PATCH V2] sched/rt, powerpc: Prepare for PREEMPT_RT

2020-11-10 Thread Christophe Leroy 




Le 10/11/2020 à 09:02, Wang Qing a écrit :

PREEMPT_RT is a separate preemption model, CONFIG_PRTTMPT will


s/CONFIG_PRTTMPT/CONFIG_PREEMPT


  be disabled when CONFIG_PREEMPT_RT is enabled,  so you need
to add CONFIG_PREEMPT_RT judgments to __die().

Signed-off-by: Wang Qing 


Otherwise

Reviewed-by: Christophe Leroy 



Changes in v2:
  - Modify as Christophe suggested.
---
  arch/powerpc/kernel/traps.c | 3 ++-
  1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
index 5006dcb..dec7b81
--- a/arch/powerpc/kernel/traps.c
+++ b/arch/powerpc/kernel/traps.c
@@ -262,10 +262,11 @@ static int __die(const char *str, struct pt_regs *regs, 
long err)
  {
printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter);
  
-	printk("%s PAGE_SIZE=%luK%s%s%s%s%s%s %s\n",

+   printk("%s PAGE_SIZE=%luK%s%s%s%s%s%s%s %s\n",
   IS_ENABLED(CONFIG_CPU_LITTLE_ENDIAN) ? "LE" : "BE",
   PAGE_SIZE / 1024, get_mmu_str(),
   IS_ENABLED(CONFIG_PREEMPT) ? " PREEMPT" : "",
+  IS_ENABLED(CONFIG_PREEMPT_RT) ? " PREEMPT_RT" : "",
   IS_ENABLED(CONFIG_SMP) ? " SMP" : "",
   IS_ENABLED(CONFIG_SMP) ? (" NR_CPUS=" __stringify(NR_CPUS)) : "",
   debug_pagealloc_enabled() ? " DEBUG_PAGEALLOC" : "",