date:20201124

Re: [PATCH 1/2] genirq: add an affinity parameter to irq_create_mapping()

2020-11-24 Thread Laurent Vivier

On 24/11/2020 23:19, Thomas Gleixner wrote:
> On Tue, Nov 24 2020 at 21:03, Laurent Vivier wrote:
>> This parameter is needed to pass it to irq_domain_alloc_descs().
>>
>> This seems to have been missed by
>> o06ee6d571f0e ("genirq: Add affinity hint to irq allocation")
> 
> No, this has not been missed at all. There was and is no reason to do
> this.
> 
>> This is needed to implement proper support for multiqueue with
>> pseries.
> 
> And because pseries needs this _all_ callers need to be changed?
> 
>>  123 files changed, 171 insertions(+), 146 deletions(-)
> 
> Lots of churn for nothing. 99% of the callers will never need that.
> 
> What's wrong with simply adding an interface which takes that parameter,
> make the existing one an inline wrapper and and leave the rest alone?

Nothing. I'm going to do like that.

Thank you for your comment.

Laurent

[PATCH V2] powerpc/perf: Exclude kernel samples while counting events in user space.

2020-11-24 Thread Athira Rajeev

Perf event attritube supports exclude_kernel flag
to avoid sampling/profiling in supervisor state (kernel).
Based on this event attr flag, Monitor Mode Control Register
bit is set to freeze on supervisor state. But sometime (due
to hardware limitation), Sampled Instruction Address
Register (SIAR) locks on to kernel address even when
freeze on supervisor is set. Patch here adds a check to
drop those samples.

Signed-off-by: Athira Rajeev 
---
Changes in v2:
- Initial patch was sent along with series:
  https://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=209195
  Moving this patch as separate since this change is applicable
  for all PMU platforms.

 arch/powerpc/perf/core-book3s.c | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c
index 08643cb..40aa117 100644
--- a/arch/powerpc/perf/core-book3s.c
+++ b/arch/powerpc/perf/core-book3s.c
@@ -2122,6 +2122,17 @@ static void record_and_restart(struct perf_event *event, 
unsigned long val,
perf_event_update_userpage(event);
 
/*
+* Due to hardware limitation, sometimes SIAR could
+* lock on to kernel address even with freeze on
+* supervisor state (kernel) is set in MMCR2.
+* Check attr.exclude_kernel and address
+* to drop the sample in these cases.
+*/
+   if (event->attr.exclude_kernel && record)
+   if (is_kernel_addr(mfspr(SPRN_SIAR)))
+   record = 0;
+
+   /*
 * Finally record data if requested.
 */
if (record) {
-- 
1.8.3.1

Re: [PATCH v4] dt-bindings: misc: convert fsl,qoriq-mc from txt to YAML

2020-11-24 Thread Ioana Ciornei

On Mon, Nov 23, 2020 at 11:00:35AM +0200, Laurentiu Tudor wrote:
> From: Ionut-robert Aron 
> 
> Convert fsl,qoriq-mc to YAML in order to automate the verification
> process of dts files. In addition, update MAINTAINERS accordingly
> and, while at it, add some missing files.
> 
> Signed-off-by: Ionut-robert Aron 
> [laurentiu.tu...@nxp.com: update MINTAINERS, updates & fixes in schema]
> Signed-off-by: Laurentiu Tudor 

Acked-by: Ioana Ciornei 


> ---
> Changes in v4:
>  - use $ref to point to fsl,qoriq-mc-dpmac binding
> 
> Changes in v3:
>  - dropped duplicated "fsl,qoriq-mc-dpmac" schema and replaced with
>reference to it
>  - fixed a dt_binding_check warning
> 
> Changes in v2:
>  - fixed errors reported by yamllint
>  - dropped multiple unnecessary quotes
>  - used schema instead of text in description
>  - added constraints on dpmac reg property
> 
>  .../devicetree/bindings/misc/fsl,qoriq-mc.txt | 196 --
>  .../bindings/misc/fsl,qoriq-mc.yaml   | 186 +
>  .../ethernet/freescale/dpaa2/overview.rst |   5 +-
>  MAINTAINERS   |   4 +-
>  4 files changed, 193 insertions(+), 198 deletions(-)
>  delete mode 100644 Documentation/devicetree/bindings/misc/fsl,qoriq-mc.txt
>  create mode 100644 Documentation/devicetree/bindings/misc/fsl,qoriq-mc.yaml
> 
> diff --git a/Documentation/devicetree/bindings/misc/fsl,qoriq-mc.txt 
> b/Documentation/devicetree/bindings/misc/fsl,qoriq-mc.txt
> deleted file mode 100644
> index 7b486d4985dc..
> --- a/Documentation/devicetree/bindings/misc/fsl,qoriq-mc.txt
> +++ /dev/null
> @@ -1,196 +0,0 @@
> -* Freescale Management Complex
> -
> -The Freescale Management Complex (fsl-mc) is a hardware resource
> -manager that manages specialized hardware objects used in
> -network-oriented packet processing applications. After the fsl-mc
> -block is enabled, pools of hardware resources are available, such as
> -queues, buffer pools, I/O interfaces. These resources are building
> -blocks that can be used to create functional hardware objects/devices
> -such as network interfaces, crypto accelerator instances, L2 switches,
> -etc.
> -
> -For an overview of the DPAA2 architecture and fsl-mc bus see:
> -Documentation/networking/device_drivers/ethernet/freescale/dpaa2/overview.rst
> -
> -As described in the above overview, all DPAA2 objects in a DPRC share the
> -same hardware "isolation context" and a 10-bit value called an ICID
> -(isolation context id) is expressed by the hardware to identify
> -the requester.
> -
> -The generic 'iommus' property is insufficient to describe the relationship
> -between ICIDs and IOMMUs, so an iommu-map property is used to define
> -the set of possible ICIDs under a root DPRC and how they map to
> -an IOMMU.
> -
> -For generic IOMMU bindings, see
> -Documentation/devicetree/bindings/iommu/iommu.txt.
> -
> -For arm-smmu binding, see:
> -Documentation/devicetree/bindings/iommu/arm,smmu.yaml.
> -
> -The MSI writes are accompanied by sideband data which is derived from the 
> ICID.
> -The msi-map property is used to associate the devices with both the ITS
> -controller and the sideband data which accompanies the writes.
> -
> -For generic MSI bindings, see
> -Documentation/devicetree/bindings/interrupt-controller/msi.txt.
> -
> -For GICv3 and GIC ITS bindings, see:
> -Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml.
> -
> -Required properties:
> -
> -- compatible
> -Value type: 
> -Definition: Must be "fsl,qoriq-mc".  A Freescale Management Complex
> -compatible with this binding must have Block Revision
> -Registers BRR1 and BRR2 at offset 0x0BF8 and 0x0BFC in
> -the MC control register region.
> -
> -- reg
> -Value type: 
> -Definition: A standard property.  Specifies one or two regions
> -defining the MC's registers:
> -
> -   -the first region is the command portal for the
> -this machine and must always be present
> -
> -   -the second region is the MC control registers. This
> -region may not be present in some scenarios, such
> -as in the device tree presented to a virtual machine.
> -
> -- ranges
> -Value type: 
> -Definition: A standard property.  Defines the mapping between the 
> child
> -MC address space and the parent system address space.
> -
> -The MC address space is defined by 3 components:
> - 
> -
> -Valid values for region type are
> -   0x0 - MC portals
> -   0x1 - QBMAN portals
> -
> -- #address-cells
> -Value type: 
> -Definition: Must be 3.  (see definition in 'ranges' property)
> -
> -- #size-cells
> -Value type: 
> -

[PATCH v1 8/8] powerpc/32: Use SPRN_SPRG_SCRATCH2 in exception prologs

2020-11-24 Thread Christophe Leroy

Use SPRN_SPRG_SCRATCH2 as a third scratch register in
exception prologs in order to simplify them and avoid
data going back and forth from/to CR.

Signed-off-by: Christophe Leroy 
---
 arch/powerpc/kernel/head_32.h | 22 +++---
 1 file changed, 7 insertions(+), 15 deletions(-)

diff --git a/arch/powerpc/kernel/head_32.h b/arch/powerpc/kernel/head_32.h
index 5e3393122d29..a1ee1e12241e 100644
--- a/arch/powerpc/kernel/head_32.h
+++ b/arch/powerpc/kernel/head_32.h
@@ -40,7 +40,7 @@
 
 .macro EXCEPTION_PROLOG_1 for_rtas=0
 #ifdef CONFIG_VMAP_STACK
-   mr  r11, r1
+   mtspr   SPRN_SPRG_SCRATCH2,r1
subir1, r1, INT_FRAME_SIZE  /* use r1 if kernel */
beq 1f
mfspr   r1,SPRN_SPRG_THREAD
@@ -61,15 +61,10 @@
 
 .macro EXCEPTION_PROLOG_2 handle_dar_dsisr=0
 #ifdef CONFIG_VMAP_STACK
-   mtcrr10
-   li  r10, MSR_KERNEL & ~(MSR_IR | MSR_RI) /* can take DTLB miss */
-   mtmsr   r10
+   li  r11, MSR_KERNEL & ~(MSR_IR | MSR_RI) /* can take DTLB miss */
+   mtmsr   r11
isync
-#else
-   stw r10,_CCR(r11)   /* save registers */
-#endif
-   mfspr   r10, SPRN_SPRG_SCRATCH0
-#ifdef CONFIG_VMAP_STACK
+   mfspr   r11, SPRN_SPRG_SCRATCH2
stw r11,GPR1(r1)
stw r11,0(r1)
mr  r11, r1
@@ -78,14 +73,12 @@
stw r1,0(r11)
tovirt(r1, r11) /* set new kernel sp */
 #endif
+   stw r10,_CCR(r11)   /* save registers */
stw r12,GPR12(r11)
stw r9,GPR9(r11)
-   stw r10,GPR10(r11)
-#ifdef CONFIG_VMAP_STACK
-   mfcrr10
-   stw r10, _CCR(r11)
-#endif
+   mfspr   r10,SPRN_SPRG_SCRATCH0
mfspr   r12,SPRN_SPRG_SCRATCH1
+   stw r10,GPR10(r11)
stw r12,GPR11(r11)
mflrr10
stw r10,_LINK(r11)
@@ -99,7 +92,6 @@
stw r10, _DSISR(r11)
.endif
lwz r9, SRR1(r12)
-   andi.   r10, r9, MSR_PR
lwz r12, SRR0(r12)
 #else
mfspr   r12,SPRN_SRR0
-- 
2.25.0

[PATCH v1 7/8] powerpc/32s: Use SPRN_SPRG_SCRATCH2 in DSI prolog

2020-11-24 Thread Christophe Leroy

Use SPRN_SPRG_SCRATCH2 as an alternative scratch register in
the early part of DSI prolog in order to avoid clobbering
SPRN_SPRG_SCRATCH0/1 used by other prologs.

The 603 doesn't like a jump from DataLoadTLBMiss to the 10 nops
that are now in the beginning of DSI exception as a result of
the feature section. To workaround this, add a jump as alternative.
It also avoids fetching 10 nops for nothing.

Signed-off-by: Christophe Leroy 
---
 arch/powerpc/include/asm/reg.h   |  1 +
 arch/powerpc/kernel/head_book3s_32.S | 24 
 2 files changed, 9 insertions(+), 16 deletions(-)

diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index a37ce826f6f6..acd334ee3936 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -1203,6 +1203,7 @@
 #ifdef CONFIG_PPC_BOOK3S_32
 #define SPRN_SPRG_SCRATCH0 SPRN_SPRG0
 #define SPRN_SPRG_SCRATCH1 SPRN_SPRG1
+#define SPRN_SPRG_SCRATCH2 SPRN_SPRG2
 #define SPRN_SPRG_603_LRU  SPRN_SPRG4
 #endif
 
diff --git a/arch/powerpc/kernel/head_book3s_32.S 
b/arch/powerpc/kernel/head_book3s_32.S
index 51eef7b82f9c..22d670263222 100644
--- a/arch/powerpc/kernel/head_book3s_32.S
+++ b/arch/powerpc/kernel/head_book3s_32.S
@@ -288,9 +288,9 @@ MachineCheck:
DO_KVM  0x300
 DataAccess:
 #ifdef CONFIG_VMAP_STACK
-   mtspr   SPRN_SPRG_SCRATCH0,r10
-   mfspr   r10, SPRN_SPRG_THREAD
 BEGIN_MMU_FTR_SECTION
+   mtspr   SPRN_SPRG_SCRATCH2,r10
+   mfspr   r10, SPRN_SPRG_THREAD
stw r11, THR11(r10)
mfspr   r10, SPRN_DSISR
mfcrr11
@@ -304,19 +304,11 @@ BEGIN_MMU_FTR_SECTION
 .Lhash_page_dsi_cont:
mtcrr11
lwz r11, THR11(r10)
-END_MMU_FTR_SECTION_IFSET(MMU_FTR_HPTE_TABLE)
-   mtspr   SPRN_SPRG_SCRATCH1,r11
-   mfspr   r11, SPRN_DAR
-   stw r11, DAR(r10)
-   mfspr   r11, SPRN_DSISR
-   stw r11, DSISR(r10)
-   mfspr   r11, SPRN_SRR0
-   stw r11, SRR0(r10)
-   mfspr   r11, SPRN_SRR1  /* check whether user or kernel */
-   stw r11, SRR1(r10)
-   mfcrr10
-   andi.   r11, r11, MSR_PR
-
+   mfspr   r10, SPRN_SPRG_SCRATCH2
+MMU_FTR_SECTION_ELSE
+   b   1f
+ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_HPTE_TABLE)
+1: EXCEPTION_PROLOG_0 handle_dar_dsisr=1
EXCEPTION_PROLOG_1
b   handle_page_fault_tramp_1
 #else  /* CONFIG_VMAP_STACK */
@@ -760,7 +752,7 @@ fast_hash_page_return:
/* DSI */
mtcrr11
lwz r11, THR11(r10)
-   mfspr   r10, SPRN_SPRG_SCRATCH0
+   mfspr   r10, SPRN_SPRG_SCRATCH2
RFI
 
 1: /* ISI */
-- 
2.25.0

[PATCH v1 6/8] powerpc/32: Simplify EXCEPTION_PROLOG_1 macro

2020-11-24 Thread Christophe Leroy

Make code more readable with a clear CONFIG_VMAP_STACK
section and a clear non CONFIG_VMAP_STACK section.

Signed-off-by: Christophe Leroy 
---
 arch/powerpc/kernel/head_32.h | 10 --
 1 file changed, 4 insertions(+), 6 deletions(-)

diff --git a/arch/powerpc/kernel/head_32.h b/arch/powerpc/kernel/head_32.h
index 7c767765071d..5e3393122d29 100644
--- a/arch/powerpc/kernel/head_32.h
+++ b/arch/powerpc/kernel/head_32.h
@@ -46,18 +46,16 @@
mfspr   r1,SPRN_SPRG_THREAD
lwz r1,TASK_STACK-THREAD(r1)
addir1, r1, THREAD_SIZE - INT_FRAME_SIZE
+1:
+   mtcrf   0x7f, r1
+   bt  32 - THREAD_ALIGN_SHIFT, stack_overflow
 #else
subir11, r1, INT_FRAME_SIZE /* use r1 if kernel */
beq 1f
mfspr   r11,SPRN_SPRG_THREAD
lwz r11,TASK_STACK-THREAD(r11)
addir11, r11, THREAD_SIZE - INT_FRAME_SIZE
-#endif
-1:
-   tophys_novmstack r11, r11
-#ifdef CONFIG_VMAP_STACK
-   mtcrf   0x7f, r1
-   bt  32 - THREAD_ALIGN_SHIFT, stack_overflow
+1: tophys(r11, r11)
 #endif
 .endm
 
-- 
2.25.0

[PATCH v1 5/8] powerpc/603: Use SPRN_SDR1 to store the pgdir phys address

2020-11-24 Thread Christophe Leroy

On the 603, SDR1 is not used.

In order to free SPRN_SPRG2, use SPRN_SDR1 to store the pgdir
phys addr.

But only some bits of SDR1 can be used (0x01ff).
As the pgdir is 4k aligned, rotate it by 4 bits to the left.

Signed-off-by: Christophe Leroy 
---
 arch/powerpc/include/asm/reg.h   |  1 -
 arch/powerpc/kernel/head_book3s_32.S | 31 +---
 2 files changed, 24 insertions(+), 8 deletions(-)

diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index f877a576b338..a37ce826f6f6 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -1203,7 +1203,6 @@
 #ifdef CONFIG_PPC_BOOK3S_32
 #define SPRN_SPRG_SCRATCH0 SPRN_SPRG0
 #define SPRN_SPRG_SCRATCH1 SPRN_SPRG1
-#define SPRN_SPRG_PGDIRSPRN_SPRG2
 #define SPRN_SPRG_603_LRU  SPRN_SPRG4
 #endif
 
diff --git a/arch/powerpc/kernel/head_book3s_32.S 
b/arch/powerpc/kernel/head_book3s_32.S
index 236a95d163be..51eef7b82f9c 100644
--- a/arch/powerpc/kernel/head_book3s_32.S
+++ b/arch/powerpc/kernel/head_book3s_32.S
@@ -457,8 +457,9 @@ InstructionTLBMiss:
lis r1, TASK_SIZE@h /* check if kernel address */
cmplw   0,r1,r3
 #endif
-   mfspr   r2, SPRN_SPRG_PGDIR
+   mfspr   r2, SPRN_SDR1
li  r1,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
+   rlwinm  r2, r2, 28, 0xf000
 #ifdef CONFIG_MODULES
bgt-112f
lis r2, (swapper_pg_dir - PAGE_OFFSET)@ha   /* if kernel address, 
use */
@@ -519,8 +520,9 @@ DataLoadTLBMiss:
mfspr   r3,SPRN_DMISS
lis r1, TASK_SIZE@h /* check if kernel address */
cmplw   0,r1,r3
-   mfspr   r2, SPRN_SPRG_PGDIR
+   mfspr   r2, SPRN_SDR1
li  r1, _PAGE_PRESENT | _PAGE_ACCESSED
+   rlwinm  r2, r2, 28, 0xf000
bgt-112f
lis r2, (swapper_pg_dir - PAGE_OFFSET)@ha   /* if kernel address, 
use */
addir2, r2, (swapper_pg_dir - PAGE_OFFSET)@l/* kernel page 
table */
@@ -595,8 +597,9 @@ DataStoreTLBMiss:
mfspr   r3,SPRN_DMISS
lis r1, TASK_SIZE@h /* check if kernel address */
cmplw   0,r1,r3
-   mfspr   r2, SPRN_SPRG_PGDIR
+   mfspr   r2, SPRN_SDR1
li  r1, _PAGE_RW | _PAGE_DIRTY | _PAGE_PRESENT | _PAGE_ACCESSED
+   rlwinm  r2, r2, 28, 0xf000
bgt-112f
lis r2, (swapper_pg_dir - PAGE_OFFSET)@ha   /* if kernel address, 
use */
addir2, r2, (swapper_pg_dir - PAGE_OFFSET)@l/* kernel page 
table */
@@ -889,9 +892,12 @@ __secondary_start:
tophys(r4,r2)
addir4,r4,THREAD/* phys address of our thread_struct */
mtspr   SPRN_SPRG_THREAD,r4
+BEGIN_MMU_FTR_SECTION
lis r4, (swapper_pg_dir - PAGE_OFFSET)@h
ori r4, r4, (swapper_pg_dir - PAGE_OFFSET)@l
-   mtspr   SPRN_SPRG_PGDIR, r4
+   rlwinm  r4, r4, 4, 0x01ff
+   mtspr   SPRN_SDR1, r4
+END_MMU_FTR_SECTION_IFCLR(MMU_FTR_HPTE_TABLE)
 
/* enable MMU and jump to start_secondary */
li  r4,MSR_KERNEL
@@ -931,11 +937,13 @@ load_up_mmu:
tlbia   /* Clear all TLB entries */
sync/* wait for tlbia/tlbie to finish */
TLBSYNC /* ... on all CPUs */
+BEGIN_MMU_FTR_SECTION
/* Load the SDR1 register (hash table base & size) */
lis r6,_SDR1@ha
tophys(r6,r6)
lwz r6,_SDR1@l(r6)
mtspr   SPRN_SDR1,r6
+END_MMU_FTR_SECTION_IFSET(MMU_FTR_HPTE_TABLE)
 
 /* Load the BAT registers with the values set up by MMU_init. */
lis r3,BATS@ha
@@ -991,9 +999,12 @@ start_here:
tophys(r4,r2)
addir4,r4,THREAD/* init task's THREAD */
mtspr   SPRN_SPRG_THREAD,r4
+BEGIN_MMU_FTR_SECTION
lis r4, (swapper_pg_dir - PAGE_OFFSET)@h
ori r4, r4, (swapper_pg_dir - PAGE_OFFSET)@l
-   mtspr   SPRN_SPRG_PGDIR, r4
+   rlwinm  r4, r4, 4, 0x01ff
+   mtspr   SPRN_SDR1, r4
+END_MMU_FTR_SECTION_IFCLR(MMU_FTR_HPTE_TABLE)
 
/* stack */
lis r1,init_thread_union@ha
@@ -1073,16 +1084,22 @@ _ENTRY(switch_mmu_context)
li  r0,NUM_USER_SEGMENTS
mtctr   r0
 
-   lwz r4, MM_PGD(r4)
 #ifdef CONFIG_BDI_SWITCH
/* Context switch the PTE pointer for the Abatron BDI2000.
 * The PGDIR is passed as second argument.
 */
+   lwz r4, MM_PGD(r4)
lis r5, abatron_pteptrs@ha
stw r4, abatron_pteptrs@l + 0x4(r5)
+#endif
+BEGIN_MMU_FTR_SECTION
+#ifndef CONFIG_BDI_SWITCH
+   lwz r4, MM_PGD(r4)
 #endif
tophys(r4, r4)
-   mtspr   SPRN_SPRG_PGDIR, r4
+   rlwinm  r4, r4, 4, 0x01ff
+   mtspr   SPRN_SDR1, r4
+END_MMU_FTR_SECTION_IFCLR(MMU_FTR_HPTE_TABLE)
li  r4,0
isync
 3:
-- 
2.25.0

[PATCH v1 2/8] powerpc/32s: Don't hash_preload() kernel text

2020-11-24 Thread Christophe Leroy

We now always map kernel text with BATs. Neither need to preload
hash with kernel text addresses nor ensure they are never evicted.

This is more or less a revert of commit ee4f2ea48674 ("[POWERPC] Fix
32-bit mm operations when not using BATs")

Signed-off-by: Christophe Leroy 
---
 arch/powerpc/mm/book3s32/hash_low.S | 18 +-
 arch/powerpc/mm/book3s32/mmu.c  |  2 +-
 arch/powerpc/mm/mmu_decl.h  |  2 --
 arch/powerpc/mm/pgtable_32.c|  4 
 4 files changed, 2 insertions(+), 24 deletions(-)

diff --git a/arch/powerpc/mm/book3s32/hash_low.S 
b/arch/powerpc/mm/book3s32/hash_low.S
index b2c912e517b9..48415c857d80 100644
--- a/arch/powerpc/mm/book3s32/hash_low.S
+++ b/arch/powerpc/mm/book3s32/hash_low.S
@@ -411,30 +411,14 @@ END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
 * and we know there is a definite (although small) speed
 * advantage to putting the PTE in the primary PTEG, we always
 * put the PTE in the primary PTEG.
-*
-* In addition, we skip any slot that is mapping kernel text in
-* order to avoid a deadlock when not using BAT mappings if
-* trying to hash in the kernel hash code itself after it has
-* already taken the hash table lock. This works in conjunction
-* with pre-faulting of the kernel text.
-*
-* If the hash table bucket is full of kernel text entries, we'll
-* lockup here but that shouldn't happen
 */
 
-1: lis r4, (next_slot - PAGE_OFFSET)@ha/* get next evict slot 
*/
+   lis r4, (next_slot - PAGE_OFFSET)@ha/* get next evict slot 
*/
lwz r6, (next_slot - PAGE_OFFSET)@l(r4)
addir6,r6,HPTE_SIZE /* search for candidate */
andi.   r6,r6,7*HPTE_SIZE
stw r6,next_slot@l(r4)
add r4,r3,r6
-   LDPTE   r0,HPTE_SIZE/2(r4)  /* get PTE second word */
-   clrrwi  r0,r0,12
-   lis r6,etext@h
-   ori r6,r6,etext@l   /* get etext */
-   tophys(r6,r6)
-   cmplcr0,r0,r6   /* compare and try again */
-   blt 1b
 
 #ifndef CONFIG_SMP
/* Store PTE in PTEG */
diff --git a/arch/powerpc/mm/book3s32/mmu.c b/arch/powerpc/mm/book3s32/mmu.c
index 5c60dcade90a..23f60e97196e 100644
--- a/arch/powerpc/mm/book3s32/mmu.c
+++ b/arch/powerpc/mm/book3s32/mmu.c
@@ -302,7 +302,7 @@ void __init setbat(int index, unsigned long virt, 
phys_addr_t phys,
 /*
  * Preload a translation in the hash table
  */
-void hash_preload(struct mm_struct *mm, unsigned long ea)
+static void hash_preload(struct mm_struct *mm, unsigned long ea)
 {
pmd_t *pmd;
 
diff --git a/arch/powerpc/mm/mmu_decl.h b/arch/powerpc/mm/mmu_decl.h
index 1b6d39e9baed..0ad6d476d01d 100644
--- a/arch/powerpc/mm/mmu_decl.h
+++ b/arch/powerpc/mm/mmu_decl.h
@@ -91,8 +91,6 @@ void print_system_hash_info(void);
 
 #ifdef CONFIG_PPC32
 
-void hash_preload(struct mm_struct *mm, unsigned long ea);
-
 extern void mapin_ram(void);
 extern void setbat(int index, unsigned long virt, phys_addr_t phys,
   unsigned int size, pgprot_t prot);
diff --git a/arch/powerpc/mm/pgtable_32.c b/arch/powerpc/mm/pgtable_32.c
index 079159e97bca..6e0083e7f008 100644
--- a/arch/powerpc/mm/pgtable_32.c
+++ b/arch/powerpc/mm/pgtable_32.c
@@ -112,10 +112,6 @@ static void __init __mapin_ram_chunk(unsigned long offset, 
unsigned long top)
ktext = ((char *)v >= _stext && (char *)v < etext) ||
((char *)v >= _sinittext && (char *)v < _einittext);
map_kernel_page(v, p, ktext ? PAGE_KERNEL_TEXT : PAGE_KERNEL);
-#ifdef CONFIG_PPC_BOOK3S_32
-   if (ktext)
-   hash_preload(&init_mm, v);
-#endif
v += PAGE_SIZE;
p += PAGE_SIZE;
}
-- 
2.25.0

[PATCH v1 3/8] powerpc/32s: Fix an FTR_SECTION_ELSE

2020-11-24 Thread Christophe Leroy

An FTR_SECTION_ELSE is in the middle of
BEGIN_MMU_FTR_SECTION/ALT_MMU_FTR_SECTION_END_IFSET

Change it to MMU_FTR_SECTION_ELSE

Signed-off-by: Christophe Leroy 
---
 arch/powerpc/kernel/head_book3s_32.S | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/powerpc/kernel/head_book3s_32.S 
b/arch/powerpc/kernel/head_book3s_32.S
index 27767f3e7ec1..236a95d163be 100644
--- a/arch/powerpc/kernel/head_book3s_32.S
+++ b/arch/powerpc/kernel/head_book3s_32.S
@@ -332,7 +332,7 @@ BEGIN_MMU_FTR_SECTION
rlwinm  r3, r5, 32 - 15, 21, 21 /* DSISR_STORE -> _PAGE_RW */
bl  hash_page
b   handle_page_fault_tramp_1
-FTR_SECTION_ELSE
+MMU_FTR_SECTION_ELSE
b   handle_page_fault_tramp_2
 ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_HPTE_TABLE)
 #endif /* CONFIG_VMAP_STACK */
-- 
2.25.0

[PATCH v1 4/8] powerpc/32s: Don't use SPRN_SPRG_PGDIR in hash_page

2020-11-24 Thread Christophe Leroy

SPRN_SPRG_PGDIR is there mainly to speedup SW TLB miss handlers
for powerpc 603.

We need to free SPRN_SPRG2 to reduce the mess with CONFIG_VMAP_STACK.

In hash_page(), reading PGDIR from thread_struct will be in the noise
performance wise.

Signed-off-by: Christophe Leroy 
---
 arch/powerpc/mm/book3s32/hash_low.S | 9 +
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/arch/powerpc/mm/book3s32/hash_low.S 
b/arch/powerpc/mm/book3s32/hash_low.S
index 48415c857d80..aca353d1c5f4 100644
--- a/arch/powerpc/mm/book3s32/hash_low.S
+++ b/arch/powerpc/mm/book3s32/hash_low.S
@@ -65,13 +65,14 @@ _GLOBAL(hash_page)
/* Get PTE (linux-style) and check access */
lis r0, TASK_SIZE@h /* check if kernel address */
cmplw   0,r4,r0
+   mfspr   r8,SPRN_SPRG_THREAD /* current task's THREAD (phys) */
ori r3,r3,_PAGE_USER|_PAGE_PRESENT /* test low addresses as user */
-   mfspr   r5, SPRN_SPRG_PGDIR /* phys page-table root */
+   lwz r5,PGDIR(r8)/* virt page-table root */
blt+112f/* assume user more likely */
-   lis r5, (swapper_pg_dir - PAGE_OFFSET)@ha   /* if kernel address, 
use */
-   addir5 ,r5 ,(swapper_pg_dir - PAGE_OFFSET)@l/* kernel page 
table */
+   lis r5,swapper_pg_dir@ha/* if kernel address, use */
+   addir5,r5,swapper_pg_dir@l  /* kernel page table */
rlwimi  r3,r9,32-12,29,29   /* MSR_PR -> _PAGE_USER */
-112:
+112:   tophys(r5, r5)
 #ifndef CONFIG_PTE_64BIT
rlwimi  r5,r4,12,20,29  /* insert top 10 bits of address */
lwz r8,0(r5)/* get pmd entry */
-- 
2.25.0

[PATCH v1 1/8] powerpc/32s: Always map kernel text and rodata with BATs

2020-11-24 Thread Christophe Leroy

Since commit 2b279c0348af ("powerpc/32s: Allow mapping with BATs with
DEBUG_PAGEALLOC"), there is no real situation where mapping without
BATs is required.

In order to simplify memory handling, always map kernel text
and rodata with BATs even when "nobats" kernel parameter is set.

Also fix the 603 TLB miss exceptions that don't require anymore
kernel page table if DEBUG_PAGEALLOC.

Signed-off-by: Christophe Leroy 
---
 arch/powerpc/kernel/head_book3s_32.S | 4 ++--
 arch/powerpc/mm/book3s32/mmu.c   | 8 +++-
 2 files changed, 5 insertions(+), 7 deletions(-)

diff --git a/arch/powerpc/kernel/head_book3s_32.S 
b/arch/powerpc/kernel/head_book3s_32.S
index a0dda2a1f2df..27767f3e7ec1 100644
--- a/arch/powerpc/kernel/head_book3s_32.S
+++ b/arch/powerpc/kernel/head_book3s_32.S
@@ -453,13 +453,13 @@ InstructionTLBMiss:
  */
/* Get PTE (linux-style) and check access */
mfspr   r3,SPRN_IMISS
-#if defined(CONFIG_MODULES) || defined(CONFIG_DEBUG_PAGEALLOC)
+#ifdef CONFIG_MODULES
lis r1, TASK_SIZE@h /* check if kernel address */
cmplw   0,r1,r3
 #endif
mfspr   r2, SPRN_SPRG_PGDIR
li  r1,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
-#if defined(CONFIG_MODULES) || defined(CONFIG_DEBUG_PAGEALLOC)
+#ifdef CONFIG_MODULES
bgt-112f
lis r2, (swapper_pg_dir - PAGE_OFFSET)@ha   /* if kernel address, 
use */
addir2, r2, (swapper_pg_dir - PAGE_OFFSET)@l/* kernel page 
table */
diff --git a/arch/powerpc/mm/book3s32/mmu.c b/arch/powerpc/mm/book3s32/mmu.c
index a59e7ec98180..5c60dcade90a 100644
--- a/arch/powerpc/mm/book3s32/mmu.c
+++ b/arch/powerpc/mm/book3s32/mmu.c
@@ -157,11 +157,9 @@ unsigned long __init mmu_mapin_ram(unsigned long base, 
unsigned long top)
unsigned long done;
unsigned long border = (unsigned long)__init_begin - PAGE_OFFSET;
 
-   if (__map_without_bats) {
-   pr_debug("RAM mapped without BATs\n");
-   return base;
-   }
-   if (debug_pagealloc_enabled()) {
+
+   if (debug_pagealloc_enabled() || __map_without_bats) {
+   pr_debug_once("Read-Write memory mapped without BATs\n");
if (base >= border)
return base;
if (top >= border)
-- 
2.25.0

Re: [PATCH 0/2] powerpc: Remove support for ppc405/440 Xilinx platforms

2020-11-24 Thread Christophe Leroy

Le 21/05/2020 à 12:38, Christophe Leroy a écrit :

Le 21/05/2020 à 09:02, Michael Ellerman a écrit :

Arnd Bergmann writes:

+On Wed, Apr 8, 2020 at 2:04 PM Michael Ellerman wrote:

Benjamin Herrenschmidt writes:

On Fri, 2020-04-03 at 15:59 +1100, Michael Ellerman wrote:

Benjamin Herrenschmidt writes:

IBM still put 40x cores inside POWER chips no ?

Oh yeah that's true. I guess most folks don't know that, or that they
run RHEL on them.

Is there a reason for not having those dts files in mainline then?
If nothing else, it would document what machines are still being
used with future kernels.

Sorry that part was a joke :D Those chips don't run Linux.

Nice to know :)

What's the plan then, do we still want to keep 40x in the kernel ?

If yes, is it ok to drop the oldies anyway as done in my series
https://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=172630 ?

(Note that this series will conflict with my series on hugepages on 8xx due to the
PTE_ATOMIC_UPDATES stuff. I can rebase the 40x modernisation series on top of the 8xx hugepages
series if it is worth it)

Do we still want to keep 40x in the kernel ? We don't even have a running 40x QEMU machine as far as
I know.

I'm asking because I'd like to drop the non CONFIG_VMAP_STACK code to simplify and ease stuff (code
that works with vmalloc'ed stacks also works with stacks in linear memory), but I can't do it
because 40x doesn't have VMAP_STACK and should I implement it for 40x, I have to means to test it.

So it would ease things if we could drop 40x completely, unless someone there has a 40x platform to
test stuff.

Thanks
Christophe

Re: [PATCH net 1/2] ibmvnic: Ensure that SCRQ entry reads are correctly ordered

2020-11-24 Thread Michael Ellerman

Thomas Falcon  writes:
> Ensure that received Subordinate Command-Response Queue (SCRQ)
> entries are properly read in order by the driver. These queues
> are used in the ibmvnic device to process RX buffer and TX completion
> descriptors. dma_rmb barriers have been added after checking for a
> pending descriptor to ensure the correct descriptor entry is checked
> and after reading the SCRQ descriptor to ensure the entire
> descriptor is read before processing.
>
> Fixes: 032c5e828 ("Driver for IBM System i/p VNIC protocol")
> Signed-off-by: Thomas Falcon 
> ---
>  drivers/net/ethernet/ibm/ibmvnic.c | 8 
>  1 file changed, 8 insertions(+)
>
> diff --git a/drivers/net/ethernet/ibm/ibmvnic.c 
> b/drivers/net/ethernet/ibm/ibmvnic.c
> index 2aa40b2..489ed5e 100644
> --- a/drivers/net/ethernet/ibm/ibmvnic.c
> +++ b/drivers/net/ethernet/ibm/ibmvnic.c
> @@ -2403,6 +2403,8 @@ static int ibmvnic_poll(struct napi_struct *napi, int 
> budget)
>  
>   if (!pending_scrq(adapter, adapter->rx_scrq[scrq_num]))
>   break;
> + /* ensure that we do not prematurely exit the polling loop */
> + dma_rmb();

I'd be happier if these comments were more specific about which read(s)
they are ordering vs which other read(s).

I'm sure it's obvious to you, but it may not be to a future author,
and/or after the code has been refactored over time.

>   next = ibmvnic_next_scrq(adapter, adapter->rx_scrq[scrq_num]);
>   rx_buff =
>   (struct ibmvnic_rx_buff *)be64_to_cpu(next->
> @@ -3098,6 +3100,9 @@ static int ibmvnic_complete_tx(struct ibmvnic_adapter 
> *adapter,
>   unsigned int pool = scrq->pool_index;
>   int num_entries = 0;
>  
> + /* ensure that the correct descriptor entry is read */
> + dma_rmb();
> +
>   next = ibmvnic_next_scrq(adapter, scrq);
>   for (i = 0; i < next->tx_comp.num_comps; i++) {
>   if (next->tx_comp.rcs[i]) {
> @@ -3498,6 +3503,9 @@ static union sub_crq *ibmvnic_next_scrq(struct 
> ibmvnic_adapter *adapter,
>   }
>   spin_unlock_irqrestore(&scrq->lock, flags);
>  
> + /* ensure that the entire SCRQ descriptor is read */
> + dma_rmb();
> +
>   return entry;
>  }

cheers

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