Re: [PATCH] powerpc/64: Fix unannotated intra-function call warning
On Fri, Feb 17, 2023 at 10:02:26AM +0530, Sathvika Vasireddy wrote: > objtool throws the following warning: > arch/powerpc/kernel/head_64.o: warning: objtool: .text+0x6128: > unannotated intra-function call > > Fix the warning by annotating start_initialization_book3s symbol with the > SYM_FUNC_START_LOCAL and SYM_FUNC_END macros. > > Reported-by: Stephen Rothwell > Signed-off-by: Sathvika Vasireddy Suggested-by: Josh Poimboeuf -- Josh
Re: linux-next: build warning after merge of the powerpc tree
On Fri, Feb 17, 2023 at 12:35:17PM +1100, Michael Ellerman wrote:
> Josh Poimboeuf writes:
> > On Thu, Feb 16, 2023 at 02:40:31PM +1100, Stephen Rothwell wrote:
> >> Hi all,
> >>
> >> After merging the powerpc tree, today's linux-next build (powerpc
> >> pseries_le_defconfig) produced this warning:
> >>
> >> arch/powerpc/kernel/head_64.o: warning: objtool: .text+0x6128: unannotated
> >> intra-function call
> >>
> >> I have no idea what caused this.
> >
> > Adding Sathvika and Christophe.
> >
> > The short term fix would be something like the below, but...
> >
> > If powerpc objtool is only doing mcount, does it even make sense to run
> > objtool on asm files? If so, there are probably a lot more cleanups
> > needed for the asm code.
>
> I would like to enable more of the objtool checks eventually, although I
> don't have a timeline for that. But I'd prefer to keep checking the asm
> code seeing as we've already enabled that.
Sounds good for now, though as you get more objtool features there will
need to be more changes.
For example a lot of the callable functions are annotated with _GLOBAL()
rather than SYM_FUNC_{START,END}. The latter adds the function size,
which objtool needs in several cases. It also has particular rules
about when to use SYM_FUNC_* vs SYM_CODE_*, etc to make the code more
structured.
> > So I'm thinking either we should cleanup all the powerpc asm code with
> > annotations like below, or we should try to make objtool mcount-mode
> > ignore asm files.
>
> I think we have most of the code annotated already, this is a new
> warning because that code is newly refactored by a commit I applied.
>
> I'll have to fix my build scripts to error out on objtool warnings.
Likewise, I'll need to add some powerpc cross-compiles to my testing.
If we get too many of these powerpc warnings, we may be looking to
recruit more objtool maintainers ;-)
--
Josh
Re: [PATCH 2/2] powerpc/{32,book3e}: kcsan: Extend KCSAN Support
Le 17/02/2023 à 00:23, Rohan McLure a écrit : >> On 16 Feb 2023, at 6:14 pm, Christophe Leroy >> wrote: >> >> >> >> Le 16/02/2023 à 06:09, Rohan McLure a écrit : >>> Enable HAVE_ARCH_KCSAN on all powerpc platforms, permitting use of the >>> kernel concurrency sanitiser through the CONFIG_KCSAN_* kconfig options. >>> >>> Boots and passes selftests on 32-bit and 64-bit platforms. See >>> documentation in Documentation/dev-tools/kcsan.rst for more information. >>> >>> Signed-off-by: Rohan McLure >>> --- >>> New patch >>> --- >>> arch/powerpc/Kconfig | 2 +- >>> 1 file changed, 1 insertion(+), 1 deletion(-) >>> >>> diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig >>> index 2c9cdf1d8761..45771448d47a 100644 >>> --- a/arch/powerpc/Kconfig >>> +++ b/arch/powerpc/Kconfig >>> @@ -197,7 +197,7 @@ config PPC >>>select HAVE_ARCH_KASAN if PPC_RADIX_MMU >>>select HAVE_ARCH_KASAN if PPC_BOOK3E_64 >>>select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN >>> - select HAVE_ARCH_KCSAN if PPC_BOOK3S_64 >>> + select HAVE_ARCH_KCSAN >> >> So that's a followup of a not yet posted version v5 of the other series ? >> Why not just add patch 1 in that series and have KCSAN for all powerpc >> at once ? > > So the v3 was accepted upstream, likely to appear in 6.3. This patch series is > just to extend support to other platforms, once kcsan supports us. Hum ... Ok. I checked in checkpatch before writting that mail and saw that v4 was flagged "changes requested", so I didn't notice v3 was accepted. > > Link: > https://patchwork.ozlabs.org/project/linuxppc-dev/cover/20230206021801.105268-1-rmcl...@linux.ibm.com/ > >> >>>select HAVE_ARCH_KFENCE if ARCH_SUPPORTS_DEBUG_PAGEALLOC >>>select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET >>>select HAVE_ARCH_KGDB > >
Re: [PATCH v5 00/10] Add the PowerQUICC audio support using the QMC
Le 17/02/2023 à 00:52, Michael Ellerman a écrit : > Herve Codina writes: >> Hi, >> >> This series adds support for audio using the QMC controller available in >> some Freescale PowerQUICC SoCs. > > Who's going to take this series? > > By lines of code it's mostly in drivers/soc/fsl, so I was expecting it > would go via that tree. > > Or is it a sound series that should go via one of the sound trees? It is a sound series, I was expecting it to go via sound tree, that's the reason why I asked and got an Acked-by: from fsl soc maintainers. Mark, is that ok for you or do you expect this series to go via soc tree ? Thanks Christophe > > cheers > > ... >> .../soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml | 172 ++ >> .../bindings/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml | 234 +++ >> .../bindings/sound/fsl,qmc-audio.yaml | 117 ++ >> MAINTAINERS | 25 + >> arch/powerpc/platforms/8xx/cpm1.c |2 +- >> drivers/soc/fsl/qe/Kconfig| 23 + >> drivers/soc/fsl/qe/Makefile |2 + >> drivers/soc/fsl/qe/qmc.c | 1533 + >> drivers/soc/fsl/qe/tsa.c | 869 ++ >> drivers/soc/fsl/qe/tsa.h | 42 + >> include/dt-bindings/soc/fsl,tsa.h | 13 + >> include/soc/fsl/qe/qmc.h | 71 + >> sound/soc/fsl/Kconfig |9 + >> sound/soc/fsl/Makefile|2 + >> sound/soc/fsl/fsl_qmc_audio.c | 735 >> 15 files changed, 3848 insertions(+), 1 deletion(-) >> create mode 100644 >> Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml >> create mode 100644 >> Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml >> create mode 100644 >> Documentation/devicetree/bindings/sound/fsl,qmc-audio.yaml >> create mode 100644 drivers/soc/fsl/qe/qmc.c >> create mode 100644 drivers/soc/fsl/qe/tsa.c >> create mode 100644 drivers/soc/fsl/qe/tsa.h >> create mode 100644 include/dt-bindings/soc/fsl,tsa.h >> create mode 100644 include/soc/fsl/qe/qmc.h >> create mode 100644 sound/soc/fsl/fsl_qmc_audio.c
Re: [PATCH] powerpc/64: Fix unannotated intra-function call warning
Hi all,
On Fri, 17 Feb 2023 10:02:26 +0530 Sathvika Vasireddy
wrote:
>
> objtool throws the following warning:
> arch/powerpc/kernel/head_64.o: warning: objtool: .text+0x6128:
> unannotated intra-function call
>
> Fix the warning by annotating start_initialization_book3s symbol with the
> SYM_FUNC_START_LOCAL and SYM_FUNC_END macros.
>
> Reported-by: Stephen Rothwell
> Signed-off-by: Sathvika Vasireddy
> ---
> arch/powerpc/kernel/head_64.S | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/arch/powerpc/kernel/head_64.S b/arch/powerpc/kernel/head_64.S
> index 3a7266fa8a18..1febb56ebaeb 100644
> --- a/arch/powerpc/kernel/head_64.S
> +++ b/arch/powerpc/kernel/head_64.S
> @@ -472,7 +472,7 @@ SYM_FUNC_START_LOCAL(__mmu_off)
> b . /* prevent speculative execution */
> SYM_FUNC_END(__mmu_off)
>
> -start_initialization_book3s:
> +SYM_FUNC_START_LOCAL(start_initialization_book3s)
> mflrr25
>
> /* Setup some critical 970 SPRs before switching MMU off */
> @@ -494,6 +494,7 @@ start_initialization_book3s:
>
> mtlrr25
> blr
> +SYM_FUNC_END(start_initialization_book3s)
> #endif
>
> /*
> --
> 2.31.1
>
That at least makes the warning go away for me.
Tested-by: Stephen Rothwell
Fixes: 58f24eea5278 ("powerpc/64s: Refactor initialisation after prom")
--
Cheers,
Stephen Rothwell
pgp6rUCXguOOf.pgp
Description: OpenPGP digital signature
[PATCH] powerpc/64: Fix unannotated intra-function call warning
objtool throws the following warning: arch/powerpc/kernel/head_64.o: warning: objtool: .text+0x6128: unannotated intra-function call Fix the warning by annotating start_initialization_book3s symbol with the SYM_FUNC_START_LOCAL and SYM_FUNC_END macros. Reported-by: Stephen Rothwell Signed-off-by: Sathvika Vasireddy --- arch/powerpc/kernel/head_64.S | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/kernel/head_64.S b/arch/powerpc/kernel/head_64.S index 3a7266fa8a18..1febb56ebaeb 100644 --- a/arch/powerpc/kernel/head_64.S +++ b/arch/powerpc/kernel/head_64.S @@ -472,7 +472,7 @@ SYM_FUNC_START_LOCAL(__mmu_off) b . /* prevent speculative execution */ SYM_FUNC_END(__mmu_off) -start_initialization_book3s: +SYM_FUNC_START_LOCAL(start_initialization_book3s) mflrr25 /* Setup some critical 970 SPRs before switching MMU off */ @@ -494,6 +494,7 @@ start_initialization_book3s: mtlrr25 blr +SYM_FUNC_END(start_initialization_book3s) #endif /* -- 2.31.1
Re: [PATCH mm-unstable v1 4/5] kvm/powerpc: add kvm_arch_test_clear_young()
On Thu, Feb 16, 2023 at 9:12 PM Yu Zhao wrote: > > This patch adds kvm_arch_test_clear_young() for the vast majority of > VMs that are not nested and run on hardware with Radix MMU enabled. > > It relies on two techniques, RCU and cmpxchg, to safely test and clear > the accessed bit without taking the MMU lock. The former protects KVM > page tables from being freed while the latter clears the accessed bit > atomically against both the hardware and other software page table > walkers. > > Signed-off-by: Yu Zhao > --- > arch/powerpc/include/asm/kvm_host.h| 18 ++ > arch/powerpc/include/asm/kvm_ppc.h | 14 + > arch/powerpc/kvm/book3s.c | 7 +++ > arch/powerpc/kvm/book3s.h | 2 + > arch/powerpc/kvm/book3s_64_mmu_radix.c | 78 +- > arch/powerpc/kvm/book3s_hv.c | 10 ++-- > 6 files changed, 110 insertions(+), 19 deletions(-) Adding Michael, Nicholas and Christophe. I'm not sure who I should add for this patch. Can you please add any interested parties that I've missed? Thank you.
Re: [PATCH mm-unstable v1 3/5] kvm/arm64: add kvm_arch_test_clear_young()
On Thu, Feb 16, 2023 at 9:12 PM Yu Zhao wrote: > > This patch adds kvm_arch_test_clear_young() for the vast majority of > VMs that are not pKVM and run on hardware that sets the accessed bit > in KVM page tables. > > It relies on two techniques, RCU and cmpxchg, to safely test and clear > the accessed bit without taking the MMU lock. The former protects KVM > page tables from being freed while the latter clears the accessed bit > atomically against both the hardware and other software page table > walkers. > > Signed-off-by: Yu Zhao > --- > arch/arm64/include/asm/kvm_host.h | 7 +++ > arch/arm64/include/asm/kvm_pgtable.h| 8 +++ > arch/arm64/include/asm/stage2_pgtable.h | 43 ++ > arch/arm64/kvm/arm.c| 1 + > arch/arm64/kvm/hyp/pgtable.c| 51 ++-- > arch/arm64/kvm/mmu.c| 77 - > 6 files changed, 141 insertions(+), 46 deletions(-) Adding Marc and Will. Can you please add other interested parties that I've missed? Thanks.
Re: [PATCH mm-unstable v1 2/5] kvm/x86: add kvm_arch_test_clear_young()
On Thu, Feb 16, 2023 at 9:12 PM Yu Zhao wrote: > > This patch adds kvm_arch_test_clear_young() for the vast majority of > VMs that are not nested and run on hardware that sets the accessed bit > in TDP MMU page tables. > > It relies on two techniques, RCU and cmpxchg, to safely test and clear > the accessed bit without taking the MMU lock. The former protects KVM > page tables from being freed while the latter clears the accessed bit > atomically against both the hardware and other software page table > walkers. > > Signed-off-by: Yu Zhao > --- > arch/x86/include/asm/kvm_host.h | 27 ++ > arch/x86/kvm/mmu/spte.h | 12 -- > arch/x86/kvm/mmu/tdp_mmu.c | 41 + > 3 files changed, 68 insertions(+), 12 deletions(-) Adding Sean and David. Can you please add other interested parties that I've missed? Thanks.
[PATCH mm-unstable v1 4/5] kvm/powerpc: add kvm_arch_test_clear_young()
This patch adds kvm_arch_test_clear_young() for the vast majority of
VMs that are not nested and run on hardware with Radix MMU enabled.
It relies on two techniques, RCU and cmpxchg, to safely test and clear
the accessed bit without taking the MMU lock. The former protects KVM
page tables from being freed while the latter clears the accessed bit
atomically against both the hardware and other software page table
walkers.
Signed-off-by: Yu Zhao
---
arch/powerpc/include/asm/kvm_host.h| 18 ++
arch/powerpc/include/asm/kvm_ppc.h | 14 +
arch/powerpc/kvm/book3s.c | 7 +++
arch/powerpc/kvm/book3s.h | 2 +
arch/powerpc/kvm/book3s_64_mmu_radix.c | 78 +-
arch/powerpc/kvm/book3s_hv.c | 10 ++--
6 files changed, 110 insertions(+), 19 deletions(-)
diff --git a/arch/powerpc/include/asm/kvm_host.h
b/arch/powerpc/include/asm/kvm_host.h
index caea15dcb91d..996850029ce0 100644
--- a/arch/powerpc/include/asm/kvm_host.h
+++ b/arch/powerpc/include/asm/kvm_host.h
@@ -886,4 +886,22 @@ static inline void kvm_arch_exit(void) {}
static inline void kvm_arch_vcpu_blocking(struct kvm_vcpu *vcpu) {}
static inline void kvm_arch_vcpu_unblocking(struct kvm_vcpu *vcpu) {}
+static inline int kvmppc_radix_possible(void)
+{
+ return cpu_has_feature(CPU_FTR_ARCH_300) && radix_enabled();
+}
+
+static inline bool kvmhv_on_pseries(void)
+{
+ return IS_ENABLED(CONFIG_PPC_PSERIES) &&
!cpu_has_feature(CPU_FTR_HVMODE);
+}
+
+/* see the comments on the generic kvm_arch_has_test_clear_young() */
+#define kvm_arch_has_test_clear_young kvm_arch_has_test_clear_young
+static inline bool kvm_arch_has_test_clear_young(void)
+{
+ return IS_ENABLED(CONFIG_KVM) &&
IS_ENABLED(CONFIG_KVM_BOOK3S_HV_POSSIBLE) &&
+ kvmppc_radix_possible() && !kvmhv_on_pseries();
+}
+
#endif /* __POWERPC_KVM_HOST_H__ */
diff --git a/arch/powerpc/include/asm/kvm_ppc.h
b/arch/powerpc/include/asm/kvm_ppc.h
index eae9619b6190..0bb772fc12b1 100644
--- a/arch/powerpc/include/asm/kvm_ppc.h
+++ b/arch/powerpc/include/asm/kvm_ppc.h
@@ -277,6 +277,8 @@ struct kvmppc_ops {
bool (*unmap_gfn_range)(struct kvm *kvm, struct kvm_gfn_range *range);
bool (*age_gfn)(struct kvm *kvm, struct kvm_gfn_range *range);
bool (*test_age_gfn)(struct kvm *kvm, struct kvm_gfn_range *range);
+ bool (*test_clear_young)(struct kvm *kvm, struct kvm_gfn_range *range,
+gfn_t lsb_gfn, unsigned long *bitmap);
bool (*set_spte_gfn)(struct kvm *kvm, struct kvm_gfn_range *range);
void (*free_memslot)(struct kvm_memory_slot *slot);
int (*init_vm)(struct kvm *kvm);
@@ -580,18 +582,6 @@ static inline bool kvm_hv_mode_active(void)
{ return false; }
#endif
-#ifdef CONFIG_PPC_PSERIES
-static inline bool kvmhv_on_pseries(void)
-{
- return !cpu_has_feature(CPU_FTR_HVMODE);
-}
-#else
-static inline bool kvmhv_on_pseries(void)
-{
- return false;
-}
-#endif
-
#ifdef CONFIG_KVM_XICS
static inline int kvmppc_xics_enabled(struct kvm_vcpu *vcpu)
{
diff --git a/arch/powerpc/kvm/book3s.c b/arch/powerpc/kvm/book3s.c
index 6d525285dbe8..f4cf330e3e81 100644
--- a/arch/powerpc/kvm/book3s.c
+++ b/arch/powerpc/kvm/book3s.c
@@ -877,6 +877,13 @@ bool kvm_test_age_gfn(struct kvm *kvm, struct
kvm_gfn_range *range)
return kvm->arch.kvm_ops->test_age_gfn(kvm, range);
}
+bool kvm_arch_test_clear_young(struct kvm *kvm, struct kvm_gfn_range *range,
+ gfn_t lsb_gfn, unsigned long *bitmap)
+{
+ return kvm->arch.kvm_ops->test_clear_young &&
+ kvm->arch.kvm_ops->test_clear_young(kvm, range, lsb_gfn, bitmap);
+}
+
bool kvm_set_spte_gfn(struct kvm *kvm, struct kvm_gfn_range *range)
{
return kvm->arch.kvm_ops->set_spte_gfn(kvm, range);
diff --git a/arch/powerpc/kvm/book3s.h b/arch/powerpc/kvm/book3s.h
index 58391b4b32ed..fe9cac423817 100644
--- a/arch/powerpc/kvm/book3s.h
+++ b/arch/powerpc/kvm/book3s.h
@@ -12,6 +12,8 @@ extern void kvmppc_core_flush_memslot_hv(struct kvm *kvm,
extern bool kvm_unmap_gfn_range_hv(struct kvm *kvm, struct kvm_gfn_range
*range);
extern bool kvm_age_gfn_hv(struct kvm *kvm, struct kvm_gfn_range *range);
extern bool kvm_test_age_gfn_hv(struct kvm *kvm, struct kvm_gfn_range *range);
+extern bool kvmhv_test_clear_young(struct kvm *kvm, struct kvm_gfn_range
*range,
+ gfn_t lsb_gfn, unsigned long *bitmap);
extern bool kvm_set_spte_gfn_hv(struct kvm *kvm, struct kvm_gfn_range *range);
extern int kvmppc_mmu_init_pr(struct kvm_vcpu *vcpu);
diff --git a/arch/powerpc/kvm/book3s_64_mmu_radix.c
b/arch/powerpc/kvm/book3s_64_mmu_radix.c
index 9d3743ca16d5..8476646c554c 100644
--- a/arch/powerpc/kvm/book3s_64_mmu_radix.c
+++ b/arch/powerpc/kvm/book3s_64_mmu_radix.c
@@ -1083,6 +1083,78 @@ bool kvm_test_age_radix(struct kvm *kvm, struct
kvm_memory_slot *memslot,
return ref;
}
+bool
[PATCH mm-unstable v1 5/5] mm: multi-gen LRU: use mmu_notifier_test_clear_young()
An existing selftest can quickly demonstrate the effectiveness of this
patch. On a generic workstation equipped with 128 CPUs and 256GB DRAM:
$ sudo max_guest_memory_test -c 64 -m 250 -s 250
MGLRU run2
---
Before~600s
After ~50s
Off ~250s
kswapd (MGLRU before)
100.00% balance_pgdat
100.00% shrink_node
100.00% shrink_one
99.97% try_to_shrink_lruvec
99.06% evict_folios
97.41% shrink_folio_list
31.33% folio_referenced
31.06% rmap_walk_file
30.89% folio_referenced_one
20.83% __mmu_notifier_clear_flush_young
20.54% kvm_mmu_notifier_clear_flush_young
=> 19.34% _raw_write_lock
kswapd (MGLRU after)
100.00% balance_pgdat
100.00% shrink_node
100.00% shrink_one
99.97% try_to_shrink_lruvec
99.51% evict_folios
71.70% shrink_folio_list
7.08% folio_referenced
6.78% rmap_walk_file
6.72% folio_referenced_one
5.60% lru_gen_look_around
=>1.53% __mmu_notifier_test_clear_young
kswapd (MGLRU off)
100.00% balance_pgdat
100.00% shrink_node
99.92% shrink_lruvec
69.95% shrink_folio_list
19.35% folio_referenced
18.37% rmap_walk_file
17.88% folio_referenced_one
13.20% __mmu_notifier_clear_flush_young
11.64% kvm_mmu_notifier_clear_flush_young
=> 9.93% _raw_write_lock
26.23% shrink_active_list
25.50% folio_referenced
25.35% rmap_walk_file
25.28% folio_referenced_one
23.87% __mmu_notifier_clear_flush_young
23.69% kvm_mmu_notifier_clear_flush_young
=> 18.98% _raw_write_lock
Signed-off-by: Yu Zhao
---
include/linux/mmzone.h | 6 +-
mm/rmap.c | 8 +--
mm/vmscan.c| 127 -
3 files changed, 121 insertions(+), 20 deletions(-)
diff --git a/include/linux/mmzone.h b/include/linux/mmzone.h
index 9fb1b03b83b2..ce34b7ea8e4c 100644
--- a/include/linux/mmzone.h
+++ b/include/linux/mmzone.h
@@ -379,6 +379,7 @@ enum {
LRU_GEN_CORE,
LRU_GEN_MM_WALK,
LRU_GEN_NONLEAF_YOUNG,
+ LRU_GEN_SPTE_WALK,
NR_LRU_GEN_CAPS
};
@@ -485,7 +486,7 @@ struct lru_gen_mm_walk {
};
void lru_gen_init_lruvec(struct lruvec *lruvec);
-void lru_gen_look_around(struct page_vma_mapped_walk *pvmw);
+bool lru_gen_look_around(struct page_vma_mapped_walk *pvmw);
#ifdef CONFIG_MEMCG
@@ -573,8 +574,9 @@ static inline void lru_gen_init_lruvec(struct lruvec
*lruvec)
{
}
-static inline void lru_gen_look_around(struct page_vma_mapped_walk *pvmw)
+static inline bool lru_gen_look_around(struct page_vma_mapped_walk *pvmw)
{
+ return false;
}
#ifdef CONFIG_MEMCG
diff --git a/mm/rmap.c b/mm/rmap.c
index 15ae24585fc4..eb0089f8f112 100644
--- a/mm/rmap.c
+++ b/mm/rmap.c
@@ -823,12 +823,10 @@ static bool folio_referenced_one(struct folio *folio,
return false; /* To break the loop */
}
- if (pvmw.pte) {
- if (lru_gen_enabled() && pte_young(*pvmw.pte)) {
- lru_gen_look_around();
+ if (lru_gen_enabled() && pvmw.pte) {
+ if (lru_gen_look_around())
referenced++;
- }
-
+ } else if (pvmw.pte) {
if (ptep_clear_flush_young_notify(vma, address,
pvmw.pte))
referenced++;
diff --git a/mm/vmscan.c b/mm/vmscan.c
index 9c1c5e8b24b8..d6d69f0baabf 100644
--- a/mm/vmscan.c
+++ b/mm/vmscan.c
@@ -57,6 +57,8 @@
#include
#include
#include
+#include
+#include
#include
#include
@@ -3923,6 +3925,55 @@ static struct folio *get_pfn_folio(unsigned long pfn,
struct mem_cgroup *memcg,
return folio;
}
+static bool test_spte_young(struct mm_struct *mm, unsigned long addr, unsigned
long end,
+ unsigned long *bitmap, unsigned long *last)
+{
+ if (!kvm_arch_has_test_clear_young() || !get_cap(LRU_GEN_SPTE_WALK))
+ return false;
+
+ if (*last > addr)
+ goto done;
+
+ *last = end - addr > MIN_LRU_BATCH * PAGE_SIZE ?
+ addr + MIN_LRU_BATCH * PAGE_SIZE - 1 : end - 1;
+ bitmap_zero(bitmap, MIN_LRU_BATCH);
+
+ mmu_notifier_test_clear_young(mm, addr, *last + 1, false, bitmap);
+done:
+ return test_bit((*last - addr) / PAGE_SIZE, bitmap);
+}
+
+static void clear_spte_young(struct mm_struct *mm, unsigned long addr,
+
[PATCH mm-unstable v1 3/5] kvm/arm64: add kvm_arch_test_clear_young()
This patch adds kvm_arch_test_clear_young() for the vast majority of
VMs that are not pKVM and run on hardware that sets the accessed bit
in KVM page tables.
It relies on two techniques, RCU and cmpxchg, to safely test and clear
the accessed bit without taking the MMU lock. The former protects KVM
page tables from being freed while the latter clears the accessed bit
atomically against both the hardware and other software page table
walkers.
Signed-off-by: Yu Zhao
---
arch/arm64/include/asm/kvm_host.h | 7 +++
arch/arm64/include/asm/kvm_pgtable.h| 8 +++
arch/arm64/include/asm/stage2_pgtable.h | 43 ++
arch/arm64/kvm/arm.c| 1 +
arch/arm64/kvm/hyp/pgtable.c| 51 ++--
arch/arm64/kvm/mmu.c| 77 -
6 files changed, 141 insertions(+), 46 deletions(-)
diff --git a/arch/arm64/include/asm/kvm_host.h
b/arch/arm64/include/asm/kvm_host.h
index 35a159d131b5..572bcd321586 100644
--- a/arch/arm64/include/asm/kvm_host.h
+++ b/arch/arm64/include/asm/kvm_host.h
@@ -1031,4 +1031,11 @@ static inline void kvm_hyp_reserve(void) { }
void kvm_arm_vcpu_power_off(struct kvm_vcpu *vcpu);
bool kvm_arm_vcpu_stopped(struct kvm_vcpu *vcpu);
+/* see the comments on the generic kvm_arch_has_test_clear_young() */
+#define kvm_arch_has_test_clear_young kvm_arch_has_test_clear_young
+static inline bool kvm_arch_has_test_clear_young(void)
+{
+ return IS_ENABLED(CONFIG_KVM) && cpu_has_hw_af() &&
!is_protected_kvm_enabled();
+}
+
#endif /* __ARM64_KVM_HOST_H__ */
diff --git a/arch/arm64/include/asm/kvm_pgtable.h
b/arch/arm64/include/asm/kvm_pgtable.h
index 63f81b27a4e3..8c9a04388c88 100644
--- a/arch/arm64/include/asm/kvm_pgtable.h
+++ b/arch/arm64/include/asm/kvm_pgtable.h
@@ -105,6 +105,7 @@ static inline bool kvm_level_supports_block_mapping(u32
level)
* @put_page: Decrement the refcount on a page. When the
* refcount reaches 0 the page is automatically
* freed.
+ * @put_page_rcu: RCU variant of put_page().
* @page_count:Return the refcount of a page.
* @phys_to_virt: Convert a physical address into a virtual
* address mapped in the current context.
@@ -122,6 +123,7 @@ struct kvm_pgtable_mm_ops {
void(*free_removed_table)(void *addr, u32 level);
void(*get_page)(void *addr);
void(*put_page)(void *addr);
+ void(*put_page_rcu)(void *addr);
int (*page_count)(void *addr);
void* (*phys_to_virt)(phys_addr_t phys);
phys_addr_t (*virt_to_phys)(void *addr);
@@ -188,6 +190,12 @@ typedef bool (*kvm_pgtable_force_pte_cb_t)(u64 addr, u64
end,
* children.
* @KVM_PGTABLE_WALK_SHARED: Indicates the page-tables may be shared
* with other software walkers.
+ *
+ * kvm_arch_test_clear_young() is a special case. It relies on two
+ * techniques, RCU and cmpxchg, to safely test and clear the accessed
+ * bit without taking the MMU lock. The former protects KVM page tables
+ * from being freed while the latter clears the accessed bit atomically
+ * against both the hardware and other software page table walkers.
*/
enum kvm_pgtable_walk_flags {
KVM_PGTABLE_WALK_LEAF = BIT(0),
diff --git a/arch/arm64/include/asm/stage2_pgtable.h
b/arch/arm64/include/asm/stage2_pgtable.h
index c8dca8ae359c..350437661d4b 100644
--- a/arch/arm64/include/asm/stage2_pgtable.h
+++ b/arch/arm64/include/asm/stage2_pgtable.h
@@ -30,4 +30,47 @@
*/
#define kvm_mmu_cache_min_pages(kvm) (kvm_stage2_levels(kvm) - 1)
+#define KVM_PTE_TYPE BIT(1)
+#define KVM_PTE_TYPE_BLOCK 0
+#define KVM_PTE_TYPE_PAGE 1
+#define KVM_PTE_TYPE_TABLE 1
+
+#define KVM_PTE_LEAF_ATTR_LO GENMASK(11, 2)
+
+#define KVM_PTE_LEAF_ATTR_LO_S1_ATTRIDXGENMASK(4, 2)
+#define KVM_PTE_LEAF_ATTR_LO_S1_AP GENMASK(7, 6)
+#define KVM_PTE_LEAF_ATTR_LO_S1_AP_RO 3
+#define KVM_PTE_LEAF_ATTR_LO_S1_AP_RW 1
+#define KVM_PTE_LEAF_ATTR_LO_S1_SH GENMASK(9, 8)
+#define KVM_PTE_LEAF_ATTR_LO_S1_SH_IS 3
+#define KVM_PTE_LEAF_ATTR_LO_S1_AF BIT(10)
+
+#define KVM_PTE_LEAF_ATTR_LO_S2_MEMATTRGENMASK(5, 2)
+#define KVM_PTE_LEAF_ATTR_LO_S2_S2AP_R BIT(6)
+#define KVM_PTE_LEAF_ATTR_LO_S2_S2AP_W BIT(7)
+#define KVM_PTE_LEAF_ATTR_LO_S2_SH GENMASK(9, 8)
+#define KVM_PTE_LEAF_ATTR_LO_S2_SH_IS 3
+#define KVM_PTE_LEAF_ATTR_LO_S2_AF BIT(10)
+
+#define KVM_PTE_LEAF_ATTR_HI GENMASK(63, 51)
+
+#define KVM_PTE_LEAF_ATTR_HI_SWGENMASK(58, 55)
+
+#define KVM_PTE_LEAF_ATTR_HI_S1_XN BIT(54)
+
+#define KVM_PTE_LEAF_ATTR_HI_S2_XN BIT(54)
+
+#define KVM_PTE_LEAF_ATTR_S2_PERMS
[PATCH mm-unstable v1 2/5] kvm/x86: add kvm_arch_test_clear_young()
This patch adds kvm_arch_test_clear_young() for the vast majority of
VMs that are not nested and run on hardware that sets the accessed bit
in TDP MMU page tables.
It relies on two techniques, RCU and cmpxchg, to safely test and clear
the accessed bit without taking the MMU lock. The former protects KVM
page tables from being freed while the latter clears the accessed bit
atomically against both the hardware and other software page table
walkers.
Signed-off-by: Yu Zhao
---
arch/x86/include/asm/kvm_host.h | 27 ++
arch/x86/kvm/mmu/spte.h | 12 --
arch/x86/kvm/mmu/tdp_mmu.c | 41 +
3 files changed, 68 insertions(+), 12 deletions(-)
diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h
index 6aaae18f1854..d2995c9e8f07 100644
--- a/arch/x86/include/asm/kvm_host.h
+++ b/arch/x86/include/asm/kvm_host.h
@@ -1367,6 +1367,12 @@ struct kvm_arch {
* the MMU lock in read mode + the tdp_mmu_pages_lock or
* the MMU lock in write mode
*
+* kvm_arch_test_clear_young() is a special case. It relies on two
+* techniques, RCU and cmpxchg, to safely test and clear the accessed
+* bit without taking the MMU lock. The former protects KVM page tables
+* from being freed while the latter clears the accessed bit atomically
+* against both the hardware and other software page table walkers.
+*
* Roots will remain in the list until their tdp_mmu_root_count
* drops to zero, at which point the thread that decremented the
* count to zero should removed the root from the list and clean
@@ -2171,4 +2177,25 @@ int memslot_rmap_alloc(struct kvm_memory_slot *slot,
unsigned long npages);
KVM_X86_QUIRK_FIX_HYPERCALL_INSN | \
KVM_X86_QUIRK_MWAIT_NEVER_UD_FAULTS)
+extern u64 __read_mostly shadow_accessed_mask;
+
+/*
+ * Returns true if A/D bits are supported in hardware and are enabled by KVM.
+ * When enabled, KVM uses A/D bits for all non-nested MMUs. Because L1 can
+ * disable A/D bits in EPTP12, SP and SPTE variants are needed to handle the
+ * scenario where KVM is using A/D bits for L1, but not L2.
+ */
+static inline bool kvm_ad_enabled(void)
+{
+ return shadow_accessed_mask;
+}
+
+/* see the comments on the generic kvm_arch_has_test_clear_young() */
+#define kvm_arch_has_test_clear_young kvm_arch_has_test_clear_young
+static inline bool kvm_arch_has_test_clear_young(void)
+{
+ return IS_ENABLED(CONFIG_KVM) && IS_ENABLED(CONFIG_X86_64) &&
+ (!IS_REACHABLE(CONFIG_KVM) || (kvm_ad_enabled() && tdp_enabled));
+}
+
#endif /* _ASM_X86_KVM_HOST_H */
diff --git a/arch/x86/kvm/mmu/spte.h b/arch/x86/kvm/mmu/spte.h
index 6f54dc9409c9..0dc7fed1f3fd 100644
--- a/arch/x86/kvm/mmu/spte.h
+++ b/arch/x86/kvm/mmu/spte.h
@@ -153,7 +153,6 @@ extern u64 __read_mostly shadow_mmu_writable_mask;
extern u64 __read_mostly shadow_nx_mask;
extern u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */
extern u64 __read_mostly shadow_user_mask;
-extern u64 __read_mostly shadow_accessed_mask;
extern u64 __read_mostly shadow_dirty_mask;
extern u64 __read_mostly shadow_mmio_value;
extern u64 __read_mostly shadow_mmio_mask;
@@ -247,17 +246,6 @@ static inline bool is_shadow_present_pte(u64 pte)
return !!(pte & SPTE_MMU_PRESENT_MASK);
}
-/*
- * Returns true if A/D bits are supported in hardware and are enabled by KVM.
- * When enabled, KVM uses A/D bits for all non-nested MMUs. Because L1 can
- * disable A/D bits in EPTP12, SP and SPTE variants are needed to handle the
- * scenario where KVM is using A/D bits for L1, but not L2.
- */
-static inline bool kvm_ad_enabled(void)
-{
- return !!shadow_accessed_mask;
-}
-
static inline bool sp_ad_disabled(struct kvm_mmu_page *sp)
{
return sp->role.ad_disabled;
diff --git a/arch/x86/kvm/mmu/tdp_mmu.c b/arch/x86/kvm/mmu/tdp_mmu.c
index d6df38d371a0..9028e09f1aab 100644
--- a/arch/x86/kvm/mmu/tdp_mmu.c
+++ b/arch/x86/kvm/mmu/tdp_mmu.c
@@ -1309,6 +1309,47 @@ bool kvm_tdp_mmu_age_gfn_range(struct kvm *kvm, struct
kvm_gfn_range *range)
return kvm_tdp_mmu_handle_gfn(kvm, range, age_gfn_range);
}
+bool kvm_arch_test_clear_young(struct kvm *kvm, struct kvm_gfn_range *range,
+ gfn_t lsb_gfn, unsigned long *bitmap)
+{
+ struct kvm_mmu_page *root;
+
+ if (WARN_ON_ONCE(!kvm_arch_has_test_clear_young()))
+ return false;
+
+ if (kvm_memslots_have_rmaps(kvm))
+ return false;
+
+ /* see the comments on kvm_arch->tdp_mmu_roots */
+ rcu_read_lock();
+
+ list_for_each_entry_rcu(root, >arch.tdp_mmu_roots, link) {
+ struct tdp_iter iter;
+
+ if (kvm_mmu_page_as_id(root) != range->slot->as_id)
+ continue;
+
+ tdp_root_for_each_leaf_pte(iter, root, range->start,
range->end) {
+
[PATCH mm-unstable v1 1/5] mm/kvm: add mmu_notifier_test_clear_young()
mmu_notifier_test_clear_young() allows the caller to safely test and
clear the accessed bit in KVM PTEs without taking the MMU lock.
This patch adds the generic infrastructure to invoke the subsequent
arch-specific patches. The arch-specific implementations generally
rely on two techniques: RCU and cmpxchg. The former protects KVM page
tables from being freed while the latter clears the accessed bit
atomically against both the hardware and other software page table
walkers.
mmu_notifier_test_clear_young() follows two design patterns: fallback
and batching. For any unsupported cases, it can optionally fall back
to mmu_notifier_ops->clear_young(). For a range of KVM PTEs, it can
test or test and clear their accessed bits according to a bitmap
provided by the caller.
mmu_notifier_test_clear_young() always returns 0 if fallback is not
allowed. If fallback happens, its return value is similar to that of
mmu_notifier_clear_young().
The bitmap parameter has the following specifications:
1. The number of bits should be at least (end-start)/PAGE_SIZE.
2. The offset of each bit is relative to the end. E.g., the offset
corresponding to addr is (end-addr)/PAGE_SIZE-1. This is to better
suit batching while forward looping.
3. For each KVM PTE with the accessed bit set (young), arch-specific
implementations flip the corresponding bit in the bitmap. It only
clears the accessed bit if the old value is 1. A caller can test or
test and clear the accessed bit by setting the corresponding bit in
the bitmap to 0 or 1, and the new value will be 1 or 0 for a young
KVM PTE.
Signed-off-by: Yu Zhao
---
include/linux/kvm_host.h | 29 ++
include/linux/mmu_notifier.h | 40 +
mm/mmu_notifier.c| 26
virt/kvm/kvm_main.c | 58
4 files changed, 153 insertions(+)
diff --git a/include/linux/kvm_host.h b/include/linux/kvm_host.h
index 4f26b244f6d0..df46fc815c8b 100644
--- a/include/linux/kvm_host.h
+++ b/include/linux/kvm_host.h
@@ -2281,4 +2281,33 @@ static inline void kvm_account_pgtable_pages(void *virt,
int nr)
/* Max number of entries allowed for each kvm dirty ring */
#define KVM_DIRTY_RING_MAX_ENTRIES 65536
+/*
+ * Architectures that implement kvm_arch_test_clear_young() should override
+ * kvm_arch_has_test_clear_young().
+ *
+ * kvm_arch_has_test_clear_young() is allowed to return false positive. It can
+ * return true if kvm_arch_test_clear_young() is supported but disabled due to
+ * some runtime constraint. In this case, kvm_arch_test_clear_young() should
+ * return false.
+ *
+ * The last parameter to kvm_arch_test_clear_young() is a bitmap with the
+ * following specifications:
+ * 1. The offset of each bit is relative to the second to the last parameter
+ *lsb_gfn. E.g., the offset corresponding to gfn is lsb_gfn-gfn. This is to
+ *better suit batching while forward looping.
+ * 2. For each KVM PTE with the accessed bit set, the implementation should
flip
+ *the corresponding bit in the bitmap. It should only clear the accessed
bit
+ *if the old value is 1. This allows the caller to test or test and clear
+ *the accessed bit.
+ */
+#ifndef kvm_arch_has_test_clear_young
+static inline bool kvm_arch_has_test_clear_young(void)
+{
+ return false;
+}
+#endif
+
+bool kvm_arch_test_clear_young(struct kvm *kvm, struct kvm_gfn_range *range,
+ gfn_t lsb_gfn, unsigned long *bitmap);
+
#endif
diff --git a/include/linux/mmu_notifier.h b/include/linux/mmu_notifier.h
index 64a3e051c3c4..432b51cd6843 100644
--- a/include/linux/mmu_notifier.h
+++ b/include/linux/mmu_notifier.h
@@ -122,6 +122,11 @@ struct mmu_notifier_ops {
struct mm_struct *mm,
unsigned long address);
+ /* see the comments on mmu_notifier_test_clear_young() */
+ bool (*test_clear_young)(struct mmu_notifier *mn, struct mm_struct *mm,
+unsigned long start, unsigned long end,
+unsigned long *bitmap);
+
/*
* change_pte is called in cases that pte mapping to page is changed:
* for example, when ksm remaps pte to point to a new shared page.
@@ -390,6 +395,9 @@ extern int __mmu_notifier_clear_flush_young(struct
mm_struct *mm,
extern int __mmu_notifier_clear_young(struct mm_struct *mm,
unsigned long start,
unsigned long end);
+extern int __mmu_notifier_test_clear_young(struct mm_struct *mm,
+ unsigned long start, unsigned long
end,
+ bool fallback, unsigned long
*bitmap);
extern int __mmu_notifier_test_young(struct mm_struct *mm,
unsigned long address);
extern void __mmu_notifier_change_pte(struct mm_struct *mm,
@@ -432,6
[PATCH mm-unstable v1 0/5] mm/kvm: lockless accessed bit harvest
TLDR This patchset RCU-protects KVM page tables and compare-and-exchanges KVM PTEs with the accessed bit set by hardware. It significantly improves the performance of guests when the host is under heavy memory pressure. ChromeOS has been using a similar approach [1] since mid 2021 and it was proven successful on tens of millions devices. [1] https://crrev.com/c/2987928 Overview The goal of this patchset is to optimize the performance of guests when the host memory is overcommitted. It focuses on the vast majority of VMs that are not nested and run on hardware that sets the accessed bit in KVM page tables. Note that nested VMs and hardware that does not support the accessed bit are both out of scope. This patchset relies on two techniques, RCU and cmpxchg, to safely test and clear the accessed bit without taking kvm->mmu_lock. The former protects KVM page tables from being freed while the latter clears the accessed bit atomically against both hardware and other software page table walkers. A new MMU notifier API, mmu_notifier_test_clear_young(), is introduced. It follows two design patterns: fallback and batching. For any unsupported cases, it can optionally fall back to mmu_notifier_ops->clear_young(). For a range of KVM PTEs, it can test or test and clear their accessed bits according to a bitmap provided by the caller. This patchset only applies mmu_notifier_test_clear_young() to MGLRU. A follow-up patchset will apply it to /proc/PID/pagemap and /prod/PID/clear_refs. Evaluation == An existing selftest can quickly demonstrate the effectiveness of this patchset. On a generic workstation equipped with 64 CPUs and 256GB DRAM: $ sudo max_guest_memory_test -c 64 -m 256 -s 256 MGLRU run2 --- Before~600s After ~50s Off ~250s kswapd (MGLRU before) 100.00% balance_pgdat 100.00% shrink_node 100.00% shrink_one 99.97% try_to_shrink_lruvec 99.06% evict_folios 97.41% shrink_folio_list 31.33% folio_referenced 31.06% rmap_walk_file 30.89% folio_referenced_one 20.83% __mmu_notifier_clear_flush_young 20.54% kvm_mmu_notifier_clear_flush_young => 19.34% _raw_write_lock kswapd (MGLRU after) 100.00% balance_pgdat 100.00% shrink_node 100.00% shrink_one 99.97% try_to_shrink_lruvec 99.51% evict_folios 71.70% shrink_folio_list 7.08% folio_referenced 6.78% rmap_walk_file 6.72% folio_referenced_one 5.60% lru_gen_look_around =>1.53% __mmu_notifier_test_clear_young kswapd (MGLRU off) 100.00% balance_pgdat 100.00% shrink_node 99.92% shrink_lruvec 69.95% shrink_folio_list 19.35% folio_referenced 18.37% rmap_walk_file 17.88% folio_referenced_one 13.20% __mmu_notifier_clear_flush_young 11.64% kvm_mmu_notifier_clear_flush_young => 9.93% _raw_write_lock 26.23% shrink_active_list 25.50% folio_referenced 25.35% rmap_walk_file 25.28% folio_referenced_one 23.87% __mmu_notifier_clear_flush_young 23.69% kvm_mmu_notifier_clear_flush_young => 18.98% _raw_write_lock Comprehensive benchmarks are coming soon. Yu Zhao (5): mm/kvm: add mmu_notifier_test_clear_young() kvm/x86: add kvm_arch_test_clear_young() kvm/arm64: add kvm_arch_test_clear_young() kvm/powerpc: add kvm_arch_test_clear_young() mm: multi-gen LRU: use mmu_notifier_test_clear_young() arch/arm64/include/asm/kvm_host.h | 7 ++ arch/arm64/include/asm/kvm_pgtable.h| 8 ++ arch/arm64/include/asm/stage2_pgtable.h | 43 arch/arm64/kvm/arm.c| 1 + arch/arm64/kvm/hyp/pgtable.c| 51 ++ arch/arm64/kvm/mmu.c| 77 +- arch/powerpc/include/asm/kvm_host.h | 18 arch/powerpc/include/asm/kvm_ppc.h | 14 +-- arch/powerpc/kvm/book3s.c | 7 ++ arch/powerpc/kvm/book3s.h | 2 + arch/powerpc/kvm/book3s_64_mmu_radix.c | 78 ++- arch/powerpc/kvm/book3s_hv.c| 10 +- arch/x86/include/asm/kvm_host.h | 27 + arch/x86/kvm/mmu/spte.h | 12 --- arch/x86/kvm/mmu/tdp_mmu.c | 41 include/linux/kvm_host.h| 29 ++ include/linux/mmu_notifier.h| 40 include/linux/mmzone.h | 6 +- mm/mmu_notifier.c | 26 + mm/rmap.c | 8 +- mm/vmscan.c | 127 +---
Re: [PATCH v3 26/35] mm: fall back to mmap_lock if vma->anon_vma is not yet set
On Thu, Feb 16, 2023 at 11:43 AM Suren Baghdasaryan wrote: > > On Thu, Feb 16, 2023 at 7:44 AM Matthew Wilcox wrote: > > > > On Wed, Feb 15, 2023 at 09:17:41PM -0800, Suren Baghdasaryan wrote: > > > When vma->anon_vma is not set, page fault handler will set it by either > > > reusing anon_vma of an adjacent VMA if VMAs are compatible or by > > > allocating a new one. find_mergeable_anon_vma() walks VMA tree to find > > > a compatible adjacent VMA and that requires not only the faulting VMA > > > to be stable but also the tree structure and other VMAs inside that tree. > > > Therefore locking just the faulting VMA is not enough for this search. > > > Fall back to taking mmap_lock when vma->anon_vma is not set. This > > > situation happens only on the first page fault and should not affect > > > overall performance. > > > > I think I asked this before, but don't remember getting an aswer. > > Why do we defer setting anon_vma to the first fault? Why don't we > > set it up at mmap time? > > Yeah, I remember that conversation Matthew and I could not find the > definitive answer at the time. I'll look into that again or maybe > someone can answer it here. After looking into it again I'm still under the impression that vma->anon_vma is populated lazily (during the first page fault rather than at mmap time) to avoid doing extra work for areas which are never faulted. Though I might be missing some important detail here. > > In the end rather than changing that logic I decided to skip > vma->anon_vma==NULL cases because I measured them being less than > 0.01% of all page faults, so ROI from changing that would be quite > low. But I agree that the logic is weird and maybe we can improve > that. I will have to review that again when I'm working on eliminating > all these special cases we skip, like swap/userfaults/etc.
[powerpc:next] BUILD SUCCESS b5ae1cde0f341c936e84e5a9c49f0cb81ba4df1c
tree/branch: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git next branch HEAD: b5ae1cde0f341c936e84e5a9c49f0cb81ba4df1c powerpc/epapr: Don't use wrteei on non booke elapsed time: 727m configs tested: 43 configs skipped: 3 The following configs have been built successfully. More configs may be tested in the coming days. gcc tested configs: alphaallyesconfig alpha defconfig arc allyesconfig arc defconfig arm allmodconfig arm allyesconfig arm defconfig arm64allyesconfig arm64 defconfig cskydefconfig i386 allyesconfig i386 debian-10.3 i386defconfig ia64 allmodconfig ia64defconfig loongarchallmodconfig loongarch allnoconfig loongarch defconfig m68k allmodconfig m68kdefconfig mips allmodconfig mips allyesconfig nios2 defconfig parisc defconfig parisc64defconfig powerpc allmodconfig powerpc allnoconfig riscvallmodconfig riscv allnoconfig riscv defconfig riscv rv32_defconfig s390 allmodconfig s390 allyesconfig s390defconfig sh allmodconfig sparc defconfig um i386_defconfig um x86_64_defconfig x86_64allnoconfig x86_64 allyesconfig x86_64 defconfig x86_64 kexec x86_64 rhel-8.3 -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests
Re: linux-next: build warning after merge of the powerpc tree
Josh Poimboeuf writes: > On Thu, Feb 16, 2023 at 02:40:31PM +1100, Stephen Rothwell wrote: >> Hi all, >> >> After merging the powerpc tree, today's linux-next build (powerpc >> pseries_le_defconfig) produced this warning: >> >> arch/powerpc/kernel/head_64.o: warning: objtool: .text+0x6128: unannotated >> intra-function call >> >> I have no idea what caused this. > > Adding Sathvika and Christophe. > > The short term fix would be something like the below, but... > > If powerpc objtool is only doing mcount, does it even make sense to run > objtool on asm files? If so, there are probably a lot more cleanups > needed for the asm code. I would like to enable more of the objtool checks eventually, although I don't have a timeline for that. But I'd prefer to keep checking the asm code seeing as we've already enabled that. > So I'm thinking either we should cleanup all the powerpc asm code with > annotations like below, or we should try to make objtool mcount-mode > ignore asm files. I think we have most of the code annotated already, this is a new warning because that code is newly refactored by a commit I applied. I'll have to fix my build scripts to error out on objtool warnings. cheers > diff --git a/arch/powerpc/kernel/head_64.S b/arch/powerpc/kernel/head_64.S > index 3a7266fa8a18..1febb56ebaeb 100644 > --- a/arch/powerpc/kernel/head_64.S > +++ b/arch/powerpc/kernel/head_64.S > @@ -472,7 +472,7 @@ SYM_FUNC_START_LOCAL(__mmu_off) > b . /* prevent speculative execution */ > SYM_FUNC_END(__mmu_off) > > -start_initialization_book3s: > +SYM_FUNC_START_LOCAL(start_initialization_book3s) > mflrr25 > > /* Setup some critical 970 SPRs before switching MMU off */ > @@ -494,6 +494,7 @@ start_initialization_book3s: > > mtlrr25 > blr > +SYM_FUNC_END(start_initialization_book3s) > #endif > > /*
[PATCH] powerpc/64s: Prevent fallthrough to hash TLB flush when using radix
In the fix reconnecting hash__tlb_flush() to tlb_flush() the
void return on radix__tlb_flush() was not restored and subsequently
falls through to the restored hash__tlb_flush().
Guard hash__tlb_flush() under an else to prevent this.
Fixes: 1665c027afb2 ("powerpc/64s: Reconnect tlb_flush() to hash__tlb_flush()")
Suggested-by: Christophe Leroy
Signed-off-by: Benjamin Gray
---
Bug report:
https://lore.kernel.org/linuxppc-dev/20230216005535.6bff7aa6@yea/
---
arch/powerpc/include/asm/book3s/64/tlbflush.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/include/asm/book3s/64/tlbflush.h
b/arch/powerpc/include/asm/book3s/64/tlbflush.h
index d5cd16270c5d..2bbc0fcce04a 100644
--- a/arch/powerpc/include/asm/book3s/64/tlbflush.h
+++ b/arch/powerpc/include/asm/book3s/64/tlbflush.h
@@ -97,8 +97,8 @@ static inline void tlb_flush(struct mmu_gather *tlb)
{
if (radix_enabled())
radix__tlb_flush(tlb);
-
- return hash__tlb_flush(tlb);
+ else
+ hash__tlb_flush(tlb);
}
#ifdef CONFIG_SMP
base-commit: 0bfb97203f5f300777624a2ad6f8f84aea3e8658
--
2.39.1
Re: [PATCH v5 00/10] Add the PowerQUICC audio support using the QMC
Herve Codina writes: > Hi, > > This series adds support for audio using the QMC controller available in > some Freescale PowerQUICC SoCs. Who's going to take this series? By lines of code it's mostly in drivers/soc/fsl, so I was expecting it would go via that tree. Or is it a sound series that should go via one of the sound trees? cheers ... > .../soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml | 172 ++ > .../bindings/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml | 234 +++ > .../bindings/sound/fsl,qmc-audio.yaml | 117 ++ > MAINTAINERS | 25 + > arch/powerpc/platforms/8xx/cpm1.c |2 +- > drivers/soc/fsl/qe/Kconfig| 23 + > drivers/soc/fsl/qe/Makefile |2 + > drivers/soc/fsl/qe/qmc.c | 1533 + > drivers/soc/fsl/qe/tsa.c | 869 ++ > drivers/soc/fsl/qe/tsa.h | 42 + > include/dt-bindings/soc/fsl,tsa.h | 13 + > include/soc/fsl/qe/qmc.h | 71 + > sound/soc/fsl/Kconfig |9 + > sound/soc/fsl/Makefile|2 + > sound/soc/fsl/fsl_qmc_audio.c | 735 > 15 files changed, 3848 insertions(+), 1 deletion(-) > create mode 100644 > Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml > create mode 100644 > Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml > create mode 100644 Documentation/devicetree/bindings/sound/fsl,qmc-audio.yaml > create mode 100644 drivers/soc/fsl/qe/qmc.c > create mode 100644 drivers/soc/fsl/qe/tsa.c > create mode 100644 drivers/soc/fsl/qe/tsa.h > create mode 100644 include/dt-bindings/soc/fsl,tsa.h > create mode 100644 include/soc/fsl/qe/qmc.h > create mode 100644 sound/soc/fsl/fsl_qmc_audio.c
Re: [PATCH 1/2] kcsan: xtensa: Add atomic builtin stubs for 32-bit systems
> On 16 Feb 2023, at 7:09 pm, Marco Elver wrote:
>
> On Thu, Feb 16, 2023 at 07:12AM +, Christophe Leroy wrote:
>>
>>
>> Le 16/02/2023 à 06:09, Rohan McLure a écrit :
>>> KCSAN instruments calls to atomic builtins, and will in turn call these
>>> builtins itself. As such, architectures supporting KCSAN must have
>>> compiler support for these atomic primitives.
>>>
>>> Since 32-bit systems are unlikely to have 64-bit compiler builtins,
>>> provide a stub for each missing builtin, and use BUG() to assert
>>> unreachability.
>>>
>>> In commit 725aea873261 ("xtensa: enable KCSAN"), xtensa implements these
>>> locally. Move these definitions to be accessible to all 32-bit
>>> architectures that do not provide the necessary builtins, with opt in
>>> for PowerPC and xtensa.
>>>
>>> Signed-off-by: Rohan McLure
>>> Reviewed-by: Max Filippov
>>
>> This series should also be addressed to KCSAN Maintainers, shouldn't it ?
>>
>> KCSAN
>> M: Marco Elver
>> R: Dmitry Vyukov
>> L: kasan-...@googlegroups.com
>> S: Maintained
>> F: Documentation/dev-tools/kcsan.rst
>> F: include/linux/kcsan*.h
>> F: kernel/kcsan/
>> F: lib/Kconfig.kcsan
>> F: scripts/Makefile.kcsan
>>
>>
>>> ---
>>> Previously issued as a part of a patch series adding KCSAN support to
>>> 64-bit.
>>> Link:
>>> https://lore.kernel.org/linuxppc-dev/167646486000.1421441.10070059569986228558.b4...@ellerman.id.au/T/#t
>>> v1: Remove __has_builtin check, as gcc is not obligated to inline
>>> builtins detected using this check, but instead is permitted to supply
>>> them in libatomic:
>>> Link: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108734
>>> Instead, opt-in PPC32 and xtensa.
>>> ---
>>> arch/xtensa/lib/Makefile | 1 -
>>> kernel/kcsan/Makefile | 2 ++
>>> arch/xtensa/lib/kcsan-stubs.c => kernel/kcsan/stubs.c | 0
>>> 3 files changed, 2 insertions(+), 1 deletion(-)
>>> rename arch/xtensa/lib/kcsan-stubs.c => kernel/kcsan/stubs.c (100%)
>>>
>>> diff --git a/arch/xtensa/lib/Makefile b/arch/xtensa/lib/Makefile
>>> index 7ecef0519a27..d69356dc97df 100644
>>> --- a/arch/xtensa/lib/Makefile
>>> +++ b/arch/xtensa/lib/Makefile
>>> @@ -8,5 +8,4 @@ lib-y += memcopy.o memset.o checksum.o \
>>> divsi3.o udivsi3.o modsi3.o umodsi3.o mulsi3.o umulsidi3.o \
>>> usercopy.o strncpy_user.o strnlen_user.o
>>> lib-$(CONFIG_PCI) += pci-auto.o
>>> -lib-$(CONFIG_KCSAN) += kcsan-stubs.o
>>> KCSAN_SANITIZE_kcsan-stubs.o := n
>>> diff --git a/kernel/kcsan/Makefile b/kernel/kcsan/Makefile
>>> index 8cf70f068d92..86dd713d8855 100644
>>> --- a/kernel/kcsan/Makefile
>>> +++ b/kernel/kcsan/Makefile
>>> @@ -12,6 +12,8 @@ CFLAGS_core.o := $(call cc-option,-fno-conserve-stack) \
>>> -fno-stack-protector -DDISABLE_BRANCH_PROFILING
>>>
>>> obj-y := core.o debugfs.o report.o
>>> +obj-$(CONFIG_PPC32) += stubs.o
>>> +obj-$(CONFIG_XTENSA) += stubs.o
>>
>> Not sure it is acceptable to do it that way.
>>
>> There should likely be something like a CONFIG_ARCH_WANTS_KCSAN_STUBS in
>> KCSAN's Kconfig then PPC32 and XTENSA should select it.
>
> The longer I think about it, since these stubs all BUG() anyway, perhaps
> we ought to just avoid them altogether. If you delete all the stubs from
> ppc and xtensa, but do this:
>
> | diff --git a/kernel/kcsan/core.c b/kernel/kcsan/core.c
> | index 54d077e1a2dc..8169d6dadd0e 100644
> | --- a/kernel/kcsan/core.c
> | +++ b/kernel/kcsan/core.c
> | @@ -1261,7 +1261,9 @@ static __always_inline void
> kcsan_atomic_builtin_memorder(int memorder)
> | DEFINE_TSAN_ATOMIC_OPS(8);
> | DEFINE_TSAN_ATOMIC_OPS(16);
> | DEFINE_TSAN_ATOMIC_OPS(32);
> | +#ifdef CONFIG_64BIT
> | DEFINE_TSAN_ATOMIC_OPS(64);
> | +#endif
> |
> | void __tsan_atomic_thread_fence(int memorder);
> | void __tsan_atomic_thread_fence(int memorder)
>
> Does that work?
This makes much more sense. Rather than assume that kcsan is the only
consumer of __atomic_*_8, and stubbing accordingly, we should just
remove its mention from relevant sub-archs.
Re: [PATCH 2/2] powerpc/{32,book3e}: kcsan: Extend KCSAN Support
> On 16 Feb 2023, at 6:14 pm, Christophe Leroy > wrote: > > > > Le 16/02/2023 à 06:09, Rohan McLure a écrit : >> Enable HAVE_ARCH_KCSAN on all powerpc platforms, permitting use of the >> kernel concurrency sanitiser through the CONFIG_KCSAN_* kconfig options. >> >> Boots and passes selftests on 32-bit and 64-bit platforms. See >> documentation in Documentation/dev-tools/kcsan.rst for more information. >> >> Signed-off-by: Rohan McLure >> --- >> New patch >> --- >> arch/powerpc/Kconfig | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig >> index 2c9cdf1d8761..45771448d47a 100644 >> --- a/arch/powerpc/Kconfig >> +++ b/arch/powerpc/Kconfig >> @@ -197,7 +197,7 @@ config PPC >> select HAVE_ARCH_KASAN if PPC_RADIX_MMU >> select HAVE_ARCH_KASAN if PPC_BOOK3E_64 >> select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN >> - select HAVE_ARCH_KCSAN if PPC_BOOK3S_64 >> + select HAVE_ARCH_KCSAN > > So that's a followup of a not yet posted version v5 of the other series ? > Why not just add patch 1 in that series and have KCSAN for all powerpc > at once ? So the v3 was accepted upstream, likely to appear in 6.3. This patch series is just to extend support to other platforms, once kcsan supports us. Link: https://patchwork.ozlabs.org/project/linuxppc-dev/cover/20230206021801.105268-1-rmcl...@linux.ibm.com/ > >> select HAVE_ARCH_KFENCE if ARCH_SUPPORTS_DEBUG_PAGEALLOC >> select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET >> select HAVE_ARCH_KGDB
RE: [PATCH v5 02/10] soc: fsl: cpm1: Add support for TSA
> -Original Message- > From: Herve Codina > Sent: Thursday, February 16, 2023 7:42 AM > To: Herve Codina ; Leo Li > ; Rob Herring ; Krzysztof > Kozlowski ; Liam Girdwood > ; Mark Brown ; Christophe > Leroy ; Michael Ellerman > ; Nicholas Piggin ; Qiang Zhao > ; Jaroslav Kysela ; Takashi Iwai > ; Shengjiu Wang ; Xiubo Li > ; Fabio Estevam ; Nicolin > Chen > Cc: linuxppc-dev@lists.ozlabs.org; linux-arm-ker...@lists.infradead.org; > devicet...@vger.kernel.org; linux-ker...@vger.kernel.org; alsa-devel@alsa- > project.org; Thomas Petazzoni > Subject: [PATCH v5 02/10] soc: fsl: cpm1: Add support for TSA > > The TSA (Time Slot Assigner) purpose is to route some > TDM time-slots to other internal serial controllers. > > It is available in some PowerQUICC SoC such as the > MPC885 or MPC866. > > It is also available on some Quicc Engine SoCs. > This current version support CPM1 SoCs only and some > enhancement are needed to support Quicc Engine SoCs. > > Signed-off-by: Herve Codina Looks good to me Acked-by: Li Yang > --- > drivers/soc/fsl/qe/Kconfig | 11 + > drivers/soc/fsl/qe/Makefile | 1 + > drivers/soc/fsl/qe/tsa.c| 869 > > drivers/soc/fsl/qe/tsa.h| 42 ++ > 4 files changed, 923 insertions(+) > create mode 100644 drivers/soc/fsl/qe/tsa.c > create mode 100644 drivers/soc/fsl/qe/tsa.h > > diff --git a/drivers/soc/fsl/qe/Kconfig b/drivers/soc/fsl/qe/Kconfig > index 357c5800b112..b0088495c323 100644 > --- a/drivers/soc/fsl/qe/Kconfig > +++ b/drivers/soc/fsl/qe/Kconfig > @@ -33,6 +33,17 @@ config UCC > bool > default y if UCC_FAST || UCC_SLOW > > +config CPM_TSA > + tristate "CPM TSA support" > + depends on OF && HAS_IOMEM > + depends on CPM1 || COMPILE_TEST > + help > + Freescale CPM Time Slot Assigner (TSA) > + controller. > + > + This option enables support for this > + controller > + > config QE_TDM > bool > default y if FSL_UCC_HDLC > diff --git a/drivers/soc/fsl/qe/Makefile b/drivers/soc/fsl/qe/Makefile > index 55a555304f3a..45c961acc81b 100644 > --- a/drivers/soc/fsl/qe/Makefile > +++ b/drivers/soc/fsl/qe/Makefile > @@ -4,6 +4,7 @@ > # > obj-$(CONFIG_QUICC_ENGINE)+= qe.o qe_common.o qe_ic.o qe_io.o > obj-$(CONFIG_CPM)+= qe_common.o > +obj-$(CONFIG_CPM_TSA)+= tsa.o > obj-$(CONFIG_UCC)+= ucc.o > obj-$(CONFIG_UCC_SLOW) += ucc_slow.o > obj-$(CONFIG_UCC_FAST) += ucc_fast.o > diff --git a/drivers/soc/fsl/qe/tsa.c b/drivers/soc/fsl/qe/tsa.c > new file mode 100644 > index ..90d9a5254d9b > --- /dev/null > +++ b/drivers/soc/fsl/qe/tsa.c > @@ -0,0 +1,869 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * TSA driver > + * > + * Copyright 2022 CS GROUP France > + * > + * Author: Herve Codina > + */ > + > +#include "tsa.h" > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > + > +/* TSA SI RAM routing tables entry */ > +#define TSA_SIRAM_ENTRY_LAST (1 << 16) > +#define TSA_SIRAM_ENTRY_BYTE (1 << 17) > +#define TSA_SIRAM_ENTRY_CNT(x) (((x) & 0x0f) << 18) > +#define TSA_SIRAM_ENTRY_CSEL_MASK(0x7 << 22) > +#define TSA_SIRAM_ENTRY_CSEL_NU (0x0 << 22) > +#define TSA_SIRAM_ENTRY_CSEL_SCC2(0x2 << 22) > +#define TSA_SIRAM_ENTRY_CSEL_SCC3(0x3 << 22) > +#define TSA_SIRAM_ENTRY_CSEL_SCC4(0x4 << 22) > +#define TSA_SIRAM_ENTRY_CSEL_SMC1(0x5 << 22) > +#define TSA_SIRAM_ENTRY_CSEL_SMC2(0x6 << 22) > + > +/* SI mode register (32 bits) */ > +#define TSA_SIMODE 0x00 > +#define TSA_SIMODE_SMC20x8000 > +#define TSA_SIMODE_SMC10x8000 > +#define TSA_SIMODE_TDMA(x) ((x) << 0) > +#define TSA_SIMODE_TDMB(x) ((x) << 16) > +#define TSA_SIMODE_TDM_MASK 0x0fff > +#define TSA_SIMODE_TDM_SDM_MASK 0x0c00 > +#define TSA_SIMODE_TDM_SDM_NORM0x > +#define TSA_SIMODE_TDM_SDM_ECHO0x0400 > +#define TSA_SIMODE_TDM_SDM_INTL_LOOP 0x0800 > +#define TSA_SIMODE_TDM_SDM_LOOP_CTRL 0x0c00 > +#define TSA_SIMODE_TDM_RFSD(x) ((x) << 8) > +#define TSA_SIMODE_TDM_DSC 0x0080 > +#define TSA_SIMODE_TDM_CRT 0x0040 > +#define TSA_SIMODE_TDM_STZ 0x0020 > +#define TSA_SIMODE_TDM_CE0x0010 > +#define TSA_SIMODE_TDM_FE0x0008 > +#define TSA_SIMODE_TDM_GM0x0004 > +#define TSA_SIMODE_TDM_TFSD(x) ((x) << 0) > + > +/* SI global mode register (8 bits) */ > +#define TSA_SIGMR0x04 > +#define TSA_SIGMR_ENB(1<<3) > +#define TSA_SIGMR_ENA(1<<2) > +#define TSA_SIGMR_RDM_MASK 0x03 > +#define TSA_SIGMR_RDM_STATIC_TDMA 0x00 > +#define
Re: [PATCH v3 26/35] mm: fall back to mmap_lock if vma->anon_vma is not yet set
On Thu, Feb 16, 2023 at 7:44 AM Matthew Wilcox wrote: > > On Wed, Feb 15, 2023 at 09:17:41PM -0800, Suren Baghdasaryan wrote: > > When vma->anon_vma is not set, page fault handler will set it by either > > reusing anon_vma of an adjacent VMA if VMAs are compatible or by > > allocating a new one. find_mergeable_anon_vma() walks VMA tree to find > > a compatible adjacent VMA and that requires not only the faulting VMA > > to be stable but also the tree structure and other VMAs inside that tree. > > Therefore locking just the faulting VMA is not enough for this search. > > Fall back to taking mmap_lock when vma->anon_vma is not set. This > > situation happens only on the first page fault and should not affect > > overall performance. > > I think I asked this before, but don't remember getting an aswer. > Why do we defer setting anon_vma to the first fault? Why don't we > set it up at mmap time? Yeah, I remember that conversation Matthew and I could not find the definitive answer at the time. I'll look into that again or maybe someone can answer it here. In the end rather than changing that logic I decided to skip vma->anon_vma==NULL cases because I measured them being less than 0.01% of all page faults, so ROI from changing that would be quite low. But I agree that the logic is weird and maybe we can improve that. I will have to review that again when I'm working on eliminating all these special cases we skip, like swap/userfaults/etc.
Re: [PATCH v3 21/35] mm/mmap: write-lock adjacent VMAs if they can grow into unmapped area
On Thu, Feb 16, 2023 at 7:34 AM Liam R. Howlett wrote:
>
>
> First, sorry I didn't see this before v3..
Feedback at any time is highly appreciated!
>
> * Suren Baghdasaryan [230216 00:18]:
> > While unmapping VMAs, adjacent VMAs might be able to grow into the area
> > being unmapped. In such cases write-lock adjacent VMAs to prevent this
> > growth.
> >
> > Signed-off-by: Suren Baghdasaryan
> > ---
> > mm/mmap.c | 8 +---
> > 1 file changed, 5 insertions(+), 3 deletions(-)
> >
> > diff --git a/mm/mmap.c b/mm/mmap.c
> > index 118b2246bba9..00f8c5798936 100644
> > --- a/mm/mmap.c
> > +++ b/mm/mmap.c
> > @@ -2399,11 +2399,13 @@ do_vmi_align_munmap(struct vma_iterator *vmi,
> > struct vm_area_struct *vma,
> >* down_read(mmap_lock) and collide with the VMA we are about to
> > unmap.
> >*/
> > if (downgrade) {
> > - if (next && (next->vm_flags & VM_GROWSDOWN))
> > + if (next && (next->vm_flags & VM_GROWSDOWN)) {
> > + vma_start_write(next);
> > downgrade = false;
>
> If the mmap write lock is insufficient to protect us from next/prev
> modifications then we need to move *most* of this block above the maple
> tree write operation, otherwise we have a race here. When I say most, I
> mean everything besides the call to mmap_write_downgrade() needs to be
> moved.
Which prior maple tree write operation are you referring to? I see
__split_vma() and munmap_sidetree() which both already lock the VMAs
they operate on, so page faults can't happen in those VMAs.
>
> If the mmap write lock is sufficient to protect us from next/prev
> modifications then we don't need to write lock the vmas themselves.
mmap write lock is not sufficient because with per-VMA locks we do not
take mmap lock at all.
>
> I believe this is for expand_stack() protection, so I believe it's okay
> to not vma write lock these vmas.. I don't think there are other areas
> where we can modify the vmas without holding the mmap lock, but others
> on the CC list please chime in if I've forgotten something.
>
> So, if I am correct, then you shouldn't lock next/prev and allow the
> vma locking fault method on these vmas. This will work because
> lock_vma_under_rcu() uses mas_walk() on the faulting address. That is,
> your lock_vma_under_rcu() will fail to find anything that needs to be
> grown and go back to mmap lock protection. As it is written today, the
> vma locking fault handler will fail and we will wait for the mmap lock
> to be released even when the vma isn't going to expand.
So, let's consider a case when the next VMA is not being removed (so
it was neither removed nor locked by munmap_sidetree()) and it is
found by lock_vma_under_rcu() in the page fault handling path. Page
fault handler can now expand it and push into the area we are
unmapping in unmap_region(). That is the race I'm trying to prevent
here by locking the next/prev VMAs which can be expanded before
unmap_region() unmaps them. Am I missing something?
>
>
> > - else if (prev && (prev->vm_flags & VM_GROWSUP))
> > + } else if (prev && (prev->vm_flags & VM_GROWSUP)) {
> > + vma_start_write(prev);
> > downgrade = false;
> > - else
> > + } else
> > mmap_write_downgrade(mm);
> > }
> >
> > --
> > 2.39.1
>
> --
> To unsubscribe from this group and stop receiving emails from it, send an
> email to kernel-team+unsubscr...@android.com.
>
[PATCH v2.1 09/24] mips/cpu: Expose play_dead()'s prototype definition
Include to make sure play_dead() matches its prototype going forward. Acked-by: Florian Fainelli Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Josh Poimboeuf --- arch/mips/cavium-octeon/smp.c | 1 + arch/mips/kernel/smp-bmips.c | 1 + arch/mips/kernel/smp-cps.c| 1 + arch/mips/loongson64/smp.c| 1 + 4 files changed, 4 insertions(+) diff --git a/arch/mips/cavium-octeon/smp.c b/arch/mips/cavium-octeon/smp.c index 89954f5f87fb..4212584e6efa 100644 --- a/arch/mips/cavium-octeon/smp.c +++ b/arch/mips/cavium-octeon/smp.c @@ -20,6 +20,7 @@ #include #include #include +#include #include diff --git a/arch/mips/kernel/smp-bmips.c b/arch/mips/kernel/smp-bmips.c index f5d7bfa3472a..df9158e8329d 100644 --- a/arch/mips/kernel/smp-bmips.c +++ b/arch/mips/kernel/smp-bmips.c @@ -38,6 +38,7 @@ #include #include #include +#include static int __maybe_unused max_cpus = 1; diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c index bcd6a944b839..6d69a9ba8167 100644 --- a/arch/mips/kernel/smp-cps.c +++ b/arch/mips/kernel/smp-cps.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/mips/loongson64/smp.c b/arch/mips/loongson64/smp.c index 660e1de4412a..4e24b317e7cb 100644 --- a/arch/mips/loongson64/smp.c +++ b/arch/mips/loongson64/smp.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include -- 2.39.1
[PATCH v2.1 04/24] arm64/cpu: Mark cpu_die() __noreturn
cpu_die() doesn't return. Annotate it as such. By extension this also
makes arch_cpu_idle_dead() noreturn.
Acked-by: Mark Rutland
Signed-off-by: Josh Poimboeuf
---
arch/arm64/include/asm/smp.h | 2 +-
arch/arm64/kernel/smp.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/include/asm/smp.h b/arch/arm64/include/asm/smp.h
index fc55f5a57a06..5733a31bab08 100644
--- a/arch/arm64/include/asm/smp.h
+++ b/arch/arm64/include/asm/smp.h
@@ -100,7 +100,7 @@ static inline void arch_send_wakeup_ipi_mask(const struct
cpumask *mask)
extern int __cpu_disable(void);
extern void __cpu_die(unsigned int cpu);
-extern void cpu_die(void);
+extern void __noreturn cpu_die(void);
extern void cpu_die_early(void);
static inline void cpu_park_loop(void)
diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c
index 4e8327264255..d5d09a18b4f8 100644
--- a/arch/arm64/kernel/smp.c
+++ b/arch/arm64/kernel/smp.c
@@ -361,7 +361,7 @@ void __cpu_die(unsigned int cpu)
* Called from the idle thread for the CPU which has been shutdown.
*
*/
-void cpu_die(void)
+void __noreturn cpu_die(void)
{
unsigned int cpu = smp_processor_id();
const struct cpu_operations *ops = get_cpu_ops(cpu);
--
2.39.1
[PATCH v2.1 03/24] arm/cpu: Add unreachable() to arch_cpu_idle_dead()
arch_cpu_idle_dead() doesn't return. Make that visible to the compiler with an unreachable() code annotation. Signed-off-by: Josh Poimboeuf --- arch/arm/kernel/smp.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c index 0b8c25763adc..441ea5cff390 100644 --- a/arch/arm/kernel/smp.c +++ b/arch/arm/kernel/smp.c @@ -382,6 +382,8 @@ void arch_cpu_idle_dead(void) : "r" (task_stack_page(current) + THREAD_SIZE - 8), "r" (current) : "r0"); + + unreachable(); } #endif /* CONFIG_HOTPLUG_CPU */ -- 2.39.1
Re: [PATCH] powerpc/perf: Add json metric events to present CPI stall cycles in powerpc
On Wed, Feb 15, 2023 at 10:12 PM Athira Rajeev
wrote:
>
> Power10 Performance Monitoring Unit (PMU) provides events
> to understand stall cycles of different pipeline stages.
> These events along with completed instructions provides
> useful metrics for application tuning.
>
> Patch implements the json changes to collect counter statistics
> to present the high level CPI stall breakdown metrics. New metric
> group is named as "CPI_STALL_RATIO" and this new metric group
> presents these stall metrics:
> - DISPATCHED_CPI ( Dispatch stall cycles per insn )
> - ISSUE_STALL_CPI ( Issue stall cycles per insn )
> - EXECUTION_STALL_CPI ( Execution stall cycles per insn )
> - COMPLETION_STALL_CPI ( Completition stall cycles per insn )
>
> To avoid multipling of events, PM_RUN_INST_CMPL event has been
> modified to use PMC5(performance monitoring counter5) instead
> of PMC4. This change is needed, since completion stall event
> is using PMC4.
>
> Usage example:
>
> ./perf stat --metric-no-group -M CPI_STALL_RATIO
>
> Performance counter stats for 'workload':
>
> 63,056,817,982 PM_CMPL_STALL# 0.28
> COMPLETION_STALL_CPI
> 1,743,988,038,896 PM_ISSUE_STALL # 7.73
> ISSUE_STALL_CPI
>225,597,495,030 PM_RUN_INST_CMPL # 6.18
> DISPATCHED_CPI
> #37.48
> EXECUTION_STALL_CPI
> 1,393,916,546,654 PM_DISP_STALL_CYC
> 8,455,376,836,463 PM_EXEC_STALL
>
> "--metric-no-group" is used for forcing PM_RUN_INST_CMPL to be scheduled
> in all group for more accuracy.
>
> Signed-off-by: Athira Rajeev
Acked-by: Ian Rogers
Thanks,
Ian
> ---
> tools/perf/pmu-events/arch/powerpc/power10/metrics.json | 8
> tools/perf/pmu-events/arch/powerpc/power10/others.json | 2 +-
> 2 files changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/tools/perf/pmu-events/arch/powerpc/power10/metrics.json
> b/tools/perf/pmu-events/arch/powerpc/power10/metrics.json
> index b57526fa44f2..6f53583a0c62 100644
> --- a/tools/perf/pmu-events/arch/powerpc/power10/metrics.json
> +++ b/tools/perf/pmu-events/arch/powerpc/power10/metrics.json
> @@ -15,7 +15,7 @@
> {
> "BriefDescription": "Average cycles per completed instruction when
> dispatch was stalled for any reason",
> "MetricExpr": "PM_DISP_STALL_CYC / PM_RUN_INST_CMPL",
> -"MetricGroup": "CPI",
> +"MetricGroup": "CPI;CPI_STALL_RATIO",
> "MetricName": "DISPATCHED_CPI"
> },
> {
> @@ -147,13 +147,13 @@
> {
> "BriefDescription": "Average cycles per completed instruction when
> the NTC instruction has been dispatched but not issued for any reason",
> "MetricExpr": "PM_ISSUE_STALL / PM_RUN_INST_CMPL",
> -"MetricGroup": "CPI",
> +"MetricGroup": "CPI;CPI_STALL_RATIO",
> "MetricName": "ISSUE_STALL_CPI"
> },
> {
> "BriefDescription": "Average cycles per completed instruction when
> the NTC instruction is waiting to be finished in one of the execution units",
> "MetricExpr": "PM_EXEC_STALL / PM_RUN_INST_CMPL",
> -"MetricGroup": "CPI",
> +"MetricGroup": "CPI;CPI_STALL_RATIO",
> "MetricName": "EXECUTION_STALL_CPI"
> },
> {
> @@ -309,7 +309,7 @@
> {
> "BriefDescription": "Average cycles per completed instruction when
> the NTC instruction cannot complete because the thread was blocked",
> "MetricExpr": "PM_CMPL_STALL / PM_RUN_INST_CMPL",
> -"MetricGroup": "CPI",
> +"MetricGroup": "CPI;CPI_STALL_RATIO",
> "MetricName": "COMPLETION_STALL_CPI"
> },
> {
> diff --git a/tools/perf/pmu-events/arch/powerpc/power10/others.json
> b/tools/perf/pmu-events/arch/powerpc/power10/others.json
> index 7d0de1a2860b..a771e4b6bec5 100644
> --- a/tools/perf/pmu-events/arch/powerpc/power10/others.json
> +++ b/tools/perf/pmu-events/arch/powerpc/power10/others.json
> @@ -265,7 +265,7 @@
> "BriefDescription": "Load Missed L1, counted at finish time."
>},
>{
> -"EventCode": "0x400FA",
> +"EventCode": "0x500FA",
> "EventName": "PM_RUN_INST_CMPL",
> "BriefDescription": "Completed PowerPC instructions gated by the run
> latch."
>}
> --
> 2.31.1
>
Re: linux-next: build warning after merge of the powerpc tree
On Thu, Feb 16, 2023 at 02:40:31PM +1100, Stephen Rothwell wrote: > Hi all, > > After merging the powerpc tree, today's linux-next build (powerpc > pseries_le_defconfig) produced this warning: > > arch/powerpc/kernel/head_64.o: warning: objtool: .text+0x6128: unannotated > intra-function call > > I have no idea what caused this. Adding Sathvika and Christophe. The short term fix would be something like the below, but... If powerpc objtool is only doing mcount, does it even make sense to run objtool on asm files? If so, there are probably a lot more cleanups needed for the asm code. So I'm thinking either we should cleanup all the powerpc asm code with annotations like below, or we should try to make objtool mcount-mode ignore asm files. diff --git a/arch/powerpc/kernel/head_64.S b/arch/powerpc/kernel/head_64.S index 3a7266fa8a18..1febb56ebaeb 100644 --- a/arch/powerpc/kernel/head_64.S +++ b/arch/powerpc/kernel/head_64.S @@ -472,7 +472,7 @@ SYM_FUNC_START_LOCAL(__mmu_off) b . /* prevent speculative execution */ SYM_FUNC_END(__mmu_off) -start_initialization_book3s: +SYM_FUNC_START_LOCAL(start_initialization_book3s) mflrr25 /* Setup some critical 970 SPRs before switching MMU off */ @@ -494,6 +494,7 @@ start_initialization_book3s: mtlrr25 blr +SYM_FUNC_END(start_initialization_book3s) #endif /*
Re: [PATCH v3 26/35] mm: fall back to mmap_lock if vma->anon_vma is not yet set
On Wed, Feb 15, 2023 at 09:17:41PM -0800, Suren Baghdasaryan wrote: > When vma->anon_vma is not set, page fault handler will set it by either > reusing anon_vma of an adjacent VMA if VMAs are compatible or by > allocating a new one. find_mergeable_anon_vma() walks VMA tree to find > a compatible adjacent VMA and that requires not only the faulting VMA > to be stable but also the tree structure and other VMAs inside that tree. > Therefore locking just the faulting VMA is not enough for this search. > Fall back to taking mmap_lock when vma->anon_vma is not set. This > situation happens only on the first page fault and should not affect > overall performance. I think I asked this before, but don't remember getting an aswer. Why do we defer setting anon_vma to the first fault? Why don't we set it up at mmap time?
Re: [PATCH v3 21/35] mm/mmap: write-lock adjacent VMAs if they can grow into unmapped area
First, sorry I didn't see this before v3..
* Suren Baghdasaryan [230216 00:18]:
> While unmapping VMAs, adjacent VMAs might be able to grow into the area
> being unmapped. In such cases write-lock adjacent VMAs to prevent this
> growth.
>
> Signed-off-by: Suren Baghdasaryan
> ---
> mm/mmap.c | 8 +---
> 1 file changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/mm/mmap.c b/mm/mmap.c
> index 118b2246bba9..00f8c5798936 100644
> --- a/mm/mmap.c
> +++ b/mm/mmap.c
> @@ -2399,11 +2399,13 @@ do_vmi_align_munmap(struct vma_iterator *vmi, struct
> vm_area_struct *vma,
>* down_read(mmap_lock) and collide with the VMA we are about to unmap.
>*/
> if (downgrade) {
> - if (next && (next->vm_flags & VM_GROWSDOWN))
> + if (next && (next->vm_flags & VM_GROWSDOWN)) {
> + vma_start_write(next);
> downgrade = false;
If the mmap write lock is insufficient to protect us from next/prev
modifications then we need to move *most* of this block above the maple
tree write operation, otherwise we have a race here. When I say most, I
mean everything besides the call to mmap_write_downgrade() needs to be
moved.
If the mmap write lock is sufficient to protect us from next/prev
modifications then we don't need to write lock the vmas themselves.
I believe this is for expand_stack() protection, so I believe it's okay
to not vma write lock these vmas.. I don't think there are other areas
where we can modify the vmas without holding the mmap lock, but others
on the CC list please chime in if I've forgotten something.
So, if I am correct, then you shouldn't lock next/prev and allow the
vma locking fault method on these vmas. This will work because
lock_vma_under_rcu() uses mas_walk() on the faulting address. That is,
your lock_vma_under_rcu() will fail to find anything that needs to be
grown and go back to mmap lock protection. As it is written today, the
vma locking fault handler will fail and we will wait for the mmap lock
to be released even when the vma isn't going to expand.
> - else if (prev && (prev->vm_flags & VM_GROWSUP))
> + } else if (prev && (prev->vm_flags & VM_GROWSUP)) {
> + vma_start_write(prev);
> downgrade = false;
> - else
> + } else
> mmap_write_downgrade(mm);
> }
>
> --
> 2.39.1
Re: Bug: Write fault blocked by KUAP! (kernel 6.2-rc6, Talos II)
On Thu, 9 Feb 2023 07:21:55 +
Christophe Leroy wrote:
> An easy fix would probably be to also check the suffix as a prefixed
> instruction with 0 as suffix is not valid :
>
> diff --git a/arch/powerpc/include/asm/inst.h
> b/arch/powerpc/include/asm/inst.h
> index 684d3f453282..87084a52598b 100644
> --- a/arch/powerpc/include/asm/inst.h
> +++ b/arch/powerpc/include/asm/inst.h
> @@ -86,7 +86,7 @@ static inline ppc_inst_t ppc_inst_read(const u32 *ptr)
>
> static inline bool ppc_inst_prefixed(ppc_inst_t x)
> {
> - return IS_ENABLED(CONFIG_PPC64) && ppc_inst_primary_opcode(x) ==
> OP_PREFIX;
> + return IS_ENABLED(CONFIG_PPC64) && ppc_inst_primary_opcode(x) ==
> OP_PREFIX && ppc_inst_suffix(x);
> }
>
> static inline ppc_inst_t ppc_inst_swab(ppc_inst_t x)
Your patch works fine for me! Applied on top of v6.2-rc7 and in the resulting
kernel the Write fault is gone. Thanks!
Regards,
Erhard
[PATCH v5 10/10] MAINTAINERS: add the Freescale QMC audio entry
After contributing the component, add myself as the maintainer for the Freescale QMC audio ASoC component. Signed-off-by: Herve Codina --- MAINTAINERS | 8 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index f8d0981a16ca..a677e2862878 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -8440,6 +8440,14 @@ F: sound/soc/fsl/fsl* F: sound/soc/fsl/imx* F: sound/soc/fsl/mpc8610_hpcd.c +FREESCALE SOC SOUND QMC DRIVER +M: Herve Codina +L: alsa-de...@alsa-project.org (moderated for non-subscribers) +L: linuxppc-dev@lists.ozlabs.org +S: Maintained +F: Documentation/devicetree/bindings/sound/fsl,qmc-audio.yaml +F: sound/soc/fsl/fsl_qmc_audio.c + FREESCALE USB PERIPHERAL DRIVERS M: Li Yang L: linux-...@vger.kernel.org -- 2.39.1
[PATCH v5 09/10] ASoC: fsl: Add support for QMC audio
The QMC audio is an ASoC component which provides DAIs
that use the QMC (QUICC Multichannel Controller) to transfer
the audio data.
It provides as many DAIs as the number of QMC channels it
references.
Signed-off-by: Herve Codina
---
sound/soc/fsl/Kconfig | 9 +
sound/soc/fsl/Makefile| 2 +
sound/soc/fsl/fsl_qmc_audio.c | 735 ++
3 files changed, 746 insertions(+)
create mode 100644 sound/soc/fsl/fsl_qmc_audio.c
diff --git a/sound/soc/fsl/Kconfig b/sound/soc/fsl/Kconfig
index 614eceda6b9e..17db29c25d96 100644
--- a/sound/soc/fsl/Kconfig
+++ b/sound/soc/fsl/Kconfig
@@ -172,6 +172,15 @@ config SND_MPC52xx_DMA
config SND_SOC_POWERPC_DMA
tristate
+config SND_SOC_POWERPC_QMC_AUDIO
+ tristate "QMC ALSA SoC support"
+ depends on CPM_QMC
+ help
+ ALSA SoC Audio support using the Freescale QUICC Multichannel
+ Controller (QMC).
+ Say Y or M if you want to add support for SoC audio using Freescale
+ QMC.
+
comment "SoC Audio support for Freescale PPC boards:"
config SND_SOC_MPC8610_HPCD
diff --git a/sound/soc/fsl/Makefile b/sound/soc/fsl/Makefile
index b54beb1a66fa..8db7e97d0bd5 100644
--- a/sound/soc/fsl/Makefile
+++ b/sound/soc/fsl/Makefile
@@ -28,6 +28,7 @@ snd-soc-fsl-easrc-objs := fsl_easrc.o
snd-soc-fsl-xcvr-objs := fsl_xcvr.o
snd-soc-fsl-aud2htx-objs := fsl_aud2htx.o
snd-soc-fsl-rpmsg-objs := fsl_rpmsg.o
+snd-soc-fsl-qmc-audio-objs := fsl_qmc_audio.o
obj-$(CONFIG_SND_SOC_FSL_AUDMIX) += snd-soc-fsl-audmix.o
obj-$(CONFIG_SND_SOC_FSL_ASOC_CARD) += snd-soc-fsl-asoc-card.o
@@ -44,6 +45,7 @@ obj-$(CONFIG_SND_SOC_POWERPC_DMA) += snd-soc-fsl-dma.o
obj-$(CONFIG_SND_SOC_FSL_XCVR) += snd-soc-fsl-xcvr.o
obj-$(CONFIG_SND_SOC_FSL_AUD2HTX) += snd-soc-fsl-aud2htx.o
obj-$(CONFIG_SND_SOC_FSL_RPMSG) += snd-soc-fsl-rpmsg.o
+obj-$(CONFIG_SND_SOC_POWERPC_QMC_AUDIO) += snd-soc-fsl-qmc-audio.o
# MPC5200 Platform Support
obj-$(CONFIG_SND_MPC52xx_DMA) += mpc5200_dma.o
diff --git a/sound/soc/fsl/fsl_qmc_audio.c b/sound/soc/fsl/fsl_qmc_audio.c
new file mode 100644
index ..7cbb8e4758cc
--- /dev/null
+++ b/sound/soc/fsl/fsl_qmc_audio.c
@@ -0,0 +1,735 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * ALSA SoC using the QUICC Multichannel Controller (QMC)
+ *
+ * Copyright 2022 CS GROUP France
+ *
+ * Author: Herve Codina
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+struct qmc_dai {
+ char *name;
+ int id;
+ struct device *dev;
+ struct qmc_chan *qmc_chan;
+ unsigned int nb_tx_ts;
+ unsigned int nb_rx_ts;
+};
+
+struct qmc_audio {
+ struct device *dev;
+ unsigned int num_dais;
+ struct qmc_dai *dais;
+ struct snd_soc_dai_driver *dai_drivers;
+};
+
+struct qmc_dai_prtd {
+ struct qmc_dai *qmc_dai;
+ dma_addr_t dma_buffer_start;
+ dma_addr_t period_ptr_submitted;
+ dma_addr_t period_ptr_ended;
+ dma_addr_t dma_buffer_end;
+ size_t period_size;
+ struct snd_pcm_substream *substream;
+};
+
+static int qmc_audio_pcm_construct(struct snd_soc_component *component,
+ struct snd_soc_pcm_runtime *rtd)
+{
+ struct snd_card *card = rtd->card->snd_card;
+ int ret;
+
+ ret = dma_coerce_mask_and_coherent(card->dev, DMA_BIT_MASK(32));
+ if (ret)
+ return ret;
+
+ snd_pcm_set_managed_buffer_all(rtd->pcm, SNDRV_DMA_TYPE_DEV, card->dev,
+ 64*1024, 64*1024);
+ return 0;
+}
+
+static int qmc_audio_pcm_hw_params(struct snd_soc_component *component,
+ struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ struct snd_pcm_runtime *runtime = substream->runtime;
+ struct qmc_dai_prtd *prtd = substream->runtime->private_data;
+
+ prtd->dma_buffer_start = runtime->dma_addr;
+ prtd->dma_buffer_end = runtime->dma_addr + params_buffer_bytes(params);
+ prtd->period_size = params_period_bytes(params);
+ prtd->period_ptr_submitted = prtd->dma_buffer_start;
+ prtd->period_ptr_ended = prtd->dma_buffer_start;
+ prtd->substream = substream;
+
+ return 0;
+}
+
+static void qmc_audio_pcm_write_complete(void *context)
+{
+ struct qmc_dai_prtd *prtd = context;
+ int ret;
+
+ prtd->period_ptr_ended += prtd->period_size;
+ if (prtd->period_ptr_ended >= prtd->dma_buffer_end)
+ prtd->period_ptr_ended = prtd->dma_buffer_start;
+
+ prtd->period_ptr_submitted += prtd->period_size;
+ if (prtd->period_ptr_submitted >= prtd->dma_buffer_end)
+ prtd->period_ptr_submitted = prtd->dma_buffer_start;
+
+ ret = qmc_chan_write_submit(prtd->qmc_dai->qmc_chan,
+ prtd->period_ptr_submitted, prtd->period_size,
+ qmc_audio_pcm_write_complete,
[PATCH v5 08/10] dt-bindings: sound: Add support for QMC audio
The QMC (QUICC mutichannel controller) is a controller
present in some PowerQUICC SoC such as MPC885.
The QMC audio is an ASoC component that uses the QMC
controller to transfer the audio data.
Signed-off-by: Herve Codina
Reviewed-by: Krzysztof Kozlowski
---
.../bindings/sound/fsl,qmc-audio.yaml | 117 ++
1 file changed, 117 insertions(+)
create mode 100644 Documentation/devicetree/bindings/sound/fsl,qmc-audio.yaml
diff --git a/Documentation/devicetree/bindings/sound/fsl,qmc-audio.yaml
b/Documentation/devicetree/bindings/sound/fsl,qmc-audio.yaml
new file mode 100644
index ..ff5cd9241941
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/fsl,qmc-audio.yaml
@@ -0,0 +1,117 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/fsl,qmc-audio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: QMC audio
+
+maintainers:
+ - Herve Codina
+
+description: |
+ The QMC audio is an ASoC component which uses QMC (QUICC Multichannel
+ Controller) channels to transfer the audio data.
+ It provides as many DAI as the number of QMC channel used.
+
+allOf:
+ - $ref: dai-common.yaml#
+
+properties:
+ compatible:
+const: fsl,qmc-audio
+
+ '#address-cells':
+const: 1
+ '#size-cells':
+const: 0
+ '#sound-dai-cells':
+const: 1
+
+patternProperties:
+ '^dai@([0-9]|[1-5][0-9]|6[0-3])$':
+description:
+ A DAI managed by this controller
+type: object
+
+properties:
+ reg:
+minimum: 0
+maximum: 63
+description:
+ The DAI number
+
+ fsl,qmc-chan:
+$ref: /schemas/types.yaml#/definitions/phandle-array
+items:
+ - items:
+ - description: phandle to QMC node
+ - description: Channel number
+description:
+ Should be a phandle/number pair. The phandle to QMC node and the QMC
+ channel to use for this DAI.
+
+required:
+ - reg
+ - fsl,qmc-chan
+
+required:
+ - compatible
+ - '#address-cells'
+ - '#size-cells'
+ - '#sound-dai-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+audio_controller: audio-controller {
+compatible = "fsl,qmc-audio";
+#address-cells = <1>;
+#size-cells = <0>;
+#sound-dai-cells = <1>;
+dai@16 {
+reg = <16>;
+fsl,qmc-chan = < 16>;
+};
+dai@17 {
+reg = <17>;
+fsl,qmc-chan = < 17>;
+};
+};
+
+sound {
+compatible = "simple-audio-card";
+#address-cells = <1>;
+#size-cells = <0>;
+simple-audio-card,dai-link@0 {
+reg = <0>;
+format = "dsp_b";
+cpu {
+sound-dai = <_controller 16>;
+};
+codec {
+sound-dai = <>;
+dai-tdm-slot-num = <4>;
+dai-tdm-slot-width = <8>;
+/* TS 3, 5, 7, 9 */
+dai-tdm-slot-tx-mask = <0 0 0 1 0 1 0 1 0 1>;
+dai-tdm-slot-rx-mask = <0 0 0 1 0 1 0 1 0 1>;
+};
+};
+simple-audio-card,dai-link@1 {
+reg = <1>;
+format = "dsp_b";
+cpu {
+sound-dai = <_controller 17>;
+};
+codec {
+sound-dai = <>;
+dai-tdm-slot-num = <4>;
+dai-tdm-slot-width = <8>;
+/* TS 2, 4, 6, 8 */
+dai-tdm-slot-tx-mask = <0 0 1 0 1 0 1 0 1>;
+dai-tdm-slot-rx-mask = <0 0 1 0 1 0 1 0 1>;
+};
+};
+};
--
2.39.1
[PATCH v5 07/10] MAINTAINERS: add the Freescale QMC controller entry
After contributing the driver, add myself as the maintainer for the Freescale QMC controller. Signed-off-by: Herve Codina --- MAINTAINERS | 8 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 0cfedb2f712c..f8d0981a16ca 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -8372,6 +8372,14 @@ S: Maintained F: drivers/soc/fsl/qe/ F: include/soc/fsl/qe/ +FREESCALE QUICC ENGINE QMC DRIVER +M: Herve Codina +L: linuxppc-dev@lists.ozlabs.org +S: Maintained +F: Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml +F: drivers/soc/fsl/qe/qmc.c +F: include/soc/fsl/qe/qmc.h + FREESCALE QUICC ENGINE TSA DRIVER M: Herve Codina L: linuxppc-dev@lists.ozlabs.org -- 2.39.1
[PATCH v5 06/10] soc: fsl: cpm1: Add support for QMC
The QMC (QUICC Multichannel Controller) emulates up to 64 channels within one serial controller using the same TDM physical interface routed from the TSA. It is available in some PowerQUICC SoC such as the MPC885 or MPC866. It is also available on some Quicc Engine SoCs. This current version support CPM1 SoCs only and some enhancement are needed to support Quicc Engine SoCs. Signed-off-by: Herve Codina Acked-by: Li Yang --- drivers/soc/fsl/qe/Kconfig | 12 + drivers/soc/fsl/qe/Makefile |1 + drivers/soc/fsl/qe/qmc.c| 1533 +++ include/soc/fsl/qe/qmc.h| 71 ++ 4 files changed, 1617 insertions(+) create mode 100644 drivers/soc/fsl/qe/qmc.c create mode 100644 include/soc/fsl/qe/qmc.h diff --git a/drivers/soc/fsl/qe/Kconfig b/drivers/soc/fsl/qe/Kconfig index b0088495c323..f90cfdf0c763 100644 --- a/drivers/soc/fsl/qe/Kconfig +++ b/drivers/soc/fsl/qe/Kconfig @@ -44,6 +44,18 @@ config CPM_TSA This option enables support for this controller +config CPM_QMC + tristate "CPM QMC support" + depends on OF && HAS_IOMEM + depends on CPM1 || (SOC_FSL && COMPILE_TEST) + depends on CPM_TSA + help + Freescale CPM QUICC Multichannel Controller + (QMC) + + This option enables support for this + controller + config QE_TDM bool default y if FSL_UCC_HDLC diff --git a/drivers/soc/fsl/qe/Makefile b/drivers/soc/fsl/qe/Makefile index 45c961acc81b..ec8506e13113 100644 --- a/drivers/soc/fsl/qe/Makefile +++ b/drivers/soc/fsl/qe/Makefile @@ -5,6 +5,7 @@ obj-$(CONFIG_QUICC_ENGINE)+= qe.o qe_common.o qe_ic.o qe_io.o obj-$(CONFIG_CPM) += qe_common.o obj-$(CONFIG_CPM_TSA) += tsa.o +obj-$(CONFIG_CPM_QMC) += qmc.o obj-$(CONFIG_UCC) += ucc.o obj-$(CONFIG_UCC_SLOW) += ucc_slow.o obj-$(CONFIG_UCC_FAST) += ucc_fast.o diff --git a/drivers/soc/fsl/qe/qmc.c b/drivers/soc/fsl/qe/qmc.c new file mode 100644 index ..cfa7207353e0 --- /dev/null +++ b/drivers/soc/fsl/qe/qmc.c @@ -0,0 +1,1533 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * QMC driver + * + * Copyright 2022 CS GROUP France + * + * Author: Herve Codina + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "tsa.h" + +/* SCC general mode register high (32 bits) */ +#define SCC_GSMRL 0x00 +#define SCC_GSMRL_ENR (1 << 5) +#define SCC_GSMRL_ENT (1 << 4) +#define SCC_GSMRL_MODE_QMC (0x0A << 0) + +/* SCC general mode register low (32 bits) */ +#define SCC_GSMRH 0x04 +#define SCC_GSMRH_CTSS (1 << 7) +#define SCC_GSMRH_CDS(1 << 8) +#define SCC_GSMRH_CTSP (1 << 9) +#define SCC_GSMRH_CDP(1 << 10) + +/* SCC event register (16 bits) */ +#define SCC_SCCE 0x10 +#define SCC_SCCE_IQOV(1 << 3) +#define SCC_SCCE_GINT(1 << 2) +#define SCC_SCCE_GUN (1 << 1) +#define SCC_SCCE_GOV (1 << 0) + +/* SCC mask register (16 bits) */ +#define SCC_SCCM 0x14 +/* Multichannel base pointer (32 bits) */ +#define QMC_GBL_MCBASE 0x00 +/* Multichannel controller state (16 bits) */ +#define QMC_GBL_QMCSTATE 0x04 +/* Maximum receive buffer length (16 bits) */ +#define QMC_GBL_MRBLR 0x06 +/* Tx time-slot assignment table pointer (16 bits) */ +#define QMC_GBL_TX_S_PTR 0x08 +/* Rx pointer (16 bits) */ +#define QMC_GBL_RXPTR 0x0A +/* Global receive frame threshold (16 bits) */ +#define QMC_GBL_GRFTHR 0x0C +/* Global receive frame count (16 bits) */ +#define QMC_GBL_GRFCNT 0x0E +/* Multichannel interrupt base address (32 bits) */ +#define QMC_GBL_INTBASE0x10 +/* Multichannel interrupt pointer (32 bits) */ +#define QMC_GBL_INTPTR 0x14 +/* Rx time-slot assignment table pointer (16 bits) */ +#define QMC_GBL_RX_S_PTR 0x18 +/* Tx pointer (16 bits) */ +#define QMC_GBL_TXPTR 0x1A +/* CRC constant (32 bits) */ +#define QMC_GBL_C_MASK32 0x1C +/* Time slot assignment table Rx (32 x 16 bits) */ +#define QMC_GBL_TSATRX 0x20 +/* Time slot assignment table Tx (32 x 16 bits) */ +#define QMC_GBL_TSATTX 0x60 +/* CRC constant (16 bits) */ +#define QMC_GBL_C_MASK16 0xA0 + +/* TSA entry (16bit entry in TSATRX and TSATTX) */ +#define QMC_TSA_VALID (1 << 15) +#define QMC_TSA_WRAP (1 << 14) +#define QMC_TSA_MASK (0x303F) +#define QMC_TSA_CHANNEL(x) ((x) << 6) + +/* Tx buffer descriptor base address (16 bits, offset from MCBASE) */ +#define QMC_SPE_TBASE 0x00 + +/* Channel mode register (16 bits) */ +#define QMC_SPE_CHAMR 0x02 +#define QMC_SPE_CHAMR_MODE_HDLC (1 << 15) +#define QMC_SPE_CHAMR_MODE_TRANSP((0 << 15) | (1 << 13)) +#define QMC_SPE_CHAMR_ENT(1 << 12) +#define QMC_SPE_CHAMR_POL(1 << 8) +#define QMC_SPE_CHAMR_HDLC_IDLM (1
[PATCH v5 05/10] dt-bindings: soc: fsl: cpm_qe: Add QMC controller
Add support for the QMC (QUICC Multichannel Controller)
available in some PowerQUICC SoC such as MPC885 or MPC866.
Signed-off-by: Herve Codina
---
.../soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml | 172 ++
1 file changed, 172 insertions(+)
create mode 100644
Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml
diff --git
a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml
b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml
new file mode 100644
index ..cb3994c412dd
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml
@@ -0,0 +1,172 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: PowerQUICC CPM QUICC Multichannel Controller (QMC)
+
+maintainers:
+ - Herve Codina
+
+description:
+ The QMC (QUICC Multichannel Controller) emulates up to 64 channels within one
+ serial controller using the same TDM physical interface routed from TSA.
+
+properties:
+ compatible:
+items:
+ - enum:
+ - fsl,mpc885-scc-qmc
+ - fsl,mpc866-scc-qmc
+ - const: fsl,cpm1-scc-qmc
+
+ reg:
+items:
+ - description: SCC (Serial communication controller) register base
+ - description: SCC parameter ram base
+ - description: Dual port ram base
+
+ reg-names:
+items:
+ - const: scc_regs
+ - const: scc_pram
+ - const: dpram
+
+ interrupts:
+maxItems: 1
+description: SCC interrupt line in the CPM interrupt controller
+
+ fsl,tsa-serial:
+$ref: /schemas/types.yaml#/definitions/phandle-array
+items:
+ - items:
+ - description: phandle to TSA node
+ - enum: [1, 2, 3]
+description: |
+ TSA serial interface (dt-bindings/soc/fsl,tsa.h defines these
+ values)
+ - 1: SCC2
+ - 2: SCC3
+ - 3: SCC4
+description:
+ Should be a phandle/number pair. The phandle to TSA node and the TSA
+ serial interface to use.
+
+ '#address-cells':
+const: 1
+
+ '#size-cells':
+const: 0
+
+ '#fsl,chan-cells':
+$ref: /schemas/types.yaml#/definitions/uint32
+const: 1
+description:
+ QMC consumers that use a phandle to QMC need to pass the channel number
+ with this phandle.
+ For instance "fsl,qmc-chan = < 16>;".
+
+patternProperties:
+ '^channel@([0-9]|[1-5][0-9]|6[0-3])$':
+description:
+ A channel managed by this controller
+type: object
+
+properties:
+ reg:
+minimum: 0
+maximum: 63
+description:
+ The channel number
+
+ fsl,operational-mode:
+$ref: /schemas/types.yaml#/definitions/string
+enum: [transparent, hdlc]
+default: transparent
+description: |
+ The channel operational mode
+- hdlc: The channel handles HDLC frames
+- transparent: The channel handles raw data without any processing
+
+ fsl,reverse-data:
+$ref: /schemas/types.yaml#/definitions/flag
+description:
+ The bit order as seen on the channels is reversed,
+ transmitting/receiving the MSB of each octet first.
+ This flag is used only in 'transparent' mode.
+
+ fsl,tx-ts-mask:
+$ref: /schemas/types.yaml#/definitions/uint64
+description:
+ Channel assigned Tx time-slots within the Tx time-slots routed by the
+ TSA to this cell.
+
+ fsl,rx-ts-mask:
+$ref: /schemas/types.yaml#/definitions/uint64
+description:
+ Channel assigned Rx time-slots within the Rx time-slots routed by the
+ TSA to this cell.
+
+required:
+ - reg
+ - fsl,tx-ts-mask
+ - fsl,rx-ts-mask
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - interrupts
+ - fsl,tsa-serial
+ - '#address-cells'
+ - '#size-cells'
+ - '#fsl,chan-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+
+qmc@a60 {
+compatible = "fsl,mpc885-scc-qmc", "fsl,cpm1-scc-qmc";
+reg = <0xa60 0x20>,
+ <0x3f00 0xc0>,
+ <0x2000 0x1000>;
+reg-names = "scc_regs", "scc_pram", "dpram";
+interrupts = <27>;
+interrupt-parent = <_PIC>;
+
+#address-cells = <1>;
+#size-cells = <0>;
+#fsl,chan-cells = <1>;
+
+fsl,tsa-serial = < FSL_CPM_TSA_SCC4>;
+
+channel@16 {
+/* Ch16 : First 4 even TS from all routed from TSA */
+reg = <16>;
+fsl,mode = "transparent";
+fsl,reverse-data;
+fsl,tx-ts-mask = <0x 0x00aa>;
+fsl,rx-ts-mask = <0x 0x00aa>;
+};
+
+channel@17 {
+/* Ch17 : First 4 odd TS from all routed from TSA */
+reg =
[PATCH v5 04/10] powerpc/8xx: Use a larger CPM1 command check mask
The CPM1 command mask is defined for use with the standard CPM1 command register as described in the user's manual: 0 |13|47|8 11|12 14| 15| RST|- |OPCODE|CH_NUM| -|FLG| In the QMC extension the CPM1 command register is redefined (QMC supplement user's manuel) with the following mapping: 0 |13|47|8 13|14| 15| RST|QMC OPCODE| 1110|CHANNEL_NUMBER| -|FLG| Extend the check command mask in order to support both the standard CH_NUM field and the QMC extension CHANNEL_NUMBER field. Signed-off-by: Herve Codina Acked-by: Christophe Leroy Acked-by: Michael Ellerman --- arch/powerpc/platforms/8xx/cpm1.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/powerpc/platforms/8xx/cpm1.c b/arch/powerpc/platforms/8xx/cpm1.c index 8ef1f4392086..6b828b9f90d9 100644 --- a/arch/powerpc/platforms/8xx/cpm1.c +++ b/arch/powerpc/platforms/8xx/cpm1.c @@ -100,7 +100,7 @@ int cpm_command(u32 command, u8 opcode) int i, ret; unsigned long flags; - if (command & 0xff0f) + if (command & 0xff03) return -EINVAL; spin_lock_irqsave(_lock, flags); -- 2.39.1
[PATCH v5 02/10] soc: fsl: cpm1: Add support for TSA
The TSA (Time Slot Assigner) purpose is to route some TDM time-slots to other internal serial controllers. It is available in some PowerQUICC SoC such as the MPC885 or MPC866. It is also available on some Quicc Engine SoCs. This current version support CPM1 SoCs only and some enhancement are needed to support Quicc Engine SoCs. Signed-off-by: Herve Codina --- drivers/soc/fsl/qe/Kconfig | 11 + drivers/soc/fsl/qe/Makefile | 1 + drivers/soc/fsl/qe/tsa.c| 869 drivers/soc/fsl/qe/tsa.h| 42 ++ 4 files changed, 923 insertions(+) create mode 100644 drivers/soc/fsl/qe/tsa.c create mode 100644 drivers/soc/fsl/qe/tsa.h diff --git a/drivers/soc/fsl/qe/Kconfig b/drivers/soc/fsl/qe/Kconfig index 357c5800b112..b0088495c323 100644 --- a/drivers/soc/fsl/qe/Kconfig +++ b/drivers/soc/fsl/qe/Kconfig @@ -33,6 +33,17 @@ config UCC bool default y if UCC_FAST || UCC_SLOW +config CPM_TSA + tristate "CPM TSA support" + depends on OF && HAS_IOMEM + depends on CPM1 || COMPILE_TEST + help + Freescale CPM Time Slot Assigner (TSA) + controller. + + This option enables support for this + controller + config QE_TDM bool default y if FSL_UCC_HDLC diff --git a/drivers/soc/fsl/qe/Makefile b/drivers/soc/fsl/qe/Makefile index 55a555304f3a..45c961acc81b 100644 --- a/drivers/soc/fsl/qe/Makefile +++ b/drivers/soc/fsl/qe/Makefile @@ -4,6 +4,7 @@ # obj-$(CONFIG_QUICC_ENGINE)+= qe.o qe_common.o qe_ic.o qe_io.o obj-$(CONFIG_CPM) += qe_common.o +obj-$(CONFIG_CPM_TSA) += tsa.o obj-$(CONFIG_UCC) += ucc.o obj-$(CONFIG_UCC_SLOW) += ucc_slow.o obj-$(CONFIG_UCC_FAST) += ucc_fast.o diff --git a/drivers/soc/fsl/qe/tsa.c b/drivers/soc/fsl/qe/tsa.c new file mode 100644 index ..90d9a5254d9b --- /dev/null +++ b/drivers/soc/fsl/qe/tsa.c @@ -0,0 +1,869 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * TSA driver + * + * Copyright 2022 CS GROUP France + * + * Author: Herve Codina + */ + +#include "tsa.h" +#include +#include +#include +#include +#include +#include +#include +#include + + +/* TSA SI RAM routing tables entry */ +#define TSA_SIRAM_ENTRY_LAST (1 << 16) +#define TSA_SIRAM_ENTRY_BYTE (1 << 17) +#define TSA_SIRAM_ENTRY_CNT(x) (((x) & 0x0f) << 18) +#define TSA_SIRAM_ENTRY_CSEL_MASK (0x7 << 22) +#define TSA_SIRAM_ENTRY_CSEL_NU(0x0 << 22) +#define TSA_SIRAM_ENTRY_CSEL_SCC2 (0x2 << 22) +#define TSA_SIRAM_ENTRY_CSEL_SCC3 (0x3 << 22) +#define TSA_SIRAM_ENTRY_CSEL_SCC4 (0x4 << 22) +#define TSA_SIRAM_ENTRY_CSEL_SMC1 (0x5 << 22) +#define TSA_SIRAM_ENTRY_CSEL_SMC2 (0x6 << 22) + +/* SI mode register (32 bits) */ +#define TSA_SIMODE 0x00 +#define TSA_SIMODE_SMC2 0x8000 +#define TSA_SIMODE_SMC1 0x8000 +#define TSA_SIMODE_TDMA(x) ((x) << 0) +#define TSA_SIMODE_TDMB(x) ((x) << 16) +#define TSA_SIMODE_TDM_MASK0x0fff +#define TSA_SIMODE_TDM_SDM_MASK0x0c00 +#define TSA_SIMODE_TDM_SDM_NORM 0x +#define TSA_SIMODE_TDM_SDM_ECHO 0x0400 +#define TSA_SIMODE_TDM_SDM_INTL_LOOP 0x0800 +#define TSA_SIMODE_TDM_SDM_LOOP_CTRL 0x0c00 +#define TSA_SIMODE_TDM_RFSD(x) ((x) << 8) +#define TSA_SIMODE_TDM_DSC 0x0080 +#define TSA_SIMODE_TDM_CRT 0x0040 +#define TSA_SIMODE_TDM_STZ 0x0020 +#define TSA_SIMODE_TDM_CE 0x0010 +#define TSA_SIMODE_TDM_FE 0x0008 +#define TSA_SIMODE_TDM_GM 0x0004 +#define TSA_SIMODE_TDM_TFSD(x) ((x) << 0) + +/* SI global mode register (8 bits) */ +#define TSA_SIGMR 0x04 +#define TSA_SIGMR_ENB (1<<3) +#define TSA_SIGMR_ENA (1<<2) +#define TSA_SIGMR_RDM_MASK 0x03 +#define TSA_SIGMR_RDM_STATIC_TDMA0x00 +#define TSA_SIGMR_RDM_DYN_TDMA 0x01 +#define TSA_SIGMR_RDM_STATIC_TDMAB 0x02 +#define TSA_SIGMR_RDM_DYN_TDMAB 0x03 + +/* SI status register (8 bits) */ +#define TSA_SISTR 0x06 + +/* SI command register (8 bits) */ +#define TSA_SICMR 0x07 + +/* SI clock route register (32 bits) */ +#define TSA_SICR 0x0C +#define TSA_SICR_SCC2(x) ((x) << 8) +#define TSA_SICR_SCC3(x) ((x) << 16) +#define TSA_SICR_SCC4(x) ((x) << 24) +#define TSA_SICR_SCC_MASK 0x0ff +#define TSA_SICR_SCC_GRX (1 << 7) +#define TSA_SICR_SCC_SCX_TSA (1 << 6) +#define TSA_SICR_SCC_RXCS_MASK (0x7 << 3) +#define TSA_SICR_SCC_RXCS_BRG1 (0x0 << 3) +#define TSA_SICR_SCC_RXCS_BRG2 (0x1 << 3) +#define TSA_SICR_SCC_RXCS_BRG3 (0x2 << 3) +#define TSA_SICR_SCC_RXCS_BRG4 (0x3 << 3) +#define TSA_SICR_SCC_RXCS_CLK15
[PATCH v5 01/10] dt-bindings: soc: fsl: cpm_qe: Add TSA controller
Add support for the time slot assigner (TSA) available in some PowerQUICC SoC such as MPC885 or MPC866. Signed-off-by: Herve Codina --- .../bindings/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml | 234 ++ include/dt-bindings/soc/fsl,tsa.h | 13 + 2 files changed, 247 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml create mode 100644 include/dt-bindings/soc/fsl,tsa.h diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml new file mode 100644 index ..bcd03f89780e --- /dev/null +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml @@ -0,0 +1,234 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: PowerQUICC CPM Time-slot assigner (TSA) controller + +maintainers: + - Herve Codina + +description: + The TSA is the time-slot assigner that can be found on some PowerQUICC SoC. + Its purpose is to route some TDM time-slots to other internal serial + controllers. + +properties: + compatible: +items: + - enum: + - fsl,mpc885-tsa + - fsl,mpc866-tsa + - const: fsl,cpm1-tsa + + reg: +items: + - description: SI (Serial Interface) register base + - description: SI RAM base + + reg-names: +items: + - const: si_regs + - const: si_ram + + '#address-cells': +const: 1 + + '#size-cells': +const: 0 + + '#fsl,serial-cells': +$ref: /schemas/types.yaml#/definitions/uint32 +const: 1 +description: + TSA consumers that use a phandle to TSA need to pass the serial identifier + with this phandle (defined in dt-bindings/soc/fsl,tsa.h). + For instance "fsl,tsa-serial = < FSL_CPM_TSA_SCC4>;". + +patternProperties: + '^tdm@[0-1]$': +description: + The TDM managed by this controller +type: object + +additionalProperties: false + +properties: + reg: +minimum: 0 +maximum: 1 +description: + The TDM number for this TDM, 0 for TDMa and 1 for TDMb + + fsl,common-rxtx-pins: +$ref: /schemas/types.yaml#/definitions/flag +description: + The hardware can use four dedicated pins for Tx clock, Tx sync, Rx + clock and Rx sync or use only two pins, Tx/Rx clock and Tx/Rx sync. + Without the 'fsl,common-rxtx-pins' property, the four pins are used. + With the 'fsl,common-rxtx-pins' property, two pins are used. + + clocks: +minItems: 2 +items: + - description: External clock connected to L1RSYNC pin + - description: External clock connected to L1RCLK pin + - description: External clock connected to L1TSYNC pin + - description: External clock connected to L1TCLK pin + clock-names: +minItems: 2 +items: + - const: l1rsync + - const: l1rclk + - const: l1tsync + - const: l1tclk + + fsl,diagnostic-mode: +$ref: /schemas/types.yaml#/definitions/string +enum: [disabled, echo, internal-loopback, control-loopback] +default: disabled +description: | + The diagnostic mode can be used to diagnose some communication issues. + It should not be set (or set to 'disabled') when diagnostic is not + needed. + Diagnostic mode: +- disabled: +Diagnostic disabled (ie. normal operation) +- echo: +Automatic echo. Rx data is resent on Tx. +- internal-loopback: +The TDM transmitter is connected to the receiver. Data appears +on Tx pin. +- control-loopback: +The TDM transmitter is connected to the receiver. The Tx pin is +disconnected. + + fsl,rx-frame-sync-delay-bits: +enum: [0, 1, 2, 3] +default: 0 +description: | + Receive frame sync delay in number of bits. + Indicates the delay between the Rx sync and the first bit of the Rx + frame. 0 for no bit delay. 1, 2 or 3 for 1, 2 or 3 bits delay. + + fsl,tx-frame-sync-delay-bits: +enum: [0, 1, 2, 3] +default: 0 +description: | + Transmit frame sync delay in number of bits. + Indicates the delay between the Tx sync and the first bit of the Tx + frame. 0 for no bit delay. 1, 2 or 3 for 1, 2 or 3 bits delay. + + fsl,clock-falling-edge: +$ref: /schemas/types.yaml#/definitions/flag +description: + Data is sent on falling edge of the clock (and received on the rising + edge). If 'clock-falling-edge' is not present, data is sent on the + rising edge (and received on the falling edge). + +
[PATCH v5 03/10] MAINTAINERS: add the Freescale TSA controller entry
After contributing the driver, add myself as the maintainer for the Freescale TSA controller. Signed-off-by: Herve Codina --- MAINTAINERS | 9 + 1 file changed, 9 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 7f86d02cb427..0cfedb2f712c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -8372,6 +8372,15 @@ S: Maintained F: drivers/soc/fsl/qe/ F: include/soc/fsl/qe/ +FREESCALE QUICC ENGINE TSA DRIVER +M: Herve Codina +L: linuxppc-dev@lists.ozlabs.org +S: Maintained +F: Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml +F: drivers/soc/fsl/qe/tsa.c +F: drivers/soc/fsl/qe/tsa.h +F: include/dt-bindings/soc/fsl,tsa.h + FREESCALE QUICC ENGINE UCC ETHERNET DRIVER M: Li Yang L: net...@vger.kernel.org -- 2.39.1
[PATCH v5 00/10] Add the PowerQUICC audio support using the QMC
Hi,
This series adds support for audio using the QMC controller available in
some Freescale PowerQUICC SoCs.
This series contains three parts in order to show the different blocks
hierarchy and their usage in this support.
The first one is related to TSA (Time Slot Assigner).
The TSA handles the data present at the pin level (TDM with up to 64
time slots) and dispatchs them to one or more serial controller (SCC).
The second is related to QMC (QUICC Multichannel Controller).
The QMC handles the data at the serial controller (SCC) level and splits
again the data to creates some virtual channels.
The last one is related to the audio component (QMC audio).
It is the glue between the QMC controller and the ASoC component. It
handles one or more QMC virtual channels and creates one DAI per QMC
virtual channels handled.
Compared to the previous iteration
https://lore.kernel.org/linux-kernel/20230126083222.374243-1-herve.cod...@bootlin.com/
this v5 series mainly:
- fixes bindings,
- removes one left out_8() specific ppc call (missed in v3),
- changes 'depends-on' in case of COMPILE_TEST.
Best regards,
Herve Codina
Changes v4 -> v5
- patch 1
Rename fsl,tsa.yaml to fsl,cpm1-tsa.yaml
Rename #serial-cells to #fsl,serial-cells and add a description
Fix typos
Remove examples present in description
Use a pattern property for fsl,[rt]x-ts-routes
- patch 2
Remove one left out_8() ppc specific function call
Remove the no more needed PPC dependency in case of COMPILE_TEST
- patch 4
Add 'Acked-by: Michael Ellerman '
- patch 5
Rename fsl,qmc.yaml to fsl,cpm1-scc-qmc.yaml
Rename #chan-cells to #fsl,chan-cells and add a description
- patch 6
Add the SOC_FSL dependency in case of COMPILE_TEST (issue raised by
the kernel test robot).
Fix a typo in commit log
Add 'Acked-by: Li Yang '
Changes v3 -> v4
- patches 2, 6 and 9
Update code comment format.
- patch 1
Fix some description formats.
Add 'additionalProperties: false' in subnode.
Move fsl,mode to fsl,diagnostic-mode.
Change clocks and clock-names properties.
Add '#serial-cells' property related to the newly introduced
fsl,tsa-serial phandle.
- patch 2
Move fsl,mode to fsl,diagnostic-mode.
Replace the fsl,tsa phandle and the fsl,tsa-cell-id property by a
fsl,tsa-serial phandle and update the related API.
Add missing locks.
- patch 5
Fix some description format.
Replace the fsl,tsa phandle and the fsl,tsa-cell-id property by a
fsl,tsa-serial phandle.
Rename fsl,mode to fsl,operational-mode and update its description.
- patch 6
Replace the fsl,tsa phandle and the fsl,tsa-cell-id property by a
fsl,tsa-serial phandle and use the TSA updated API.
Rename fsl,mode to fsl,operational-mode.
- patch 8
Add 'Reviewed-by: Krzysztof Kozlowski '
Changes v2 -> v3
- All bindings
Rename fsl-tsa.h to fsl,tsa.h
Add missing vendor prefix
Various fixes (quotes, node names, upper/lower case)
- patches 1 and 2 (TSA binding specific)
Remove 'reserved' values in the routing tables
Remove fsl,grant-mode
Add a better description for 'fsl,common-rxtx-pins'
Fix clocks/clocks-name handling against fsl,common-rxtx-pins
Add information related to the delays unit
Removed FSL_CPM_TSA_NBCELL
Fix license in binding header file fsl,tsa.h
- patches 5 and 6 (QMC binding specific)
Remove fsl,cpm-command property
Add interrupt property constraint
- patches 8 and 9 (QMC audio binding specific)
Remove 'items' in compatible property definition
Add missing 'dai-common.yaml' reference
Fix the qmc_chan phandle definition
- patch 2 and 6
Use io{read,write}be{32,16}
Change commit subjects and logs
- patch 4
Add 'Acked-by: Christophe Leroy '
Changes v1 -> v2:
- patch 2 and 6
Fix kernel test robot errors
- other patches
No changes
Herve Codina (10):
dt-bindings: soc: fsl: cpm_qe: Add TSA controller
soc: fsl: cpm1: Add support for TSA
MAINTAINERS: add the Freescale TSA controller entry
powerpc/8xx: Use a larger CPM1 command check mask
dt-bindings: soc: fsl: cpm_qe: Add QMC controller
soc: fsl: cpm1: Add support for QMC
MAINTAINERS: add the Freescale QMC controller entry
dt-bindings: sound: Add support for QMC audio
ASoC: fsl: Add support for QMC audio
MAINTAINERS: add the Freescale QMC audio entry
.../soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml | 172 ++
.../bindings/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml | 234 +++
.../bindings/sound/fsl,qmc-audio.yaml | 117 ++
MAINTAINERS | 25 +
arch/powerpc/platforms/8xx/cpm1.c |2 +-
drivers/soc/fsl/qe/Kconfig| 23 +
drivers/soc/fsl/qe/Makefile |2 +
drivers/soc/fsl/qe/qmc.c | 1533 +
drivers/soc/fsl/qe/tsa.c | 869 ++
[PATCH v4 14/16] powerpc: mm: Convert to GENERIC_IOREMAP
From: Christophe Leroy
By taking GENERIC_IOREMAP method, the generic generic_ioremap_prot(),
generic_iounmap(), and their generic wrapper ioremap_prot(), ioremap()
and iounmap() are all visible and available to arch. Arch needs to
provide wrapper functions to override the generic versions if there's
arch specific handling in its ioremap_prot(), ioremap() or iounmap().
This change will simplify implementation by removing duplicated codes
with generic_ioremap_prot() and generic_iounmap(), and has the equivalent
functioality as before.
Here, add wrapper functions ioremap_prot() and iounmap() for powerpc's
special operation when ioremap() and iounmap().
Signed-off-by: Christophe Leroy
Signed-off-by: Baoquan He
Cc: Michael Ellerman
Cc: Nicholas Piggin
Cc: linuxppc-dev@lists.ozlabs.org
---
arch/powerpc/Kconfig | 1 +
arch/powerpc/include/asm/io.h | 8 +++-
arch/powerpc/mm/ioremap.c | 26 +-
arch/powerpc/mm/ioremap_32.c | 19 +--
arch/powerpc/mm/ioremap_64.c | 12 ++--
5 files changed, 16 insertions(+), 50 deletions(-)
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 7a5f8dbfbdd0..02ae9e6afed6 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -181,6 +181,7 @@ config PPC
select GENERIC_CPU_VULNERABILITIES if PPC_BARRIER_NOSPEC
select GENERIC_EARLY_IOREMAP
select GENERIC_GETTIMEOFDAY
+ select GENERIC_IOREMAP
select GENERIC_IRQ_SHOW
select GENERIC_IRQ_SHOW_LEVEL
select GENERIC_PCI_IOMAPif PCI
diff --git a/arch/powerpc/include/asm/io.h b/arch/powerpc/include/asm/io.h
index fc112a91d0c2..127d8300b40b 100644
--- a/arch/powerpc/include/asm/io.h
+++ b/arch/powerpc/include/asm/io.h
@@ -859,8 +859,8 @@ static inline void iosync(void)
*
*/
extern void __iomem *ioremap(phys_addr_t address, unsigned long size);
-extern void __iomem *ioremap_prot(phys_addr_t address, unsigned long size,
- unsigned long flags);
+#define ioremap ioremap
+#define ioremap_prot ioremap_prot
extern void __iomem *ioremap_wc(phys_addr_t address, unsigned long size);
#define ioremap_wc ioremap_wc
@@ -874,14 +874,12 @@ void __iomem *ioremap_coherent(phys_addr_t address,
unsigned long size);
#define ioremap_cache(addr, size) \
ioremap_prot((addr), (size), pgprot_val(PAGE_KERNEL))
-extern void iounmap(volatile void __iomem *addr);
+#define iounmap iounmap
void __iomem *ioremap_phb(phys_addr_t paddr, unsigned long size);
int early_ioremap_range(unsigned long ea, phys_addr_t pa,
unsigned long size, pgprot_t prot);
-void __iomem *do_ioremap(phys_addr_t pa, phys_addr_t offset, unsigned long
size,
-pgprot_t prot, void *caller);
extern void __iomem *__ioremap_caller(phys_addr_t, unsigned long size,
pgprot_t prot, void *caller);
diff --git a/arch/powerpc/mm/ioremap.c b/arch/powerpc/mm/ioremap.c
index 4f12504fb405..705e8e8ffde4 100644
--- a/arch/powerpc/mm/ioremap.c
+++ b/arch/powerpc/mm/ioremap.c
@@ -41,7 +41,7 @@ void __iomem *ioremap_coherent(phys_addr_t addr, unsigned
long size)
return __ioremap_caller(addr, size, prot, caller);
}
-void __iomem *ioremap_prot(phys_addr_t addr, unsigned long size, unsigned long
flags)
+void __iomem *ioremap_prot(phys_addr_t addr, size_t size, unsigned long flags)
{
pte_t pte = __pte(flags);
void *caller = __builtin_return_address(0);
@@ -74,27 +74,3 @@ int early_ioremap_range(unsigned long ea, phys_addr_t pa,
return 0;
}
-
-void __iomem *do_ioremap(phys_addr_t pa, phys_addr_t offset, unsigned long
size,
-pgprot_t prot, void *caller)
-{
- struct vm_struct *area;
- int ret;
- unsigned long va;
-
- area = __get_vm_area_caller(size, VM_IOREMAP, IOREMAP_START,
IOREMAP_END, caller);
- if (area == NULL)
- return NULL;
-
- area->phys_addr = pa;
- va = (unsigned long)area->addr;
-
- ret = ioremap_page_range(va, va + size, pa, prot);
- if (!ret)
- return (void __iomem *)area->addr + offset;
-
- vunmap_range(va, va + size);
- free_vm_area(area);
-
- return NULL;
-}
diff --git a/arch/powerpc/mm/ioremap_32.c b/arch/powerpc/mm/ioremap_32.c
index 9d13143b8be4..ca5bc6be3e6f 100644
--- a/arch/powerpc/mm/ioremap_32.c
+++ b/arch/powerpc/mm/ioremap_32.c
@@ -21,6 +21,13 @@ __ioremap_caller(phys_addr_t addr, unsigned long size,
pgprot_t prot, void *call
phys_addr_t p, offset;
int err;
+ /*
+* If the address lies within the first 16 MB, assume it's in ISA
+* memory space
+*/
+ if (addr < SZ_16M)
+ addr += _ISA_MEM_BASE;
+
/*
* Choose an address to map it to.
* Once the vmalloc system is running, we use it.
@@ -31,13 +38,6 @@ __ioremap_caller(phys_addr_t addr, unsigned
Re: [PATCH v2] usb: fix some spelling mistakes in comment of gadget
On Wed, Feb 15, 2023 at 05:35:35PM -0800, Zhou nan wrote: > usb: Fix spelling mistake in comments of gadget. > > Signed-off-by: Zhou nan > --- Hi, This is the friendly patch-bot of Greg Kroah-Hartman. You have sent him a patch that has triggered this response. He used to manually respond to these common problems, but in order to save his sanity (he kept writing the same thing over and over, yet to different people), I was created. Hopefully you will not take offence and will fix the problem in your patch and resubmit it so that it can be accepted into the Linux kernel tree. You are receiving this message because of the following common error(s) as indicated below: - You did not specify a description of why the patch is needed, or possibly, any description at all, in the email body. Please read the section entitled "The canonical patch format" in the kernel file, Documentation/process/submitting-patches.rst for what is needed in order to properly describe the change. - You did not write a descriptive Subject: for the patch, allowing Greg, and everyone else, to know what this patch is all about. Please read the section entitled "The canonical patch format" in the kernel file, Documentation/process/submitting-patches.rst for what a proper Subject: line should look like. If you wish to discuss this problem further, or you have questions about how to resolve this issue, please feel free to respond to this email and Greg will reply once he has dug out from the pending patches received from other developers. thanks, greg k-h's patch email bot
[PATCH] powerpc/nohash: Fix build with llvm-as
When using the LLVM integrated assembler (llvm-as), the book3e build fails with: arch/powerpc/mm/nohash/tlb_low_64e.S:354:2: error: invalid instruction tlbilxva 0,%r15 ^ tlbilxva is an extended mnemonic for tlbilx, but llvm-as also doesn't support tlbilx, despite it being an e500mc instruction. Fix it by using the existing PPC_TLBILX_VA macro. The resulting binary is identical when building with binutils. Signed-off-by: Michael Ellerman --- arch/powerpc/mm/nohash/tlb_low_64e.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/powerpc/mm/nohash/tlb_low_64e.S b/arch/powerpc/mm/nohash/tlb_low_64e.S index 76cf456d7976..7e0b8fe1c279 100644 --- a/arch/powerpc/mm/nohash/tlb_low_64e.S +++ b/arch/powerpc/mm/nohash/tlb_low_64e.S @@ -351,7 +351,7 @@ END_FTR_SECTION_NESTED(CPU_FTR_EMB_HV,CPU_FTR_EMB_HV,532) mfspr r15,SPRN_MAS2 isync - tlbilxva 0,r15 + PPC_TLBILX_VA(0,R15) isync mtspr SPRN_MAS6,r10 -- 2.39.1
Re: 6.2-rc7 fails building on Talos II: memory.c:(.text+0x2e14): undefined reference to `hash__tlb_flush'
On Thu, 16 Feb 2023 06:29:52 +
Christophe Leroy wrote:
> Can you try with :
>
> diff --git a/arch/powerpc/include/asm/book3s/64/tlbflush.h
> b/arch/powerpc/include/asm/book3s/64/tlbflush.h
> index d5cd16270c5d..2bbc0fcce04a 100644
> --- a/arch/powerpc/include/asm/book3s/64/tlbflush.h
> +++ b/arch/powerpc/include/asm/book3s/64/tlbflush.h
> @@ -97,8 +97,8 @@ static inline void tlb_flush(struct mmu_gather *tlb)
> {
> if (radix_enabled())
> radix__tlb_flush(tlb);
> -
> - return hash__tlb_flush(tlb);
> + else
> + hash__tlb_flush(tlb);
> }
>
> #ifdef CONFIG_SMP
With the patch applied my 6.2-rc7 .config builds. Thanks Christophe!
Regards,
Erhard
Re: 6.2-rc7 fails building on Talos II: memory.c:(.text+0x2e14): undefined reference to `hash__tlb_flush'
[TLDR: I'm adding this report to the list of tracked Linux kernel regressions; the text you find below is based on a few templates paragraphs you might have encountered already in similar form. See link in footer if these mails annoy you.] [CCing the regression list, as it should be in the loop for regressions: https://docs.kernel.org/admin-guide/reporting-regressions.html] On 16.02.23 00:55, Erhard F. wrote: > Just noticed a build failure on 6.2-rc7 for my Talos 2 (.config attached): > > # make > CALLscripts/checksyscalls.sh > UPD include/generated/utsversion.h > CC init/version-timestamp.o > LD .tmp_vmlinux.kallsyms1 > ld: ld: DWARF error: could not find abbrev number 6 > mm/memory.o: in function `unmap_page_range': > memory.c:(.text+0x2e14): undefined reference to `hash__tlb_flush' > ld: memory.c:(.text+0x2f8c): undefined reference to `hash__tlb_flush' > ld: ld: DWARF error: could not find abbrev number 3117 > mm/mmu_gather.o: in function `tlb_remove_table': > mmu_gather.c:(.text+0x584): undefined reference to `hash__tlb_flush' > ld: mmu_gather.c:(.text+0x6c4): undefined reference to `hash__tlb_flush' > ld: mm/mmu_gather.o: in function `tlb_flush_mmu': > mmu_gather.c:(.text+0x80c): undefined reference to `hash__tlb_flush' > ld: mm/mmu_gather.o:mmu_gather.c:(.text+0xbe0): more undefined references to > `hash__tlb_flush' follow > make[1]: *** [scripts/Makefile.vmlinux:35: vmlinux] Fehler 1 > make: *** [Makefile:1264: vmlinux] Error 2 > > As 6.2-rc6 was good on this machine I did a quick bisect which revealed this > commit: > > # git bisect bad > 1665c027afb225882a5a0b014c45e84290b826c2 is the first bad commit > [...] Thanks for the report. To be sure the issue doesn't fall through the cracks unnoticed, I'm adding it to regzbot, the Linux kernel regression tracking bot: #regzbot ^introduced 1665c027afb225 #regzbot title powerpc: 6.2-rc7 fails building on Talos II #regzbot ignore-activity This isn't a regression? This issue or a fix for it are already discussed somewhere else? It was fixed already? You want to clarify when the regression started to happen? Or point out I got the title or something else totally wrong? Then just reply and tell me -- ideally while also telling regzbot about it, as explained by the page listed in the footer of this mail. Developers: When fixing the issue, remember to add 'Link:' tags pointing to the report (the parent of this mail). See page linked in footer for details. Ciao, Thorsten (wearing his 'the Linux kernel's regression tracker' hat) -- Everything you wanna know about Linux kernel regression tracking: https://linux-regtracking.leemhuis.info/about/#tldr That page also explains what to do if mails like this annoy you.
Re: [PATCH 1/2] kcsan: xtensa: Add atomic builtin stubs for 32-bit systems
On Thu, Feb 16, 2023 at 07:12AM +, Christophe Leroy wrote:
>
>
> Le 16/02/2023 à 06:09, Rohan McLure a écrit :
> > KCSAN instruments calls to atomic builtins, and will in turn call these
> > builtins itself. As such, architectures supporting KCSAN must have
> > compiler support for these atomic primitives.
> >
> > Since 32-bit systems are unlikely to have 64-bit compiler builtins,
> > provide a stub for each missing builtin, and use BUG() to assert
> > unreachability.
> >
> > In commit 725aea873261 ("xtensa: enable KCSAN"), xtensa implements these
> > locally. Move these definitions to be accessible to all 32-bit
> > architectures that do not provide the necessary builtins, with opt in
> > for PowerPC and xtensa.
> >
> > Signed-off-by: Rohan McLure
> > Reviewed-by: Max Filippov
>
> This series should also be addressed to KCSAN Maintainers, shouldn't it ?
>
> KCSAN
> M:Marco Elver
> R:Dmitry Vyukov
> L:kasan-...@googlegroups.com
> S:Maintained
> F:Documentation/dev-tools/kcsan.rst
> F:include/linux/kcsan*.h
> F:kernel/kcsan/
> F:lib/Kconfig.kcsan
> F:scripts/Makefile.kcsan
>
>
> > ---
> > Previously issued as a part of a patch series adding KCSAN support to
> > 64-bit.
> > Link:
> > https://lore.kernel.org/linuxppc-dev/167646486000.1421441.10070059569986228558.b4...@ellerman.id.au/T/#t
> > v1: Remove __has_builtin check, as gcc is not obligated to inline
> > builtins detected using this check, but instead is permitted to supply
> > them in libatomic:
> > Link: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108734
> > Instead, opt-in PPC32 and xtensa.
> > ---
> > arch/xtensa/lib/Makefile | 1 -
> > kernel/kcsan/Makefile | 2 ++
> > arch/xtensa/lib/kcsan-stubs.c => kernel/kcsan/stubs.c | 0
> > 3 files changed, 2 insertions(+), 1 deletion(-)
> > rename arch/xtensa/lib/kcsan-stubs.c => kernel/kcsan/stubs.c (100%)
> >
> > diff --git a/arch/xtensa/lib/Makefile b/arch/xtensa/lib/Makefile
> > index 7ecef0519a27..d69356dc97df 100644
> > --- a/arch/xtensa/lib/Makefile
> > +++ b/arch/xtensa/lib/Makefile
> > @@ -8,5 +8,4 @@ lib-y += memcopy.o memset.o checksum.o \
> >divsi3.o udivsi3.o modsi3.o umodsi3.o mulsi3.o umulsidi3.o \
> >usercopy.o strncpy_user.o strnlen_user.o
> > lib-$(CONFIG_PCI) += pci-auto.o
> > -lib-$(CONFIG_KCSAN) += kcsan-stubs.o
> > KCSAN_SANITIZE_kcsan-stubs.o := n
> > diff --git a/kernel/kcsan/Makefile b/kernel/kcsan/Makefile
> > index 8cf70f068d92..86dd713d8855 100644
> > --- a/kernel/kcsan/Makefile
> > +++ b/kernel/kcsan/Makefile
> > @@ -12,6 +12,8 @@ CFLAGS_core.o := $(call cc-option,-fno-conserve-stack) \
> > -fno-stack-protector -DDISABLE_BRANCH_PROFILING
> >
> > obj-y := core.o debugfs.o report.o
> > +obj-$(CONFIG_PPC32) += stubs.o
> > +obj-$(CONFIG_XTENSA) += stubs.o
>
> Not sure it is acceptable to do it that way.
>
> There should likely be something like a CONFIG_ARCH_WANTS_KCSAN_STUBS in
> KCSAN's Kconfig then PPC32 and XTENSA should select it.
The longer I think about it, since these stubs all BUG() anyway, perhaps
we ought to just avoid them altogether. If you delete all the stubs from
ppc and xtensa, but do this:
| diff --git a/kernel/kcsan/core.c b/kernel/kcsan/core.c
| index 54d077e1a2dc..8169d6dadd0e 100644
| --- a/kernel/kcsan/core.c
| +++ b/kernel/kcsan/core.c
| @@ -1261,7 +1261,9 @@ static __always_inline void
kcsan_atomic_builtin_memorder(int memorder)
| DEFINE_TSAN_ATOMIC_OPS(8);
| DEFINE_TSAN_ATOMIC_OPS(16);
| DEFINE_TSAN_ATOMIC_OPS(32);
| +#ifdef CONFIG_64BIT
| DEFINE_TSAN_ATOMIC_OPS(64);
| +#endif
|
| void __tsan_atomic_thread_fence(int memorder);
| void __tsan_atomic_thread_fence(int memorder)
Does that work?
[PATCH V3 3/3] skiboot: Update IMC PMU node names for power10
The nest IMC (In Memory Collection) Performance Monitoring
Unit(PMU) node names are saved as "struct nest_pmus_struct"
in the "hw/imc.c" IMC code. Not all the IMC PMUs listed in
the device tree may be available. Nest IMC PMU names along with
their bit values is represented in imc availability vector.
This struct is used to remove the unavailable nodes by checking
this vector.
For power10, the imc_chip_avl_vector ie, imc availability vector
( which is a part of the IMC control block structure ), has
change in mapping of units and bit positions. Hence rename the
existing nest_pmus array to nest_pmus_p9 and add entry for power10
as nest_pmus_p10.
Also the avl_vector has another change in bit positions 11:34. These
bit positions tells the availability of Xlink/Alink/CAPI. There
are total 8 links and three bit field combination says which link
is available. Patch implements all these change to handle
nest_pmus_p10.
Signed-off-by: Athira Rajeev
---
Changelog:
v2 -> v3:
- After review comments from Mahesh, fixed the code
to consider string upto "@" for both input node name
as well as child node name. V2 version was comparing
input node name and child node name upto string length
of child name. But this will return wrong node if input
name is larger than child name. Because it will match
as substring for child name.
https://lists.ozlabs.org/pipermail/skiboot/2023-January/018596.html
v1 -> v2:
- Addressed review comment from Dan to update
the utility funtion to search and compare
upto "@". Renamed it as dt_find_by_name_substr.
hw/imc.c | 195 ---
1 file changed, 185 insertions(+), 10 deletions(-)
diff --git a/hw/imc.c b/hw/imc.c
index 72fbe92a..d3bad4e5 100644
--- a/hw/imc.c
+++ b/hw/imc.c
@@ -49,7 +49,7 @@ static unsigned int *htm_scom_index;
* imc_chip_avl_vector(in struct imc_chip_cb, look at include/imc.h).
* nest_pmus[] is an array containing all the possible nest IMC PMU node names.
*/
-static char const *nest_pmus[] = {
+static char const *nest_pmus_p9[] = {
"powerbus0",
"mcs0",
"mcs1",
@@ -104,6 +104,67 @@ static char const *nest_pmus[] = {
/* reserved bits : 51 - 63 */
};
+static char const *nest_pmus_p10[] = {
+ "pb",
+ "mcs0",
+ "mcs1",
+ "mcs2",
+ "mcs3",
+ "mcs4",
+ "mcs5",
+ "mcs6",
+ "mcs7",
+ "pec0",
+ "pec1",
+ "NA",
+ "NA",
+ "NA",
+ "NA",
+ "NA",
+ "NA",
+ "NA",
+ "NA",
+ "NA",
+ "NA",
+ "NA",
+ "NA",
+ "NA",
+ "NA",
+ "NA",
+ "NA",
+ "NA",
+ "NA",
+ "NA",
+ "NA",
+ "NA",
+ "NA",
+ "NA",
+ "NA",
+ "phb0",
+ "phb1",
+ "phb2",
+ "phb3",
+ "phb4",
+ "phb5",
+ "ocmb0",
+ "ocmb1",
+ "ocmb2",
+ "ocmb3",
+ "ocmb4",
+ "ocmb5",
+ "ocmb6",
+ "ocmb7",
+ "ocmb8",
+ "ocmb9",
+ "ocmb10",
+ "ocmb11",
+ "ocmb12",
+ "ocmb13",
+ "ocmb14",
+ "ocmb15",
+ "nx",
+};
+
/*
* Due to Nest HW/OCC restriction, microcode will not support individual unit
* events for these nest units mcs0, mcs1 ... mcs7 in the accumulation mode.
@@ -371,7 +432,7 @@ static void disable_unavailable_units(struct dt_node *dev)
uint64_t avl_vec;
struct imc_chip_cb *cb;
struct dt_node *target;
- int i;
+ int i, j;
bool disable_all_nests = false;
struct proc_chip *chip;
@@ -409,14 +470,128 @@ static void disable_unavailable_units(struct dt_node
*dev)
avl_vec = (0xffULL) << 56;
}
- for (i = 0; i < ARRAY_SIZE(nest_pmus); i++) {
- if (!(PPC_BITMASK(i, i) & avl_vec)) {
- /* Check if the device node exists */
- target = dt_find_by_name_substr(dev, nest_pmus[i]);
- if (!target)
- continue;
- /* Remove the device node */
- dt_free(target);
+ if (proc_gen == proc_gen_p9) {
+ for (i = 0; i < ARRAY_SIZE(nest_pmus_p9); i++) {
+ if (!(PPC_BITMASK(i, i) & avl_vec)) {
+ /* Check if the device node exists */
+ target = dt_find_by_name_substr(dev,
nest_pmus_p9[i]);
+ if (!target)
+ continue;
+ /* Remove the device node */
+ dt_free(target);
+ }
+ }
+ } else if (proc_gen == proc_gen_p10) {
+ int val;
+ char al[8], xl[8], otl[8], phb[8];
+ for (i = 0; i < 11; i++) {
+ if (!(PPC_BITMASK(i, i) & avl_vec)) {
+
[PATCH V3 2/3] skiboot: Update IMC code to use dt_find_by_name_substr for checking dt nodes
The nest IMC (In Memory Collection) Performance Monitoring
Unit(PMU) node names are saved in nest_pmus[] array in the
"hw/imc.c" IMC code. Not all the IMC PMUs listed in the device
tree may be available. Nest IMC PMU names along with their
bit values is represented in imc availability vector.
The nest_pmus[] array is used to remove the unavailable nodes
by checking this vector.
To check node availability, code was using "dt_find_by_substr".
But since the node names have format like: "name@offset",
dt_find_by_name doesn't return the expected result. Fix this
by using dt_find_by_name_substr. Also, update the char array
to use correct node names.
Signed-off-by: Athira Rajeev
---
Changelog:
v2 -> v3:
- After review comments from Mahesh, fixed the code
to consider string upto "@" for both input node name
as well as child node name. V2 version was comparing
input node name and child node name upto string length
of child name. But this will return wrong node if input
name is larger than child name. Because it will match
as substring for child name.
https://lists.ozlabs.org/pipermail/skiboot/2023-January/018596.html
v1 -> v2:
- Addressed review comment from Dan to update
the utility funtion to search and compare
upto "@". Renamed it as dt_find_by_name_substr.
hw/imc.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/hw/imc.c b/hw/imc.c
index 97e0809f..72fbe92a 100644
--- a/hw/imc.c
+++ b/hw/imc.c
@@ -67,14 +67,14 @@ static char const *nest_pmus[] = {
"mba5",
"mba6",
"mba7",
- "cen0",
- "cen1",
- "cen2",
- "cen3",
- "cen4",
- "cen5",
- "cen6",
- "cen7",
+ "centaur0",
+ "centaur1",
+ "centaur2",
+ "centaur3",
+ "centaur4",
+ "centaur5",
+ "centaur6",
+ "centaur7",
"xlink0",
"xlink1",
"xlink2",
@@ -412,7 +412,7 @@ static void disable_unavailable_units(struct dt_node *dev)
for (i = 0; i < ARRAY_SIZE(nest_pmus); i++) {
if (!(PPC_BITMASK(i, i) & avl_vec)) {
/* Check if the device node exists */
- target = dt_find_by_name(dev, nest_pmus[i]);
+ target = dt_find_by_name_substr(dev, nest_pmus[i]);
if (!target)
continue;
/* Remove the device node */
--
2.27.0
[PATCH V3 1/3] core/device: Add function to return child node using name at substring "@"
Add a function dt_find_by_name_substr() that returns the child node if
it matches till first occurence at "@" of a given name, otherwise NULL.
This is helpful for cases with node name like: "name@addr". In
scenarios where nodes are added with "name@addr" format and if the
value of "addr" is not known, that node can't be matched with node
name or addr. Hence matching with substring as node name will return
the expected result. Patch adds dt_find_by_name_substr() function
and testcase for the same in core/test/run-device.c
Signed-off-by: Athira Rajeev
---
Changelog:
v2 -> v3:
- After review comments from Mahesh, fixed the code
to consider string upto "@" for both input node name
as well as child node name. V2 version was comparing
input node name and child node name upto string length
of child name. But this will return wrong node if input
name is larger than child name. Because it will match
as substring for child name.
https://lists.ozlabs.org/pipermail/skiboot/2023-January/018596.html
v1 -> v2:
- Addressed review comment from Dan to update
the utility funtion to search and compare
upto "@". Renamed it as dt_find_by_name_substr.
core/device.c | 35 +++
core/test/run-device.c | 15 +++
include/device.h | 3 +++
3 files changed, 53 insertions(+)
diff --git a/core/device.c b/core/device.c
index 2de37c74..26562235 100644
--- a/core/device.c
+++ b/core/device.c
@@ -395,6 +395,41 @@ struct dt_node *dt_find_by_name(struct dt_node *root,
const char *name)
}
+struct dt_node *dt_find_by_name_substr(struct dt_node *root, const char *name)
+{
+ struct dt_node *child, *match;
+ char *node, *child_node = NULL;
+
+ node = malloc(strlen(name) + 1);
+ if (!node)
+ return NULL;
+ memcpy(node, name, strlen(name));
+ node[strlen(name)] = '\0';
+ node = strtok(node, "@");
+ list_for_each(>children, child, list) {
+ child_node = malloc(strlen(child->name) + 1);
+ if (!child_node)
+ goto err;
+ memcpy(child_node, child->name, strlen(child->name));
+ child_node[strlen(child->name)] = '\0';
+ child_node = strtok(child_node, "@");
+ if (!strcmp(child_node, node)) {
+ free(child_node);
+ free(node);
+ return child;
+ }
+
+ match = dt_find_by_name_substr(child, name);
+ if (match)
+ return match;
+ }
+
+ free(child_node);
+err:
+ free(node);
+ return NULL;
+}
+
struct dt_node *dt_new_check(struct dt_node *parent, const char *name)
{
struct dt_node *node = dt_find_by_name(parent, name);
diff --git a/core/test/run-device.c b/core/test/run-device.c
index 4a12382b..6997452e 100644
--- a/core/test/run-device.c
+++ b/core/test/run-device.c
@@ -466,6 +466,21 @@ int main(void)
new_prop_ph = dt_prop_get_u32(ut2, "something");
assert(!(new_prop_ph == ev1_ph));
dt_free(subtree);
+
+ /* Test dt_find_by_name_substr */
+ root = dt_new_root("");
+ addr1 = dt_new_addr(root, "node", 0x1);
+ addr2 = dt_new_addr(root, "node0_1", 0x2);
+ assert(dt_find_by_name(root, "node@1") == addr1);
+ assert(dt_find_by_name(root, "node0_1@2") == addr2);
+ assert(dt_find_by_name_substr(root, "node@1") == addr1);
+ assert(dt_find_by_name_substr(root, "node0_1@2") == addr2);
+ assert(dt_find_by_name_substr(root, "node0_") == NULL);
+ assert(dt_find_by_name_substr(root, "node0_1") == addr2);
+ assert(dt_find_by_name_substr(root, "node0@") == NULL);
+ assert(dt_find_by_name_substr(root, "node0_@") == NULL);
+ dt_free(root);
+
return 0;
}
diff --git a/include/device.h b/include/device.h
index 93fb90ff..b6a1a813 100644
--- a/include/device.h
+++ b/include/device.h
@@ -184,6 +184,9 @@ struct dt_node *dt_find_by_path(struct dt_node *root, const
char *path);
/* Find a child node by name */
struct dt_node *dt_find_by_name(struct dt_node *root, const char *name);
+/* Find a child node by name and substring */
+struct dt_node *dt_find_by_name_substr(struct dt_node *root, const char *name);
+
/* Find a node by phandle */
struct dt_node *dt_find_by_phandle(struct dt_node *root, u32 phandle);
--
2.27.0
