Re: BUG: Kernel NULL pointer dereference on read at 0x00000000 in pnv_get_random_long()
Le Thu, Oct 03, 2024 at 11:49:27AM +0530, Madhavan Srinivasan a écrit : > > > On 10/2/24 5:31 PM, Corentin LABBE wrote: > > Hello > > > > I have a 8335-GCA POWER8 which got a kernel crash during boot: > > [ 11.754238] Kernel attempted to read user page (0) - exploit attempt? > > (uid: 0) > > [ 11.754437] BUG: Kernel NULL pointer dereference on read at 0x > > [ 11.754499] Faulting instruction address: 0xc00c3758 > > [ 11.754518] Oops: Kernel access of bad area, sig: 11 [#1] > > [ 11.754534] LE PAGE_SIZE=64K MMU=Hash SMP NR_CPUS=2048 NUMA PowerNV > > [ 11.754699] Modules linked in: powernv_rng(+) ecb ctr sr_mod hid ofpart > > fb_sys_fops cdrom i2c_algo_bit powernv_flash sg mtd vmx_crypto(+) > > ipmi_powernv ipmi_devintf at24(+) ipmi_msghandler opal_prd regmap_i2c nfsd > > gf128mul auth_rpcgss nfs_acl lockd grace sunrpc drm fuse configfs loop > > drm_panel_orientation_quirks ip_tables x_tables autofs4 uas usb_storage > > ext4 crc16 mbcache jbd2 crc32c_generic dm_mod xhci_pci xhci_hcd sd_mod > > t10_pi crc64_rocksoft crc64 crc_t10dif crct10dif_generic crct10dif_common > > usbcore tg3 libphy crc32c_vpmsum ahci usb_common libahci > > [ 11.754869] CPU: 25 PID: 1332 Comm: (udev-worker) Not tainted 6.1.106 #4 > > [ 11.754890] Hardware name: 8335-GCA POWER8 (raw) 0x4d0200 > > opal:skiboot-5.4.8-5787ad3 PowerNV > > [ 11.754926] NIP: c00c3758 LR: c00c3754 CTR: > > > > [ 11.754947] REGS: cec3af70 TRAP: 0300 Not tainted (6.1.106) > > [ 11.754966] MSR: 9280b033 > > CR: 4482 XER: 2000 > > [ 11.755168] CFAR: c01dfbb4 DAR: DSISR: 4000 > > IRQMASK: 0 > >GPR00: c00c3754 cec3b210 c113cd00 > > 002c > >GPR04: 7fff cec3b010 cec3b008 > > 000ff57e > >GPR08: 0027 c00ff7907f98 0001 > > 2200 > >GPR12: c00eaf00 0020 > > 2200 > >GPR16: 0009 > > 00013c86f5d8 > >GPR20: 01002cd75d90 > > 0005 > >GPR24: 01002cd794a0 01002cd75d90 c285e6fc > > c0f9e4a0 > >GPR28: 0003 0004 > > c010103ca180 > > [ 11.755363] NIP [c00c3758] pnv_get_random_long+0x88/0x170 > > [ 11.755386] LR [c00c3754] pnv_get_random_long+0x84/0x170 > > [ 11.755407] Call Trace: > > [ 11.755416] [cec3b210] [c00c3754] > > pnv_get_random_long+0x84/0x170 (unreliable) > > [ 11.755444] [cec3b280] [c00821c50130] > > powernv_rng_read+0x98/0x120 [powernv_rng] > > [ 11.755473] [cec3b300] [c091ac88] > > add_early_randomness+0x88/0x150 > > [ 11.755577] [cec3b340] [c091b2c4] > > hwrng_register+0x344/0x420 > > [ 11.755678] [cec3b3a0] [c091b408] > > devm_hwrng_register+0x68/0xf0 > > [ 11.755703] [cec3b3e0] [c00821c5003c] > > powernv_rng_probe+0x34/0x90 [powernv_rng] > > [ 11.755728] [cec3b450] [c0949218] > > platform_probe+0x78/0x110 > > [ 11.755750] [cec3b4d0] [c09442d8] > > really_probe+0x108/0x590 > > [ 11.755773] [cec3b560] [c0944814] > > __driver_probe_device+0xb4/0x230 > > [ 11.755799] [cec3b5e0] [c09449e4] > > driver_probe_device+0x54/0x130 > > [ 11.755824] [cec3b620] [c09456d8] > > __driver_attach+0x158/0x2b0 > > [ 11.755850] [cec3b6a0] [c0940764] > > bus_for_each_dev+0xb4/0x140 > > [ 11.755874] [cec3b700] [c0943734] driver_attach+0x34/0x50 > > [ 11.755896] [cec3b720] [c0942d88] > > bus_add_driver+0x218/0x300 > > [ 11.755921] [cec3b7b0] [c0946b84] > > driver_register+0xb4/0x1c0 > > [ 11.755947] [cec3b820] [c0948b98] > > __platform_driver_register+0x38/0x50 > > [ 11.755969] [cec3b840] [c00821c501e8] > > powernv_rng_driver_init+0x30/0x4c [powernv_rng] > > [ 11.755997] [cec3b860] [c00121b0] > > do_one_initcall+0x80/0x320 > > [ 11.756020] [cec3b940] [c02198bc] > > do_init_module+0x6c/0x290 > > [ 11.75604
BUG: Kernel NULL pointer dereference on read at 0x00000000 in pnv_get_random_long()
Hello I have a 8335-GCA POWER8 which got a kernel crash during boot: [ 11.754238] Kernel attempted to read user page (0) - exploit attempt? (uid: 0) [ 11.754437] BUG: Kernel NULL pointer dereference on read at 0x [ 11.754499] Faulting instruction address: 0xc00c3758 [ 11.754518] Oops: Kernel access of bad area, sig: 11 [#1] [ 11.754534] LE PAGE_SIZE=64K MMU=Hash SMP NR_CPUS=2048 NUMA PowerNV [ 11.754699] Modules linked in: powernv_rng(+) ecb ctr sr_mod hid ofpart fb_sys_fops cdrom i2c_algo_bit powernv_flash sg mtd vmx_crypto(+) ipmi_powernv ipmi_devintf at24(+) ipmi_msghandler opal_prd regmap_i2c nfsd gf128mul auth_rpcgss nfs_acl lockd grace sunrpc drm fuse configfs loop drm_panel_orientation_quirks ip_tables x_tables autofs4 uas usb_storage ext4 crc16 mbcache jbd2 crc32c_generic dm_mod xhci_pci xhci_hcd sd_mod t10_pi crc64_rocksoft crc64 crc_t10dif crct10dif_generic crct10dif_common usbcore tg3 libphy crc32c_vpmsum ahci usb_common libahci [ 11.754869] CPU: 25 PID: 1332 Comm: (udev-worker) Not tainted 6.1.106 #4 [ 11.754890] Hardware name: 8335-GCA POWER8 (raw) 0x4d0200 opal:skiboot-5.4.8-5787ad3 PowerNV [ 11.754926] NIP: c00c3758 LR: c00c3754 CTR: [ 11.754947] REGS: cec3af70 TRAP: 0300 Not tainted (6.1.106) [ 11.754966] MSR: 9280b033 CR: 4482 XER: 2000 [ 11.755168] CFAR: c01dfbb4 DAR: DSISR: 4000 IRQMASK: 0 GPR00: c00c3754 cec3b210 c113cd00 002c GPR04: 7fff cec3b010 cec3b008 000ff57e GPR08: 0027 c00ff7907f98 0001 2200 GPR12: c00eaf00 0020 2200 GPR16: 0009 00013c86f5d8 GPR20: 01002cd75d90 0005 GPR24: 01002cd794a0 01002cd75d90 c285e6fc c0f9e4a0 GPR28: 0003 0004 c010103ca180 [ 11.755363] NIP [c00c3758] pnv_get_random_long+0x88/0x170 [ 11.755386] LR [c00c3754] pnv_get_random_long+0x84/0x170 [ 11.755407] Call Trace: [ 11.755416] [cec3b210] [c00c3754] pnv_get_random_long+0x84/0x170 (unreliable) [ 11.755444] [cec3b280] [c00821c50130] powernv_rng_read+0x98/0x120 [powernv_rng] [ 11.755473] [cec3b300] [c091ac88] add_early_randomness+0x88/0x150 [ 11.755577] [cec3b340] [c091b2c4] hwrng_register+0x344/0x420 [ 11.755678] [cec3b3a0] [c091b408] devm_hwrng_register+0x68/0xf0 [ 11.755703] [cec3b3e0] [c00821c5003c] powernv_rng_probe+0x34/0x90 [powernv_rng] [ 11.755728] [cec3b450] [c0949218] platform_probe+0x78/0x110 [ 11.755750] [cec3b4d0] [c09442d8] really_probe+0x108/0x590 [ 11.755773] [cec3b560] [c0944814] __driver_probe_device+0xb4/0x230 [ 11.755799] [cec3b5e0] [c09449e4] driver_probe_device+0x54/0x130 [ 11.755824] [cec3b620] [c09456d8] __driver_attach+0x158/0x2b0 [ 11.755850] [cec3b6a0] [c0940764] bus_for_each_dev+0xb4/0x140 [ 11.755874] [cec3b700] [c0943734] driver_attach+0x34/0x50 [ 11.755896] [cec3b720] [c0942d88] bus_add_driver+0x218/0x300 [ 11.755921] [cec3b7b0] [c0946b84] driver_register+0xb4/0x1c0 [ 11.755947] [cec3b820] [c0948b98] __platform_driver_register+0x38/0x50 [ 11.755969] [cec3b840] [c00821c501e8] powernv_rng_driver_init+0x30/0x4c [powernv_rng] [ 11.755997] [cec3b860] [c00121b0] do_one_initcall+0x80/0x320 [ 11.756020] [cec3b940] [c02198bc] do_init_module+0x6c/0x290 [ 11.756042] [cec3b9c0] [c021d118] __do_sys_finit_module+0xd8/0x190 [ 11.756066] [cec3baf0] [c002b038] system_call_exception+0x138/0x260 [ 11.756091] [cec3be10] [c000c654] system_call_common+0xf4/0x258 [ 11.756117] --- interrupt: c00 at 0x7fffaae9a9e4 [ 11.756134] NIP: 7fffaae9a9e4 LR: 7fffab110500 CTR: [ 11.756153] REGS: cec3be80 TRAP: 0c00 Not tainted (6.1.106) [ 11.762944] MSR: 9280f033 CR: 2448 XER: [ 11.765251] IRQMASK: 0 GPR00: 0161 74b57210 7fffaafa6f00 0006 GPR04: 7fffab11be88 0006 GPR08: GPR12: 7fffab1fe240 0020 2200 GPR16: 000
[PATCH] macintosh: macio_asic: remove useless cast for driver.name
pci_driver name is const char pointer, so the cast it not necessary.
Signed-off-by: Corentin Labbe
---
drivers/macintosh/macio_asic.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/macintosh/macio_asic.c b/drivers/macintosh/macio_asic.c
index c1fdf2896021..1943a007e2d5 100644
--- a/drivers/macintosh/macio_asic.c
+++ b/drivers/macintosh/macio_asic.c
@@ -756,7 +756,7 @@ MODULE_DEVICE_TABLE (pci, pci_ids);
/* pci driver glue; this is a "new style" PCI driver module */
static struct pci_driver macio_pci_driver = {
- .name = (char *) "macio",
+ .name = "macio",
.id_table = pci_ids,
.probe = macio_pci_probe,
--
2.34.1
Re: [PATCH 1/4] crypto: nintendo-aes - add a new AES driver
Le Tue, Sep 21, 2021 at 11:39:27PM +0200, Emmanuel Gil Peyrot a écrit :
> This engine implements AES in CBC mode, using 128-bit keys only. It is
> present on both the Wii and the Wii U, and is apparently identical in
> both consoles.
>
> The hardware is capable of firing an interrupt when the operation is
> done, but this driver currently uses a busy loop, I’m not too sure
> whether it would be preferable to switch, nor how to achieve that.
>
> It also supports a mode where no operation is done, and thus could be
> used as a DMA copy engine, but I don’t know how to expose that to the
> kernel or whether it would even be useful.
>
> In my testing, on a Wii U, this driver reaches 80.7 MiB/s, while the
> aes-generic driver only reaches 30.9 MiB/s, so it is a quite welcome
> speedup.
>
> This driver was written based on reversed documentation, see:
> https://wiibrew.org/wiki/Hardware/AES
>
> Signed-off-by: Emmanuel Gil Peyrot
> Tested-by: Emmanuel Gil Peyrot # on Wii U
[...]
> +static int
> +do_crypt(const void *src, void *dst, u32 len, u32 flags)
> +{
> + u32 blocks = ((len >> 4) - 1) & AES_CTRL_BLOCK;
> + u32 status;
> + u32 counter = OP_TIMEOUT;
> + u32 i;
> +
> + /* Flush out all of src, we can’t know whether any of it is in cache */
> + for (i = 0; i < len; i += 32)
> + __asm__("dcbf 0, %0" : : "r" (src + i));
> + __asm__("sync" : : : "memory");
> +
> + /* Set the addresses for DMA */
> + iowrite32be(virt_to_phys((void *)src), base + AES_SRC);
> + iowrite32be(virt_to_phys(dst), base + AES_DEST);
Hello
Since you do DMA operation, I think you should use the DMA-API and call
dma_map_xxx()
This will prevent the use of __asm__ and virt_to_phys().
Regards
[PATCH v2] powerpc: build virtex dtb
I wanted to test the virtex440-ml507 qemu machine and found that the dtb for it was not builded. All powerpc DTB are only built when CONFIG_OF_ALL_DTBS is set which depend on COMPILE_TEST. This patchs adds build of virtex dtbs depending on CONFIG_XILINX_VIRTEX440_GENERIC_BOARD option. Signed-off-by: Corentin Labbe --- Changes since v1: - squashed the two dtb into one make line arch/powerpc/boot/dts/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/powerpc/boot/dts/Makefile b/arch/powerpc/boot/dts/Makefile index fb335d05aae8..1cbc0e4ce857 100644 --- a/arch/powerpc/boot/dts/Makefile +++ b/arch/powerpc/boot/dts/Makefile @@ -4,3 +4,4 @@ subdir-y += fsl dtstree:= $(srctree)/$(src) dtb-$(CONFIG_OF_ALL_DTBS) := $(patsubst $(dtstree)/%.dts,%.dtb, $(wildcard $(dtstree)/*.dts)) +dtb-$(CONFIG_XILINX_VIRTEX440_GENERIC_BOARD) += virtex440-ml507.dtb virtex440-ml510.dtb -- 2.19.2
[PATCH] powerpc: build virtex dtb
I wanted to test the virtex440-ml507 qemu machine and found that the dtb for it was not builded. All powerpc DTB are only built when CONFIG_OF_ALL_DTBS is set which depend on COMPILE_TEST. This patchs adds build of virtex dtbs depending on CONFIG_XILINX_VIRTEX440_GENERIC_BOARD option. Signed-off-by: Corentin Labbe --- arch/powerpc/boot/dts/Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/powerpc/boot/dts/Makefile b/arch/powerpc/boot/dts/Makefile index fb335d05aae8..cae14fca682e 100644 --- a/arch/powerpc/boot/dts/Makefile +++ b/arch/powerpc/boot/dts/Makefile @@ -4,3 +4,5 @@ subdir-y += fsl dtstree:= $(srctree)/$(src) dtb-$(CONFIG_OF_ALL_DTBS) := $(patsubst $(dtstree)/%.dts,%.dtb, $(wildcard $(dtstree)/*.dts)) +dtb-$(CONFIG_XILINX_VIRTEX440_GENERIC_BOARD) += virtex440-ml507.dtb +dtb-$(CONFIG_XILINX_VIRTEX440_GENERIC_BOARD) += virtex440-ml510.dtb -- 2.19.2
[PATCH] powerpc: build dtb even without COMPILE_TEST
I wanted to test the virtex440-ml507 qemu machine and found that the dtb for it was not builded. All powerpc DTB are only built when CONFIG_OF_ALL_DTBS is set which depend on COMPILE_TEST. But building DTB is not related to a "compile build test". So this patch made building of DTB independent of COMPILE_TEST (by depending only on the PPC arch) A better selection of which DTB to build could be done in the future like that do the ARM arch. Signed-off-by: Corentin Labbe --- arch/powerpc/boot/dts/Makefile | 2 +- arch/powerpc/boot/dts/fsl/Makefile | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/boot/dts/Makefile b/arch/powerpc/boot/dts/Makefile index fb335d05aae8..3a73cf41585b 100644 --- a/arch/powerpc/boot/dts/Makefile +++ b/arch/powerpc/boot/dts/Makefile @@ -3,4 +3,4 @@ subdir-y += fsl dtstree:= $(srctree)/$(src) -dtb-$(CONFIG_OF_ALL_DTBS) := $(patsubst $(dtstree)/%.dts,%.dtb, $(wildcard $(dtstree)/*.dts)) +dtb-$(CONFIG_PPC) := $(patsubst $(dtstree)/%.dts,%.dtb, $(wildcard $(dtstree)/*.dts)) diff --git a/arch/powerpc/boot/dts/fsl/Makefile b/arch/powerpc/boot/dts/fsl/Makefile index 3bae982641e9..27c5ca3a35be 100644 --- a/arch/powerpc/boot/dts/fsl/Makefile +++ b/arch/powerpc/boot/dts/fsl/Makefile @@ -1,4 +1,4 @@ # SPDX-License-Identifier: GPL-2.0 dtstree:= $(srctree)/$(src) -dtb-$(CONFIG_OF_ALL_DTBS) := $(patsubst $(dtstree)/%.dts,%.dtb, $(wildcard $(dtstree)/*.dts)) +dtb-$(CONFIG_PPC) := $(patsubst $(dtstree)/%.dts,%.dtb, $(wildcard $(dtstree)/*.dts)) -- 2.19.2
[PATCH v3 7/7] net: stmmac: dwmac-meson8b: use xxxsetbits_le32
This patch convert meson stmmac glue driver to use all xxxsetbits_le32
functions.
Signed-off-by: Corentin Labbe
Reviewed-by: Neil Armstrong
---
.../ethernet/stmicro/stmmac/dwmac-meson8b.c | 56 ---
1 file changed, 22 insertions(+), 34 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
index c5979569fd60..abcf65588576 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
@@ -23,6 +23,7 @@
#include
#include
#include
+#include
#include "stmmac_platform.h"
@@ -75,18 +76,6 @@ struct meson8b_dwmac_clk_configs {
struct clk_gate rgmii_tx_en;
};
-static void meson8b_dwmac_mask_bits(struct meson8b_dwmac *dwmac, u32 reg,
- u32 mask, u32 value)
-{
- u32 data;
-
- data = readl(dwmac->regs + reg);
- data &= ~mask;
- data |= (value & mask);
-
- writel(data, dwmac->regs + reg);
-}
-
static struct clk *meson8b_dwmac_register_clk(struct meson8b_dwmac *dwmac,
const char *name_suffix,
const char **parent_names,
@@ -192,14 +181,13 @@ static int meson8b_set_phy_mode(struct meson8b_dwmac
*dwmac)
case PHY_INTERFACE_MODE_RGMII_ID:
case PHY_INTERFACE_MODE_RGMII_TXID:
/* enable RGMII mode */
- meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
- PRG_ETH0_RGMII_MODE,
- PRG_ETH0_RGMII_MODE);
+ clrsetbits_le32(dwmac->regs + PRG_ETH0, PRG_ETH0_RGMII_MODE,
+ PRG_ETH0_RGMII_MODE);
break;
case PHY_INTERFACE_MODE_RMII:
/* disable RGMII mode -> enables RMII mode */
- meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
- PRG_ETH0_RGMII_MODE, 0);
+ clrsetbits_le32(dwmac->regs + PRG_ETH0, PRG_ETH0_RGMII_MODE,
+ 0);
break;
default:
dev_err(dwmac->dev, "fail to set phy-mode %s\n",
@@ -218,15 +206,15 @@ static int meson_axg_set_phy_mode(struct meson8b_dwmac
*dwmac)
case PHY_INTERFACE_MODE_RGMII_ID:
case PHY_INTERFACE_MODE_RGMII_TXID:
/* enable RGMII mode */
- meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
- PRG_ETH0_EXT_PHY_MODE_MASK,
- PRG_ETH0_EXT_RGMII_MODE);
+ clrsetbits_le32(dwmac->regs + PRG_ETH0,
+ PRG_ETH0_EXT_PHY_MODE_MASK,
+ PRG_ETH0_EXT_RGMII_MODE);
break;
case PHY_INTERFACE_MODE_RMII:
/* disable RGMII mode -> enables RMII mode */
- meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
- PRG_ETH0_EXT_PHY_MODE_MASK,
- PRG_ETH0_EXT_RMII_MODE);
+ clrsetbits_le32(dwmac->regs + PRG_ETH0,
+ PRG_ETH0_EXT_PHY_MODE_MASK,
+ PRG_ETH0_EXT_RMII_MODE);
break;
default:
dev_err(dwmac->dev, "fail to set phy-mode %s\n",
@@ -255,11 +243,11 @@ static int meson8b_init_prg_eth(struct meson8b_dwmac
*dwmac)
case PHY_INTERFACE_MODE_RGMII_ID:
case PHY_INTERFACE_MODE_RGMII_TXID:
/* only relevant for RMII mode -> disable in RGMII mode */
- meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
- PRG_ETH0_INVERTED_RMII_CLK, 0);
+ clrsetbits_le32(dwmac->regs + PRG_ETH0,
+ PRG_ETH0_INVERTED_RMII_CLK, 0);
- meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_TXDLY_MASK,
- tx_dly_val << PRG_ETH0_TXDLY_SHIFT);
+ clrsetbits_le32(dwmac->regs + PRG_ETH0, PRG_ETH0_TXDLY_MASK,
+ tx_dly_val << PRG_ETH0_TXDLY_SHIFT);
/* Configure the 125MHz RGMII TX clock, the IP block changes
* the output automatically (= without us having to configure
@@ -287,13 +275,13 @@ static int meson8b_init_prg_eth(struct meson8b_dwmac
*dwmac)
case PHY_INTERFACE_MODE_RMII:
/* invert internal clk_rmii_i to generate 25/2.5 tx_rx_clk */
- meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
- PRG_ETH0_INVERTED_RMII_CLK,
- PRG_ETH0_INVERTED_RMII_CLK);
+ clrsetbits_le32(dwmac->regs + PRG_ETH0,
+ PRG_ETH0_INVERTED_RMII_CLK,
+
[PATCH v3 6/7] drm: meson: use xxxsetbits_le32
This patch convert meson DRM driver to use all xxxsetbits_le32 functions.
Signed-off-by: Corentin Labbe
Reviewed-by: Neil Armstrong
Tested-by: Neil Armstrong
---
drivers/gpu/drm/meson/meson_crtc.c | 14 +++---
drivers/gpu/drm/meson/meson_dw_hdmi.c | 33 +++--
drivers/gpu/drm/meson/meson_plane.c | 13 ++---
drivers/gpu/drm/meson/meson_registers.h | 3 --
drivers/gpu/drm/meson/meson_venc.c | 13 ++---
drivers/gpu/drm/meson/meson_venc_cvbs.c | 4 +-
drivers/gpu/drm/meson/meson_viu.c | 65 +
drivers/gpu/drm/meson/meson_vpp.c | 22 -
8 files changed, 86 insertions(+), 81 deletions(-)
diff --git a/drivers/gpu/drm/meson/meson_crtc.c
b/drivers/gpu/drm/meson/meson_crtc.c
index 05520202c967..98f17ddd6b00 100644
--- a/drivers/gpu/drm/meson/meson_crtc.c
+++ b/drivers/gpu/drm/meson/meson_crtc.c
@@ -25,6 +25,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -98,8 +99,8 @@ static void meson_crtc_atomic_enable(struct drm_crtc *crtc,
writel(crtc_state->mode.hdisplay,
priv->io_base + _REG(VPP_POSTBLEND_H_SIZE));
- writel_bits_relaxed(VPP_POSTBLEND_ENABLE, VPP_POSTBLEND_ENABLE,
- priv->io_base + _REG(VPP_MISC));
+ clrsetbits_le32_relaxed(priv->io_base + _REG(VPP_MISC),
+ VPP_POSTBLEND_ENABLE, VPP_POSTBLEND_ENABLE);
priv->viu.osd1_enabled = true;
}
@@ -114,8 +115,8 @@ static void meson_crtc_atomic_disable(struct drm_crtc *crtc,
priv->viu.osd1_commit = false;
/* Disable VPP Postblend */
- writel_bits_relaxed(VPP_POSTBLEND_ENABLE, 0,
- priv->io_base + _REG(VPP_MISC));
+ clrsetbits_le32_relaxed(priv->io_base + _REG(VPP_MISC),
+ VPP_POSTBLEND_ENABLE, 0);
if (crtc->state->event && !crtc->state->active) {
spin_lock_irq(&crtc->dev->event_lock);
@@ -199,8 +200,9 @@ void meson_crtc_irq(struct meson_drm *priv)
MESON_CANVAS_BLKMODE_LINEAR);
/* Enable OSD1 */
- writel_bits_relaxed(VPP_OSD1_POSTBLEND, VPP_OSD1_POSTBLEND,
- priv->io_base + _REG(VPP_MISC));
+ clrsetbits_le32_relaxed(priv->io_base + _REG(VPP_MISC),
+ VPP_OSD1_POSTBLEND,
+ VPP_OSD1_POSTBLEND);
priv->viu.osd1_commit = false;
}
diff --git a/drivers/gpu/drm/meson/meson_dw_hdmi.c
b/drivers/gpu/drm/meson/meson_dw_hdmi.c
index df7247cd93f9..99a136209e15 100644
--- a/drivers/gpu/drm/meson/meson_dw_hdmi.c
+++ b/drivers/gpu/drm/meson/meson_dw_hdmi.c
@@ -24,6 +24,7 @@
#include
#include
#include
+#include
#include
#include
@@ -427,10 +428,10 @@ static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void
*data,
writel_relaxed(0, priv->io_base + _REG(ENCP_VIDEO_EN));
/* Temporary Disable HDMI video stream to HDMI-TX */
- writel_bits_relaxed(0x3, 0,
- priv->io_base + _REG(VPU_HDMI_SETTING));
- writel_bits_relaxed(0xf << 8, 0,
- priv->io_base + _REG(VPU_HDMI_SETTING));
+ clrsetbits_le32_relaxed(priv->io_base + _REG(VPU_HDMI_SETTING), 0x3,
+ 0);
+ clrsetbits_le32_relaxed(priv->io_base + _REG(VPU_HDMI_SETTING),
+ 0xf << 8, 0);
/* Re-Enable VENC video stream */
if (priv->venc.hdmi_use_enci)
@@ -439,16 +440,16 @@ static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void
*data,
writel_relaxed(1, priv->io_base + _REG(ENCP_VIDEO_EN));
/* Push back HDMI clock settings */
- writel_bits_relaxed(0xf << 8, wr_clk & (0xf << 8),
- priv->io_base + _REG(VPU_HDMI_SETTING));
+ clrsetbits_le32_relaxed(priv->io_base + _REG(VPU_HDMI_SETTING),
+ 0xf << 8, wr_clk & (0xf << 8));
/* Enable and Select HDMI video source for HDMI-TX */
if (priv->venc.hdmi_use_enci)
- writel_bits_relaxed(0x3, MESON_VENC_SOURCE_ENCI,
- priv->io_base + _REG(VPU_HDMI_SETTING));
+ clrsetbits_le32_relaxed(priv->io_base + _REG(VPU_HDMI_SETTING),
+ 0x3, MESON_VENC_SOURCE_ENCI);
else
- writel_bits_relaxed(0x3, MESON_VENC_SOURCE_ENCP,
- priv->io_base + _REG(VPU_HDMI_SETTING));
+ clrsetbits_le32_relaxed(priv->io_base + _REG(VPU_HDMI_SETTING),
+ 0x3, MESON_VENC_SOURCE_ENCP);
return 0;
}
@@ -632,8 +633,8 @@ static void meson_venc_hdmi_encoder_disable(s
[PATCH v3 5/7] net: ethernet: stmmac: dwmac-sun8i: use xxxsetbits_le32
This patch convert dwmac-sun8i driver to use all xxxsetbits_le32 functions.
Signed-off-by: Corentin Labbe
---
.../net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 62 +--
1 file changed, 16 insertions(+), 46 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
index f9a61f90cfbc..74067a59af50 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
@@ -28,6 +28,7 @@
#include
#include
#include
+#include
#include "stmmac.h"
#include "stmmac_platform.h"
@@ -342,50 +343,30 @@ static void sun8i_dwmac_disable_dma_irq(void __iomem
*ioaddr, u32 chan)
static void sun8i_dwmac_dma_start_tx(void __iomem *ioaddr, u32 chan)
{
- u32 v;
-
- v = readl(ioaddr + EMAC_TX_CTL1);
- v |= EMAC_TX_DMA_START;
- v |= EMAC_TX_DMA_EN;
- writel(v, ioaddr + EMAC_TX_CTL1);
+ setbits_le32(ioaddr + EMAC_TX_CTL1,
+EMAC_TX_DMA_START | EMAC_TX_DMA_EN);
}
static void sun8i_dwmac_enable_dma_transmission(void __iomem *ioaddr)
{
- u32 v;
-
- v = readl(ioaddr + EMAC_TX_CTL1);
- v |= EMAC_TX_DMA_START;
- v |= EMAC_TX_DMA_EN;
- writel(v, ioaddr + EMAC_TX_CTL1);
+ setbits_le32(ioaddr + EMAC_TX_CTL1,
+EMAC_TX_DMA_START | EMAC_TX_DMA_EN);
}
static void sun8i_dwmac_dma_stop_tx(void __iomem *ioaddr, u32 chan)
{
- u32 v;
-
- v = readl(ioaddr + EMAC_TX_CTL1);
- v &= ~EMAC_TX_DMA_EN;
- writel(v, ioaddr + EMAC_TX_CTL1);
+ clrbits_le32(ioaddr + EMAC_TX_CTL1, EMAC_TX_DMA_EN);
}
static void sun8i_dwmac_dma_start_rx(void __iomem *ioaddr, u32 chan)
{
- u32 v;
-
- v = readl(ioaddr + EMAC_RX_CTL1);
- v |= EMAC_RX_DMA_START;
- v |= EMAC_RX_DMA_EN;
- writel(v, ioaddr + EMAC_RX_CTL1);
+ setbits_le32(ioaddr + EMAC_RX_CTL1,
+EMAC_RX_DMA_START | EMAC_RX_DMA_EN);
}
static void sun8i_dwmac_dma_stop_rx(void __iomem *ioaddr, u32 chan)
{
- u32 v;
-
- v = readl(ioaddr + EMAC_RX_CTL1);
- v &= ~EMAC_RX_DMA_EN;
- writel(v, ioaddr + EMAC_RX_CTL1);
+ clrbits_le32(ioaddr + EMAC_RX_CTL1, EMAC_RX_DMA_EN);
}
static int sun8i_dwmac_dma_interrupt(void __iomem *ioaddr,
@@ -578,7 +559,6 @@ static void sun8i_dwmac_set_umac_addr(struct
mac_device_info *hw,
unsigned int reg_n)
{
void __iomem *ioaddr = hw->pcsr;
- u32 v;
if (!addr) {
writel(0, ioaddr + EMAC_MACADDR_HI(reg_n));
@@ -588,9 +568,8 @@ static void sun8i_dwmac_set_umac_addr(struct
mac_device_info *hw,
stmmac_set_mac_addr(ioaddr, addr, EMAC_MACADDR_HI(reg_n),
EMAC_MACADDR_LO(reg_n));
if (reg_n > 0) {
- v = readl(ioaddr + EMAC_MACADDR_HI(reg_n));
- v |= MAC_ADDR_TYPE_DST;
- writel(v, ioaddr + EMAC_MACADDR_HI(reg_n));
+ setbits_le32(ioaddr + EMAC_MACADDR_HI(reg_n),
+MAC_ADDR_TYPE_DST);
}
}
@@ -608,11 +587,8 @@ static void sun8i_dwmac_get_umac_addr(struct
mac_device_info *hw,
static int sun8i_dwmac_rx_ipc_enable(struct mac_device_info *hw)
{
void __iomem *ioaddr = hw->pcsr;
- u32 v;
- v = readl(ioaddr + EMAC_RX_CTL0);
- v |= EMAC_RX_DO_CRC;
- writel(v, ioaddr + EMAC_RX_CTL0);
+ setbits_le32(ioaddr + EMAC_RX_CTL0, EMAC_RX_DO_CRC);
return 1;
}
@@ -662,21 +638,15 @@ static void sun8i_dwmac_flow_ctrl(struct mac_device_info
*hw,
unsigned int pause_time, u32 tx_cnt)
{
void __iomem *ioaddr = hw->pcsr;
- u32 v;
- v = readl(ioaddr + EMAC_RX_CTL0);
if (fc == FLOW_AUTO)
- v |= EMAC_RX_FLOW_CTL_EN;
+ setbits_le32(ioaddr + EMAC_RX_CTL0, EMAC_RX_FLOW_CTL_EN);
else
- v &= ~EMAC_RX_FLOW_CTL_EN;
- writel(v, ioaddr + EMAC_RX_CTL0);
-
- v = readl(ioaddr + EMAC_TX_FLOW_CTL);
+ clrbits_le32(ioaddr + EMAC_RX_CTL0, EMAC_RX_FLOW_CTL_EN);
if (fc == FLOW_AUTO)
- v |= EMAC_TX_FLOW_CTL_EN;
+ setbits_le32(ioaddr + EMAC_TX_FLOW_CTL, EMAC_TX_FLOW_CTL_EN);
else
- v &= ~EMAC_TX_FLOW_CTL_EN;
- writel(v, ioaddr + EMAC_TX_FLOW_CTL);
+ clrbits_le32(ioaddr + EMAC_TX_FLOW_CTL, EMAC_TX_FLOW_CTL_EN);
}
static int sun8i_dwmac_reset(struct stmmac_priv *priv)
--
2.18.1
[PATCH v3 3/7 DONOTMERGE] coccinelle: add xxxsetbits_leXX converting spatch
This patch add a spatch which convert all open coded of
setbits_le32/clrbits_le32/clrsetbits_le32
and their 64 bits counterparts.
Note that 64 and 32_relaxed are generated via
cp scripts/coccinelle/misc/setbits32.cocci
scripts/coccinelle/misc/setbits32_relaxed.cocci
sed -i 's,readl,readl_relaxed,' scripts/coccinelle/misc/setbits32_relaxed.cocci
sed -i 's,writel,writel_relaxed,'
scripts/coccinelle/misc/setbits32_relaxed.cocci
sed -i 's,setbits_le32,setbits_le32_relaxed,g'
scripts/coccinelle/misc/setbits32_relaxed.cocci
sed -i 's,clrbits_le32,clrbits_le32_relaxed,g'
scripts/coccinelle/misc/setbits32_relaxed.cocci
cp scripts/coccinelle/misc/setbits32.cocci
scripts/coccinelle/misc/setbits64.cocci
sed -i 's,readl,readq,' scripts/coccinelle/misc/setbits64.cocci
sed -i 's,writel,writeq,' scripts/coccinelle/misc/setbits64.cocci
sed -i 's,le32,le64,' scripts/coccinelle/misc/setbits64.cocci
Signed-off-by: Corentin Labbe
---
scripts/add_new_include_in_source.py | 61 +++
scripts/coccinelle/misc/setbits32.cocci | 487 ++
.../coccinelle/misc/setbits32_relaxed.cocci | 487 ++
scripts/coccinelle/misc/setbits64.cocci | 487 ++
scripts/coccinelle/misc/setbits_dev.cocci | 235 +
5 files changed, 1757 insertions(+)
create mode 100755 scripts/add_new_include_in_source.py
create mode 100644 scripts/coccinelle/misc/setbits32.cocci
create mode 100644 scripts/coccinelle/misc/setbits32_relaxed.cocci
create mode 100644 scripts/coccinelle/misc/setbits64.cocci
create mode 100644 scripts/coccinelle/misc/setbits_dev.cocci
diff --git a/scripts/add_new_include_in_source.py
b/scripts/add_new_include_in_source.py
new file mode 100755
index ..a43ccfbf9921
--- /dev/null
+++ b/scripts/add_new_include_in_source.py
@@ -0,0 +1,61 @@
+#!/usr/bin/env python
+
+# add
+
+import os, sys
+import re
+import shutil
+
+if len(sys.argv) < 2:
+print("Usage: %s pathtosourcefile" % (sys.argv[0]))
+sys.exit(1)
+
+found_global_headers = False
+found_local_headers = False
+#first check it does already here
+with open(sys.argv[1], 'r') as fp:
+for line in fp:
+if re.search("#include \n", line):
+print("INFO: header already here")
+sys.exit(0)
+if re.search("^#include <", line):
+found_global_headers = True
+if re.search("^#include \"", line):
+found_local_headers = True
+fp.close()
+
+if not found_global_headers and not found_local_headers:
+print("No header included do it at hand")
+sys.exit(1)
+
+if found_global_headers:
+done = False
+inheader = False
+with open("%s.new" % sys.argv[1], 'w') as fw:
+with open(sys.argv[1], 'r') as fp:
+for line in fp:
+if re.search("^#include = "s" and line[17] >= "e" and
line[18] >= "t" and line[19] >= 'b'):
+done = True
+fw.write("#include \n")
+if not done and not re.search("^#include \n")
+fw.write(line)
+fw.close()
+fp.close()
+else:
+done = False
+with open("%s.new" % sys.argv[1], 'w') as fw:
+with open(sys.argv[1], 'r') as fp:
+for line in fp:
+if not done and re.search("^#include \"", line):
+fw.write("#include \n")
+done = True
+fw.write(line)
+fw.close()
+fp.close()
+
+shutil.move("%s.new" % sys.argv[1], sys.argv[1])
+print("%s done" % sys.argv[1])
diff --git a/scripts/coccinelle/misc/setbits32.cocci
b/scripts/coccinelle/misc/setbits32.cocci
new file mode 100644
index ..71400cac6830
--- /dev/null
+++ b/scripts/coccinelle/misc/setbits32.cocci
@@ -0,0 +1,487 @@
+// SPDX-License-Identifier: GPL-2.0
+// Confidence: High
+// Copyright: (c) 2018 Corentin LABBE
+
+virtual patch
+
+@p_clrsetbits_le32_l4@
+local idexpression rr;
+expression addr;
+expression set;
+expression clear;
+expression e;
+position p;
+@@
+
+- rr@p = readl(addr);
+- rr &= ~clear;
+- rr |= set;
+- writel(rr, addr);
++ clrsetbits_le32(addr, clear, set);
+ ... when != rr
+? rr = e
+
+@script:python depends on p_clrsetbits_le32_l4@
+p1 << p_clrsetbits_le32_l4.p;
+@@
+list.append(p1[0].file)
+
+
+@p_clrsetbits_le32_l3@
+local idexpression rr;
+expression addr;
+expression set;
+expression clear;
+expression e;
+position p;
+@@
+
+- rr@p = readl(addr);
+- rr &= ~clear | set;
+- writel(rr, addr);
++ clrsetbits_le32(addr, clear, set);
+ ... when != rr
+? rr = e
+
+@script:python depends on p_clrsetbits_le32_l3@
+p1 << p_clrsetbits_le32_l3.p;
+@@
+
[PATCH v3 4/7] ata: ahci_sunxi: use xxxsetbitsi_le32 functions
This patch converts ahci_sunxi to use xxxsetbits_le32 functions
Signed-off-by: Corentin Labbe
---
drivers/ata/ahci_sunxi.c | 62 +++-
1 file changed, 17 insertions(+), 45 deletions(-)
diff --git a/drivers/ata/ahci_sunxi.c b/drivers/ata/ahci_sunxi.c
index 911710643305..69c2e01c3d52 100644
--- a/drivers/ata/ahci_sunxi.c
+++ b/drivers/ata/ahci_sunxi.c
@@ -25,6 +25,7 @@
#include
#include
#include
+#include
#include "ahci.h"
#define DRV_NAME "ahci-sunxi"
@@ -58,34 +59,6 @@ MODULE_PARM_DESC(enable_pmp,
#define AHCI_P0PHYCR 0x0178
#define AHCI_P0PHYSR 0x017c
-static void sunxi_clrbits(void __iomem *reg, u32 clr_val)
-{
- u32 reg_val;
-
- reg_val = readl(reg);
- reg_val &= ~(clr_val);
- writel(reg_val, reg);
-}
-
-static void sunxi_setbits(void __iomem *reg, u32 set_val)
-{
- u32 reg_val;
-
- reg_val = readl(reg);
- reg_val |= set_val;
- writel(reg_val, reg);
-}
-
-static void sunxi_clrsetbits(void __iomem *reg, u32 clr_val, u32 set_val)
-{
- u32 reg_val;
-
- reg_val = readl(reg);
- reg_val &= ~(clr_val);
- reg_val |= set_val;
- writel(reg_val, reg);
-}
-
static u32 sunxi_getbits(void __iomem *reg, u8 mask, u8 shift)
{
return (readl(reg) >> shift) & mask;
@@ -100,22 +73,21 @@ static int ahci_sunxi_phy_init(struct device *dev, void
__iomem *reg_base)
writel(0, reg_base + AHCI_RWCR);
msleep(5);
- sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(19));
- sunxi_clrsetbits(reg_base + AHCI_PHYCS0R,
-(0x7 << 24),
-(0x5 << 24) | BIT(23) | BIT(18));
- sunxi_clrsetbits(reg_base + AHCI_PHYCS1R,
-(0x3 << 16) | (0x1f << 8) | (0x3 << 6),
-(0x2 << 16) | (0x6 << 8) | (0x2 << 6));
- sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(28) | BIT(15));
- sunxi_clrbits(reg_base + AHCI_PHYCS1R, BIT(19));
- sunxi_clrsetbits(reg_base + AHCI_PHYCS0R,
-(0x7 << 20), (0x3 << 20));
- sunxi_clrsetbits(reg_base + AHCI_PHYCS2R,
-(0x1f << 5), (0x19 << 5));
+ setbits_le32(reg_base + AHCI_PHYCS1R, BIT(19));
+ clrsetbits_le32(reg_base + AHCI_PHYCS0R, (0x7 << 24),
+ (0x5 << 24) | BIT(23) | BIT(18));
+ clrsetbits_le32(reg_base + AHCI_PHYCS1R,
+ (0x3 << 16) | (0x1f << 8) | (0x3 << 6),
+ (0x2 << 16) | (0x6 << 8) | (0x2 << 6));
+ setbits_le32(reg_base + AHCI_PHYCS1R, BIT(28) | BIT(15));
+ clrbits_le32(reg_base + AHCI_PHYCS1R, BIT(19));
+ clrsetbits_le32(reg_base + AHCI_PHYCS0R,
+ (0x7 << 20), (0x3 << 20));
+ clrsetbits_le32(reg_base + AHCI_PHYCS2R,
+ (0x1f << 5), (0x19 << 5));
msleep(5);
- sunxi_setbits(reg_base + AHCI_PHYCS0R, (0x1 << 19));
+ setbits_le32(reg_base + AHCI_PHYCS0R, (0x1 << 19));
timeout = 250; /* Power up takes aprox 50 us */
do {
@@ -130,7 +102,7 @@ static int ahci_sunxi_phy_init(struct device *dev, void
__iomem *reg_base)
udelay(1);
} while (1);
- sunxi_setbits(reg_base + AHCI_PHYCS2R, (0x1 << 24));
+ setbits_le32(reg_base + AHCI_PHYCS2R, (0x1 << 24));
timeout = 100; /* Calibration takes aprox 10 us */
do {
@@ -158,10 +130,10 @@ static void ahci_sunxi_start_engine(struct ata_port *ap)
struct ahci_host_priv *hpriv = ap->host->private_data;
/* Setup DMA before DMA start */
- sunxi_clrsetbits(hpriv->mmio + AHCI_P0DMACR, 0xff00, 0x4400);
+ clrsetbits_le32(hpriv->mmio + AHCI_P0DMACR, 0xff00, 0x4400);
/* Start DMA */
- sunxi_setbits(port_mmio + PORT_CMD, PORT_CMD_START);
+ setbits_le32(port_mmio + PORT_CMD, PORT_CMD_START);
}
static const struct ata_port_info ahci_sunxi_port_info = {
--
2.18.1
[PATCH v3 1/7] powerpc: rename setbits32/clrbits32 to setbits_be32/clrbits_be32
Since setbits32/clrbits32 work on be32, it's better to remove ambiguity on
the used data type.
Signed-off-by: Corentin Labbe
---
arch/powerpc/include/asm/fsl_lbc.h| 2 +-
arch/powerpc/include/asm/io.h | 4 +-
arch/powerpc/platforms/44x/canyonlands.c | 4 +-
arch/powerpc/platforms/4xx/gpio.c | 28 +++
arch/powerpc/platforms/512x/pdm360ng.c| 6 +-
arch/powerpc/platforms/52xx/mpc52xx_common.c | 6 +-
arch/powerpc/platforms/52xx/mpc52xx_gpt.c | 12 +--
arch/powerpc/platforms/82xx/ep8248e.c | 2 +-
arch/powerpc/platforms/82xx/km82xx.c | 6 +-
arch/powerpc/platforms/82xx/mpc8272_ads.c | 10 +--
arch/powerpc/platforms/82xx/pq2.c | 2 +-
arch/powerpc/platforms/82xx/pq2ads-pci-pic.c | 4 +-
arch/powerpc/platforms/82xx/pq2fads.c | 10 +--
arch/powerpc/platforms/83xx/km83xx.c | 6 +-
arch/powerpc/platforms/83xx/mpc836x_mds.c | 2 +-
arch/powerpc/platforms/85xx/mpc85xx_mds.c | 2 +-
arch/powerpc/platforms/85xx/mpc85xx_pm_ops.c | 4 +-
arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 2 +-
arch/powerpc/platforms/85xx/p1022_ds.c| 6 +-
arch/powerpc/platforms/85xx/p1022_rdk.c | 6 +-
arch/powerpc/platforms/85xx/t1042rdb_diu.c| 6 +-
arch/powerpc/platforms/85xx/twr_p102x.c | 2 +-
arch/powerpc/platforms/86xx/mpc8610_hpcd.c| 6 +-
arch/powerpc/platforms/8xx/adder875.c | 2 +-
arch/powerpc/platforms/8xx/m8xx_setup.c | 4 +-
arch/powerpc/platforms/8xx/mpc86xads_setup.c | 4 +-
arch/powerpc/platforms/8xx/mpc885ads_setup.c | 28 +++
.../platforms/embedded6xx/flipper-pic.c | 6 +-
arch/powerpc/platforms/embedded6xx/hlwd-pic.c | 8 +-
arch/powerpc/platforms/embedded6xx/wii.c | 12 +--
arch/powerpc/sysdev/cpm1.c| 26 +++
arch/powerpc/sysdev/cpm2.c| 16 ++--
arch/powerpc/sysdev/cpm_common.c | 4 +-
arch/powerpc/sysdev/fsl_85xx_l2ctlr.c | 16 ++--
arch/powerpc/sysdev/fsl_lbc.c | 2 +-
arch/powerpc/sysdev/fsl_pci.c | 12 +--
arch/powerpc/sysdev/fsl_pmc.c | 2 +-
arch/powerpc/sysdev/fsl_rcpm.c| 74 +--
arch/powerpc/sysdev/fsl_rio.c | 4 +-
arch/powerpc/sysdev/fsl_rmu.c | 9 ++-
arch/powerpc/sysdev/mpic_timer.c | 12 +--
41 files changed, 190 insertions(+), 189 deletions(-)
diff --git a/arch/powerpc/include/asm/fsl_lbc.h
b/arch/powerpc/include/asm/fsl_lbc.h
index c7240a024b96..4d6a56b48a28 100644
--- a/arch/powerpc/include/asm/fsl_lbc.h
+++ b/arch/powerpc/include/asm/fsl_lbc.h
@@ -276,7 +276,7 @@ static inline void fsl_upm_start_pattern(struct fsl_upm
*upm, u8 pat_offset)
*/
static inline void fsl_upm_end_pattern(struct fsl_upm *upm)
{
- clrbits32(upm->mxmr, MxMR_OP_RP);
+ clrbits_be32(upm->mxmr, MxMR_OP_RP);
while (in_be32(upm->mxmr) & MxMR_OP_RP)
cpu_relax();
diff --git a/arch/powerpc/include/asm/io.h b/arch/powerpc/include/asm/io.h
index 0a034519957d..bc2fc014fd4f 100644
--- a/arch/powerpc/include/asm/io.h
+++ b/arch/powerpc/include/asm/io.h
@@ -882,8 +882,8 @@ static inline void * bus_to_virt(unsigned long address)
#endif /* CONFIG_PPC32 */
/* access ports */
-#define setbits32(_addr, _v) out_be32((_addr), in_be32(_addr) | (_v))
-#define clrbits32(_addr, _v) out_be32((_addr), in_be32(_addr) & ~(_v))
+#define setbits_be32(_addr, _v) out_be32((_addr), in_be32(_addr) | (_v))
+#define clrbits_be32(_addr, _v) out_be32((_addr), in_be32(_addr) & ~(_v))
#define setbits16(_addr, _v) out_be16((_addr), in_be16(_addr) | (_v))
#define clrbits16(_addr, _v) out_be16((_addr), in_be16(_addr) & ~(_v))
diff --git a/arch/powerpc/platforms/44x/canyonlands.c
b/arch/powerpc/platforms/44x/canyonlands.c
index 157f4ce46386..6aeb4ca64d09 100644
--- a/arch/powerpc/platforms/44x/canyonlands.c
+++ b/arch/powerpc/platforms/44x/canyonlands.c
@@ -113,8 +113,8 @@ static int __init ppc460ex_canyonlands_fixup(void)
* USB2HStop and gpio19 will be USB2DStop. For more details refer to
* table 34-7 of PPC460EX user manual.
*/
- setbits32((vaddr + GPIO0_OSRH), 0x4200);
- setbits32((vaddr + GPIO0_TSRH), 0x4200);
+ setbits_be32((vaddr + GPIO0_OSRH), 0x4200);
+ setbits_be32((vaddr + GPIO0_TSRH), 0x4200);
err_gpio:
iounmap(vaddr);
err_bcsr:
diff --git a/arch/powerpc/platforms/4xx/gpio.c
b/arch/powerpc/platforms/4xx/gpio.c
index 2238e369cde4..8436da0617fd 100644
--- a/arch/powerpc/platforms/4xx/gpio.c
+++ b/arch/powerpc/platforms/4xx/gpio.c
@@ -82,9 +82,9 @@ __ppc4xx_gpio_set(struct gpio_chip *gc, unsigned int gpio,
int val)
struct ppc4xx_gpio __iomem *regs = mm_gc->regs;
if (val)
- setbits32(®s->or, GPIO_MASK(gpio));
+ setbits_be32(®s->or, GPIO_MASK(gpio));
[PATCH v3 0/7] include: add setbits32/clrbits32/clrsetbits32/setbits64/clrbits64/clrsetbits64
Hello This patchset adds a new set of functions which are open-coded in lot of place. Basicly the pattern is always the same, "read, modify a bit, write" some driver and the powerpc arch already have thoses pattern them as functions. (like ahci_sunxi.c or dwmac-meson8b) The first patch rename some powerpc functions for being consistent with the new name convention. The second patch adds the header with all setbits functions. The third patch is a try to implement a coccinelle semantic patch to find all place where xxxbits function could be used. It should not be merged since it is un-finalized. For the moment, the "add setbits.h header" is not working and need a future coccinelle version. The four last patch are example of some drivers conversion. Thoses patchs give an example of the reduction of code won by using xxxbits32. I would like to thanks Julia Lawall for her help on the coccinelle patch. Note that I dont know which maintainer will take the linux/setbits.h include patch. Regards Changes since v2: - Fixed patch title - Fixed style problems - shorted macro arguments name Changes since v1: - renamed LE functions to _leXX - updated coccinnelle patch with JLawall's comments Corentin Labbe (7): powerpc: rename setbits32/clrbits32 to setbits_be32/clrbits_be32 include: add setbits_leXX/clrbits_leXX/clrsetbits_leXX in linux/setbits.h coccinelle: add xxxsetbits_leXX converting spatch ata: ahci_sunxi: use xxxsetbitsi_le32 functions net: ethernet: stmmac: dwmac-sun8i: use xxxsetbits_le32 drm: meson: use xxxsetbits_le32 net: stmmac: dwmac-meson8b: use xxxsetbits_le32 arch/powerpc/include/asm/fsl_lbc.h| 2 +- arch/powerpc/include/asm/io.h | 4 +- arch/powerpc/platforms/44x/canyonlands.c | 4 +- arch/powerpc/platforms/4xx/gpio.c | 28 +- arch/powerpc/platforms/512x/pdm360ng.c| 6 +- arch/powerpc/platforms/52xx/mpc52xx_common.c | 6 +- arch/powerpc/platforms/52xx/mpc52xx_gpt.c | 12 +- arch/powerpc/platforms/82xx/ep8248e.c | 2 +- arch/powerpc/platforms/82xx/km82xx.c | 6 +- arch/powerpc/platforms/82xx/mpc8272_ads.c | 10 +- arch/powerpc/platforms/82xx/pq2.c | 2 +- arch/powerpc/platforms/82xx/pq2ads-pci-pic.c | 4 +- arch/powerpc/platforms/82xx/pq2fads.c | 10 +- arch/powerpc/platforms/83xx/km83xx.c | 6 +- arch/powerpc/platforms/83xx/mpc836x_mds.c | 2 +- arch/powerpc/platforms/85xx/mpc85xx_mds.c | 2 +- arch/powerpc/platforms/85xx/mpc85xx_pm_ops.c | 4 +- arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 2 +- arch/powerpc/platforms/85xx/p1022_ds.c| 6 +- arch/powerpc/platforms/85xx/p1022_rdk.c | 6 +- arch/powerpc/platforms/85xx/t1042rdb_diu.c| 6 +- arch/powerpc/platforms/85xx/twr_p102x.c | 2 +- arch/powerpc/platforms/86xx/mpc8610_hpcd.c| 6 +- arch/powerpc/platforms/8xx/adder875.c | 2 +- arch/powerpc/platforms/8xx/m8xx_setup.c | 4 +- arch/powerpc/platforms/8xx/mpc86xads_setup.c | 4 +- arch/powerpc/platforms/8xx/mpc885ads_setup.c | 28 +- .../platforms/embedded6xx/flipper-pic.c | 6 +- arch/powerpc/platforms/embedded6xx/hlwd-pic.c | 8 +- arch/powerpc/platforms/embedded6xx/wii.c | 12 +- arch/powerpc/sysdev/cpm1.c| 26 +- arch/powerpc/sysdev/cpm2.c| 16 +- arch/powerpc/sysdev/cpm_common.c | 4 +- arch/powerpc/sysdev/fsl_85xx_l2ctlr.c | 16 +- arch/powerpc/sysdev/fsl_lbc.c | 2 +- arch/powerpc/sysdev/fsl_pci.c | 12 +- arch/powerpc/sysdev/fsl_pmc.c | 2 +- arch/powerpc/sysdev/fsl_rcpm.c| 74 +-- arch/powerpc/sysdev/fsl_rio.c | 4 +- arch/powerpc/sysdev/fsl_rmu.c | 9 +- arch/powerpc/sysdev/mpic_timer.c | 12 +- drivers/ata/ahci_sunxi.c | 62 +-- drivers/gpu/drm/meson/meson_crtc.c| 14 +- drivers/gpu/drm/meson/meson_dw_hdmi.c | 33 +- drivers/gpu/drm/meson/meson_plane.c | 13 +- drivers/gpu/drm/meson/meson_registers.h | 3 - drivers/gpu/drm/meson/meson_venc.c| 13 +- drivers/gpu/drm/meson/meson_venc_cvbs.c | 4 +- drivers/gpu/drm/meson/meson_viu.c | 65 +-- drivers/gpu/drm/meson/meson_vpp.c | 22 +- .../ethernet/stmicro/stmmac/dwmac-meson8b.c | 56 +- .../net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 62 +-- include/linux/setbits.h | 84 +++ scripts/add_new_include_in_source.py | 61 +++ scripts/coccinelle/misc/setbits32.cocci | 487 ++ .../coccinelle/misc/setbits32_relaxed.cocci | 487 ++ scripts/coccinelle/misc/setbits64.cocci | 487 ++ scripts/coccinelle/misc/setbits_dev.cocci | 235 + 58 files changed, 2172 insertions(+), 395
[PATCH v3 2/7] include: add setbits_leXX/clrbits_leXX/clrsetbits_leXX in linux/setbits.h
This patch adds setbits_le32/clrbits_le32/clrsetbits_le32 and setbits_le64/clrbits_le64/clrsetbits_le64 in linux/setbits.h header. Signed-off-by: Corentin Labbe --- include/linux/setbits.h | 84 + 1 file changed, 84 insertions(+) create mode 100644 include/linux/setbits.h diff --git a/include/linux/setbits.h b/include/linux/setbits.h new file mode 100644 index ..c82faf8d7fe4 --- /dev/null +++ b/include/linux/setbits.h @@ -0,0 +1,84 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __LINUX_SETBITS_H +#define __LINUX_SETBITS_H + +#include + +#define __setbits(rfn, wfn, addr, set) wfn((rfn(addr) | (set)), addr) +#define __clrbits(rfn, wfn, addr, mask) wfn((rfn(addr) & ~(mask)), addr) +#define __clrsetbits(rfn, wfn, addr, mask, set) wfn(((rfn(addr) & ~(mask)) | (set)), addr) +#define __setclrbits(rfn, wfn, addr, mask, set) wfn(((rfn(addr) | (set)) & ~(mask)), addr) + +#ifndef setbits_le32 +#define setbits_le32(addr, set) __setbits(readl, writel, addr, set) +#endif +#ifndef setbits_le32_relaxed +#define setbits_le32_relaxed(addr, set) __setbits(readl_relaxed, writel_relaxed, \ + addr, set) +#endif + +#ifndef clrbits_le32 +#define clrbits_le32(addr, mask) __clrbits(readl, writel, addr, mask) +#endif +#ifndef clrbits_le32_relaxed +#define clrbits_le32_relaxed(addr, mask) __clrbits(readl_relaxed, writel_relaxed, \ + addr, mask) +#endif + +#ifndef clrsetbits_le32 +#define clrsetbits_le32(addr, mask, set) __clrsetbits(readl, writel, addr, mask, set) +#endif +#ifndef clrsetbits_le32_relaxed +#define clrsetbits_le32_relaxed(addr, mask, set) __clrsetbits(readl_relaxed, \ + writel_relaxed, \ + addr, mask, set) +#endif + +#ifndef setclrbits_le32 +#define setclrbits_le32(addr, mask, set) __setclrbits(readl, writel, addr, mask, set) +#endif +#ifndef setclrbits_le32_relaxed +#define setclrbits_le32_relaxed(addr, mask, set) __setclrbits(readl_relaxed, \ + writel_relaxed, \ + addr, mask, set) +#endif + +/* We cannot use CONFIG_64BIT as some x86 drivers use non-atomicwriteq() */ +#if defined(writeq) && defined(readq) +#ifndef setbits_le64 +#define setbits_le64(addr, set) __setbits(readq, writeq, addr, set) +#endif +#ifndef setbits_le64_relaxed +#define setbits_le64_relaxed(addr, set) __setbits(readq_relaxed, writeq_relaxed, \ + addr, set) +#endif + +#ifndef clrbits_le64 +#define clrbits_le64(addr, mask) __clrbits(readq, writeq, addr, mask) +#endif +#ifndef clrbits_le64_relaxed +#define clrbits_le64_relaxed(addr, mask) __clrbits(readq_relaxed, writeq_relaxed, \ + addr, mask) +#endif + +#ifndef clrsetbits_le64 +#define clrsetbits_le64(addr, mask, set) __clrsetbits(readq, writeq, addr, mask, set) +#endif +#ifndef clrsetbits_le64_relaxed +#define clrsetbits_le64_relaxed(addr, mask, set) __clrsetbits(readq_relaxed, \ + writeq_relaxed, \ + addr, mask, set) +#endif + +#ifndef setclrbits_le64 +#define setclrbits_le64(addr, mask, set) __setclrbits(readq, writeq, addr, mask, set) +#endif +#ifndef setclrbits_le64_relaxed +#define setclrbits_le64_relaxed(addr, mask, set) __setclrbits(readq_relaxed, \ + writeq_relaxed, \ + addr, mask, set) +#endif + +#endif /* writeq/readq */ + +#endif /* __LINUX_SETBITS_H */ -- 2.18.1
[PATCH v2 7/7] net: stmmac: dwmac-meson8b: use xxxsetbits32
This patch convert meson stmmac glue driver to use all xxxsetbits32 functions.
Signed-off-by: Corentin Labbe
---
.../net/ethernet/stmicro/stmmac/dwmac-meson8b.c| 56 +-
1 file changed, 22 insertions(+), 34 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
index c5979569fd60..abcf65588576 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
@@ -23,6 +23,7 @@
#include
#include
#include
+#include
#include "stmmac_platform.h"
@@ -75,18 +76,6 @@ struct meson8b_dwmac_clk_configs {
struct clk_gate rgmii_tx_en;
};
-static void meson8b_dwmac_mask_bits(struct meson8b_dwmac *dwmac, u32 reg,
- u32 mask, u32 value)
-{
- u32 data;
-
- data = readl(dwmac->regs + reg);
- data &= ~mask;
- data |= (value & mask);
-
- writel(data, dwmac->regs + reg);
-}
-
static struct clk *meson8b_dwmac_register_clk(struct meson8b_dwmac *dwmac,
const char *name_suffix,
const char **parent_names,
@@ -192,14 +181,13 @@ static int meson8b_set_phy_mode(struct meson8b_dwmac
*dwmac)
case PHY_INTERFACE_MODE_RGMII_ID:
case PHY_INTERFACE_MODE_RGMII_TXID:
/* enable RGMII mode */
- meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
- PRG_ETH0_RGMII_MODE,
- PRG_ETH0_RGMII_MODE);
+ clrsetbits_le32(dwmac->regs + PRG_ETH0, PRG_ETH0_RGMII_MODE,
+ PRG_ETH0_RGMII_MODE);
break;
case PHY_INTERFACE_MODE_RMII:
/* disable RGMII mode -> enables RMII mode */
- meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
- PRG_ETH0_RGMII_MODE, 0);
+ clrsetbits_le32(dwmac->regs + PRG_ETH0, PRG_ETH0_RGMII_MODE,
+ 0);
break;
default:
dev_err(dwmac->dev, "fail to set phy-mode %s\n",
@@ -218,15 +206,15 @@ static int meson_axg_set_phy_mode(struct meson8b_dwmac
*dwmac)
case PHY_INTERFACE_MODE_RGMII_ID:
case PHY_INTERFACE_MODE_RGMII_TXID:
/* enable RGMII mode */
- meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
- PRG_ETH0_EXT_PHY_MODE_MASK,
- PRG_ETH0_EXT_RGMII_MODE);
+ clrsetbits_le32(dwmac->regs + PRG_ETH0,
+ PRG_ETH0_EXT_PHY_MODE_MASK,
+ PRG_ETH0_EXT_RGMII_MODE);
break;
case PHY_INTERFACE_MODE_RMII:
/* disable RGMII mode -> enables RMII mode */
- meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
- PRG_ETH0_EXT_PHY_MODE_MASK,
- PRG_ETH0_EXT_RMII_MODE);
+ clrsetbits_le32(dwmac->regs + PRG_ETH0,
+ PRG_ETH0_EXT_PHY_MODE_MASK,
+ PRG_ETH0_EXT_RMII_MODE);
break;
default:
dev_err(dwmac->dev, "fail to set phy-mode %s\n",
@@ -255,11 +243,11 @@ static int meson8b_init_prg_eth(struct meson8b_dwmac
*dwmac)
case PHY_INTERFACE_MODE_RGMII_ID:
case PHY_INTERFACE_MODE_RGMII_TXID:
/* only relevant for RMII mode -> disable in RGMII mode */
- meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
- PRG_ETH0_INVERTED_RMII_CLK, 0);
+ clrsetbits_le32(dwmac->regs + PRG_ETH0,
+ PRG_ETH0_INVERTED_RMII_CLK, 0);
- meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_TXDLY_MASK,
- tx_dly_val << PRG_ETH0_TXDLY_SHIFT);
+ clrsetbits_le32(dwmac->regs + PRG_ETH0, PRG_ETH0_TXDLY_MASK,
+ tx_dly_val << PRG_ETH0_TXDLY_SHIFT);
/* Configure the 125MHz RGMII TX clock, the IP block changes
* the output automatically (= without us having to configure
@@ -287,13 +275,13 @@ static int meson8b_init_prg_eth(struct meson8b_dwmac
*dwmac)
case PHY_INTERFACE_MODE_RMII:
/* invert internal clk_rmii_i to generate 25/2.5 tx_rx_clk */
- meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
- PRG_ETH0_INVERTED_RMII_CLK,
- PRG_ETH0_INVERTED_RMII_CLK);
+ clrsetbits_le32(dwmac->regs + PRG_ETH0,
+ PRG_ETH0_INVERTED_RMII_CLK,
+ PRG_ET
[PATCH v2 6/7] drm: meson: use xxxsetbits32
This patch convert meson DRM driver to use all xxxsetbits32 functions.
Signed-off-by: Corentin Labbe
---
drivers/gpu/drm/meson/meson_crtc.c | 14 ---
drivers/gpu/drm/meson/meson_dw_hdmi.c | 33 +
drivers/gpu/drm/meson/meson_plane.c | 13 ---
drivers/gpu/drm/meson/meson_registers.h | 3 --
drivers/gpu/drm/meson/meson_venc.c | 13 ---
drivers/gpu/drm/meson/meson_venc_cvbs.c | 4 +-
drivers/gpu/drm/meson/meson_viu.c | 65 +
drivers/gpu/drm/meson/meson_vpp.c | 22 +--
8 files changed, 86 insertions(+), 81 deletions(-)
diff --git a/drivers/gpu/drm/meson/meson_crtc.c
b/drivers/gpu/drm/meson/meson_crtc.c
index 05520202c967..98f17ddd6b00 100644
--- a/drivers/gpu/drm/meson/meson_crtc.c
+++ b/drivers/gpu/drm/meson/meson_crtc.c
@@ -25,6 +25,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -98,8 +99,8 @@ static void meson_crtc_atomic_enable(struct drm_crtc *crtc,
writel(crtc_state->mode.hdisplay,
priv->io_base + _REG(VPP_POSTBLEND_H_SIZE));
- writel_bits_relaxed(VPP_POSTBLEND_ENABLE, VPP_POSTBLEND_ENABLE,
- priv->io_base + _REG(VPP_MISC));
+ clrsetbits_le32_relaxed(priv->io_base + _REG(VPP_MISC),
+ VPP_POSTBLEND_ENABLE, VPP_POSTBLEND_ENABLE);
priv->viu.osd1_enabled = true;
}
@@ -114,8 +115,8 @@ static void meson_crtc_atomic_disable(struct drm_crtc *crtc,
priv->viu.osd1_commit = false;
/* Disable VPP Postblend */
- writel_bits_relaxed(VPP_POSTBLEND_ENABLE, 0,
- priv->io_base + _REG(VPP_MISC));
+ clrsetbits_le32_relaxed(priv->io_base + _REG(VPP_MISC),
+ VPP_POSTBLEND_ENABLE, 0);
if (crtc->state->event && !crtc->state->active) {
spin_lock_irq(&crtc->dev->event_lock);
@@ -199,8 +200,9 @@ void meson_crtc_irq(struct meson_drm *priv)
MESON_CANVAS_BLKMODE_LINEAR);
/* Enable OSD1 */
- writel_bits_relaxed(VPP_OSD1_POSTBLEND, VPP_OSD1_POSTBLEND,
- priv->io_base + _REG(VPP_MISC));
+ clrsetbits_le32_relaxed(priv->io_base + _REG(VPP_MISC),
+ VPP_OSD1_POSTBLEND,
+ VPP_OSD1_POSTBLEND);
priv->viu.osd1_commit = false;
}
diff --git a/drivers/gpu/drm/meson/meson_dw_hdmi.c
b/drivers/gpu/drm/meson/meson_dw_hdmi.c
index df7247cd93f9..99a136209e15 100644
--- a/drivers/gpu/drm/meson/meson_dw_hdmi.c
+++ b/drivers/gpu/drm/meson/meson_dw_hdmi.c
@@ -24,6 +24,7 @@
#include
#include
#include
+#include
#include
#include
@@ -427,10 +428,10 @@ static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void
*data,
writel_relaxed(0, priv->io_base + _REG(ENCP_VIDEO_EN));
/* Temporary Disable HDMI video stream to HDMI-TX */
- writel_bits_relaxed(0x3, 0,
- priv->io_base + _REG(VPU_HDMI_SETTING));
- writel_bits_relaxed(0xf << 8, 0,
- priv->io_base + _REG(VPU_HDMI_SETTING));
+ clrsetbits_le32_relaxed(priv->io_base + _REG(VPU_HDMI_SETTING), 0x3,
+ 0);
+ clrsetbits_le32_relaxed(priv->io_base + _REG(VPU_HDMI_SETTING),
+ 0xf << 8, 0);
/* Re-Enable VENC video stream */
if (priv->venc.hdmi_use_enci)
@@ -439,16 +440,16 @@ static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void
*data,
writel_relaxed(1, priv->io_base + _REG(ENCP_VIDEO_EN));
/* Push back HDMI clock settings */
- writel_bits_relaxed(0xf << 8, wr_clk & (0xf << 8),
- priv->io_base + _REG(VPU_HDMI_SETTING));
+ clrsetbits_le32_relaxed(priv->io_base + _REG(VPU_HDMI_SETTING),
+ 0xf << 8, wr_clk & (0xf << 8));
/* Enable and Select HDMI video source for HDMI-TX */
if (priv->venc.hdmi_use_enci)
- writel_bits_relaxed(0x3, MESON_VENC_SOURCE_ENCI,
- priv->io_base + _REG(VPU_HDMI_SETTING));
+ clrsetbits_le32_relaxed(priv->io_base + _REG(VPU_HDMI_SETTING),
+ 0x3, MESON_VENC_SOURCE_ENCI);
else
- writel_bits_relaxed(0x3, MESON_VENC_SOURCE_ENCP,
- priv->io_base + _REG(VPU_HDMI_SETTING));
+ clrsetbits_le32_relaxed(priv->io_base + _REG(VPU_HDMI_SETTING),
+ 0x3, MESON_VENC_SOURCE_ENCP);
return 0;
}
@@ -632,8 +633,8 @@ static void meson_venc_hdmi_encoder_disable(struct
drm_encoder *encoder)
DRM_DEBUG_DRI
[PATCH v2 5/7] net: ethernet: stmmac: dwmac-sun8i: use xxxsetbits32
This patch convert dwmac-sun8i driver to use all xxxsetbits32 functions.
Signed-off-by: Corentin Labbe
---
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 62 ++-
1 file changed, 16 insertions(+), 46 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
index f9a61f90cfbc..74067a59af50 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
@@ -28,6 +28,7 @@
#include
#include
#include
+#include
#include "stmmac.h"
#include "stmmac_platform.h"
@@ -342,50 +343,30 @@ static void sun8i_dwmac_disable_dma_irq(void __iomem
*ioaddr, u32 chan)
static void sun8i_dwmac_dma_start_tx(void __iomem *ioaddr, u32 chan)
{
- u32 v;
-
- v = readl(ioaddr + EMAC_TX_CTL1);
- v |= EMAC_TX_DMA_START;
- v |= EMAC_TX_DMA_EN;
- writel(v, ioaddr + EMAC_TX_CTL1);
+ setbits_le32(ioaddr + EMAC_TX_CTL1,
+EMAC_TX_DMA_START | EMAC_TX_DMA_EN);
}
static void sun8i_dwmac_enable_dma_transmission(void __iomem *ioaddr)
{
- u32 v;
-
- v = readl(ioaddr + EMAC_TX_CTL1);
- v |= EMAC_TX_DMA_START;
- v |= EMAC_TX_DMA_EN;
- writel(v, ioaddr + EMAC_TX_CTL1);
+ setbits_le32(ioaddr + EMAC_TX_CTL1,
+EMAC_TX_DMA_START | EMAC_TX_DMA_EN);
}
static void sun8i_dwmac_dma_stop_tx(void __iomem *ioaddr, u32 chan)
{
- u32 v;
-
- v = readl(ioaddr + EMAC_TX_CTL1);
- v &= ~EMAC_TX_DMA_EN;
- writel(v, ioaddr + EMAC_TX_CTL1);
+ clrbits_le32(ioaddr + EMAC_TX_CTL1, EMAC_TX_DMA_EN);
}
static void sun8i_dwmac_dma_start_rx(void __iomem *ioaddr, u32 chan)
{
- u32 v;
-
- v = readl(ioaddr + EMAC_RX_CTL1);
- v |= EMAC_RX_DMA_START;
- v |= EMAC_RX_DMA_EN;
- writel(v, ioaddr + EMAC_RX_CTL1);
+ setbits_le32(ioaddr + EMAC_RX_CTL1,
+EMAC_RX_DMA_START | EMAC_RX_DMA_EN);
}
static void sun8i_dwmac_dma_stop_rx(void __iomem *ioaddr, u32 chan)
{
- u32 v;
-
- v = readl(ioaddr + EMAC_RX_CTL1);
- v &= ~EMAC_RX_DMA_EN;
- writel(v, ioaddr + EMAC_RX_CTL1);
+ clrbits_le32(ioaddr + EMAC_RX_CTL1, EMAC_RX_DMA_EN);
}
static int sun8i_dwmac_dma_interrupt(void __iomem *ioaddr,
@@ -578,7 +559,6 @@ static void sun8i_dwmac_set_umac_addr(struct
mac_device_info *hw,
unsigned int reg_n)
{
void __iomem *ioaddr = hw->pcsr;
- u32 v;
if (!addr) {
writel(0, ioaddr + EMAC_MACADDR_HI(reg_n));
@@ -588,9 +568,8 @@ static void sun8i_dwmac_set_umac_addr(struct
mac_device_info *hw,
stmmac_set_mac_addr(ioaddr, addr, EMAC_MACADDR_HI(reg_n),
EMAC_MACADDR_LO(reg_n));
if (reg_n > 0) {
- v = readl(ioaddr + EMAC_MACADDR_HI(reg_n));
- v |= MAC_ADDR_TYPE_DST;
- writel(v, ioaddr + EMAC_MACADDR_HI(reg_n));
+ setbits_le32(ioaddr + EMAC_MACADDR_HI(reg_n),
+MAC_ADDR_TYPE_DST);
}
}
@@ -608,11 +587,8 @@ static void sun8i_dwmac_get_umac_addr(struct
mac_device_info *hw,
static int sun8i_dwmac_rx_ipc_enable(struct mac_device_info *hw)
{
void __iomem *ioaddr = hw->pcsr;
- u32 v;
- v = readl(ioaddr + EMAC_RX_CTL0);
- v |= EMAC_RX_DO_CRC;
- writel(v, ioaddr + EMAC_RX_CTL0);
+ setbits_le32(ioaddr + EMAC_RX_CTL0, EMAC_RX_DO_CRC);
return 1;
}
@@ -662,21 +638,15 @@ static void sun8i_dwmac_flow_ctrl(struct mac_device_info
*hw,
unsigned int pause_time, u32 tx_cnt)
{
void __iomem *ioaddr = hw->pcsr;
- u32 v;
- v = readl(ioaddr + EMAC_RX_CTL0);
if (fc == FLOW_AUTO)
- v |= EMAC_RX_FLOW_CTL_EN;
+ setbits_le32(ioaddr + EMAC_RX_CTL0, EMAC_RX_FLOW_CTL_EN);
else
- v &= ~EMAC_RX_FLOW_CTL_EN;
- writel(v, ioaddr + EMAC_RX_CTL0);
-
- v = readl(ioaddr + EMAC_TX_FLOW_CTL);
+ clrbits_le32(ioaddr + EMAC_RX_CTL0, EMAC_RX_FLOW_CTL_EN);
if (fc == FLOW_AUTO)
- v |= EMAC_TX_FLOW_CTL_EN;
+ setbits_le32(ioaddr + EMAC_TX_FLOW_CTL, EMAC_TX_FLOW_CTL_EN);
else
- v &= ~EMAC_TX_FLOW_CTL_EN;
- writel(v, ioaddr + EMAC_TX_FLOW_CTL);
+ clrbits_le32(ioaddr + EMAC_TX_FLOW_CTL, EMAC_TX_FLOW_CTL_EN);
}
static int sun8i_dwmac_reset(struct stmmac_priv *priv)
--
2.16.4
[PATCH v2 3/7] coccinelle: add xxxsetbitsXX converting spatch
This patch add a spatch which convert all open coded of
setbits32/clrbits32/clrsetbits32
and their 64 bits counterparts.
Note that 64 and 32_relaxed are generated via
cp scripts/coccinelle/misc/setbits32.cocci
scripts/coccinelle/misc/setbits32_relaxed.cocci
sed -i 's,readl,readl_relaxed,' scripts/coccinelle/misc/setbits32_relaxed.cocci
sed -i 's,writel,writel_relaxed,'
scripts/coccinelle/misc/setbits32_relaxed.cocci
sed -i 's,setbits_le32,setbits_le32_relaxed,g'
scripts/coccinelle/misc/setbits32_relaxed.cocci
sed -i 's,clrbits_le32,clrbits_le32_relaxed,g'
scripts/coccinelle/misc/setbits32_relaxed.cocci
cp scripts/coccinelle/misc/setbits32.cocci
scripts/coccinelle/misc/setbits64.cocci
sed -i 's,readl,readq,' scripts/coccinelle/misc/setbits64.cocci
sed -i 's,writel,writeq,' scripts/coccinelle/misc/setbits64.cocci
sed -i 's,le32,le64,' scripts/coccinelle/misc/setbits64.cocci
Signed-off-by: Corentin Labbe
---
scripts/add_new_include_in_source.py| 61 +++
scripts/coccinelle/misc/setbits32.cocci | 487
scripts/coccinelle/misc/setbits32_relaxed.cocci | 487
scripts/coccinelle/misc/setbits64.cocci | 487
scripts/coccinelle/misc/setbits_dev.cocci | 235
5 files changed, 1757 insertions(+)
create mode 100755 scripts/add_new_include_in_source.py
create mode 100644 scripts/coccinelle/misc/setbits32.cocci
create mode 100644 scripts/coccinelle/misc/setbits32_relaxed.cocci
create mode 100644 scripts/coccinelle/misc/setbits64.cocci
create mode 100644 scripts/coccinelle/misc/setbits_dev.cocci
diff --git a/scripts/add_new_include_in_source.py
b/scripts/add_new_include_in_source.py
new file mode 100755
index ..a43ccfbf9921
--- /dev/null
+++ b/scripts/add_new_include_in_source.py
@@ -0,0 +1,61 @@
+#!/usr/bin/env python
+
+# add
+
+import os, sys
+import re
+import shutil
+
+if len(sys.argv) < 2:
+print("Usage: %s pathtosourcefile" % (sys.argv[0]))
+sys.exit(1)
+
+found_global_headers = False
+found_local_headers = False
+#first check it does already here
+with open(sys.argv[1], 'r') as fp:
+for line in fp:
+if re.search("#include \n", line):
+print("INFO: header already here")
+sys.exit(0)
+if re.search("^#include <", line):
+found_global_headers = True
+if re.search("^#include \"", line):
+found_local_headers = True
+fp.close()
+
+if not found_global_headers and not found_local_headers:
+print("No header included do it at hand")
+sys.exit(1)
+
+if found_global_headers:
+done = False
+inheader = False
+with open("%s.new" % sys.argv[1], 'w') as fw:
+with open(sys.argv[1], 'r') as fp:
+for line in fp:
+if re.search("^#include = "s" and line[17] >= "e" and
line[18] >= "t" and line[19] >= 'b'):
+done = True
+fw.write("#include \n")
+if not done and not re.search("^#include \n")
+fw.write(line)
+fw.close()
+fp.close()
+else:
+done = False
+with open("%s.new" % sys.argv[1], 'w') as fw:
+with open(sys.argv[1], 'r') as fp:
+for line in fp:
+if not done and re.search("^#include \"", line):
+fw.write("#include \n")
+done = True
+fw.write(line)
+fw.close()
+fp.close()
+
+shutil.move("%s.new" % sys.argv[1], sys.argv[1])
+print("%s done" % sys.argv[1])
diff --git a/scripts/coccinelle/misc/setbits32.cocci
b/scripts/coccinelle/misc/setbits32.cocci
new file mode 100644
index ..71400cac6830
--- /dev/null
+++ b/scripts/coccinelle/misc/setbits32.cocci
@@ -0,0 +1,487 @@
+// SPDX-License-Identifier: GPL-2.0
+// Confidence: High
+// Copyright: (c) 2018 Corentin LABBE
+
+virtual patch
+
+@p_clrsetbits_le32_l4@
+local idexpression rr;
+expression addr;
+expression set;
+expression clear;
+expression e;
+position p;
+@@
+
+- rr@p = readl(addr);
+- rr &= ~clear;
+- rr |= set;
+- writel(rr, addr);
++ clrsetbits_le32(addr, clear, set);
+ ... when != rr
+? rr = e
+
+@script:python depends on p_clrsetbits_le32_l4@
+p1 << p_clrsetbits_le32_l4.p;
+@@
+list.append(p1[0].file)
+
+
+@p_clrsetbits_le32_l3@
+local idexpression rr;
+expression addr;
+expression set;
+expression clear;
+expression e;
+position p;
+@@
+
+- rr@p = readl(addr);
+- rr &= ~clear | set;
+- writel(rr, addr);
++ clrsetbits_le32(addr, clear, set);
+ ... when != rr
+? rr = e
+
+@script:python depends on p_clrsetbits_le32_l3@
+p1 <<
[PATCH v2 4/7] ata: ahci_sunxi: use xxxsetbits32 functions
This patch converts ahci_sunxi to use xxxsetbits32 functions
Signed-off-by: Corentin Labbe
---
drivers/ata/ahci_sunxi.c | 51
1 file changed, 12 insertions(+), 39 deletions(-)
diff --git a/drivers/ata/ahci_sunxi.c b/drivers/ata/ahci_sunxi.c
index 911710643305..5b285a6dff60 100644
--- a/drivers/ata/ahci_sunxi.c
+++ b/drivers/ata/ahci_sunxi.c
@@ -25,6 +25,7 @@
#include
#include
#include
+#include
#include "ahci.h"
#define DRV_NAME "ahci-sunxi"
@@ -58,34 +59,6 @@ MODULE_PARM_DESC(enable_pmp,
#define AHCI_P0PHYCR 0x0178
#define AHCI_P0PHYSR 0x017c
-static void sunxi_clrbits(void __iomem *reg, u32 clr_val)
-{
- u32 reg_val;
-
- reg_val = readl(reg);
- reg_val &= ~(clr_val);
- writel(reg_val, reg);
-}
-
-static void sunxi_setbits(void __iomem *reg, u32 set_val)
-{
- u32 reg_val;
-
- reg_val = readl(reg);
- reg_val |= set_val;
- writel(reg_val, reg);
-}
-
-static void sunxi_clrsetbits(void __iomem *reg, u32 clr_val, u32 set_val)
-{
- u32 reg_val;
-
- reg_val = readl(reg);
- reg_val &= ~(clr_val);
- reg_val |= set_val;
- writel(reg_val, reg);
-}
-
static u32 sunxi_getbits(void __iomem *reg, u8 mask, u8 shift)
{
return (readl(reg) >> shift) & mask;
@@ -100,22 +73,22 @@ static int ahci_sunxi_phy_init(struct device *dev, void
__iomem *reg_base)
writel(0, reg_base + AHCI_RWCR);
msleep(5);
- sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(19));
- sunxi_clrsetbits(reg_base + AHCI_PHYCS0R,
+ setbits_le32(reg_base + AHCI_PHYCS1R, BIT(19));
+ clrsetbits_le32(reg_base + AHCI_PHYCS0R,
(0x7 << 24),
(0x5 << 24) | BIT(23) | BIT(18));
- sunxi_clrsetbits(reg_base + AHCI_PHYCS1R,
+ clrsetbits_le32(reg_base + AHCI_PHYCS1R,
(0x3 << 16) | (0x1f << 8) | (0x3 << 6),
(0x2 << 16) | (0x6 << 8) | (0x2 << 6));
- sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(28) | BIT(15));
- sunxi_clrbits(reg_base + AHCI_PHYCS1R, BIT(19));
- sunxi_clrsetbits(reg_base + AHCI_PHYCS0R,
+ setbits_le32(reg_base + AHCI_PHYCS1R, BIT(28) | BIT(15));
+ clrbits_le32(reg_base + AHCI_PHYCS1R, BIT(19));
+ clrsetbits_le32(reg_base + AHCI_PHYCS0R,
(0x7 << 20), (0x3 << 20));
- sunxi_clrsetbits(reg_base + AHCI_PHYCS2R,
+ clrsetbits_le32(reg_base + AHCI_PHYCS2R,
(0x1f << 5), (0x19 << 5));
msleep(5);
- sunxi_setbits(reg_base + AHCI_PHYCS0R, (0x1 << 19));
+ setbits_le32(reg_base + AHCI_PHYCS0R, (0x1 << 19));
timeout = 250; /* Power up takes aprox 50 us */
do {
@@ -130,7 +103,7 @@ static int ahci_sunxi_phy_init(struct device *dev, void
__iomem *reg_base)
udelay(1);
} while (1);
- sunxi_setbits(reg_base + AHCI_PHYCS2R, (0x1 << 24));
+ setbits_le32(reg_base + AHCI_PHYCS2R, (0x1 << 24));
timeout = 100; /* Calibration takes aprox 10 us */
do {
@@ -158,10 +131,10 @@ static void ahci_sunxi_start_engine(struct ata_port *ap)
struct ahci_host_priv *hpriv = ap->host->private_data;
/* Setup DMA before DMA start */
- sunxi_clrsetbits(hpriv->mmio + AHCI_P0DMACR, 0xff00, 0x4400);
+ clrsetbits_le32(hpriv->mmio + AHCI_P0DMACR, 0xff00, 0x4400);
/* Start DMA */
- sunxi_setbits(port_mmio + PORT_CMD, PORT_CMD_START);
+ setbits_le32(port_mmio + PORT_CMD, PORT_CMD_START);
}
static const struct ata_port_info ahci_sunxi_port_info = {
--
2.16.4
[PATCH v2 1/7] powerpc: rename setbits32/clrbits32 to setbits32_be/clrbits32_be
Since setbits32/clrbits32 work on be32, it's better to remove ambiguity on
the used data type.
Signed-off-by: Corentin Labbe
---
arch/powerpc/include/asm/fsl_lbc.h | 2 +-
arch/powerpc/include/asm/io.h| 5 +-
arch/powerpc/platforms/44x/canyonlands.c | 4 +-
arch/powerpc/platforms/4xx/gpio.c| 28 -
arch/powerpc/platforms/512x/pdm360ng.c | 6 +-
arch/powerpc/platforms/52xx/mpc52xx_common.c | 6 +-
arch/powerpc/platforms/52xx/mpc52xx_gpt.c| 10 ++--
arch/powerpc/platforms/82xx/ep8248e.c| 2 +-
arch/powerpc/platforms/82xx/km82xx.c | 6 +-
arch/powerpc/platforms/82xx/mpc8272_ads.c| 10 ++--
arch/powerpc/platforms/82xx/pq2.c| 2 +-
arch/powerpc/platforms/82xx/pq2ads-pci-pic.c | 4 +-
arch/powerpc/platforms/82xx/pq2fads.c| 10 ++--
arch/powerpc/platforms/83xx/km83xx.c | 6 +-
arch/powerpc/platforms/83xx/mpc836x_mds.c| 2 +-
arch/powerpc/platforms/85xx/mpc85xx_mds.c| 2 +-
arch/powerpc/platforms/85xx/mpc85xx_pm_ops.c | 4 +-
arch/powerpc/platforms/85xx/mpc85xx_rdb.c| 2 +-
arch/powerpc/platforms/85xx/p1022_ds.c | 4 +-
arch/powerpc/platforms/85xx/p1022_rdk.c | 4 +-
arch/powerpc/platforms/85xx/t1042rdb_diu.c | 4 +-
arch/powerpc/platforms/85xx/twr_p102x.c | 2 +-
arch/powerpc/platforms/86xx/mpc8610_hpcd.c | 4 +-
arch/powerpc/platforms/8xx/adder875.c| 2 +-
arch/powerpc/platforms/8xx/m8xx_setup.c | 4 +-
arch/powerpc/platforms/8xx/mpc86xads_setup.c | 4 +-
arch/powerpc/platforms/8xx/mpc885ads_setup.c | 28 -
arch/powerpc/platforms/embedded6xx/flipper-pic.c | 6 +-
arch/powerpc/platforms/embedded6xx/hlwd-pic.c| 8 +--
arch/powerpc/platforms/embedded6xx/wii.c | 10 ++--
arch/powerpc/sysdev/cpm1.c | 26 -
arch/powerpc/sysdev/cpm2.c | 16 ++---
arch/powerpc/sysdev/cpm_common.c | 4 +-
arch/powerpc/sysdev/fsl_85xx_l2ctlr.c| 8 +--
arch/powerpc/sysdev/fsl_lbc.c| 2 +-
arch/powerpc/sysdev/fsl_pci.c| 8 +--
arch/powerpc/sysdev/fsl_pmc.c| 2 +-
arch/powerpc/sysdev/fsl_rcpm.c | 74
arch/powerpc/sysdev/fsl_rio.c| 4 +-
arch/powerpc/sysdev/fsl_rmu.c| 8 +--
arch/powerpc/sysdev/mpic_timer.c | 12 ++--
41 files changed, 178 insertions(+), 177 deletions(-)
diff --git a/arch/powerpc/include/asm/fsl_lbc.h
b/arch/powerpc/include/asm/fsl_lbc.h
index c7240a024b96..4d6a56b48a28 100644
--- a/arch/powerpc/include/asm/fsl_lbc.h
+++ b/arch/powerpc/include/asm/fsl_lbc.h
@@ -276,7 +276,7 @@ static inline void fsl_upm_start_pattern(struct fsl_upm
*upm, u8 pat_offset)
*/
static inline void fsl_upm_end_pattern(struct fsl_upm *upm)
{
- clrbits32(upm->mxmr, MxMR_OP_RP);
+ clrbits_be32(upm->mxmr, MxMR_OP_RP);
while (in_be32(upm->mxmr) & MxMR_OP_RP)
cpu_relax();
diff --git a/arch/powerpc/include/asm/io.h b/arch/powerpc/include/asm/io.h
index e0331e754568..57486a1b9992 100644
--- a/arch/powerpc/include/asm/io.h
+++ b/arch/powerpc/include/asm/io.h
@@ -873,8 +873,8 @@ static inline void * bus_to_virt(unsigned long address)
#endif /* CONFIG_PPC32 */
/* access ports */
-#define setbits32(_addr, _v) out_be32((_addr), in_be32(_addr) | (_v))
-#define clrbits32(_addr, _v) out_be32((_addr), in_be32(_addr) & ~(_v))
+#define setbits_be32(_addr, _v) out_be32((_addr), in_be32(_addr) | (_v))
+#define clrbits_be32(_addr, _v) out_be32((_addr), in_be32(_addr) & ~(_v))
#define setbits16(_addr, _v) out_be16((_addr), in_be16(_addr) | (_v))
#define clrbits16(_addr, _v) out_be16((_addr), in_be16(_addr) & ~(_v))
@@ -904,6 +904,7 @@ static inline void * bus_to_virt(unsigned long address)
#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
+#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
#endif /* __KERNEL__ */
diff --git a/arch/powerpc/platforms/44x/canyonlands.c
b/arch/powerpc/platforms/44x/canyonlands.c
index 157f4ce46386..6aeb4ca64d09 100644
--- a/arch/powerpc/platforms/44x/canyonlands.c
+++ b/arch/powerpc/platforms/44x/canyonlands.c
@@ -113,8 +113,8 @@ static int __init ppc460ex_canyonlands_fixup(void)
* USB2HStop and gpio19 will be USB2DStop. For more details refer to
* table 34-7 of PPC460EX user manual.
*/
- setbits32((vaddr + GPIO0_OSRH), 0x4200);
- setbits32((vaddr + GPIO0_TSRH), 0x4200);
+ setbits_be32((vaddr + GPIO0_OSRH), 0x4200);
+ setbits_be32((vaddr + GPIO0_TSRH), 0x4200);
err_gpio:
iounmap(vaddr);
err_bcsr:
diff --gi
[PATCH v2 2/7] include: add setbits32/clrbits32/clrsetbits32/setbits64/clrbits64/clrsetbits64 in linux/setbits.h
This patch adds setbits32/clrbits32/clrsetbits32 and setbits64/clrbits64/clrsetbits64 in linux/setbits.h header. Signed-off-by: Corentin Labbe --- include/linux/setbits.h | 88 + 1 file changed, 88 insertions(+) create mode 100644 include/linux/setbits.h diff --git a/include/linux/setbits.h b/include/linux/setbits.h new file mode 100644 index ..6e7e257134ae --- /dev/null +++ b/include/linux/setbits.h @@ -0,0 +1,88 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __LINUX_SETBITS_H +#define __LINUX_SETBITS_H + +#include + +#define __setbits(readfunction, writefunction, addr, set) \ + writefunction((readfunction(addr) | (set)), addr) +#define __clrbits(readfunction, writefunction, addr, mask) \ + writefunction((readfunction(addr) & ~(mask)), addr) +#define __clrsetbits(readfunction, writefunction, addr, mask, set) \ + writefunction(((readfunction(addr) & ~(mask)) | (set)), addr) +#define __setclrbits(readfunction, writefunction, addr, mask, set) \ + writefunction(((readfunction(addr) | (set)) & ~(mask)), addr) + +#ifndef setbits_le32 +#define setbits_le32(addr, set) __setbits(readl, writel, addr, set) +#endif +#ifndef setbits_le32_relaxed +#define setbits_le32_relaxed(addr, set) __setbits(readl_relaxed, writel_relaxed, \ + addr, set) +#endif + +#ifndef clrbits_le32 +#define clrbits_le32(addr, mask) __clrbits(readl, writel, addr, mask) +#endif +#ifndef clrbits_le32_relaxed +#define clrbits_le32_relaxed(addr, mask) __clrbits(readl_relaxed, writel_relaxed, \ + addr, mask) +#endif + +#ifndef clrsetbits_le32 +#define clrsetbits_le32(addr, mask, set) __clrsetbits(readl, writel, addr, mask, set) +#endif +#ifndef clrsetbits_le32_relaxed +#define clrsetbits_le32_relaxed(addr, mask, set) __clrsetbits(readl_relaxed, \ + writel_relaxed, \ + addr, mask, set) +#endif + +#ifndef setclrbits_le32 +#define setclrbits_le32(addr, mask, set) __setclrbits(readl, writel, addr, mask, set) +#endif +#ifndef setclrbits_le32_relaxed +#define setclrbits_le32_relaxed(addr, mask, set) __setclrbits(readl_relaxed, \ + writel_relaxed, \ + addr, mask, set) +#endif + +/* We cannot use CONFIG_64BIT as some x86 drivers use non-atomicwriteq() */ +#if defined(writeq) && defined(readq) +#ifndef setbits_le64 +#define setbits_le64(addr, set) __setbits(readq, writeq, addr, set) +#endif +#ifndef setbits_le64_relaxed +#define setbits_le64_relaxed(addr, set) __setbits(readq_relaxed, writeq_relaxed, \ + addr, set) +#endif + +#ifndef clrbits_le64 +#define clrbits_le64(addr, mask) __clrbits(readq, writeq, addr, mask) +#endif +#ifndef clrbits_le64_relaxed +#define clrbits_le64_relaxed(addr, mask) __clrbits(readq_relaxed, writeq_relaxed, \ + addr, mask) +#endif + +#ifndef clrsetbits_le64 +#define clrsetbits_le64(addr, mask, set) __clrsetbits(readq, writeq, addr, mask, set) +#endif +#ifndef clrsetbits_le64_relaxed +#define clrsetbits_le64_relaxed(addr, mask, set) __clrsetbits(readq_relaxed, \ + writeq_relaxed, \ + addr, mask, set) +#endif + +#ifndef setclrbits_le64 +#define setclrbits_le64(addr, mask, set) __setclrbits(readq, writeq, addr, mask, set) +#endif +#ifndef setclrbits_le64_relaxed +#define setclrbits_le64_relaxed(addr, mask, set) __setclrbits(readq_relaxed, \ + writeq_relaxed, \ + addr, mask, set) +#endif + +#endif /* writeq/readq */ + +#endif /* __LINUX_SETBITS_H */ -- 2.16.4
[PATCH v2 0/7] include: add setbits32/clrbits32/clrsetbits32/setbits64/clrbits64/clrsetbits64
Hello This patchset adds a new set of functions which are open-coded in lot of place. Basicly the pattern is always the same, "read, modify a bit, write" some driver and the powerpc arch already have thoses pattern them as functions. (like ahci_sunxi.c or dwmac-meson8b) The first patch rename some powerpc funtions for being consistent with the new name convention. The second patch adds the header with all setbits functions. The third patch is a try to implement a coccinelle semantic patch to find all place where xxxbits function could be used. It should not be merged since it is un-finalized. For the moment, the "add setbits.h header" is not working and need a future coccinelle version. The four last patch are example of some drivers convertion. Thoses patchs give an example of the reduction of code won by using xxxbits32. I would like to thanks Julia Lawall for her help on the coccinelle patch. Regards Changes since v1: - renamed LE functions to _leXX - updated coccinnelle patch with JLawall's comments Corentin Labbe (7): powerpc: rename setbits32/clrbits32 to setbits32_be/clrbits32_be include: add setbits32/clrbits32/clrsetbits32/setbits64/clrbits64/clrsetbits64 in linux/setbits.h coccinelle: add xxxsetbitsXX converting spatch ata: ahci_sunxi: use xxxsetbits32 functions net: ethernet: stmmac: dwmac-sun8i: use xxxsetbits32 drm: meson: use xxxsetbits32 net: stmmac: dwmac-meson8b: use xxxsetbits32 arch/powerpc/include/asm/fsl_lbc.h | 2 +- arch/powerpc/include/asm/io.h | 5 +- arch/powerpc/platforms/44x/canyonlands.c | 4 +- arch/powerpc/platforms/4xx/gpio.c | 28 +- arch/powerpc/platforms/512x/pdm360ng.c | 6 +- arch/powerpc/platforms/52xx/mpc52xx_common.c | 6 +- arch/powerpc/platforms/52xx/mpc52xx_gpt.c | 10 +- arch/powerpc/platforms/82xx/ep8248e.c | 2 +- arch/powerpc/platforms/82xx/km82xx.c | 6 +- arch/powerpc/platforms/82xx/mpc8272_ads.c | 10 +- arch/powerpc/platforms/82xx/pq2.c | 2 +- arch/powerpc/platforms/82xx/pq2ads-pci-pic.c | 4 +- arch/powerpc/platforms/82xx/pq2fads.c | 10 +- arch/powerpc/platforms/83xx/km83xx.c | 6 +- arch/powerpc/platforms/83xx/mpc836x_mds.c | 2 +- arch/powerpc/platforms/85xx/mpc85xx_mds.c | 2 +- arch/powerpc/platforms/85xx/mpc85xx_pm_ops.c | 4 +- arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 2 +- arch/powerpc/platforms/85xx/p1022_ds.c | 4 +- arch/powerpc/platforms/85xx/p1022_rdk.c| 4 +- arch/powerpc/platforms/85xx/t1042rdb_diu.c | 4 +- arch/powerpc/platforms/85xx/twr_p102x.c| 2 +- arch/powerpc/platforms/86xx/mpc8610_hpcd.c | 4 +- arch/powerpc/platforms/8xx/adder875.c | 2 +- arch/powerpc/platforms/8xx/m8xx_setup.c| 4 +- arch/powerpc/platforms/8xx/mpc86xads_setup.c | 4 +- arch/powerpc/platforms/8xx/mpc885ads_setup.c | 28 +- arch/powerpc/platforms/embedded6xx/flipper-pic.c | 6 +- arch/powerpc/platforms/embedded6xx/hlwd-pic.c | 8 +- arch/powerpc/platforms/embedded6xx/wii.c | 10 +- arch/powerpc/sysdev/cpm1.c | 26 +- arch/powerpc/sysdev/cpm2.c | 16 +- arch/powerpc/sysdev/cpm_common.c | 4 +- arch/powerpc/sysdev/fsl_85xx_l2ctlr.c | 8 +- arch/powerpc/sysdev/fsl_lbc.c | 2 +- arch/powerpc/sysdev/fsl_pci.c | 8 +- arch/powerpc/sysdev/fsl_pmc.c | 2 +- arch/powerpc/sysdev/fsl_rcpm.c | 74 ++-- arch/powerpc/sysdev/fsl_rio.c | 4 +- arch/powerpc/sysdev/fsl_rmu.c | 8 +- arch/powerpc/sysdev/mpic_timer.c | 12 +- drivers/ata/ahci_sunxi.c | 51 +-- drivers/gpu/drm/meson/meson_crtc.c | 14 +- drivers/gpu/drm/meson/meson_dw_hdmi.c | 33 +- drivers/gpu/drm/meson/meson_plane.c| 13 +- drivers/gpu/drm/meson/meson_registers.h| 3 - drivers/gpu/drm/meson/meson_venc.c | 13 +- drivers/gpu/drm/meson/meson_venc_cvbs.c| 4 +- drivers/gpu/drm/meson/meson_viu.c | 65 +-- drivers/gpu/drm/meson/meson_vpp.c | 22 +- .../net/ethernet/stmicro/stmmac/dwmac-meson8b.c| 56 +-- drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 62 +-- include/linux/setbits.h| 88 scripts/add_new_include_in_source.py | 61 +++ scripts/coccinelle/misc/setbits32.cocci| 487 + scripts/coccinelle/misc/setbits32_relaxed.cocci| 487 + scripts/coccinelle/misc/setbits
[PATCH 1/5] powerpc: rename setbits32/clrbits32 to setbits32_be/clrbits32_be
Since setbits32/clrbits32 work on be32, it's better to remove ambiguity on
the used data type.
Signed-off-by: Corentin Labbe
---
arch/powerpc/include/asm/fsl_lbc.h | 2 +-
arch/powerpc/include/asm/io.h| 5 +-
arch/powerpc/platforms/44x/canyonlands.c | 4 +-
arch/powerpc/platforms/4xx/gpio.c| 28 -
arch/powerpc/platforms/512x/pdm360ng.c | 6 +-
arch/powerpc/platforms/52xx/mpc52xx_common.c | 6 +-
arch/powerpc/platforms/52xx/mpc52xx_gpt.c| 10 ++--
arch/powerpc/platforms/82xx/ep8248e.c| 2 +-
arch/powerpc/platforms/82xx/km82xx.c | 6 +-
arch/powerpc/platforms/82xx/mpc8272_ads.c| 10 ++--
arch/powerpc/platforms/82xx/pq2.c| 2 +-
arch/powerpc/platforms/82xx/pq2ads-pci-pic.c | 4 +-
arch/powerpc/platforms/82xx/pq2fads.c| 10 ++--
arch/powerpc/platforms/83xx/km83xx.c | 6 +-
arch/powerpc/platforms/83xx/mpc836x_mds.c| 2 +-
arch/powerpc/platforms/85xx/mpc85xx_mds.c| 2 +-
arch/powerpc/platforms/85xx/mpc85xx_pm_ops.c | 4 +-
arch/powerpc/platforms/85xx/mpc85xx_rdb.c| 2 +-
arch/powerpc/platforms/85xx/p1022_ds.c | 4 +-
arch/powerpc/platforms/85xx/p1022_rdk.c | 4 +-
arch/powerpc/platforms/85xx/t1042rdb_diu.c | 4 +-
arch/powerpc/platforms/85xx/twr_p102x.c | 2 +-
arch/powerpc/platforms/86xx/mpc8610_hpcd.c | 4 +-
arch/powerpc/platforms/8xx/adder875.c| 2 +-
arch/powerpc/platforms/8xx/m8xx_setup.c | 4 +-
arch/powerpc/platforms/8xx/mpc86xads_setup.c | 4 +-
arch/powerpc/platforms/8xx/mpc885ads_setup.c | 28 -
arch/powerpc/platforms/embedded6xx/flipper-pic.c | 6 +-
arch/powerpc/platforms/embedded6xx/hlwd-pic.c| 8 +--
arch/powerpc/platforms/embedded6xx/wii.c | 10 ++--
arch/powerpc/sysdev/cpm1.c | 26 -
arch/powerpc/sysdev/cpm2.c | 16 ++---
arch/powerpc/sysdev/cpm_common.c | 4 +-
arch/powerpc/sysdev/fsl_85xx_l2ctlr.c| 8 +--
arch/powerpc/sysdev/fsl_lbc.c| 2 +-
arch/powerpc/sysdev/fsl_pci.c| 8 +--
arch/powerpc/sysdev/fsl_pmc.c| 2 +-
arch/powerpc/sysdev/fsl_rcpm.c | 74
arch/powerpc/sysdev/fsl_rio.c| 4 +-
arch/powerpc/sysdev/fsl_rmu.c| 8 +--
arch/powerpc/sysdev/mpic_timer.c | 12 ++--
41 files changed, 178 insertions(+), 177 deletions(-)
diff --git a/arch/powerpc/include/asm/fsl_lbc.h
b/arch/powerpc/include/asm/fsl_lbc.h
index c7240a024b96..55d7aa0c27cf 100644
--- a/arch/powerpc/include/asm/fsl_lbc.h
+++ b/arch/powerpc/include/asm/fsl_lbc.h
@@ -276,7 +276,7 @@ static inline void fsl_upm_start_pattern(struct fsl_upm
*upm, u8 pat_offset)
*/
static inline void fsl_upm_end_pattern(struct fsl_upm *upm)
{
- clrbits32(upm->mxmr, MxMR_OP_RP);
+ clrbits32_be(upm->mxmr, MxMR_OP_RP);
while (in_be32(upm->mxmr) & MxMR_OP_RP)
cpu_relax();
diff --git a/arch/powerpc/include/asm/io.h b/arch/powerpc/include/asm/io.h
index e0331e754568..29ecefd41ecb 100644
--- a/arch/powerpc/include/asm/io.h
+++ b/arch/powerpc/include/asm/io.h
@@ -873,8 +873,8 @@ static inline void * bus_to_virt(unsigned long address)
#endif /* CONFIG_PPC32 */
/* access ports */
-#define setbits32(_addr, _v) out_be32((_addr), in_be32(_addr) | (_v))
-#define clrbits32(_addr, _v) out_be32((_addr), in_be32(_addr) & ~(_v))
+#define setbits32_be(_addr, _v) out_be32((_addr), in_be32(_addr) | (_v))
+#define clrbits32_be(_addr, _v) out_be32((_addr), in_be32(_addr) & ~(_v))
#define setbits16(_addr, _v) out_be16((_addr), in_be16(_addr) | (_v))
#define clrbits16(_addr, _v) out_be16((_addr), in_be16(_addr) & ~(_v))
@@ -904,6 +904,7 @@ static inline void * bus_to_virt(unsigned long address)
#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
+#define clrsetbits32_be(addr, clear, set) clrsetbits(be32, addr, clear, set)
#endif /* __KERNEL__ */
diff --git a/arch/powerpc/platforms/44x/canyonlands.c
b/arch/powerpc/platforms/44x/canyonlands.c
index 157f4ce46386..7145a730769d 100644
--- a/arch/powerpc/platforms/44x/canyonlands.c
+++ b/arch/powerpc/platforms/44x/canyonlands.c
@@ -113,8 +113,8 @@ static int __init ppc460ex_canyonlands_fixup(void)
* USB2HStop and gpio19 will be USB2DStop. For more details refer to
* table 34-7 of PPC460EX user manual.
*/
- setbits32((vaddr + GPIO0_OSRH), 0x4200);
- setbits32((vaddr + GPIO0_TSRH), 0x4200);
+ setbits32_be((vaddr + GPIO0_OSRH), 0x4200);
+ setbits32_be((vaddr + GPIO0_TSRH), 0x4200);
err_gpio:
iounmap(vaddr);
err_bcsr:
diff --gi
[PATCH 4/5] net: ethernet: stmmac: use xxxsetbits32
This patch convert stmmac driver to use all xxxsetbits32 functions.
Signed-off-by: Corentin Labbe
---
.../net/ethernet/stmicro/stmmac/dwmac-meson8b.c| 54 +++--
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 55 -
.../net/ethernet/stmicro/stmmac/dwmac1000_core.c | 21 +++
drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c | 51 ++--
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c | 13 ++--
drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c | 42 +++--
drivers/net/ethernet/stmicro/stmmac/dwmac5.c | 11 +---
drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c| 17 ++
.../net/ethernet/stmicro/stmmac/dwxgmac2_core.c| 30 --
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c | 69 +-
.../net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c | 11 +---
drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c | 7 +--
12 files changed, 108 insertions(+), 273 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
index c5979569fd60..035a2ab7b479 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
@@ -22,6 +22,7 @@
#include
#include
#include
+#include
#include
#include "stmmac_platform.h"
@@ -75,18 +76,6 @@ struct meson8b_dwmac_clk_configs {
struct clk_gate rgmii_tx_en;
};
-static void meson8b_dwmac_mask_bits(struct meson8b_dwmac *dwmac, u32 reg,
- u32 mask, u32 value)
-{
- u32 data;
-
- data = readl(dwmac->regs + reg);
- data &= ~mask;
- data |= (value & mask);
-
- writel(data, dwmac->regs + reg);
-}
-
static struct clk *meson8b_dwmac_register_clk(struct meson8b_dwmac *dwmac,
const char *name_suffix,
const char **parent_names,
@@ -192,14 +181,12 @@ static int meson8b_set_phy_mode(struct meson8b_dwmac
*dwmac)
case PHY_INTERFACE_MODE_RGMII_ID:
case PHY_INTERFACE_MODE_RGMII_TXID:
/* enable RGMII mode */
- meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
- PRG_ETH0_RGMII_MODE,
- PRG_ETH0_RGMII_MODE);
+ clrsetbits32(dwmac->regs + PRG_ETH0, PRG_ETH0_RGMII_MODE,
+PRG_ETH0_RGMII_MODE);
break;
case PHY_INTERFACE_MODE_RMII:
/* disable RGMII mode -> enables RMII mode */
- meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
- PRG_ETH0_RGMII_MODE, 0);
+ clrsetbits32(dwmac->regs + PRG_ETH0, PRG_ETH0_RGMII_MODE, 0);
break;
default:
dev_err(dwmac->dev, "fail to set phy-mode %s\n",
@@ -218,15 +205,15 @@ static int meson_axg_set_phy_mode(struct meson8b_dwmac
*dwmac)
case PHY_INTERFACE_MODE_RGMII_ID:
case PHY_INTERFACE_MODE_RGMII_TXID:
/* enable RGMII mode */
- meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
- PRG_ETH0_EXT_PHY_MODE_MASK,
- PRG_ETH0_EXT_RGMII_MODE);
+ clrsetbits32(dwmac->regs + PRG_ETH0,
+PRG_ETH0_EXT_PHY_MODE_MASK,
+PRG_ETH0_EXT_RGMII_MODE);
break;
case PHY_INTERFACE_MODE_RMII:
/* disable RGMII mode -> enables RMII mode */
- meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
- PRG_ETH0_EXT_PHY_MODE_MASK,
- PRG_ETH0_EXT_RMII_MODE);
+ clrsetbits32(dwmac->regs + PRG_ETH0,
+PRG_ETH0_EXT_PHY_MODE_MASK,
+PRG_ETH0_EXT_RMII_MODE);
break;
default:
dev_err(dwmac->dev, "fail to set phy-mode %s\n",
@@ -255,11 +242,11 @@ static int meson8b_init_prg_eth(struct meson8b_dwmac
*dwmac)
case PHY_INTERFACE_MODE_RGMII_ID:
case PHY_INTERFACE_MODE_RGMII_TXID:
/* only relevant for RMII mode -> disable in RGMII mode */
- meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
- PRG_ETH0_INVERTED_RMII_CLK, 0);
+ clrsetbits32(dwmac->regs + PRG_ETH0,
+PRG_ETH0_INVERTED_RMII_CLK, 0);
- meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_TXDLY_MASK,
- tx_dly_val << PRG_ETH0_TXDLY_SHIFT);
+ clrsetbits32(dwmac->regs + PRG_ETH0, PRG_ETH0_TXDLY_MASK,
+tx_dly_val << PRG_ETH0_TXDLY_SHIFT);
/* Configure the 125MHz RGMII
[PATCH 5/5] ata: ahci_sunxi: use xxxsetbits32 functions
This patch converts ahci_sunxi to use xxxsetbits32 functions
Signed-off-by: Corentin Labbe
---
drivers/ata/ahci_sunxi.c | 51
1 file changed, 12 insertions(+), 39 deletions(-)
diff --git a/drivers/ata/ahci_sunxi.c b/drivers/ata/ahci_sunxi.c
index 911710643305..0799441f1237 100644
--- a/drivers/ata/ahci_sunxi.c
+++ b/drivers/ata/ahci_sunxi.c
@@ -25,6 +25,7 @@
#include
#include
#include
+#include
#include "ahci.h"
#define DRV_NAME "ahci-sunxi"
@@ -58,34 +59,6 @@ MODULE_PARM_DESC(enable_pmp,
#define AHCI_P0PHYCR 0x0178
#define AHCI_P0PHYSR 0x017c
-static void sunxi_clrbits(void __iomem *reg, u32 clr_val)
-{
- u32 reg_val;
-
- reg_val = readl(reg);
- reg_val &= ~(clr_val);
- writel(reg_val, reg);
-}
-
-static void sunxi_setbits(void __iomem *reg, u32 set_val)
-{
- u32 reg_val;
-
- reg_val = readl(reg);
- reg_val |= set_val;
- writel(reg_val, reg);
-}
-
-static void sunxi_clrsetbits(void __iomem *reg, u32 clr_val, u32 set_val)
-{
- u32 reg_val;
-
- reg_val = readl(reg);
- reg_val &= ~(clr_val);
- reg_val |= set_val;
- writel(reg_val, reg);
-}
-
static u32 sunxi_getbits(void __iomem *reg, u8 mask, u8 shift)
{
return (readl(reg) >> shift) & mask;
@@ -100,22 +73,22 @@ static int ahci_sunxi_phy_init(struct device *dev, void
__iomem *reg_base)
writel(0, reg_base + AHCI_RWCR);
msleep(5);
- sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(19));
- sunxi_clrsetbits(reg_base + AHCI_PHYCS0R,
+ setbits32(reg_base + AHCI_PHYCS1R, BIT(19));
+ clrsetbits32(reg_base + AHCI_PHYCS0R,
(0x7 << 24),
(0x5 << 24) | BIT(23) | BIT(18));
- sunxi_clrsetbits(reg_base + AHCI_PHYCS1R,
+ clrsetbits32(reg_base + AHCI_PHYCS1R,
(0x3 << 16) | (0x1f << 8) | (0x3 << 6),
(0x2 << 16) | (0x6 << 8) | (0x2 << 6));
- sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(28) | BIT(15));
- sunxi_clrbits(reg_base + AHCI_PHYCS1R, BIT(19));
- sunxi_clrsetbits(reg_base + AHCI_PHYCS0R,
+ setbits32(reg_base + AHCI_PHYCS1R, BIT(28) | BIT(15));
+ clrbits32(reg_base + AHCI_PHYCS1R, BIT(19));
+ clrsetbits32(reg_base + AHCI_PHYCS0R,
(0x7 << 20), (0x3 << 20));
- sunxi_clrsetbits(reg_base + AHCI_PHYCS2R,
+ clrsetbits32(reg_base + AHCI_PHYCS2R,
(0x1f << 5), (0x19 << 5));
msleep(5);
- sunxi_setbits(reg_base + AHCI_PHYCS0R, (0x1 << 19));
+ setbits32(reg_base + AHCI_PHYCS0R, (0x1 << 19));
timeout = 250; /* Power up takes aprox 50 us */
do {
@@ -130,7 +103,7 @@ static int ahci_sunxi_phy_init(struct device *dev, void
__iomem *reg_base)
udelay(1);
} while (1);
- sunxi_setbits(reg_base + AHCI_PHYCS2R, (0x1 << 24));
+ setbits32(reg_base + AHCI_PHYCS2R, (0x1 << 24));
timeout = 100; /* Calibration takes aprox 10 us */
do {
@@ -158,10 +131,10 @@ static void ahci_sunxi_start_engine(struct ata_port *ap)
struct ahci_host_priv *hpriv = ap->host->private_data;
/* Setup DMA before DMA start */
- sunxi_clrsetbits(hpriv->mmio + AHCI_P0DMACR, 0xff00, 0x4400);
+ clrsetbits32(hpriv->mmio + AHCI_P0DMACR, 0xff00, 0x4400);
/* Start DMA */
- sunxi_setbits(port_mmio + PORT_CMD, PORT_CMD_START);
+ setbits32(port_mmio + PORT_CMD, PORT_CMD_START);
}
static const struct ata_port_info ahci_sunxi_port_info = {
--
2.16.4
[PATCH 2/5] include: add setbits32/clrbits32/clrsetbits32/setbits64/clrbits64/clrsetbits64 in linux/setbits.h
This patch adds setbits32/clrbits32/clrsetbits32 and setbits64/clrbits64/clrsetbits64 in linux/setbits.h header. Signed-off-by: Corentin Labbe --- include/linux/setbits.h | 55 + 1 file changed, 55 insertions(+) create mode 100644 include/linux/setbits.h diff --git a/include/linux/setbits.h b/include/linux/setbits.h new file mode 100644 index ..3e1e273551bb --- /dev/null +++ b/include/linux/setbits.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __LINUX_SETBITS_H +#define __LINUX_SETBITS_H + +#include + +#define __setbits(readfunction, writefunction, addr, set) \ + writefunction((readfunction(addr) | (set)), addr) +#define __clrbits(readfunction, writefunction, addr, mask) \ + writefunction((readfunction(addr) & ~(mask)), addr) +#define __clrsetbits(readfunction, writefunction, addr, mask, set) \ + writefunction(((readfunction(addr) & ~(mask)) | (set)), addr) +#define __setclrbits(readfunction, writefunction, addr, mask, set) \ + writefunction(((readfunction(addr) | (seti)) & ~(mask)), addr) + +#define setbits32(addr, set) __setbits(readl, writel, addr, set) +#define setbits32_relaxed(addr, set) __setbits(readl_relaxed, writel_relaxed, \ + addr, set) + +#define clrbits32(addr, mask) __clrbits(readl, writel, addr, mask) +#define clrbits32_relaxed(addr, mask) __clrbits(readl_relaxed, writel_relaxed, \ + addr, mask) + +#define clrsetbits32(addr, mask, set) __clrsetbits(readl, writel, addr, mask, set) +#define clrsetbits32_relaxed(addr, mask, set) __clrsetbits(readl_relaxed, \ + writel_relaxed, \ + addr, mask, set) + +#define setclrbits32(addr, mask, set) __setclrbits(readl, writel, addr, mask, set) +#define setclrbits32_relaxed(addr, mask, set) __setclrbits(readl_relaxed, \ + writel_relaxed, \ + addr, mask, set) + +/* We cannot use CONFIG_64BIT as some x86 drivers use writeq */ +#if defined(writeq) && defined(readq) +#define setbits64(addr, set) __setbits(readq, writeq, addr, set) +#define setbits64_relaxed(addr, set) __setbits(readq_relaxed, writeq_relaxed, \ + addr, set) + +#define clrbits64(addr, mask) __clrbits(readq, writeq, addr, mask) +#define clrbits64_relaxed(addr, mask) __clrbits(readq_relaxed, writeq_relaxed, \ + addr, mask) + +#define clrsetbits64(addr, mask, set) __clrsetbits(readq, writeq, addr, mask, set) +#define clrsetbits64_relaxed(addr, mask, set) __clrsetbits(readq_relaxed, \ + writeq_relaxed, \ + addr, mask, set) + +#define setclrbits64(addr, mask, set) __setclrbits(readq, writeq, addr, mask, set) +#define setclrbits64_relaxed(addr, mask, set) __setclrbits(readq_relaxed, \ + writeq_relaxed, \ + addr, mask, set) +#endif /* writeq/readq */ + +#endif /* __LINUX_SETBITS_H */ -- 2.16.4
[PATCH 0/5] introduce setbits32/clrbits32/clrsetbits32/setbits64/clrbits64/clrsetbits64 functions
Hello This patchset adds a new set of functions which are open-coded in lot of place. Basicly the pattern is always the same, "read, modify a bit, write" some driver already have thoses pattern them as functions. (like ahci_sunxi.c or dwmac-meson8b) The first patch rename some powerpc funtions which already use the same name (xxxbits32) but with only bigendian values. The second patch adds the header. The third patch is an ugly try to implement a coccinelle semantic patch to find all place where xxxbits function could be used. Probably this spatch could be better written and I didnt found an easy way to add the "linux/setbits" header. The two last patch are example of convertion of two drivers. Thoses patchs give an example of the reduction of code won by using xxxbits32. This patchset is tested with the ahci_sunxi and dwmac-sun8i drivers. Regards Corentin Labbe (5): powerpc: rename setbits32/clrbits32 to setbits32_be/clrbits32_be include: add setbits32/clrbits32/clrsetbits32/setbits64/clrbits64/clrsetbits64 in linux/setbits.h coccinelle: add xxxsetbitsXX converting spatch net: ethernet: stmmac: use xxxsetbits32 ata: ahci_sunxi: use xxxsetbits32 functions arch/powerpc/include/asm/fsl_lbc.h | 2 +- arch/powerpc/include/asm/io.h | 5 +- arch/powerpc/platforms/44x/canyonlands.c | 4 +- arch/powerpc/platforms/4xx/gpio.c | 28 +- arch/powerpc/platforms/512x/pdm360ng.c | 6 +- arch/powerpc/platforms/52xx/mpc52xx_common.c | 6 +- arch/powerpc/platforms/52xx/mpc52xx_gpt.c | 10 +- arch/powerpc/platforms/82xx/ep8248e.c | 2 +- arch/powerpc/platforms/82xx/km82xx.c | 6 +- arch/powerpc/platforms/82xx/mpc8272_ads.c | 10 +- arch/powerpc/platforms/82xx/pq2.c | 2 +- arch/powerpc/platforms/82xx/pq2ads-pci-pic.c | 4 +- arch/powerpc/platforms/82xx/pq2fads.c | 10 +- arch/powerpc/platforms/83xx/km83xx.c | 6 +- arch/powerpc/platforms/83xx/mpc836x_mds.c | 2 +- arch/powerpc/platforms/85xx/mpc85xx_mds.c | 2 +- arch/powerpc/platforms/85xx/mpc85xx_pm_ops.c | 4 +- arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 2 +- arch/powerpc/platforms/85xx/p1022_ds.c | 4 +- arch/powerpc/platforms/85xx/p1022_rdk.c| 4 +- arch/powerpc/platforms/85xx/t1042rdb_diu.c | 4 +- arch/powerpc/platforms/85xx/twr_p102x.c| 2 +- arch/powerpc/platforms/86xx/mpc8610_hpcd.c | 4 +- arch/powerpc/platforms/8xx/adder875.c | 2 +- arch/powerpc/platforms/8xx/m8xx_setup.c| 4 +- arch/powerpc/platforms/8xx/mpc86xads_setup.c | 4 +- arch/powerpc/platforms/8xx/mpc885ads_setup.c | 28 +- arch/powerpc/platforms/embedded6xx/flipper-pic.c | 6 +- arch/powerpc/platforms/embedded6xx/hlwd-pic.c | 8 +- arch/powerpc/platforms/embedded6xx/wii.c | 10 +- arch/powerpc/sysdev/cpm1.c | 26 +- arch/powerpc/sysdev/cpm2.c | 16 +- arch/powerpc/sysdev/cpm_common.c | 4 +- arch/powerpc/sysdev/fsl_85xx_l2ctlr.c | 8 +- arch/powerpc/sysdev/fsl_lbc.c | 2 +- arch/powerpc/sysdev/fsl_pci.c | 8 +- arch/powerpc/sysdev/fsl_pmc.c | 2 +- arch/powerpc/sysdev/fsl_rcpm.c | 74 ++-- arch/powerpc/sysdev/fsl_rio.c | 4 +- arch/powerpc/sysdev/fsl_rmu.c | 8 +- arch/powerpc/sysdev/mpic_timer.c | 12 +- drivers/ata/ahci_sunxi.c | 51 +-- .../net/ethernet/stmicro/stmmac/dwmac-meson8b.c| 54 +-- drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 55 +-- .../net/ethernet/stmicro/stmmac/dwmac1000_core.c | 21 +- drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c | 51 +-- drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c | 13 +- drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c | 42 +- drivers/net/ethernet/stmicro/stmmac/dwmac5.c | 11 +- drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c| 17 +- .../net/ethernet/stmicro/stmmac/dwxgmac2_core.c| 30 +- drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c | 69 +--- .../net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c | 11 +- drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c | 7 +- include/linux/setbits.h| 55 +++ scripts/coccinelle/misc/setbits.cocci | 423 + 56 files changed, 776 insertions(+), 489 deletions(-) create mode 100644 include/linux/setbits.h create mode 100644 scripts/coccinelle/misc/setbits.cocci -- 2.16.4
[PATCH RFC 3/5] coccinelle: add xxxsetbitsXX converting spatch
This patch add a spatch which convert all open coded of setbits32/clrbits32/clrsetbits32 and their 64 bits counterparts. Signed-off-by: Corentin Labbe --- scripts/coccinelle/misc/setbits.cocci | 423 ++ 1 file changed, 423 insertions(+) create mode 100644 scripts/coccinelle/misc/setbits.cocci diff --git a/scripts/coccinelle/misc/setbits.cocci b/scripts/coccinelle/misc/setbits.cocci new file mode 100644 index ..c01ab6d75eb4 --- /dev/null +++ b/scripts/coccinelle/misc/setbits.cocci @@ -0,0 +1,423 @@ +virtual context + +@pclrsetbits32a@ +identifier rr; +expression reg; +expression set; +expression clear; +@@ + + u32 rr; + ... +- rr = readl(reg); +- rr &= ~clear; +- rr |= set; +- writel(rr, reg); ++ clrsetbits32(reg, clear, set); + +@pclrsetbits32b@ +identifier rr; +expression reg; +expression set; +expression clear; +@@ + + u32 rr; + ... +- rr = readl(reg); +- rr |= set; +- rr &= ~clear; +- writel(rr, reg); ++ clrsetbits32(reg, clear, set); + +@pclrbits32@ +identifier rr; +expression reg; +expression clear; +@@ + + u32 rr; + ... +- rr = readl(reg); +- rr &= ~clear; +- writel(rr, reg); ++ clrbits32(reg, clear); + +@psetbits32@ +identifier rr; +expression reg; +expression set; +@@ + + u32 rr; + ... +- rr = readl(reg); +- rr |= set; +- writel(rr, reg); ++ setbits32(reg, set); + +@psetbits32b@ +identifier rr; +expression reg; +expression set1; +expression set2; +@@ + + u32 rr; + ... +- rr = readl(reg); +- rr |= set1; +- rr |= set2; +- writel(rr, reg); ++ setbits32(reg, set1 | set2); + +@pclrsetbits64a@ +identifier rr; +expression reg; +expression set; +expression clear; +@@ + + u64 rr; + ... +- rr = readq(reg); +- rr &= ~clear; +- rr |= set; +- writeq(rr, reg); ++ clrsetbits64(reg, clear, set); + +@pclrsetbits64b@ +identifier rr; +expression reg; +expression set; +expression clear; +@@ + + u64 rr; + ... +- rr = readq(reg); +- rr |= set; +- rr &= ~clear; +- writeq(rr, reg); ++ clrsetbits64(reg, clear, set); + +@pclrbits64@ +identifier rr; +expression reg; +expression clear; +@@ + + u64 rr; + ... +- rr = readq(reg); +- rr &= ~clear; +- writeq(rr, reg); ++ clrbits64(reg, clear); + +@psetbits64@ +identifier rr; +expression reg; +expression set; +@@ + + u64 rr; + ... +- rr = readq(reg); +- rr |= set; +- writeq(rr, reg); ++ setbits64(reg, set); + +@@ +expression dwmac; +expression reg; +expression mask; +expression value; +@@ + +- meson8b_dwmac_mask_bits(dwmac, reg, mask, value); ++ clrsetbits32(dwmac->regs + reg, mask, value); + +@ppclrsetbits32a@ +identifier rr; +expression reg; +expression set; +expression clear; +@@ + +- u32 rr = readl(reg); +- rr &= ~clear; +- rr |= set; +- writel(rr, reg); ++ clrsetbits32(reg, clear, set); + +@ppclrsetbits32b@ +identifier rr; +expression reg; +expression set; +expression clear; +@@ + +- u32 rr = readl(reg); +- rr |= set; +- rr &= ~clear; +- writel(rr, reg); ++ clrsetbits32(reg, clear, set); + +@ppclrbits32@ +identifier rr; +expression reg; +expression clear; +@@ + +- u32 rr = readl(reg); +- rr &= ~clear; +- writel(rr, reg); ++ clrbits32(reg, clear); + +@ppsetbits32@ +identifier rr; +expression reg; +expression set; +@@ + +- u32 rr = readl(reg); +- rr |= set; +- writel(rr, reg); ++ setbits32(reg, set); + +@ppclrsetbits64a@ +identifier rr; +expression reg; +expression set; +expression clear; +@@ + +- u64 rr = readq(reg); +- rr &= ~clear; +- rr |= set; +- writeq(rr, reg); ++ clrsetbits64(reg, clear, set); + +@ppclrsetbits64b@ +identifier rr; +expression reg; +expression set; +expression clear; +@@ + +- u64 rr = readq(reg); +- rr |= set; +- rr &= ~clear; +- writeq(rr, reg); ++ clrsetbits64(reg, clear, set); + +@ppclrbits64@ +identifier rr; +expression reg; +expression clear; +@@ + +- u64 rr = readq(reg); +- rr &= ~clear; +- writeq(rr, reg); ++ clrbits64(reg, clear); + +@ppsetbits64@ +identifier rr; +expression reg; +expression set; +@@ + +- u64 rr = readq(reg); +- rr |= set; +- writeq(rr, reg); ++ setbits64(reg, set); + +@pif_set_clr@ +identifier rr; +expression reg; +expression set; +expression clear; +@@ + + u32 rr; + ... +- rr = readl(reg); + if (...) +- rr |= set; ++ setbits32(reg, set); + else +- rr &= ~clear; ++ clrbits32(reg, clear); +- writel(rr, reg); + +@pifclrset@ +identifier rr; +expression reg; +expression set; +expression clear; +@@ + + u32 rr; + ... +- rr = readl(reg); + if (...) +- rr &= ~clear; ++ clrbits32(reg, clear); + else +- rr |= set; ++ setbits32(reg, set); +- writel(rr, reg); + +@pif_set_clr64@ +identifier rr; +expression reg; +expression set; +expression clear; +@@ + + u64 rr; + ... +- rr = readq(reg); + if (...) +- rr |= set; ++ setbits64(reg, set); + else +- rr &= ~clear; ++ clrbits64(reg, clear); +- writeq(rr, reg); + +@pif_clr_set64@ +identifier rr; +expression reg; +expression set; +expression clear; +@@ + + u64 rr; + ... +- rr = readq(reg); + if (...) +- rr &= ~clear; ++ clrbits64(reg, clea
Re: [PATCH] crypto: reorder paes test lexicographically
On Fri, May 11, 2018 at 09:04:06AM +0100, Gilad Ben-Yossef wrote:
> Due to a snafu "paes" testmgr tests were not ordered
> lexicographically, which led to boot time warnings.
> Reorder the tests as needed.
>
> Fixes: a794d8d ("crypto: ccree - enable support for hardware keys")
> Reported-by: Abdul Haleem
> Signed-off-by: Gilad Ben-Yossef
Tested-by: Corentin Labbe
Thanks
[PATCH] powerpc: add empty update_numa_cpu_lookup_table for !CONFIG_NUMA
When CONFIG_NUMA is not set, build fail with:
arch/powerpc/platforms/pseries/hotplug-cpu.c:335:4: error: déclaration
implicite de la fonction « update_numa_cpu_lookup_table »
[-Werror=implicit-function-declaration]
So we have to add update_numa_cpu_lookup_table as an empty function when
CONFIG_NUMA is not set.
Fixes: 1d9a090783be ("powerpc/numa: Invalidate numa_cpu_lookup_table on cpu
remove")
Signed-off-by: Corentin Labbe
---
arch/powerpc/include/asm/topology.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/powerpc/include/asm/topology.h
b/arch/powerpc/include/asm/topology.h
index 593248110902..9f421641a35c 100644
--- a/arch/powerpc/include/asm/topology.h
+++ b/arch/powerpc/include/asm/topology.h
@@ -81,6 +81,9 @@ static inline int numa_update_cpu_topology(bool cpus_locked)
{
return 0;
}
+
+static inline void update_numa_cpu_lookup_table(unsigned int cpu, int node) {}
+
#endif /* CONFIG_NUMA */
#if defined(CONFIG_NUMA) && defined(CONFIG_PPC_SPLPAR)
--
2.13.6
[PATCH 11/11] crypto: aesni - Use GCM IV size constant
This patch replace GCM IV size value by their constant name.
Signed-off-by: Corentin Labbe
---
arch/x86/crypto/aesni-intel_glue.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/arch/x86/crypto/aesni-intel_glue.c
b/arch/x86/crypto/aesni-intel_glue.c
index 5c15d6b57329..80664368bf14 100644
--- a/arch/x86/crypto/aesni-intel_glue.c
+++ b/arch/x86/crypto/aesni-intel_glue.c
@@ -28,6 +28,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -1131,7 +1132,7 @@ static struct aead_alg aesni_aead_algs[] = { {
.setauthsize= common_rfc4106_set_authsize,
.encrypt= helper_rfc4106_encrypt,
.decrypt= helper_rfc4106_decrypt,
- .ivsize = 8,
+ .ivsize = GCM_RFC4106_IV_SIZE,
.maxauthsize= 16,
.base = {
.cra_name = "__gcm-aes-aesni",
@@ -1149,7 +1150,7 @@ static struct aead_alg aesni_aead_algs[] = { {
.setauthsize= rfc4106_set_authsize,
.encrypt= rfc4106_encrypt,
.decrypt= rfc4106_decrypt,
- .ivsize = 8,
+ .ivsize = GCM_RFC4106_IV_SIZE,
.maxauthsize= 16,
.base = {
.cra_name = "rfc4106(gcm(aes))",
@@ -1165,7 +1166,7 @@ static struct aead_alg aesni_aead_algs[] = { {
.setauthsize= generic_gcmaes_set_authsize,
.encrypt= generic_gcmaes_encrypt,
.decrypt= generic_gcmaes_decrypt,
- .ivsize = 12,
+ .ivsize = GCM_AES_IV_SIZE,
.maxauthsize= 16,
.base = {
.cra_name = "gcm(aes)",
--
2.13.0
[PATCH 10/11] crypto: gcm - Use GCM IV size constant
This patch replace GCM IV size value by their constant name.
Signed-off-by: Corentin Labbe
---
crypto/gcm.c | 23 ---
1 file changed, 12 insertions(+), 11 deletions(-)
diff --git a/crypto/gcm.c b/crypto/gcm.c
index 3841b5eafa7e..80cf6cfe082b 100644
--- a/crypto/gcm.c
+++ b/crypto/gcm.c
@@ -14,6 +14,7 @@
#include
#include
#include
+#include
#include
#include "internal.h"
#include
@@ -197,8 +198,8 @@ static void crypto_gcm_init_common(struct aead_request *req)
struct scatterlist *sg;
memset(pctx->auth_tag, 0, sizeof(pctx->auth_tag));
- memcpy(pctx->iv, req->iv, 12);
- memcpy(pctx->iv + 12, &counter, 4);
+ memcpy(pctx->iv, req->iv, GCM_AES_IV_SIZE);
+ memcpy(pctx->iv + GCM_AES_IV_SIZE, &counter, 4);
sg_init_table(pctx->src, 3);
sg_set_buf(pctx->src, pctx->auth_tag, sizeof(pctx->auth_tag));
@@ -695,7 +696,7 @@ static int crypto_gcm_create_common(struct crypto_template
*tmpl,
inst->alg.base.cra_alignmask = ghash->base.cra_alignmask |
ctr->base.cra_alignmask;
inst->alg.base.cra_ctxsize = sizeof(struct crypto_gcm_ctx);
- inst->alg.ivsize = 12;
+ inst->alg.ivsize = GCM_AES_IV_SIZE;
inst->alg.chunksize = crypto_skcipher_alg_chunksize(ctr);
inst->alg.maxauthsize = 16;
inst->alg.init = crypto_gcm_init_tfm;
@@ -832,20 +833,20 @@ static struct aead_request *crypto_rfc4106_crypt(struct
aead_request *req)
u8 *iv = PTR_ALIGN((u8 *)(subreq + 1) + crypto_aead_reqsize(child),
crypto_aead_alignmask(child) + 1);
- scatterwalk_map_and_copy(iv + 12, req->src, 0, req->assoclen - 8, 0);
+ scatterwalk_map_and_copy(iv + GCM_AES_IV_SIZE, req->src, 0,
req->assoclen - 8, 0);
memcpy(iv, ctx->nonce, 4);
memcpy(iv + 4, req->iv, 8);
sg_init_table(rctx->src, 3);
- sg_set_buf(rctx->src, iv + 12, req->assoclen - 8);
+ sg_set_buf(rctx->src, iv + GCM_AES_IV_SIZE, req->assoclen - 8);
sg = scatterwalk_ffwd(rctx->src + 1, req->src, req->assoclen);
if (sg != rctx->src + 1)
sg_chain(rctx->src, 2, sg);
if (req->src != req->dst) {
sg_init_table(rctx->dst, 3);
- sg_set_buf(rctx->dst, iv + 12, req->assoclen - 8);
+ sg_set_buf(rctx->dst, iv + GCM_AES_IV_SIZE, req->assoclen - 8);
sg = scatterwalk_ffwd(rctx->dst + 1, req->dst, req->assoclen);
if (sg != rctx->dst + 1)
sg_chain(rctx->dst, 2, sg);
@@ -957,7 +958,7 @@ static int crypto_rfc4106_create(struct crypto_template
*tmpl,
err = -EINVAL;
/* Underlying IV size must be 12. */
- if (crypto_aead_alg_ivsize(alg) != 12)
+ if (crypto_aead_alg_ivsize(alg) != GCM_AES_IV_SIZE)
goto out_drop_alg;
/* Not a stream cipher? */
@@ -980,7 +981,7 @@ static int crypto_rfc4106_create(struct crypto_template
*tmpl,
inst->alg.base.cra_ctxsize = sizeof(struct crypto_rfc4106_ctx);
- inst->alg.ivsize = 8;
+ inst->alg.ivsize = GCM_RFC4106_IV_SIZE;
inst->alg.chunksize = crypto_aead_alg_chunksize(alg);
inst->alg.maxauthsize = crypto_aead_alg_maxauthsize(alg);
@@ -1134,7 +1135,7 @@ static int crypto_rfc4543_init_tfm(struct crypto_aead
*tfm)
tfm,
sizeof(struct crypto_rfc4543_req_ctx) +
ALIGN(crypto_aead_reqsize(aead), crypto_tfm_ctx_alignment()) +
- align + 12);
+ align + GCM_AES_IV_SIZE);
return 0;
@@ -1199,7 +1200,7 @@ static int crypto_rfc4543_create(struct crypto_template
*tmpl,
err = -EINVAL;
/* Underlying IV size must be 12. */
- if (crypto_aead_alg_ivsize(alg) != 12)
+ if (crypto_aead_alg_ivsize(alg) != GCM_AES_IV_SIZE)
goto out_drop_alg;
/* Not a stream cipher? */
@@ -1222,7 +1223,7 @@ static int crypto_rfc4543_create(struct crypto_template
*tmpl,
inst->alg.base.cra_ctxsize = sizeof(struct crypto_rfc4543_ctx);
- inst->alg.ivsize = 8;
+ inst->alg.ivsize = GCM_RFC4543_IV_SIZE;
inst->alg.chunksize = crypto_aead_alg_chunksize(alg);
inst->alg.maxauthsize = crypto_aead_alg_maxauthsize(alg);
--
2.13.0
[PATCH 09/11] crypto: omap - Use GCM IV size constant
This patch replace GCM IV size value by their constant name.
Signed-off-by: Corentin Labbe
---
drivers/crypto/omap-aes-gcm.c | 7 ---
drivers/crypto/omap-aes.c | 5 +++--
2 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/crypto/omap-aes-gcm.c b/drivers/crypto/omap-aes-gcm.c
index 7d4f8a4be6d8..9b8f1c752168 100644
--- a/drivers/crypto/omap-aes-gcm.c
+++ b/drivers/crypto/omap-aes-gcm.c
@@ -18,6 +18,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -311,7 +312,7 @@ static int omap_aes_gcm_crypt(struct aead_request *req,
unsigned long mode)
int err, assoclen;
memset(rctx->auth_tag, 0, sizeof(rctx->auth_tag));
- memcpy(rctx->iv + 12, &counter, 4);
+ memcpy(rctx->iv + GCM_AES_IV_SIZE, &counter, 4);
err = do_encrypt_iv(req, (u32 *)rctx->auth_tag, (u32 *)rctx->iv);
if (err)
@@ -339,7 +340,7 @@ int omap_aes_gcm_encrypt(struct aead_request *req)
{
struct omap_aes_reqctx *rctx = aead_request_ctx(req);
- memcpy(rctx->iv, req->iv, 12);
+ memcpy(rctx->iv, req->iv, GCM_AES_IV_SIZE);
return omap_aes_gcm_crypt(req, FLAGS_ENCRYPT | FLAGS_GCM);
}
@@ -347,7 +348,7 @@ int omap_aes_gcm_decrypt(struct aead_request *req)
{
struct omap_aes_reqctx *rctx = aead_request_ctx(req);
- memcpy(rctx->iv, req->iv, 12);
+ memcpy(rctx->iv, req->iv, GCM_AES_IV_SIZE);
return omap_aes_gcm_crypt(req, FLAGS_GCM);
}
diff --git a/drivers/crypto/omap-aes.c b/drivers/crypto/omap-aes.c
index c376a3ee7c2c..1f3686a1ebfa 100644
--- a/drivers/crypto/omap-aes.c
+++ b/drivers/crypto/omap-aes.c
@@ -35,6 +35,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -767,7 +768,7 @@ static struct aead_alg algs_aead_gcm[] = {
},
.init = omap_aes_gcm_cra_init,
.exit = omap_aes_gcm_cra_exit,
- .ivsize = 12,
+ .ivsize = GCM_AES_IV_SIZE,
.maxauthsize= AES_BLOCK_SIZE,
.setkey = omap_aes_gcm_setkey,
.encrypt= omap_aes_gcm_encrypt,
@@ -788,7 +789,7 @@ static struct aead_alg algs_aead_gcm[] = {
.init = omap_aes_gcm_cra_init,
.exit = omap_aes_gcm_cra_exit,
.maxauthsize= AES_BLOCK_SIZE,
- .ivsize = 8,
+ .ivsize = GCM_RFC4106_IV_SIZE,
.setkey = omap_aes_4106gcm_setkey,
.encrypt= omap_aes_4106gcm_encrypt,
.decrypt= omap_aes_4106gcm_decrypt,
--
2.13.0
[PATCH 08/11] crypto: chelsio - Use GCM IV size constant
This patch replace GCM IV size value by their constant name.
Signed-off-by: Corentin Labbe
---
drivers/crypto/chelsio/chcr_algo.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/crypto/chelsio/chcr_algo.c
b/drivers/crypto/chelsio/chcr_algo.c
index 0e8160701833..936bdd895efa 100644
--- a/drivers/crypto/chelsio/chcr_algo.c
+++ b/drivers/crypto/chelsio/chcr_algo.c
@@ -53,6 +53,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -2534,9 +2535,9 @@ static struct sk_buff *create_gcm_wr(struct aead_request
*req,
if (get_aead_subtype(tfm) ==
CRYPTO_ALG_SUB_TYPE_AEAD_RFC4106) {
memcpy(reqctx->iv, aeadctx->salt, 4);
- memcpy(reqctx->iv + 4, req->iv, 8);
+ memcpy(reqctx->iv + 4, req->iv, GCM_RFC4106_IV_SIZE);
} else {
- memcpy(reqctx->iv, req->iv, 12);
+ memcpy(reqctx->iv, req->iv, GCM_AES_IV_SIZE);
}
*((unsigned int *)(reqctx->iv + 12)) = htonl(0x01);
@@ -3385,7 +3386,7 @@ static struct chcr_alg_template driver_algs[] = {
sizeof(struct chcr_aead_ctx) +
sizeof(struct chcr_gcm_ctx),
},
- .ivsize = 12,
+ .ivsize = GCM_AES_IV_SIZE,
.maxauthsize = GHASH_DIGEST_SIZE,
.setkey = chcr_gcm_setkey,
.setauthsize = chcr_gcm_setauthsize,
@@ -3405,7 +3406,7 @@ static struct chcr_alg_template driver_algs[] = {
sizeof(struct chcr_gcm_ctx),
},
- .ivsize = 8,
+ .ivsize = GCM_RFC4106_IV_SIZE,
.maxauthsize= GHASH_DIGEST_SIZE,
.setkey = chcr_gcm_setkey,
.setauthsize= chcr_4106_4309_setauthsize,
--
2.13.0
[PATCH 07/11] crypto: mediatek - Use GCM IV size constant
This patch replace GCM IV size value by their constant name.
Signed-off-by: Corentin Labbe
---
drivers/crypto/mediatek/mtk-aes.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/crypto/mediatek/mtk-aes.c
b/drivers/crypto/mediatek/mtk-aes.c
index 9e845e866dec..87e15b624f84 100644
--- a/drivers/crypto/mediatek/mtk-aes.c
+++ b/drivers/crypto/mediatek/mtk-aes.c
@@ -13,6 +13,7 @@
*/
#include
+#include
#include "mtk-platform.h"
#define AES_QUEUE_SIZE 512
@@ -1098,7 +1099,7 @@ static struct aead_alg aes_gcm_alg = {
.decrypt= mtk_aes_gcm_decrypt,
.init = mtk_aes_gcm_init,
.exit = mtk_aes_gcm_exit,
- .ivsize = 12,
+ .ivsize = GCM_AES_IV_SIZE,
.maxauthsize= AES_BLOCK_SIZE,
.base = {
--
2.13.0
[PATCH 06/11] crypto: bcm - Use GCM IV size constant
This patch replace GCM IV size value by their constant name.
Signed-off-by: Corentin Labbe
---
drivers/crypto/bcm/cipher.c | 8
drivers/crypto/bcm/cipher.h | 3 +--
2 files changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/crypto/bcm/cipher.c b/drivers/crypto/bcm/cipher.c
index 8685c7e4debd..537a67483aa3 100644
--- a/drivers/crypto/bcm/cipher.c
+++ b/drivers/crypto/bcm/cipher.c
@@ -1367,11 +1367,11 @@ static int handle_aead_req(struct iproc_reqctx_s *rctx)
* expects AAD to include just SPI and seqno. So
* subtract off the IV len.
*/
- aead_parms.assoc_size -= GCM_ESP_IV_SIZE;
+ aead_parms.assoc_size -= GCM_RFC4106_IV_SIZE;
if (rctx->is_encrypt) {
aead_parms.return_iv = true;
- aead_parms.ret_iv_len = GCM_ESP_IV_SIZE;
+ aead_parms.ret_iv_len = GCM_RFC4106_IV_SIZE;
aead_parms.ret_iv_off = GCM_ESP_SALT_SIZE;
}
} else {
@@ -3255,7 +3255,7 @@ static struct iproc_alg_s driver_algs[] = {
.cra_flags = CRYPTO_ALG_NEED_FALLBACK
},
.setkey = aead_gcm_esp_setkey,
-.ivsize = GCM_ESP_IV_SIZE,
+.ivsize = GCM_RFC4106_IV_SIZE,
.maxauthsize = AES_BLOCK_SIZE,
},
.cipher_info = {
@@ -3301,7 +3301,7 @@ static struct iproc_alg_s driver_algs[] = {
.cra_flags = CRYPTO_ALG_NEED_FALLBACK
},
.setkey = rfc4543_gcm_esp_setkey,
-.ivsize = GCM_ESP_IV_SIZE,
+.ivsize = GCM_RFC4106_IV_SIZE,
.maxauthsize = AES_BLOCK_SIZE,
},
.cipher_info = {
diff --git a/drivers/crypto/bcm/cipher.h b/drivers/crypto/bcm/cipher.h
index 57a55eb2a255..763c425c41ca 100644
--- a/drivers/crypto/bcm/cipher.h
+++ b/drivers/crypto/bcm/cipher.h
@@ -23,6 +23,7 @@
#include
#include
#include
+#include
#include
#include
@@ -39,8 +40,6 @@
#define ARC4_STATE_SIZE 4
#define CCM_AES_IV_SIZE16
-#define GCM_AES_IV_SIZE12
-#define GCM_ESP_IV_SIZE 8
#define CCM_ESP_IV_SIZE 8
#define RFC4543_ICV_SIZE 16
--
2.13.0
[PATCH 04/11] crypto: nx - Use GCM IV size constant
This patch replace GCM IV size value by their constant name.
Signed-off-by: Corentin Labbe
---
drivers/crypto/nx/nx-aes-gcm.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/crypto/nx/nx-aes-gcm.c b/drivers/crypto/nx/nx-aes-gcm.c
index abd465f479c4..a810596b97c2 100644
--- a/drivers/crypto/nx/nx-aes-gcm.c
+++ b/drivers/crypto/nx/nx-aes-gcm.c
@@ -22,6 +22,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -433,7 +434,7 @@ static int gcm_aes_nx_encrypt(struct aead_request *req)
struct nx_gcm_rctx *rctx = aead_request_ctx(req);
char *iv = rctx->iv;
- memcpy(iv, req->iv, 12);
+ memcpy(iv, req->iv, GCM_AES_IV_SIZE);
return gcm_aes_nx_crypt(req, 1, req->assoclen);
}
@@ -443,7 +444,7 @@ static int gcm_aes_nx_decrypt(struct aead_request *req)
struct nx_gcm_rctx *rctx = aead_request_ctx(req);
char *iv = rctx->iv;
- memcpy(iv, req->iv, 12);
+ memcpy(iv, req->iv, GCM_AES_IV_SIZE);
return gcm_aes_nx_crypt(req, 0, req->assoclen);
}
@@ -498,7 +499,7 @@ struct aead_alg nx_gcm_aes_alg = {
},
.init= nx_crypto_ctx_aes_gcm_init,
.exit= nx_crypto_ctx_aead_exit,
- .ivsize = 12,
+ .ivsize = GCM_AES_IV_SIZE,
.maxauthsize = AES_BLOCK_SIZE,
.setkey = gcm_aes_nx_set_key,
.encrypt = gcm_aes_nx_encrypt,
@@ -516,7 +517,7 @@ struct aead_alg nx_gcm4106_aes_alg = {
},
.init= nx_crypto_ctx_aes_gcm_init,
.exit= nx_crypto_ctx_aead_exit,
- .ivsize = 8,
+ .ivsize = GCM_RFC4106_IV_SIZE,
.maxauthsize = AES_BLOCK_SIZE,
.setkey = gcm4106_aes_nx_set_key,
.setauthsize = gcm4106_aes_nx_setauthsize,
--
2.13.0
[PATCH 05/11] crypto: atmel - Use GCM IV size constant
This patch replace GCM IV size value by their constant name.
Signed-off-by: Corentin Labbe
---
drivers/crypto/atmel-aes.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/crypto/atmel-aes.c b/drivers/crypto/atmel-aes.c
index 29e20c37f3a6..903fd43f23a5 100644
--- a/drivers/crypto/atmel-aes.c
+++ b/drivers/crypto/atmel-aes.c
@@ -36,6 +36,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -1532,7 +1533,7 @@ static int atmel_aes_gcm_start(struct atmel_aes_dev *dd)
if (err)
return atmel_aes_complete(dd, err);
- if (likely(ivsize == 12)) {
+ if (likely(ivsize == GCM_AES_IV_SIZE)) {
memcpy(ctx->j0, iv, ivsize);
ctx->j0[3] = cpu_to_be32(1);
return atmel_aes_gcm_process(dd);
@@ -1820,7 +1821,7 @@ static struct aead_alg aes_gcm_alg = {
.decrypt= atmel_aes_gcm_decrypt,
.init = atmel_aes_gcm_init,
.exit = atmel_aes_gcm_exit,
- .ivsize = 12,
+ .ivsize = GCM_AES_IV_SIZE,
.maxauthsize= AES_BLOCK_SIZE,
.base = {
--
2.13.0
[PATCH 03/11] crypto: ccp - Use GCM IV size constant
This patch replace GCM IV size value by their constant name.
Signed-off-by: Corentin Labbe
---
drivers/crypto/ccp/ccp-crypto-aes-galois.c | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/drivers/crypto/ccp/ccp-crypto-aes-galois.c
b/drivers/crypto/ccp/ccp-crypto-aes-galois.c
index 52313524a4dd..ff02b713c6f6 100644
--- a/drivers/crypto/ccp/ccp-crypto-aes-galois.c
+++ b/drivers/crypto/ccp/ccp-crypto-aes-galois.c
@@ -19,13 +19,12 @@
#include
#include
#include
+#include
#include
#include
#include "ccp-crypto.h"
-#defineAES_GCM_IVSIZE 12
-
static int ccp_aes_gcm_complete(struct crypto_async_request *async_req, int
ret)
{
return ret;
@@ -95,9 +94,9 @@ static int ccp_aes_gcm_crypt(struct aead_request *req, bool
encrypt)
*/
/* Prepare the IV: 12 bytes + an integer (counter) */
- memcpy(rctx->iv, req->iv, AES_GCM_IVSIZE);
+ memcpy(rctx->iv, req->iv, GCM_AES_IV_SIZE);
for (i = 0; i < 3; i++)
- rctx->iv[i + AES_GCM_IVSIZE] = 0;
+ rctx->iv[i + GCM_AES_IV_SIZE] = 0;
rctx->iv[AES_BLOCK_SIZE - 1] = 1;
/* Set up a scatterlist for the IV */
@@ -160,7 +159,7 @@ static struct aead_alg ccp_aes_gcm_defaults = {
.encrypt = ccp_aes_gcm_encrypt,
.decrypt = ccp_aes_gcm_decrypt,
.init = ccp_aes_gcm_cra_init,
- .ivsize = AES_GCM_IVSIZE,
+ .ivsize = GCM_AES_IV_SIZE,
.maxauthsize = AES_BLOCK_SIZE,
.base = {
.cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
--
2.13.0
[PATCH 02/11] crypto: caam - Use GCM IV size constant
This patch replace GCM IV size value by their constant name.
Signed-off-by: Corentin Labbe
---
drivers/crypto/caam/caamalg.c | 10 +-
drivers/crypto/caam/compat.h | 1 +
2 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/crypto/caam/caamalg.c b/drivers/crypto/caam/caamalg.c
index 54f3b375a453..baa8dd52472d 100644
--- a/drivers/crypto/caam/caamalg.c
+++ b/drivers/crypto/caam/caamalg.c
@@ -992,7 +992,7 @@ static void init_gcm_job(struct aead_request *req,
struct caam_ctx *ctx = crypto_aead_ctx(aead);
unsigned int ivsize = crypto_aead_ivsize(aead);
u32 *desc = edesc->hw_desc;
- bool generic_gcm = (ivsize == 12);
+ bool generic_gcm = (ivsize == GCM_AES_IV_SIZE);
unsigned int last;
init_aead_job(req, edesc, all_contig, encrypt);
@@ -1004,7 +1004,7 @@ static void init_gcm_job(struct aead_request *req,
/* Read GCM IV */
append_cmd(desc, CMD_FIFO_LOAD | FIFOLD_CLASS_CLASS1 | IMMEDIATE |
-FIFOLD_TYPE_IV | FIFOLD_TYPE_FLUSH1 | 12 | last);
+FIFOLD_TYPE_IV | FIFOLD_TYPE_FLUSH1 | GCM_AES_IV_SIZE
| last);
/* Append Salt */
if (!generic_gcm)
append_data(desc, ctx->key + ctx->cdata.keylen, 4);
@@ -1953,7 +1953,7 @@ static struct caam_aead_alg driver_aeads[] = {
.setauthsize = rfc4106_setauthsize,
.encrypt = ipsec_gcm_encrypt,
.decrypt = ipsec_gcm_decrypt,
- .ivsize = 8,
+ .ivsize = GCM_RFC4106_IV_SIZE,
.maxauthsize = AES_BLOCK_SIZE,
},
.caam = {
@@ -1971,7 +1971,7 @@ static struct caam_aead_alg driver_aeads[] = {
.setauthsize = rfc4543_setauthsize,
.encrypt = ipsec_gcm_encrypt,
.decrypt = ipsec_gcm_decrypt,
- .ivsize = 8,
+ .ivsize = GCM_RFC4543_IV_SIZE,
.maxauthsize = AES_BLOCK_SIZE,
},
.caam = {
@@ -1990,7 +1990,7 @@ static struct caam_aead_alg driver_aeads[] = {
.setauthsize = gcm_setauthsize,
.encrypt = gcm_encrypt,
.decrypt = gcm_decrypt,
- .ivsize = 12,
+ .ivsize = GCM_AES_IV_SIZE,
.maxauthsize = AES_BLOCK_SIZE,
},
.caam = {
diff --git a/drivers/crypto/caam/compat.h b/drivers/crypto/caam/compat.h
index 7149cd2492e0..5b8d930f3dd8 100644
--- a/drivers/crypto/caam/compat.h
+++ b/drivers/crypto/caam/compat.h
@@ -31,6 +31,7 @@
#include
#include
#include
+#include
#include
#include
#include
--
2.13.0
[PATCH 01/11] crypto: gcm - add GCM IV size constant
Many GCM users use directly GCM IV size instead of using some constant. This patch add all IV size constant used by GCM. Signed-off-by: Corentin Labbe --- include/crypto/gcm.h | 8 1 file changed, 8 insertions(+) create mode 100644 include/crypto/gcm.h diff --git a/include/crypto/gcm.h b/include/crypto/gcm.h new file mode 100644 index ..c50e057ea17e --- /dev/null +++ b/include/crypto/gcm.h @@ -0,0 +1,8 @@ +#ifndef _CRYPTO_GCM_H +#define _CRYPTO_GCM_H + +#define GCM_AES_IV_SIZE 12 +#define GCM_RFC4106_IV_SIZE 8 +#define GCM_RFC4543_IV_SIZE 8 + +#endif -- 2.13.0
[PATCH 00/11] crypto: gcm - add GCM IV size constant
Many GCM users use directly GCM IV size instead of using some constant. This patch add all IV size constant used by GCM and convert drivers for using them.. Corentin Labbe (11): crypto: gcm - add GCM iv size constant crypto: caam - Use GCM IV size constant crypto: ccp - Use GCM IV size constant crypto: nx - Use GCM IV size constant crypto: atmel - Use GCM IV size constant crypto: bcm - Use GCM IV size constant crypto: mediatek - Use GCM IV size constant crypto: chelsio - Use GCM IV size constant crypto: omap - Use GCM IV size constant crypto: gcm - Use GCM IV size constant crypto: aesni - Use GCM IV size constant arch/x86/crypto/aesni-intel_glue.c | 7 --- crypto/gcm.c | 23 --- drivers/crypto/atmel-aes.c | 5 +++-- drivers/crypto/bcm/cipher.c| 8 drivers/crypto/bcm/cipher.h| 3 +-- drivers/crypto/caam/caamalg.c | 10 +- drivers/crypto/caam/compat.h | 1 + drivers/crypto/ccp/ccp-crypto-aes-galois.c | 9 - drivers/crypto/chelsio/chcr_algo.c | 9 + drivers/crypto/mediatek/mtk-aes.c | 3 ++- drivers/crypto/nx/nx-aes-gcm.c | 9 + drivers/crypto/omap-aes-gcm.c | 7 --- drivers/crypto/omap-aes.c | 5 +++-- include/crypto/gcm.h | 8 14 files changed, 61 insertions(+), 46 deletions(-) create mode 100644 include/crypto/gcm.h -- 2.13.0
Re: [PATCH] powerpc: powernv: Fix build error on const discarding
On Thu, Aug 17, 2017 at 10:52:11PM +1000, Michael Ellerman wrote: > Corentin Labbe writes: > > > When building a random powerpc kernel I hit this build error: > > CC arch/powerpc/platforms/powernv/opal-imc.o > > arch/powerpc/platforms/powernv/opal-imc.c: In function « > > disable_nest_pmu_counters »: > > arch/powerpc/platforms/powernv/opal-imc.c:130:13: error : assignment > > discards « const » qualifier from pointer target type > > [-Werror=discarded-qualifiers] > >l_cpumask = cpumask_of_node(nid); > > ^ > > This patch simply add const to l_cpumask to fix this issue. > > Thanks. I'm not sure why we haven't seen that. > > Do you mind attaching your .config ? > > cheers Yes Regards # # Automatically generated file; DO NOT EDIT. # Linux/powerpc 4.13.0-rc5 Kernel Configuration # CONFIG_PPC64=y # # Processor support # CONFIG_PPC_BOOK3S_64=y # CONFIG_PPC_BOOK3E_64 is not set CONFIG_GENERIC_CPU=y # CONFIG_CELL_CPU is not set # CONFIG_POWER4_CPU is not set # CONFIG_POWER5_CPU is not set # CONFIG_POWER6_CPU is not set # CONFIG_POWER7_CPU is not set # CONFIG_POWER8_CPU is not set CONFIG_PPC_BOOK3S=y CONFIG_PPC_FPU=y # CONFIG_ALTIVEC is not set CONFIG_PPC_STD_MMU=y CONFIG_PPC_STD_MMU_64=y CONFIG_PPC_RADIX_MMU=y CONFIG_PPC_MM_SLICES=y CONFIG_PPC_HAVE_PMU_SUPPORT=y CONFIG_PPC_PERF_CTRS=y CONFIG_FORCE_SMP=y CONFIG_SMP=y CONFIG_NR_CPUS=4 CONFIG_PPC_DOORBELL=y CONFIG_VDSO32=y CONFIG_CPU_BIG_ENDIAN=y # CONFIG_CPU_LITTLE_ENDIAN is not set CONFIG_64BIT=y CONFIG_ARCH_PHYS_ADDR_T_64BIT=y CONFIG_ARCH_DMA_ADDR_T_64BIT=y CONFIG_MMU=y CONFIG_ARCH_MMAP_RND_BITS_MAX=33 CONFIG_ARCH_MMAP_RND_BITS_MIN=18 CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=17 CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 CONFIG_HAVE_SETUP_PER_CPU_AREA=y CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y CONFIG_NR_IRQS=512 CONFIG_STACKTRACE_SUPPORT=y CONFIG_TRACE_IRQFLAGS_SUPPORT=y CONFIG_LOCKDEP_SUPPORT=y CONFIG_RWSEM_XCHGADD_ALGORITHM=y CONFIG_GENERIC_LOCKBREAK=y CONFIG_GENERIC_HWEIGHT=y CONFIG_ARCH_HAS_DMA_SET_COHERENT_MASK=y CONFIG_PPC=y # CONFIG_GENERIC_CSUM is not set CONFIG_EARLY_PRINTK=y CONFIG_PANIC_TIMEOUT=0 CONFIG_COMPAT=y CONFIG_SYSVIPC_COMPAT=y CONFIG_SCHED_OMIT_FRAME_POINTER=y CONFIG_ARCH_MAY_HAVE_PC_FDC=y CONFIG_PPC_UDBG_16550=y CONFIG_GENERIC_TBSYNC=y CONFIG_AUDIT_ARCH=y CONFIG_GENERIC_BUG=y CONFIG_EPAPR_BOOT=y # CONFIG_DEFAULT_UIMAGE is not set CONFIG_ARCH_HIBERNATION_POSSIBLE=y CONFIG_ARCH_SUSPEND_POSSIBLE=y # CONFIG_PPC_DCR_NATIVE is not set # CONFIG_PPC_DCR_MMIO is not set # CONFIG_PPC_OF_PLATFORM_PCI is not set CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y CONFIG_ARCH_SUPPORTS_UPROBES=y CONFIG_PPC_EMULATE_SSTEP=y CONFIG_ZONE_DMA32=y CONFIG_PGTABLE_LEVELS=4 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" CONFIG_IRQ_WORK=y CONFIG_BUILDTIME_EXTABLE_SORT=y # # General setup # CONFIG_INIT_ENV_ARG_LIMIT=32 CONFIG_CROSS_COMPILE="" # CONFIG_COMPILE_TEST is not set CONFIG_LOCALVERSION="" # CONFIG_LOCALVERSION_AUTO is not set CONFIG_HAVE_KERNEL_GZIP=y CONFIG_HAVE_KERNEL_XZ=y CONFIG_KERNEL_GZIP=y # CONFIG_KERNEL_XZ is not set CONFIG_DEFAULT_HOSTNAME="(none)" # CONFIG_SWAP is not set CONFIG_SYSVIPC=y CONFIG_SYSVIPC_SYSCTL=y CONFIG_POSIX_MQUEUE=y CONFIG_POSIX_MQUEUE_SYSCTL=y CONFIG_CROSS_MEMORY_ATTACH=y CONFIG_FHANDLE=y # CONFIG_USELIB is not set CONFIG_AUDIT=y CONFIG_HAVE_ARCH_AUDITSYSCALL=y CONFIG_AUDITSYSCALL=y CONFIG_AUDIT_WATCH=y CONFIG_AUDIT_TREE=y # # IRQ subsystem # CONFIG_GENERIC_IRQ_SHOW=y CONFIG_GENERIC_IRQ_SHOW_LEVEL=y CONFIG_GENERIC_IRQ_MIGRATION=y CONFIG_HARDIRQS_SW_RESEND=y CONFIG_IRQ_DOMAIN=y CONFIG_GENERIC_MSI_IRQ=y # CONFIG_IRQ_DOMAIN_DEBUG is not set CONFIG_IRQ_FORCED_THREADING=y CONFIG_SPARSE_IRQ=y # CONFIG_GENERIC_IRQ_DEBUGFS is not set CONFIG_GENERIC_TIME_VSYSCALL=y CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_ARCH_HAS_TICK_BROADCAST=y CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y CONFIG_GENERIC_CMOS_UPDATE=y # # Timers subsystem # CONFIG_TICK_ONESHOT=y CONFIG_NO_HZ_COMMON=y # CONFIG_HZ_PERIODIC is not set CONFIG_NO_HZ_IDLE=y # CONFIG_NO_HZ_FULL is not set CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y # # CPU/Task time and stats accounting # CONFIG_TICK_CPU_ACCOUNTING=y # CONFIG_VIRT_CPU_ACCOUNTING_NATIVE is not set # CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set # CONFIG_IRQ_TIME_ACCOUNTING is not set CONFIG_BSD_PROCESS_ACCT=y CONFIG_BSD_PROCESS_ACCT_V3=y # CONFIG_TASKSTATS is not set # # RCU Subsystem # CONFIG_PREEMPT_RCU=y # CONFIG_RCU_EXPERT is not set CONFIG_SRCU=y CONFIG_TREE_SRCU=y CONFIG_TASKS_RCU=y CONFIG_RCU_STALL_COMMON=y CONFIG_RCU_NEED_SEGCBLIST=y CONFIG_BUILD_BIN2C=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=19 CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13 CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y CONFIG_CGROUPS=y # CONFIG_MEMCG is not set CONFIG_BLK_CGROUP=y # CONFIG_DEBUG_BLK_CGROUP is not set CONFIG_CGROUP_SCHED=y CONFIG_FAIR_GROUP_SCHED=y
[PATCH] powerpc: powernv: Fix build error on const discarding
When building a random powerpc kernel I hit this build error:
CC arch/powerpc/platforms/powernv/opal-imc.o
arch/powerpc/platforms/powernv/opal-imc.c: In function «
disable_nest_pmu_counters »:
arch/powerpc/platforms/powernv/opal-imc.c:130:13: error : assignment discards «
const » qualifier from pointer target type [-Werror=discarded-qualifiers]
l_cpumask = cpumask_of_node(nid);
^
This patch simply add const to l_cpumask to fix this issue.
Signed-off-by: Corentin Labbe
---
arch/powerpc/platforms/powernv/opal-imc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/platforms/powernv/opal-imc.c
b/arch/powerpc/platforms/powernv/opal-imc.c
index b903bf5e6006..21f6531fae20 100644
--- a/arch/powerpc/platforms/powernv/opal-imc.c
+++ b/arch/powerpc/platforms/powernv/opal-imc.c
@@ -123,7 +123,7 @@ static int imc_pmu_create(struct device_node *parent, int
pmu_index, int domain)
static void disable_nest_pmu_counters(void)
{
int nid, cpu;
- struct cpumask *l_cpumask;
+ const struct cpumask *l_cpumask;
get_online_cpus();
for_each_online_node(nid) {
--
2.13.0
