Re: [Jfs-discussion] [PATCH] fs: convert a pile of fsync routines to errseq_t based reporting
On 07/28/2017 09:23 AM, Jeff Layton wrote:
> From: Jeff Layton <jlay...@redhat.com>
>
> This patch converts most of the in-kernel filesystems that do writeback
> out of the pagecache to report errors using the errseq_t-based
> infrastructure that was recently added. This allows them to report
> errors once for each open file description.
>
> Most filesystems have a fairly straightforward fsync operation. They
> call filemap_write_and_wait_range to write back all of the data and
> wait on it, and then (sometimes) sync out the metadata.
>
> For those filesystems this is a straightforward conversion from calling
> filemap_write_and_wait_range in their fsync operation to calling
> file_write_and_wait_range.
>
> Signed-off-by: Jeff Layton <jlay...@redhat.com>
Acked-by: Dave Kleikamp <dave.kleik...@oracle.com>
(for jfs)
> ---
> arch/powerpc/platforms/cell/spufs/file.c | 2 +-
> drivers/staging/lustre/lustre/llite/file.c | 2 +-
> drivers/video/fbdev/core/fb_defio.c| 2 +-
> fs/9p/vfs_file.c | 4 ++--
> fs/affs/file.c | 2 +-
> fs/afs/write.c | 2 +-
> fs/cifs/file.c | 4 ++--
> fs/exofs/file.c| 2 +-
> fs/f2fs/file.c | 2 +-
> fs/hfs/inode.c | 2 +-
> fs/hfsplus/inode.c | 2 +-
> fs/hostfs/hostfs_kern.c| 2 +-
> fs/hpfs/file.c | 2 +-
> fs/jffs2/file.c| 2 +-
> fs/jfs/file.c | 2 +-
> fs/ncpfs/file.c| 2 +-
> fs/ntfs/dir.c | 2 +-
> fs/ntfs/file.c | 2 +-
> fs/ocfs2/file.c| 2 +-
> fs/reiserfs/dir.c | 2 +-
> fs/reiserfs/file.c | 2 +-
> fs/ubifs/file.c| 2 +-
> 22 files changed, 24 insertions(+), 24 deletions(-)
>
> Rolling up all of these conversions into a single patch, as Christoph
> Hellwig suggested. Most of these are not tested, but the conversion
> here is fairly straightforward.
>
> Any maintainers who object, please let me know and I'll yank that
> part out of this patch.
>
> diff --git a/arch/powerpc/platforms/cell/spufs/file.c
> b/arch/powerpc/platforms/cell/spufs/file.c
> index ae2f740a82f1..5ffcdeb1eb17 100644
> --- a/arch/powerpc/platforms/cell/spufs/file.c
> +++ b/arch/powerpc/platforms/cell/spufs/file.c
> @@ -1749,7 +1749,7 @@ static int spufs_mfc_flush(struct file *file,
> fl_owner_t id)
> static int spufs_mfc_fsync(struct file *file, loff_t start, loff_t end, int
> datasync)
> {
> struct inode *inode = file_inode(file);
> - int err = filemap_write_and_wait_range(inode->i_mapping, start, end);
> + int err = file_write_and_wait_range(file, start, end);
> if (!err) {
> inode_lock(inode);
> err = spufs_mfc_flush(file, NULL);
> diff --git a/drivers/staging/lustre/lustre/llite/file.c
> b/drivers/staging/lustre/lustre/llite/file.c
> index ab1c85c1ed38..f7d07735ac66 100644
> --- a/drivers/staging/lustre/lustre/llite/file.c
> +++ b/drivers/staging/lustre/lustre/llite/file.c
> @@ -2364,7 +2364,7 @@ int ll_fsync(struct file *file, loff_t start, loff_t
> end, int datasync)
> PFID(ll_inode2fid(inode)), inode);
> ll_stats_ops_tally(ll_i2sbi(inode), LPROC_LL_FSYNC, 1);
>
> - rc = filemap_write_and_wait_range(inode->i_mapping, start, end);
> + rc = file_write_and_wait_range(file, start, end);
> inode_lock(inode);
>
> /* catch async errors that were recorded back when async writeback
> diff --git a/drivers/video/fbdev/core/fb_defio.c
> b/drivers/video/fbdev/core/fb_defio.c
> index 37f69c061210..487d5e336e1b 100644
> --- a/drivers/video/fbdev/core/fb_defio.c
> +++ b/drivers/video/fbdev/core/fb_defio.c
> @@ -69,7 +69,7 @@ int fb_deferred_io_fsync(struct file *file, loff_t start,
> loff_t end, int datasy
> {
> struct fb_info *info = file->private_data;
> struct inode *inode = file_inode(file);
> - int err = filemap_write_and_wait_range(inode->i_mapping, start, end);
> + int err = file_write_and_wait_range(file, start, end);
> if (err)
> return err;
>
> diff --git a/fs/9p/vfs_file.c b/fs/9p/vfs_file.c
> index 3de3b4a89d89..4802d75b3cf7 100644
> --- a/fs/9p/vfs_file.c
> +++ b/fs/9p/vfs_file.c
> @@ -445,7 +445,7 @@ static int v9fs_file_fsync(struct file *filp, loff_t
> start, loff_t end,
> struct p9_wstat wstat;
Re: [PATCH V2 1/6] powerpc: Move udbg_early_init() after early_init_devtree()
On Wed, 2011-03-02 at 14:37 +1100, Benjamin Herrenschmidt wrote: On Mon, 2011-02-07 at 19:29 +1100, David Gibson wrote: On Wed, Feb 02, 2011 at 06:00:25PM -0600, Dave Kleikamp wrote: On Thu, 2011-02-03 at 10:06 +1100, David Gibson wrote: On Tue, Feb 01, 2011 at 12:48:41PM -0600, Dave Kleikamp wrote: so that it can use information from the device tree. Hrm. On the other hand this means that the early_init_devtree() code can't benefit from hardcoded early debugging. Since you don't actually appear to use devtree information in udbg_early_init() in the latest series, I'd suggest dropping this patch. Patch 2 depends on early_init_devtree() being run. Until then, I don't know of a way to get at the bootargs. Ah, yes. Drat. Doesn't matter. _Early_ debug has (or should have) the address in the .config file anyways, so it really shouldn't have to care about the arguments. So I'll drop this patch. There are plenty of reasons why we want to be able to use the early debug stuff to debug what's happening inside early_init_devtree() :-) Fair enough. I wasn't sure this was the right thing to do. It's either turn off early debug for AMP, or build separate kernels with a different address in .config. Shaggy ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH V2 3/6] powerpc/47x: allow kernel to be loaded in higher physical memory
On Wed, 2011-02-02 at 01:45 -0600, Kumar Gala wrote: On Feb 1, 2011, at 12:48 PM, Dave Kleikamp wrote: Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com Cc: Benjamin Herrenschmidt b...@kernel.crashing.org Cc: Josh Boyer jwbo...@linux.vnet.ibm.com Cc: linuxppc-dev@lists.ozlabs.org --- arch/powerpc/Kconfig |2 +- arch/powerpc/configs/44x/iss476-smp_defconfig |6 ++-- arch/powerpc/kernel/head_44x.S| 42 - arch/powerpc/mm/44x_mmu.c | 13 ++-- 4 files changed, 48 insertions(+), 15 deletions(-) Would be nice to expand in the commit message on what higher physical means. right. should be clear in the next set -- Dave Kleikamp IBM Linux Technology Center ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH V2 6/6] powerpc/476: Create a dts files for two 476 AMP instances under ISS
On Wed, 2011-02-02 at 13:43 +1100, David Gibson wrote:
On Tue, Feb 01, 2011 at 12:48:46PM -0600, Dave Kleikamp wrote:
These are completely independent OS instances, each running on 2
cores.
[snip]
+/memreserve/ 0x01f0 0x0010;
A comment describing what this reserved section is for would be good.
I with I knew what it was for. I've blindly carried it along for a
while. Removing it doesn't appear to do any harm. Ben, any idea why
this was ever in here?
+/ {
+ #address-cells = 2;
+ #size-cells = 1;
+ model = ibm,iss-4xx;
+ compatible = ibm,iss-4xx, ibm,47x-AMP;
+ dcr-parent = {/cpus/cpu@0};
+
+ aliases {
+ serial0 = UART0;
+ };
+
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ cpu@0 {
+ device_type = cpu;
+ model = PowerPC,4xx; // real CPU changed in sim
If the comment is true, then it's probably simpler to just omit the
model property. I'm pretty sure nothing will look at it.
It doesn't appear to be true. Another bit I've been carrying along
without checking it. Removing the comment.
+ reg = 0;
+ clock-frequency = 1; // 100Mhz :-)
+ timebase-frequency = 1; +
i-cache-line-size = 32;
+ d-cache-line-size = 32;
+ i-cache-size = 32768;
+ d-cache-size = 32768;
+ dcr-controller;
+ dcr-access-method = native;
+ status = ok;
Should be okay rather than ok.
okay :-)
[snip]
+ UART0: serial@4200 {
+ device_type = serial;
+ compatible = ns16550a;
+ reg = 0x4200 0x0008;
+ virtual-reg = 0xe200;
+ clock-frequency = 11059200;
+ current-speed = 115200;
+ interrupt-parent = MPIC;
+ interrupts = 0x0 0x2;
+ };
+ };
+ };
+
+ nvrtc {
+ compatible = ds1743-nvram, ds1743, rtc-ds1743;
+ reg = 0 0xEF703000 0x2000;
+ };
+
+ chosen {
+ linux,stdout-path = /plb/opb/serial@4200;
You can use a string reference here:
linux,stdout-path = UART0;
no problem
Shaggy
--
Dave Kleikamp
IBM Linux Technology Center
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[PATCH v3 0/6] powerpc: AMP support for 47x
These patches add Asynchonous MultiProcessing support for the 47x chipset. This allows independent OS instances to run on separate cores. v3: 1. switched from using compatible string to boolean cooperative-partition 2. fixed missing type in boot wrapper 3. fixed check for unspecified memory range in boot wrapper 4. Cleaned up the dts files v2: 1. Replace ugly hack in boot wrapper with generic solution Dave Kleikamp (6): powerpc: Move udbg_early_init() after early_init_devtree() powerpc/44x: allow override to hard-coded uart address powerpc/47x: allow kernel to be loaded in higher physical memory powerpc/44x: don't use tlbivax on AMP systems powerpc/44x: boot wrapper: allow kernel to load into non-zero address powerpc/476: Create a dts files for two 476 AMP instances under ISS arch/powerpc/Kconfig |2 +- arch/powerpc/boot/Makefile|6 +- arch/powerpc/boot/dts/iss476-amp1.dts | 119 arch/powerpc/boot/dts/iss476-amp2.dts | 120 + arch/powerpc/boot/treeboot-iss4xx.c | 22 +- arch/powerpc/boot/wrapper |7 ++ arch/powerpc/configs/44x/iss476-smp_defconfig |6 +- arch/powerpc/include/asm/mmu.h|2 +- arch/powerpc/kernel/head_44x.S| 42 +++-- arch/powerpc/kernel/setup_32.c|6 +- arch/powerpc/kernel/udbg_16550.c | 17 +++- arch/powerpc/mm/44x_mmu.c | 13 ++- arch/powerpc/mm/tlb_nohash.c | 23 +- 13 files changed, 361 insertions(+), 24 deletions(-) create mode 100644 arch/powerpc/boot/dts/iss476-amp1.dts create mode 100644 arch/powerpc/boot/dts/iss476-amp2.dts -- 1.7.3.4 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v3 4/6] powerpc/44x: don't use tlbivax on AMP systems
Since other OS's may be running on the other cores don't use tlbivax
Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com
Cc: Benjamin Herrenschmidt b...@kernel.crashing.org
Cc: Josh Boyer jwbo...@linux.vnet.ibm.com
Cc: linuxppc-dev@lists.ozlabs.org
---
arch/powerpc/include/asm/mmu.h |2 +-
arch/powerpc/kernel/setup_32.c |2 ++
arch/powerpc/mm/tlb_nohash.c | 23 ++-
3 files changed, 25 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h
index bb40a06..f3a7c65 100644
--- a/arch/powerpc/include/asm/mmu.h
+++ b/arch/powerpc/include/asm/mmu.h
@@ -80,7 +80,7 @@ static inline int mmu_has_feature(unsigned long feature)
extern unsigned int __start___mmu_ftr_fixup, __stop___mmu_ftr_fixup;
-/* MMU initialization (64-bit only fo now) */
+/* MMU initialization */
extern void early_init_mmu(void);
extern void early_init_mmu_secondary(void);
diff --git a/arch/powerpc/kernel/setup_32.c b/arch/powerpc/kernel/setup_32.c
index d1ca976..e50ead7 100644
--- a/arch/powerpc/kernel/setup_32.c
+++ b/arch/powerpc/kernel/setup_32.c
@@ -126,6 +126,8 @@ notrace void __init machine_init(unsigned long dt_ptr)
/* Enable early debugging if any specified (see udbg.h) */
udbg_early_init();
+ early_init_mmu();
+
probe_machine();
setup_kdump_trampoline();
diff --git a/arch/powerpc/mm/tlb_nohash.c b/arch/powerpc/mm/tlb_nohash.c
index 2a030d8..5f753b8 100644
--- a/arch/powerpc/mm/tlb_nohash.c
+++ b/arch/powerpc/mm/tlb_nohash.c
@@ -35,6 +35,7 @@
#include linux/preempt.h
#include linux/spinlock.h
#include linux/memblock.h
+#include linux/of_fdt.h
#include asm/tlbflush.h
#include asm/tlb.h
@@ -153,6 +154,8 @@ EXPORT_SYMBOL(local_flush_tlb_page);
*/
#ifdef CONFIG_SMP
+static int amp;
+
static DEFINE_RAW_SPINLOCK(tlbivax_lock);
static int mm_is_core_local(struct mm_struct *mm)
@@ -232,7 +235,7 @@ void __flush_tlb_page(struct mm_struct *mm, unsigned long
vmaddr,
cpu_mask = mm_cpumask(mm);
if (!mm_is_core_local(mm)) {
/* If broadcast tlbivax is supported, use it */
- if (mmu_has_feature(MMU_FTR_USE_TLBIVAX_BCAST)) {
+ if (!amp mmu_has_feature(MMU_FTR_USE_TLBIVAX_BCAST)) {
int lock = mmu_has_feature(MMU_FTR_LOCK_BCAST_INVAL);
if (lock)
raw_spin_lock(tlbivax_lock);
@@ -266,6 +269,17 @@ EXPORT_SYMBOL(flush_tlb_page);
#endif /* CONFIG_SMP */
+#ifdef CONFIG_PPC_47x
+void __init early_init_mmu_47x(void)
+{
+#ifdef CONFIG_SMP
+ unsigned long root = of_get_flat_dt_root();
+ if (of_get_flat_dt_prop(root, cooperative-partition, NULL))
+ amp = 1;
+#endif /* CONFIG_SMP */
+}
+#endif /* CONFIG_PPC_47x */
+
/*
* Flush kernel TLB entries in the given range
*/
@@ -587,4 +601,11 @@ void setup_initial_memory_limit(phys_addr_t
first_memblock_base,
/* Finally limit subsequent allocations */
memblock_set_current_limit(first_memblock_base + ppc64_rma_size);
}
+#else /* ! CONFIG_PPC64 */
+void __init early_init_mmu(void)
+{
+#ifdef CONFIG_PPC_47x
+ early_init_mmu_47x();
+#endif
+}
#endif /* CONFIG_PPC64 */
--
1.7.3.4
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[PATCH v3 6/6] powerpc/476: Create a dts files for two 476 AMP instances under ISS
These are completely independent OS instances, each running on 2 cores.
Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com
Cc: Benjamin Herrenschmidt b...@kernel.crashing.org
Cc: Josh Boyer jwbo...@linux.vnet.ibm.com
Cc: linuxppc-dev@lists.ozlabs.org
---
arch/powerpc/boot/Makefile|6 ++-
arch/powerpc/boot/dts/iss476-amp1.dts | 119
arch/powerpc/boot/dts/iss476-amp2.dts | 120 +
arch/powerpc/boot/wrapper |7 ++
4 files changed, 251 insertions(+), 1 deletions(-)
create mode 100644 arch/powerpc/boot/dts/iss476-amp1.dts
create mode 100644 arch/powerpc/boot/dts/iss476-amp2.dts
diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile
index 8917816..99dbc39 100644
--- a/arch/powerpc/boot/Makefile
+++ b/arch/powerpc/boot/Makefile
@@ -45,6 +45,8 @@ $(obj)/cuboot-katmai.o: BOOTCFLAGS += -mcpu=405
$(obj)/cuboot-acadia.o: BOOTCFLAGS += -mcpu=405
$(obj)/treeboot-walnut.o: BOOTCFLAGS += -mcpu=405
$(obj)/treeboot-iss4xx.o: BOOTCFLAGS += -mcpu=405
+$(obj)/treeboot-iss476-amp1.o: BOOTCFLAGS += -mcpu=405
+$(obj)/treeboot-iss476-amp2.o: BOOTCFLAGS += -mcpu=405
$(obj)/virtex405-head.o: BOOTAFLAGS += -mcpu=405
@@ -208,7 +210,9 @@ image-$(CONFIG_KATMAI) +=
cuImage.katmai
image-$(CONFIG_WARP) += cuImage.warp
image-$(CONFIG_YOSEMITE) += cuImage.yosemite
image-$(CONFIG_ISS4xx) += treeImage.iss4xx \
- treeImage.iss4xx-mpic
+ treeImage.iss4xx-mpic \
+ treeImage.iss476-amp1 \
+ treeImage.iss476-amp2
# Board ports in arch/powerpc/platform/8xx/Kconfig
image-$(CONFIG_MPC86XADS) += cuImage.mpc866ads
diff --git a/arch/powerpc/boot/dts/iss476-amp1.dts
b/arch/powerpc/boot/dts/iss476-amp1.dts
new file mode 100644
index 000..1fa882c
--- /dev/null
+++ b/arch/powerpc/boot/dts/iss476-amp1.dts
@@ -0,0 +1,119 @@
+/*
+ * Device Tree Source for IBM Embedded PPC 476 Platform
+ *
+ * Copyright 2010 Torez Smith, IBM Corporation.
+ *
+ * Based on earlier code:
+ * Copyright (c) 2006, 2007 IBM Corp.
+ * Josh Boyer jwbo...@linux.vnet.ibm.com, David Gibson d...@au1.ibm.com
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed as is without
+ * any warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+
+/ {
+ #address-cells = 2;
+ #size-cells = 1;
+ model = ibm,iss-4xx;
+ compatible = ibm,iss-4xx;
+ cooperative-partition;
+ dcr-parent = {/cpus/cpu@0};
+
+ aliases {
+ serial0 = UART0;
+ };
+
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ cpu@0 {
+ device_type = cpu;
+ model = PowerPC,4xx;
+ reg = 0;
+ clock-frequency = 1; // 100Mhz :-)
+ timebase-frequency = 1;
+ i-cache-line-size = 32;
+ d-cache-line-size = 32;
+ i-cache-size = 32768;
+ d-cache-size = 32768;
+ dcr-controller;
+ dcr-access-method = native;
+ status = okay;
+ };
+ cpu@1 {
+ device_type = cpu;
+ model = PowerPC,4xx; // real CPU changed in sim
+ reg = 1;
+ clock-frequency = 1; // 100Mhz :-)
+ timebase-frequency = 1;
+ i-cache-line-size = 32;
+ d-cache-line-size = 32;
+ i-cache-size = 32768;
+ d-cache-size = 32768;
+ dcr-controller;
+ dcr-access-method = native;
+ status = disabled;
+ enable-method = spin-table;
+ cpu-release-addr = 0 0x01f00100;
+ };
+ };
+
+ memory {
+ device_type = memory;
+ reg = 0x 0x 0x0200;
+
+ };
+
+ MPIC: interrupt-controller {
+ compatible = chrp,open-pic;
+ interrupt-controller;
+ dcr-reg = 0xffc0 0x0003;
+ #address-cells = 0;
+ #size-cells = 0;
+ #interrupt-cells = 2;
+ protected-sources = 1;/* uart */
+
+ };
+
+ plb {
+ compatible = ibm,plb-4xx, ibm,plb4; /* Could be PLB6,
doesn't matter */
+ #address-cells = 2;
+ #size-cells = 1;
+ ranges;
+ clock-frequency = 0; // Filled
[PATCH v3 1/6] powerpc: Move udbg_early_init() after early_init_devtree()
so that it can use information from the device tree.
Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com
Cc: Benjamin Herrenschmidt b...@kernel.crashing.org
Cc: Josh Boyer jwbo...@linux.vnet.ibm.com
Cc: linuxppc-dev@lists.ozlabs.org
---
arch/powerpc/kernel/setup_32.c |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/kernel/setup_32.c b/arch/powerpc/kernel/setup_32.c
index 1d2fbc9..d1ca976 100644
--- a/arch/powerpc/kernel/setup_32.c
+++ b/arch/powerpc/kernel/setup_32.c
@@ -120,12 +120,12 @@ notrace void __init machine_init(unsigned long dt_ptr)
{
lockdep_init();
- /* Enable early debugging if any specified (see udbg.h) */
- udbg_early_init();
-
/* Do some early initialization based on the flat device tree */
early_init_devtree(__va(dt_ptr));
+ /* Enable early debugging if any specified (see udbg.h) */
+ udbg_early_init();
+
probe_machine();
setup_kdump_trampoline();
--
1.7.3.4
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[PATCH v3 3/6] powerpc/47x: allow kernel to be loaded in higher physical memory
The 44x code (which is shared by 47x) assumes the available physical memory begins at 0x. This is not necessarily the case in an AMP environment. Support CONFIG_RELOCATABLE for 476 in order to allow the kernel to be loaded into a higher memory range. Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com Cc: Benjamin Herrenschmidt b...@kernel.crashing.org Cc: Josh Boyer jwbo...@linux.vnet.ibm.com Cc: linuxppc-dev@lists.ozlabs.org --- arch/powerpc/Kconfig |2 +- arch/powerpc/configs/44x/iss476-smp_defconfig |6 ++-- arch/powerpc/kernel/head_44x.S| 42 - arch/powerpc/mm/44x_mmu.c | 13 ++-- 4 files changed, 48 insertions(+), 15 deletions(-) diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index 7d69e9b..fa41026 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -827,7 +827,7 @@ config LOWMEM_CAM_NUM config RELOCATABLE bool Build a relocatable kernel (EXPERIMENTAL) - depends on EXPERIMENTAL ADVANCED_OPTIONS FLATMEM FSL_BOOKE + depends on EXPERIMENTAL ADVANCED_OPTIONS FLATMEM (FSL_BOOKE || PPC_47x) help This builds a kernel image that is capable of running at the location the kernel is loaded at (some alignment restrictions may diff --git a/arch/powerpc/configs/44x/iss476-smp_defconfig b/arch/powerpc/configs/44x/iss476-smp_defconfig index 92f863a..a6eb6ad 100644 --- a/arch/powerpc/configs/44x/iss476-smp_defconfig +++ b/arch/powerpc/configs/44x/iss476-smp_defconfig @@ -3,8 +3,8 @@ CONFIG_SMP=y CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y +CONFIG_SPARSE_IRQ=y CONFIG_LOG_BUF_SHIFT=14 -CONFIG_SYSFS_DEPRECATED_V2=y CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set CONFIG_EXPERT=y @@ -21,10 +21,11 @@ CONFIG_ISS4xx=y CONFIG_HZ_100=y CONFIG_MATH_EMULATION=y CONFIG_IRQ_ALL_CPUS=y -CONFIG_SPARSE_IRQ=y CONFIG_CMDLINE_BOOL=y CONFIG_CMDLINE=root=/dev/issblk0 # CONFIG_PCI is not set +CONFIG_ADVANCED_OPTIONS=y +CONFIG_RELOCATABLE=y CONFIG_NET=y CONFIG_PACKET=y CONFIG_UNIX=y @@ -67,7 +68,6 @@ CONFIG_EXT3_FS=y # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set CONFIG_EXT3_FS_POSIX_ACL=y CONFIG_EXT3_FS_SECURITY=y -CONFIG_INOTIFY=y CONFIG_PROC_KCORE=y CONFIG_TMPFS=y CONFIG_CRAMFS=y diff --git a/arch/powerpc/kernel/head_44x.S b/arch/powerpc/kernel/head_44x.S index cbb3436..1da9b7e 100644 --- a/arch/powerpc/kernel/head_44x.S +++ b/arch/powerpc/kernel/head_44x.S @@ -93,6 +93,30 @@ _ENTRY(_start); bl early_init +#ifdef CONFIG_RELOCATABLE + /* +* r25 will contain RPN/ERPN for the start address of memory +* +* Add the difference between KERNELBASE and PAGE_OFFSET to the +* start of physical memory to get kernstart_addr. +*/ + lis r3,kernstart_addr@ha + la r3,kernstart_addr@l(r3) + + lis r4,KERNELBASE@h + ori r4,r4,KERNELBASE@l + lis r5,PAGE_OFFSET@h + ori r5,r5,PAGE_OFFSET@l + subfr4,r5,r4 + + rlwinm r6,r25,0,28,31 /* ERPN */ + rlwinm r7,r25,0,0,3/* RPN - assuming 256 MB page size */ + add r7,r7,r4 + + stw r6,0(r3) + stw r7,4(r3) +#endif + /* * Decide what sort of machine this is and initialize the MMU. */ @@ -1001,9 +1025,6 @@ clear_utlb_entry: lis r3,PAGE_OFFSET@h ori r3,r3,PAGE_OFFSET@l - /* Kernel is at the base of RAM */ - li r4, 0/* Load the kernel physical address */ - /* Load the kernel PID = 0 */ li r0,0 mtspr SPRN_PID,r0 @@ -1013,9 +1034,8 @@ clear_utlb_entry: clrrwi r3,r3,12/* Mask off the effective page number */ ori r3,r3,PPC47x_TLB0_VALID | PPC47x_TLB0_256M - /* Word 1 */ - clrrwi r4,r4,12/* Mask off the real page number */ - /* ERPN is 0 for first 4GB page */ + /* Word 1 - use r25. RPN is the same as the original entry */ + /* Word 2 */ li r5,0 ori r5,r5,PPC47x_TLB2_S_RWX @@ -1026,7 +1046,7 @@ clear_utlb_entry: /* We write to way 0 and bolted 0 */ lis r0,0x8800 tlbwe r3,r0,0 - tlbwe r4,r0,1 + tlbwe r25,r0,1 tlbwe r5,r0,2 /* @@ -1124,7 +1144,13 @@ head_start_common: lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */ mtspr SPRN_IVPR,r4 - addis r22,r22,KERNELBASE@h + /* +* If the kernel was loaded at a non-zero 256 MB page, we need to +* mask off the most significant 4 bits to get the relative address +* from the start of physical memory +*/ + rlwinm r22,r22,0,4,31 + addis r22,r22,PAGE_OFFSET@h mtlrr22 isync blr diff --git a/arch/powerpc/mm/44x_mmu.c b/arch/powerpc/mm/44x_mmu.c index
[PATCH v3 5/6] powerpc/44x: boot wrapper: allow kernel to load into non-zero address
For AMP, different kernel instances load into separate memory regions.
Read the start of memory from the device tree and limit the memory to what's
specified in the device tree.
Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com
Cc: Benjamin Herrenschmidt b...@kernel.crashing.org
Cc: Josh Boyer jwbo...@linux.vnet.ibm.com
Cc: linuxppc-dev@lists.ozlabs.org
---
arch/powerpc/boot/treeboot-iss4xx.c | 22 +-
1 files changed, 21 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/boot/treeboot-iss4xx.c
b/arch/powerpc/boot/treeboot-iss4xx.c
index fcc4495..674e3bd 100644
--- a/arch/powerpc/boot/treeboot-iss4xx.c
+++ b/arch/powerpc/boot/treeboot-iss4xx.c
@@ -34,9 +34,28 @@
BSS_STACK(4096);
+static u32 ibm4xx_memstart;
+
static void iss_4xx_fixups(void)
{
- ibm4xx_sdram_fixup_memsize();
+ void *memory;
+ u32 reg[3];
+
+ memory = finddevice(/memory);
+ if (!memory)
+ fatal(Can't find memory node\n);
+ getprop(memory, reg, reg, sizeof(reg));
+ if (reg[2])
+ /* If the device tree specifies the memory range, use it */
+ ibm4xx_memstart = reg[1];
+ else
+ /* othersize, read it from the SDRAM controller */
+ ibm4xx_sdram_fixup_memsize();
+}
+
+static void *iss_4xx_vmlinux_alloc(unsigned long size)
+{
+ return (void *)ibm4xx_memstart;
}
#define SPRN_PIR 0x11E /* Processor Indentification Register */
@@ -48,6 +67,7 @@ void platform_init(void)
simple_alloc_init(_end, avail_ram, 128, 64);
platform_ops.fixups = iss_4xx_fixups;
+ platform_ops.vmlinux_alloc = iss_4xx_vmlinux_alloc;
platform_ops.exit = ibm44x_dbcr_reset;
pir_reg = mfspr(SPRN_PIR);
fdt_set_boot_cpuid_phys(_dtb_start, pir_reg);
--
1.7.3.4
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[PATCH v3 2/6] powerpc/44x: allow override to hard-coded uart address
Allow the early debug uart address to be overridden from the kernel
command line.
I would have preferred use the uart's virtual-reg property, but the device
tree hasn't been unflatted yet, and I don't know a reliable way to find it.
Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com
Cc: Benjamin Herrenschmidt b...@kernel.crashing.org
Cc: Josh Boyer jwbo...@linux.vnet.ibm.com
Cc: linuxppc-dev@lists.ozlabs.org
---
arch/powerpc/kernel/udbg_16550.c | 17 ++---
1 files changed, 14 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/kernel/udbg_16550.c b/arch/powerpc/kernel/udbg_16550.c
index b4b167b..d36021a 100644
--- a/arch/powerpc/kernel/udbg_16550.c
+++ b/arch/powerpc/kernel/udbg_16550.c
@@ -219,6 +219,19 @@ void udbg_init_pas_realmode(void)
#ifdef CONFIG_PPC_EARLY_DEBUG_44x
#include platforms/44x/44x.h
+static unsigned long udbg_44x_comport = PPC44x_EARLY_DEBUG_VIRTADDR;
+
+static int __init early_parse_comport(char *p)
+{
+ if (!p || !(*p))
+ return 0;
+
+ udbg_44x_comport = simple_strtoul(p, 0, 16);
+
+ return 0;
+}
+early_param(uart_addr, early_parse_comport);
+
static void udbg_44x_as1_flush(void)
{
if (udbg_comport) {
@@ -249,9 +262,7 @@ static int udbg_44x_as1_getc(void)
void __init udbg_init_44x_as1(void)
{
- udbg_comport =
- (struct NS16550 __iomem *)PPC44x_EARLY_DEBUG_VIRTADDR;
-
+ udbg_comport = (struct NS16550 __iomem *)udbg_44x_comport;
udbg_putc = udbg_44x_as1_putc;
udbg_flush = udbg_44x_as1_flush;
udbg_getc = udbg_44x_as1_getc;
--
1.7.3.4
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Re: [PATCH V2 5/6] powerpc/44x: boot wrapper: allow kernel to load into non-zero address
On Fri, 2011-02-04 at 09:07 -0500, Josh Boyer wrote:
On Tue, Feb 01, 2011 at 12:48:45PM -0600, Dave Kleikamp wrote:
+static ibm4xx_memstart;
+
static void iss_4xx_fixups(void)
{
-ibm4xx_sdram_fixup_memsize();
+void *memory;
+u32 reg[3];
+
+memory = finddevice(/memory);
+if (!memory)
+fatal(Can't find memory node\n);
+getprop(memory, reg, reg, sizeof(reg));
+if (reg[1] || reg[2])
Wouldn't this test allow for a faulty device tree that specified a 0
size (0x0 in reg[2])? Maybe just check reg[2] for non-zero instead?
That make sense.
josh
--
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Re: [PATCH V2 4/6] powerpc/44x: don't use tlbivax on AMP systems
On Thu, 2011-02-03 at 16:03 +1100, David Gibson wrote:
On Wed, Feb 02, 2011 at 05:53:59PM -0600, Dave Kleikamp wrote:
On Thu, 2011-02-03 at 10:08 +1100, David Gibson wrote:
On Tue, Feb 01, 2011 at 12:48:44PM -0600, Dave Kleikamp wrote:
Since other OS's may be running on the other cores don't use tlbivax
[snip]
+#ifdef CONFIG_44x
+void __init early_init_mmu_44x(void)
+{
+ unsigned long root = of_get_flat_dt_root();
+ if (of_flat_dt_is_compatible(root, ibm,47x-AMP))
+ amp = 1;
+}
+#endif /* CONFIG_44x */
A test against a hardcoded compatible string seems a nasty way to do
this. Maybe we should define a new boolean property for the root
node.
I'm not crazy about this string, but I needed something in the device
tree to key off of. Freescale has something similar (i.e.
MPC8572DS-CAMP), so I chose to follow their example. I'd be happy to
replace it with a boolean property. Any objection to just using
amp?
Bit too short, I think. I'd suggest either spelling out
'asymmetric-multiprocessor' or 'cooperative-partition' (a more
accurate term, IMO).
I could be wrong, but I thought the A stands for Asynchronous, not
Asymmetric. I thought Asymmetric means that different types of tasks
run on the secondary processors, as on the Cell. Anyway, going with
'cooperative-partition' would avoid that confusion.
Shaggy
--
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Re: [PATCH V2 4/6] powerpc/44x: don't use tlbivax on AMP systems
On Wed, 2011-02-02 at 01:48 -0600, Kumar Gala wrote: On Feb 1, 2011, at 12:48 PM, Dave Kleikamp wrote: Since other OS's may be running on the other cores don't use tlbivax Are you guys building SMP kernel for use with AMP? Just wondering why you'd be using tlbivax at all. Yes, for instance, a 4-core chip could run two 2-way instances. Shaggy -- Dave Kleikamp IBM Linux Technology Center ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH V2 4/6] powerpc/44x: don't use tlbivax on AMP systems
On Thu, 2011-02-03 at 10:08 +1100, David Gibson wrote:
On Tue, Feb 01, 2011 at 12:48:44PM -0600, Dave Kleikamp wrote:
Since other OS's may be running on the other cores don't use tlbivax
[snip]
+#ifdef CONFIG_44x
+void __init early_init_mmu_44x(void)
+{
+ unsigned long root = of_get_flat_dt_root();
+ if (of_flat_dt_is_compatible(root, ibm,47x-AMP))
+ amp = 1;
+}
+#endif /* CONFIG_44x */
A test against a hardcoded compatible string seems a nasty way to do
this. Maybe we should define a new boolean property for the root
node.
I'm not crazy about this string, but I needed something in the device
tree to key off of. Freescale has something similar (i.e.
MPC8572DS-CAMP), so I chose to follow their example. I'd be happy to
replace it with a boolean property. Any objection to just using amp?
Thanks,
Shaggy
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Re: [PATCH V2 1/6] powerpc: Move udbg_early_init() after early_init_devtree()
On Thu, 2011-02-03 at 10:06 +1100, David Gibson wrote: On Tue, Feb 01, 2011 at 12:48:41PM -0600, Dave Kleikamp wrote: so that it can use information from the device tree. Hrm. On the other hand this means that the early_init_devtree() code can't benefit from hardcoded early debugging. Since you don't actually appear to use devtree information in udbg_early_init() in the latest series, I'd suggest dropping this patch. Patch 2 depends on early_init_devtree() being run. Until then, I don't know of a way to get at the bootargs. -- Dave Kleikamp IBM Linux Technology Center ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH V2 0/6] powerpc: AMP support for 47x
These patches add Asynchonous MultiProcessing support for the 47x chipset. This allows independent OS instances to run on separate cores. V2: 1. Replace ugly hack in boot wrapper with generic solution Dave Kleikamp (6): powerpc: Move udbg_early_init() after early_init_devtree() powerpc/44x: allow override to hard-coded uart address powerpc/47x: allow kernel to be loaded in higher physical memory powerpc/44x: don't use tlbivax on AMP systems powerpc/44x: boot wrapper: allow kernel to load into non-zero address powerpc/476: Create a dts files for two 476 AMP instances under ISS arch/powerpc/Kconfig |2 +- arch/powerpc/boot/Makefile|6 +- arch/powerpc/boot/dts/iss476-amp1.dts | 119 arch/powerpc/boot/dts/iss476-amp2.dts | 120 + arch/powerpc/boot/treeboot-iss4xx.c | 22 +- arch/powerpc/boot/wrapper |7 ++ arch/powerpc/configs/44x/iss476-smp_defconfig |6 +- arch/powerpc/include/asm/mmu.h|2 +- arch/powerpc/kernel/head_44x.S| 42 +++-- arch/powerpc/kernel/setup_32.c|6 +- arch/powerpc/kernel/udbg_16550.c | 17 +++- arch/powerpc/mm/44x_mmu.c | 13 ++- arch/powerpc/mm/tlb_nohash.c | 21 - 13 files changed, 359 insertions(+), 24 deletions(-) create mode 100644 arch/powerpc/boot/dts/iss476-amp1.dts create mode 100644 arch/powerpc/boot/dts/iss476-amp2.dts -- 1.7.3.4 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH V2 2/6] powerpc/44x: allow override to hard-coded uart address
Allow the early debug uart address to be overridden from the kernel
command line.
I would have preferred use the uart's virtual-reg property, but the device
tree hasn't been unflatted yet, and I don't know a reliable way to find it.
Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com
Cc: Benjamin Herrenschmidt b...@kernel.crashing.org
Cc: Josh Boyer jwbo...@linux.vnet.ibm.com
Cc: linuxppc-dev@lists.ozlabs.org
---
arch/powerpc/kernel/udbg_16550.c | 17 ++---
1 files changed, 14 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/kernel/udbg_16550.c b/arch/powerpc/kernel/udbg_16550.c
index b4b167b..d36021a 100644
--- a/arch/powerpc/kernel/udbg_16550.c
+++ b/arch/powerpc/kernel/udbg_16550.c
@@ -219,6 +219,19 @@ void udbg_init_pas_realmode(void)
#ifdef CONFIG_PPC_EARLY_DEBUG_44x
#include platforms/44x/44x.h
+static unsigned long udbg_44x_comport = PPC44x_EARLY_DEBUG_VIRTADDR;
+
+static int __init early_parse_comport(char *p)
+{
+ if (!p || !(*p))
+ return 0;
+
+ udbg_44x_comport = simple_strtoul(p, 0, 16);
+
+ return 0;
+}
+early_param(uart_addr, early_parse_comport);
+
static void udbg_44x_as1_flush(void)
{
if (udbg_comport) {
@@ -249,9 +262,7 @@ static int udbg_44x_as1_getc(void)
void __init udbg_init_44x_as1(void)
{
- udbg_comport =
- (struct NS16550 __iomem *)PPC44x_EARLY_DEBUG_VIRTADDR;
-
+ udbg_comport = (struct NS16550 __iomem *)udbg_44x_comport;
udbg_putc = udbg_44x_as1_putc;
udbg_flush = udbg_44x_as1_flush;
udbg_getc = udbg_44x_as1_getc;
--
1.7.3.4
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[PATCH V2 1/6] powerpc: Move udbg_early_init() after early_init_devtree()
so that it can use information from the device tree.
Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com
Cc: Benjamin Herrenschmidt b...@kernel.crashing.org
Cc: Josh Boyer jwbo...@linux.vnet.ibm.com
Cc: linuxppc-dev@lists.ozlabs.org
---
arch/powerpc/kernel/setup_32.c |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/kernel/setup_32.c b/arch/powerpc/kernel/setup_32.c
index 1d2fbc9..d1ca976 100644
--- a/arch/powerpc/kernel/setup_32.c
+++ b/arch/powerpc/kernel/setup_32.c
@@ -120,12 +120,12 @@ notrace void __init machine_init(unsigned long dt_ptr)
{
lockdep_init();
- /* Enable early debugging if any specified (see udbg.h) */
- udbg_early_init();
-
/* Do some early initialization based on the flat device tree */
early_init_devtree(__va(dt_ptr));
+ /* Enable early debugging if any specified (see udbg.h) */
+ udbg_early_init();
+
probe_machine();
setup_kdump_trampoline();
--
1.7.3.4
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[PATCH V2 3/6] powerpc/47x: allow kernel to be loaded in higher physical memory
Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com
Cc: Benjamin Herrenschmidt b...@kernel.crashing.org
Cc: Josh Boyer jwbo...@linux.vnet.ibm.com
Cc: linuxppc-dev@lists.ozlabs.org
---
arch/powerpc/Kconfig |2 +-
arch/powerpc/configs/44x/iss476-smp_defconfig |6 ++--
arch/powerpc/kernel/head_44x.S| 42 -
arch/powerpc/mm/44x_mmu.c | 13 ++--
4 files changed, 48 insertions(+), 15 deletions(-)
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 7d69e9b..fa41026 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -827,7 +827,7 @@ config LOWMEM_CAM_NUM
config RELOCATABLE
bool Build a relocatable kernel (EXPERIMENTAL)
- depends on EXPERIMENTAL ADVANCED_OPTIONS FLATMEM FSL_BOOKE
+ depends on EXPERIMENTAL ADVANCED_OPTIONS FLATMEM (FSL_BOOKE ||
PPC_47x)
help
This builds a kernel image that is capable of running at the
location the kernel is loaded at (some alignment restrictions may
diff --git a/arch/powerpc/configs/44x/iss476-smp_defconfig
b/arch/powerpc/configs/44x/iss476-smp_defconfig
index 92f863a..a6eb6ad 100644
--- a/arch/powerpc/configs/44x/iss476-smp_defconfig
+++ b/arch/powerpc/configs/44x/iss476-smp_defconfig
@@ -3,8 +3,8 @@ CONFIG_SMP=y
CONFIG_EXPERIMENTAL=y
CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
+CONFIG_SPARSE_IRQ=y
CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SYSFS_DEPRECATED_V2=y
CONFIG_BLK_DEV_INITRD=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_EXPERT=y
@@ -21,10 +21,11 @@ CONFIG_ISS4xx=y
CONFIG_HZ_100=y
CONFIG_MATH_EMULATION=y
CONFIG_IRQ_ALL_CPUS=y
-CONFIG_SPARSE_IRQ=y
CONFIG_CMDLINE_BOOL=y
CONFIG_CMDLINE=root=/dev/issblk0
# CONFIG_PCI is not set
+CONFIG_ADVANCED_OPTIONS=y
+CONFIG_RELOCATABLE=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
@@ -67,7 +68,6 @@ CONFIG_EXT3_FS=y
# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
CONFIG_EXT3_FS_POSIX_ACL=y
CONFIG_EXT3_FS_SECURITY=y
-CONFIG_INOTIFY=y
CONFIG_PROC_KCORE=y
CONFIG_TMPFS=y
CONFIG_CRAMFS=y
diff --git a/arch/powerpc/kernel/head_44x.S b/arch/powerpc/kernel/head_44x.S
index cbb3436..1da9b7e 100644
--- a/arch/powerpc/kernel/head_44x.S
+++ b/arch/powerpc/kernel/head_44x.S
@@ -93,6 +93,30 @@ _ENTRY(_start);
bl early_init
+#ifdef CONFIG_RELOCATABLE
+ /*
+* r25 will contain RPN/ERPN for the start address of memory
+*
+* Add the difference between KERNELBASE and PAGE_OFFSET to the
+* start of physical memory to get kernstart_addr.
+*/
+ lis r3,kernstart_addr@ha
+ la r3,kernstart_addr@l(r3)
+
+ lis r4,KERNELBASE@h
+ ori r4,r4,KERNELBASE@l
+ lis r5,PAGE_OFFSET@h
+ ori r5,r5,PAGE_OFFSET@l
+ subfr4,r5,r4
+
+ rlwinm r6,r25,0,28,31 /* ERPN */
+ rlwinm r7,r25,0,0,3/* RPN - assuming 256 MB page size */
+ add r7,r7,r4
+
+ stw r6,0(r3)
+ stw r7,4(r3)
+#endif
+
/*
* Decide what sort of machine this is and initialize the MMU.
*/
@@ -1001,9 +1025,6 @@ clear_utlb_entry:
lis r3,PAGE_OFFSET@h
ori r3,r3,PAGE_OFFSET@l
- /* Kernel is at the base of RAM */
- li r4, 0/* Load the kernel physical address */
-
/* Load the kernel PID = 0 */
li r0,0
mtspr SPRN_PID,r0
@@ -1013,9 +1034,8 @@ clear_utlb_entry:
clrrwi r3,r3,12/* Mask off the effective page number */
ori r3,r3,PPC47x_TLB0_VALID | PPC47x_TLB0_256M
- /* Word 1 */
- clrrwi r4,r4,12/* Mask off the real page number */
- /* ERPN is 0 for first 4GB page */
+ /* Word 1 - use r25. RPN is the same as the original entry */
+
/* Word 2 */
li r5,0
ori r5,r5,PPC47x_TLB2_S_RWX
@@ -1026,7 +1046,7 @@ clear_utlb_entry:
/* We write to way 0 and bolted 0 */
lis r0,0x8800
tlbwe r3,r0,0
- tlbwe r4,r0,1
+ tlbwe r25,r0,1
tlbwe r5,r0,2
/*
@@ -1124,7 +1144,13 @@ head_start_common:
lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */
mtspr SPRN_IVPR,r4
- addis r22,r22,KERNELBASE@h
+ /*
+* If the kernel was loaded at a non-zero 256 MB page, we need to
+* mask off the most significant 4 bits to get the relative address
+* from the start of physical memory
+*/
+ rlwinm r22,r22,0,4,31
+ addis r22,r22,PAGE_OFFSET@h
mtlrr22
isync
blr
diff --git a/arch/powerpc/mm/44x_mmu.c b/arch/powerpc/mm/44x_mmu.c
index 024acab..f60e006 100644
--- a/arch/powerpc/mm/44x_mmu.c
+++ b/arch/powerpc/mm/44x_mmu.c
@@ -186,10 +186,11 @@ void __init MMU_init_hw(void)
unsigned long __init mmu_mapin_ram(unsigned long top)
{
unsigned long addr;
+ unsigned long memstart
[PATCH V2 6/6] powerpc/476: Create a dts files for two 476 AMP instances under ISS
These are completely independent OS instances, each running on 2 cores.
Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com
Cc: Benjamin Herrenschmidt b...@kernel.crashing.org
Cc: Josh Boyer jwbo...@linux.vnet.ibm.com
Cc: linuxppc-dev@lists.ozlabs.org
---
arch/powerpc/boot/Makefile|6 ++-
arch/powerpc/boot/dts/iss476-amp1.dts | 119
arch/powerpc/boot/dts/iss476-amp2.dts | 120 +
arch/powerpc/boot/wrapper |7 ++
4 files changed, 251 insertions(+), 1 deletions(-)
create mode 100644 arch/powerpc/boot/dts/iss476-amp1.dts
create mode 100644 arch/powerpc/boot/dts/iss476-amp2.dts
diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile
index 8917816..99dbc39 100644
--- a/arch/powerpc/boot/Makefile
+++ b/arch/powerpc/boot/Makefile
@@ -45,6 +45,8 @@ $(obj)/cuboot-katmai.o: BOOTCFLAGS += -mcpu=405
$(obj)/cuboot-acadia.o: BOOTCFLAGS += -mcpu=405
$(obj)/treeboot-walnut.o: BOOTCFLAGS += -mcpu=405
$(obj)/treeboot-iss4xx.o: BOOTCFLAGS += -mcpu=405
+$(obj)/treeboot-iss476-amp1.o: BOOTCFLAGS += -mcpu=405
+$(obj)/treeboot-iss476-amp2.o: BOOTCFLAGS += -mcpu=405
$(obj)/virtex405-head.o: BOOTAFLAGS += -mcpu=405
@@ -208,7 +210,9 @@ image-$(CONFIG_KATMAI) +=
cuImage.katmai
image-$(CONFIG_WARP) += cuImage.warp
image-$(CONFIG_YOSEMITE) += cuImage.yosemite
image-$(CONFIG_ISS4xx) += treeImage.iss4xx \
- treeImage.iss4xx-mpic
+ treeImage.iss4xx-mpic \
+ treeImage.iss476-amp1 \
+ treeImage.iss476-amp2
# Board ports in arch/powerpc/platform/8xx/Kconfig
image-$(CONFIG_MPC86XADS) += cuImage.mpc866ads
diff --git a/arch/powerpc/boot/dts/iss476-amp1.dts
b/arch/powerpc/boot/dts/iss476-amp1.dts
new file mode 100644
index 000..b503523
--- /dev/null
+++ b/arch/powerpc/boot/dts/iss476-amp1.dts
@@ -0,0 +1,119 @@
+/*
+ * Device Tree Source for IBM Embedded PPC 476 Platform
+ *
+ * Copyright 2010 Torez Smith, IBM Corporation.
+ *
+ * Based on earlier code:
+ * Copyright (c) 2006, 2007 IBM Corp.
+ * Josh Boyer jwbo...@linux.vnet.ibm.com, David Gibson d...@au1.ibm.com
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed as is without
+ * any warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+
+/memreserve/ 0x01f0 0x0010;
+
+/ {
+ #address-cells = 2;
+ #size-cells = 1;
+ model = ibm,iss-4xx;
+ compatible = ibm,iss-4xx, ibm,47x-AMP;
+ dcr-parent = {/cpus/cpu@0};
+
+ aliases {
+ serial0 = UART0;
+ };
+
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ cpu@0 {
+ device_type = cpu;
+ model = PowerPC,4xx; // real CPU changed in sim
+ reg = 0;
+ clock-frequency = 1; // 100Mhz :-)
+ timebase-frequency = 1;
+ i-cache-line-size = 32;
+ d-cache-line-size = 32;
+ i-cache-size = 32768;
+ d-cache-size = 32768;
+ dcr-controller;
+ dcr-access-method = native;
+ status = ok;
+ };
+ cpu@1 {
+ device_type = cpu;
+ model = PowerPC,4xx; // real CPU changed in sim
+ reg = 1;
+ clock-frequency = 1; // 100Mhz :-)
+ timebase-frequency = 1;
+ i-cache-line-size = 32;
+ d-cache-line-size = 32;
+ i-cache-size = 32768;
+ d-cache-size = 32768;
+ dcr-controller;
+ dcr-access-method = native;
+ status = disabled;
+ enable-method = spin-table;
+ cpu-release-addr = 0 0x01f00100;
+ };
+ };
+
+ memory {
+ device_type = memory;
+ reg = 0x 0x 0x0200;
+
+ };
+
+ MPIC: interrupt-controller {
+ compatible = chrp,open-pic;
+ interrupt-controller;
+ dcr-reg = 0xffc0 0x0003;
+ #address-cells = 0;
+ #size-cells = 0;
+ #interrupt-cells = 2;
+
+ };
+
+ plb {
+ compatible = ibm,plb-4xx, ibm,plb4; /* Could be PLB6,
doesn't matter */
+ #address-cells = 2;
+ #size-cells = 1;
+ ranges;
+ clock-frequency = 0; // Filled in by zImage
[PATCH V2 5/6] powerpc/44x: boot wrapper: allow kernel to load into non-zero address
For AMP, different kernel instances load into separate memory regions.
Read the start of memory from the device tree and limit the memory to what's
specified in the device tree.
Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com
Cc: Benjamin Herrenschmidt b...@kernel.crashing.org
Cc: Josh Boyer jwbo...@linux.vnet.ibm.com
Cc: linuxppc-dev@lists.ozlabs.org
---
arch/powerpc/boot/treeboot-iss4xx.c | 22 +-
1 files changed, 21 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/boot/treeboot-iss4xx.c
b/arch/powerpc/boot/treeboot-iss4xx.c
index fcc4495..868c8b4 100644
--- a/arch/powerpc/boot/treeboot-iss4xx.c
+++ b/arch/powerpc/boot/treeboot-iss4xx.c
@@ -34,9 +34,28 @@
BSS_STACK(4096);
+static ibm4xx_memstart;
+
static void iss_4xx_fixups(void)
{
- ibm4xx_sdram_fixup_memsize();
+ void *memory;
+ u32 reg[3];
+
+ memory = finddevice(/memory);
+ if (!memory)
+ fatal(Can't find memory node\n);
+ getprop(memory, reg, reg, sizeof(reg));
+ if (reg[1] || reg[2])
+ /* If the device tree specifies the memory range, use it */
+ ibm4xx_memstart = reg[1];
+ else
+ /* othersize, read it from the SDRAM controller */
+ ibm4xx_sdram_fixup_memsize();
+}
+
+static void *iss_4xx_vmlinux_alloc(unsigned long size)
+{
+ return ibm4xx_memstart;
}
#define SPRN_PIR 0x11E /* Processor Indentification Register */
@@ -48,6 +67,7 @@ void platform_init(void)
simple_alloc_init(_end, avail_ram, 128, 64);
platform_ops.fixups = iss_4xx_fixups;
+ platform_ops.vmlinux_alloc = iss_4xx_vmlinux_alloc;
platform_ops.exit = ibm44x_dbcr_reset;
pir_reg = mfspr(SPRN_PIR);
fdt_set_boot_cpuid_phys(_dtb_start, pir_reg);
--
1.7.3.4
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[PATCH V2 4/6] powerpc/44x: don't use tlbivax on AMP systems
Since other OS's may be running on the other cores don't use tlbivax
Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com
Cc: Benjamin Herrenschmidt b...@kernel.crashing.org
Cc: Josh Boyer jwbo...@linux.vnet.ibm.com
Cc: linuxppc-dev@lists.ozlabs.org
---
arch/powerpc/include/asm/mmu.h |2 +-
arch/powerpc/kernel/setup_32.c |2 ++
arch/powerpc/mm/tlb_nohash.c | 21 -
3 files changed, 23 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h
index bb40a06..f3a7c65 100644
--- a/arch/powerpc/include/asm/mmu.h
+++ b/arch/powerpc/include/asm/mmu.h
@@ -80,7 +80,7 @@ static inline int mmu_has_feature(unsigned long feature)
extern unsigned int __start___mmu_ftr_fixup, __stop___mmu_ftr_fixup;
-/* MMU initialization (64-bit only fo now) */
+/* MMU initialization */
extern void early_init_mmu(void);
extern void early_init_mmu_secondary(void);
diff --git a/arch/powerpc/kernel/setup_32.c b/arch/powerpc/kernel/setup_32.c
index d1ca976..e50ead7 100644
--- a/arch/powerpc/kernel/setup_32.c
+++ b/arch/powerpc/kernel/setup_32.c
@@ -126,6 +126,8 @@ notrace void __init machine_init(unsigned long dt_ptr)
/* Enable early debugging if any specified (see udbg.h) */
udbg_early_init();
+ early_init_mmu();
+
probe_machine();
setup_kdump_trampoline();
diff --git a/arch/powerpc/mm/tlb_nohash.c b/arch/powerpc/mm/tlb_nohash.c
index 2a030d8..b33c5e6 100644
--- a/arch/powerpc/mm/tlb_nohash.c
+++ b/arch/powerpc/mm/tlb_nohash.c
@@ -35,6 +35,7 @@
#include linux/preempt.h
#include linux/spinlock.h
#include linux/memblock.h
+#include linux/of_fdt.h
#include asm/tlbflush.h
#include asm/tlb.h
@@ -153,6 +154,17 @@ EXPORT_SYMBOL(local_flush_tlb_page);
*/
#ifdef CONFIG_SMP
+static int amp;
+
+#ifdef CONFIG_44x
+void __init early_init_mmu_44x(void)
+{
+ unsigned long root = of_get_flat_dt_root();
+ if (of_flat_dt_is_compatible(root, ibm,47x-AMP))
+ amp = 1;
+}
+#endif /* CONFIG_44x */
+
static DEFINE_RAW_SPINLOCK(tlbivax_lock);
static int mm_is_core_local(struct mm_struct *mm)
@@ -232,7 +244,7 @@ void __flush_tlb_page(struct mm_struct *mm, unsigned long
vmaddr,
cpu_mask = mm_cpumask(mm);
if (!mm_is_core_local(mm)) {
/* If broadcast tlbivax is supported, use it */
- if (mmu_has_feature(MMU_FTR_USE_TLBIVAX_BCAST)) {
+ if (!amp mmu_has_feature(MMU_FTR_USE_TLBIVAX_BCAST)) {
int lock = mmu_has_feature(MMU_FTR_LOCK_BCAST_INVAL);
if (lock)
raw_spin_lock(tlbivax_lock);
@@ -587,4 +599,11 @@ void setup_initial_memory_limit(phys_addr_t
first_memblock_base,
/* Finally limit subsequent allocations */
memblock_set_current_limit(first_memblock_base + ppc64_rma_size);
}
+#else /* ! CONFIG_PPC64 */
+void __init early_init_mmu(void)
+{
+#if defined(CONFIG_SMP) defined(CONFIG_44x)
+ early_init_mmu_44x();
+#endif
+}
#endif /* CONFIG_PPC64 */
--
1.7.3.4
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Re: [PATCH V2 5/6] powerpc/44x: boot wrapper: allow kernel to load into non-zero address
On Tue, 2011-02-01 at 13:13 -0600, Scott Wood wrote:
On Tue, 1 Feb 2011 12:48:45 -0600
Dave Kleikamp sha...@linux.vnet.ibm.com wrote:
For AMP, different kernel instances load into separate memory regions.
Read the start of memory from the device tree and limit the memory to what's
specified in the device tree.
Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com
Cc: Benjamin Herrenschmidt b...@kernel.crashing.org
Cc: Josh Boyer jwbo...@linux.vnet.ibm.com
Cc: linuxppc-dev@lists.ozlabs.org
---
arch/powerpc/boot/treeboot-iss4xx.c | 22 +-
1 files changed, 21 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/boot/treeboot-iss4xx.c
b/arch/powerpc/boot/treeboot-iss4xx.c
index fcc4495..868c8b4 100644
--- a/arch/powerpc/boot/treeboot-iss4xx.c
+++ b/arch/powerpc/boot/treeboot-iss4xx.c
@@ -34,9 +34,28 @@
BSS_STACK(4096);
+static ibm4xx_memstart;
type?
Oops, I'll fix this
+static void *iss_4xx_vmlinux_alloc(unsigned long size)
+{
+ return ibm4xx_memstart;
}
Doesn't this generate a warning for implicitly casting int to void *?
Probably. I could have missed it. I'll fix this too.
-Scott
Thanks,
Shaggy
--
Dave Kleikamp
IBM Linux Technology Center
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[PATCH 2/2] powerpc/476: Workaround for PLB6 hang
The 476FP core may hang if an instruction fetch happens during an msync following a tlbsync. This workaround makes sure that enough instruction cache lines are pre-fetched before executing the msync. (sync and msync are the same to the compiler.) Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com --- arch/powerpc/mm/tlb_nohash_low.S | 35 +++ 1 files changed, 35 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/mm/tlb_nohash_low.S b/arch/powerpc/mm/tlb_nohash_low.S index af405ee..7c63c0e 100644 --- a/arch/powerpc/mm/tlb_nohash_low.S +++ b/arch/powerpc/mm/tlb_nohash_low.S @@ -189,6 +189,13 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_47x) blr #ifdef CONFIG_PPC_47x + +/* + * 47x variant of icbt + */ +# define ICBT(CT,RA,RB)\ + .long 0x7c2c | ((CT) 21) | ((RA) 16) | ((RB) 11) + /* * _tlbivax_bcast is only on 47x. We don't bother doing a runtime * check though, it will blow up soon enough if we mistakenly try @@ -206,7 +213,35 @@ _GLOBAL(_tlbivax_bcast) isync eieio tlbsync +BEGIN_FTR_SECTION + b 1f +END_FTR_SECTION_IFSET(CPU_FTR_476_DD2) + sync + wrtee r10 + blr +/* + * DD2 HW could hang if in instruction fetch happens before msync completes. + * Touch enough instruction cache lines to ensure cache hits + */ +1: mflrr9 + bl 2f +2: mflrr6 + li r7,32 + ICBT(0,r6,r7) /* touch next cache line */ + add r6,r6,r7 + ICBT(0,r6,r7) /* touch next cache line */ + add r6,r6,r7 + ICBT(0,r6,r7) /* touch next cache line */ sync + nop + nop + nop + nop + nop + nop + nop + nop + mtlrr9 wrtee r10 blr #endif /* CONFIG_PPC_47x */ -- 1.7.3.4 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 0/2] Workaround for PowerPC 476FP hardware bug
These patches add a workaround to avoid a hang on the DD2 level of the 476FP core. This hardware bug will be fixed in future products, but this particular core will used in production. Dave Kleikamp (2): powerpc/476: define specific cpu table entry DD2 core powerpc/476: Workaround for PLB6 hang arch/powerpc/include/asm/cputable.h |3 ++- arch/powerpc/kernel/cputable.c | 22 ++ arch/powerpc/mm/tlb_nohash_low.S| 35 +++ 3 files changed, 55 insertions(+), 5 deletions(-) -- 1.7.3.4 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 1/2] powerpc/476: define specific cpu table entry DD2 core
The DD2 core still has some unstability. Define CPU_FTR_476_DD2 to
enable workarounds in later patches.
This is based on an earlier, unreleased patch for DD1 by Ben Herrenschmidt.
Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/cputable.h |3 ++-
arch/powerpc/kernel/cputable.c | 22 ++
2 files changed, 20 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/include/asm/cputable.h
b/arch/powerpc/include/asm/cputable.h
index f0a211d..be3cdf9 100644
--- a/arch/powerpc/include/asm/cputable.h
+++ b/arch/powerpc/include/asm/cputable.h
@@ -154,6 +154,7 @@ extern const char *powerpc_base_platform;
#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x2000)
#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x4000)
#define CPU_FTR_NO_DPM ASM_CONST(0x8000)
+#define CPU_FTR_476_DD2ASM_CONST(0x0001)
#define CPU_FTR_NEED_COHERENT ASM_CONST(0x0002)
#define CPU_FTR_NO_BTICASM_CONST(0x0004)
#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0010)
@@ -465,7 +466,7 @@ enum {
CPU_FTRS_44X | CPU_FTRS_440x6 |
#endif
#ifdef CONFIG_PPC_47x
- CPU_FTRS_47X |
+ CPU_FTRS_47X | CPU_FTR_476_DD2 |
#endif
#ifdef CONFIG_E200
CPU_FTRS_E200 |
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index 8d74a24..436e1e5 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -1811,11 +1811,11 @@ static struct cpu_spec __initdata cpu_specs[] = {
.machine_check = machine_check_440A,
.platform = ppc440,
},
- { /* 476 core */
- .pvr_mask = 0x,
- .pvr_value = 0x11a5,
+ { /* 476 DD2 core */
+ .pvr_mask = 0x,
+ .pvr_value = 0x11a52080,
.cpu_name = 476,
- .cpu_features = CPU_FTRS_47X,
+ .cpu_features = CPU_FTRS_47X | CPU_FTR_476_DD2,
.cpu_user_features = COMMON_USER_BOOKE |
PPC_FEATURE_HAS_FPU,
.mmu_features = MMU_FTR_TYPE_47x |
@@ -1839,6 +1839,20 @@ static struct cpu_spec __initdata cpu_specs[] = {
.machine_check = machine_check_47x,
.platform = ppc470,
},
+ { /* 476 others */
+ .pvr_mask = 0x,
+ .pvr_value = 0x11a5,
+ .cpu_name = 476,
+ .cpu_features = CPU_FTRS_47X,
+ .cpu_user_features = COMMON_USER_BOOKE |
+ PPC_FEATURE_HAS_FPU,
+ .mmu_features = MMU_FTR_TYPE_47x |
+ MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_LOCK_BCAST_INVAL,
+ .icache_bsize = 32,
+ .dcache_bsize = 128,
+ .machine_check = machine_check_47x,
+ .platform = ppc470,
+ },
{ /* default match */
.pvr_mask = 0x,
.pvr_value = 0x,
--
1.7.3.4
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[PATCH 2/5] powerpc/44x: allow override to hard-coded uart address
Allow the early debug uart address to be overridden from the kernel
command line.
I would have preferred use the uart's virtual-reg property, but the device
tree hasn't been unflatted yet, and I don't know a reliable way to find it.
Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com
---
arch/powerpc/kernel/udbg_16550.c | 17 ++---
1 files changed, 14 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/kernel/udbg_16550.c b/arch/powerpc/kernel/udbg_16550.c
index b4b167b..d36021a 100644
--- a/arch/powerpc/kernel/udbg_16550.c
+++ b/arch/powerpc/kernel/udbg_16550.c
@@ -219,6 +219,19 @@ void udbg_init_pas_realmode(void)
#ifdef CONFIG_PPC_EARLY_DEBUG_44x
#include platforms/44x/44x.h
+static unsigned long udbg_44x_comport = PPC44x_EARLY_DEBUG_VIRTADDR;
+
+static int __init early_parse_comport(char *p)
+{
+ if (!p || !(*p))
+ return 0;
+
+ udbg_44x_comport = simple_strtoul(p, 0, 16);
+
+ return 0;
+}
+early_param(uart_addr, early_parse_comport);
+
static void udbg_44x_as1_flush(void)
{
if (udbg_comport) {
@@ -249,9 +262,7 @@ static int udbg_44x_as1_getc(void)
void __init udbg_init_44x_as1(void)
{
- udbg_comport =
- (struct NS16550 __iomem *)PPC44x_EARLY_DEBUG_VIRTADDR;
-
+ udbg_comport = (struct NS16550 __iomem *)udbg_44x_comport;
udbg_putc = udbg_44x_as1_putc;
udbg_flush = udbg_44x_as1_flush;
udbg_getc = udbg_44x_as1_getc;
--
1.7.3.4
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[PATCH 0/5] powerpc: AMP support for 47x
These patches add Asynchonous MultiProcessing support for the 47x chipset. This allows independent OS instances to run on separate cores. Dave Kleikamp (5): powerpc: Move udbg_early_init() after early_init_devtree() powerpc/44x: allow override to hard-coded uart address powerpc/47x: allow kernel to be loaded in higher physical memory powerpc/44x: don't use tlbivax on AMP systems powerpc/476: Create a dts files for two 476 AMP instances under ISS arch/powerpc/Kconfig |2 +- arch/powerpc/boot/Makefile|9 ++- arch/powerpc/boot/dts/iss476-amp1.dts | 119 arch/powerpc/boot/dts/iss476-amp2.dts | 123 + arch/powerpc/boot/treeboot-iss4xx-hi.c| 65 + arch/powerpc/boot/wrapper |7 ++ arch/powerpc/configs/44x/iss476-smp_defconfig |6 +- arch/powerpc/include/asm/mmu.h|2 +- arch/powerpc/kernel/head_44x.S| 42 +++-- arch/powerpc/kernel/setup_32.c|6 +- arch/powerpc/kernel/udbg_16550.c | 17 +++- arch/powerpc/mm/44x_mmu.c | 13 ++- arch/powerpc/mm/tlb_nohash.c | 21 - 13 files changed, 408 insertions(+), 24 deletions(-) create mode 100644 arch/powerpc/boot/dts/iss476-amp1.dts create mode 100644 arch/powerpc/boot/dts/iss476-amp2.dts create mode 100644 arch/powerpc/boot/treeboot-iss4xx-hi.c -- 1.7.3.4 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 5/5] powerpc/476: Create a dts files for two 476 AMP instances under ISS
These are completely independent OS instances, each running on 2 cores.
Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com
---
arch/powerpc/boot/Makefile |9 ++-
arch/powerpc/boot/dts/iss476-amp1.dts | 119 ++
arch/powerpc/boot/dts/iss476-amp2.dts | 123
arch/powerpc/boot/treeboot-iss4xx-hi.c | 65 +
arch/powerpc/boot/wrapper |7 ++
5 files changed, 321 insertions(+), 2 deletions(-)
create mode 100644 arch/powerpc/boot/dts/iss476-amp1.dts
create mode 100644 arch/powerpc/boot/dts/iss476-amp2.dts
create mode 100644 arch/powerpc/boot/treeboot-iss4xx-hi.c
diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile
index 8917816..417502a 100644
--- a/arch/powerpc/boot/Makefile
+++ b/arch/powerpc/boot/Makefile
@@ -45,6 +45,8 @@ $(obj)/cuboot-katmai.o: BOOTCFLAGS += -mcpu=405
$(obj)/cuboot-acadia.o: BOOTCFLAGS += -mcpu=405
$(obj)/treeboot-walnut.o: BOOTCFLAGS += -mcpu=405
$(obj)/treeboot-iss4xx.o: BOOTCFLAGS += -mcpu=405
+$(obj)/treeboot-iss476-amp1.o: BOOTCFLAGS += -mcpu=405
+$(obj)/treeboot-iss476-amp2.o: BOOTCFLAGS += -mcpu=405
$(obj)/virtex405-head.o: BOOTAFLAGS += -mcpu=405
@@ -78,7 +80,8 @@ src-plat := of.c cuboot-52xx.c cuboot-824x.c cuboot-83xx.c
cuboot-85xx.c holly.c
cuboot-warp.c cuboot-85xx-cpm2.c cuboot-yosemite.c simpleboot.c
\
virtex405-head.S virtex.c redboot-83xx.c cuboot-sam440ep.c \
cuboot-acadia.c cuboot-amigaone.c cuboot-kilauea.c \
- gamecube-head.S gamecube.c wii-head.S wii.c treeboot-iss4xx.c
+ gamecube-head.S gamecube.c wii-head.S wii.c treeboot-iss4xx.c \
+ treeboot-iss4xx-hi.c
src-boot := $(src-wlib) $(src-plat) empty.c
src-boot := $(addprefix $(obj)/, $(src-boot))
@@ -208,7 +211,9 @@ image-$(CONFIG_KATMAI) +=
cuImage.katmai
image-$(CONFIG_WARP) += cuImage.warp
image-$(CONFIG_YOSEMITE) += cuImage.yosemite
image-$(CONFIG_ISS4xx) += treeImage.iss4xx \
- treeImage.iss4xx-mpic
+ treeImage.iss4xx-mpic \
+ treeImage.iss476-amp1 \
+ treeImage.iss476-amp2
# Board ports in arch/powerpc/platform/8xx/Kconfig
image-$(CONFIG_MPC86XADS) += cuImage.mpc866ads
diff --git a/arch/powerpc/boot/dts/iss476-amp1.dts
b/arch/powerpc/boot/dts/iss476-amp1.dts
new file mode 100644
index 000..7de3485
--- /dev/null
+++ b/arch/powerpc/boot/dts/iss476-amp1.dts
@@ -0,0 +1,119 @@
+/*
+ * Device Tree Source for IBM Embedded PPC 476 Platform
+ *
+ * Copyright 2010 Torez Smith, IBM Corporation.
+ *
+ * Based on earlier code:
+ * Copyright (c) 2006, 2007 IBM Corp.
+ * Josh Boyer jwbo...@linux.vnet.ibm.com, David Gibson d...@au1.ibm.com
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed as is without
+ * any warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+
+/memreserve/ 0x01f0 0x0010;
+
+/ {
+ #address-cells = 2;
+ #size-cells = 1;
+ model = ibm,iss-4xx;
+ compatible = ibm,iss-4xx, ibm,47x-AMP;
+ dcr-parent = {/cpus/cpu@0};
+
+ aliases {
+ serial0 = UART0;
+ };
+
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ cpu@0 {
+ device_type = cpu;
+ model = PowerPC,4xx; // real CPU changed in sim
+ reg = 0;
+ clock-frequency = 1; // 100Mhz :-)
+ timebase-frequency = 1;
+ i-cache-line-size = 32;
+ d-cache-line-size = 32;
+ i-cache-size = 32768;
+ d-cache-size = 32768;
+ dcr-controller;
+ dcr-access-method = native;
+ status = ok;
+ };
+ cpu@1 {
+ device_type = cpu;
+ model = PowerPC,4xx; // real CPU changed in sim
+ reg = 1;
+ clock-frequency = 1; // 100Mhz :-)
+ timebase-frequency = 1;
+ i-cache-line-size = 32;
+ d-cache-line-size = 32;
+ i-cache-size = 32768;
+ d-cache-size = 32768;
+ dcr-controller;
+ dcr-access-method = native;
+ status = disabled;
+ enable-method = spin-table;
+ cpu-release-addr = 0 0x01f00100;
+ };
+ };
+
+ memory {
+ device_type = memory
[PATCH 1/5] powerpc: Move udbg_early_init() after early_init_devtree()
so that it can use information from the device tree.
Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com
---
arch/powerpc/kernel/setup_32.c |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/kernel/setup_32.c b/arch/powerpc/kernel/setup_32.c
index 1d2fbc9..d1ca976 100644
--- a/arch/powerpc/kernel/setup_32.c
+++ b/arch/powerpc/kernel/setup_32.c
@@ -120,12 +120,12 @@ notrace void __init machine_init(unsigned long dt_ptr)
{
lockdep_init();
- /* Enable early debugging if any specified (see udbg.h) */
- udbg_early_init();
-
/* Do some early initialization based on the flat device tree */
early_init_devtree(__va(dt_ptr));
+ /* Enable early debugging if any specified (see udbg.h) */
+ udbg_early_init();
+
probe_machine();
setup_kdump_trampoline();
--
1.7.3.4
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[PATCH 4/5] powerpc/44x: don't use tlbivax on AMP systems
Since other OS's may be running on the other cores don't use tlbivax
Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/mmu.h |2 +-
arch/powerpc/kernel/setup_32.c |2 ++
arch/powerpc/mm/tlb_nohash.c | 21 -
3 files changed, 23 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h
index bb40a06..f3a7c65 100644
--- a/arch/powerpc/include/asm/mmu.h
+++ b/arch/powerpc/include/asm/mmu.h
@@ -80,7 +80,7 @@ static inline int mmu_has_feature(unsigned long feature)
extern unsigned int __start___mmu_ftr_fixup, __stop___mmu_ftr_fixup;
-/* MMU initialization (64-bit only fo now) */
+/* MMU initialization */
extern void early_init_mmu(void);
extern void early_init_mmu_secondary(void);
diff --git a/arch/powerpc/kernel/setup_32.c b/arch/powerpc/kernel/setup_32.c
index d1ca976..e50ead7 100644
--- a/arch/powerpc/kernel/setup_32.c
+++ b/arch/powerpc/kernel/setup_32.c
@@ -126,6 +126,8 @@ notrace void __init machine_init(unsigned long dt_ptr)
/* Enable early debugging if any specified (see udbg.h) */
udbg_early_init();
+ early_init_mmu();
+
probe_machine();
setup_kdump_trampoline();
diff --git a/arch/powerpc/mm/tlb_nohash.c b/arch/powerpc/mm/tlb_nohash.c
index 2a030d8..b33c5e6 100644
--- a/arch/powerpc/mm/tlb_nohash.c
+++ b/arch/powerpc/mm/tlb_nohash.c
@@ -35,6 +35,7 @@
#include linux/preempt.h
#include linux/spinlock.h
#include linux/memblock.h
+#include linux/of_fdt.h
#include asm/tlbflush.h
#include asm/tlb.h
@@ -153,6 +154,17 @@ EXPORT_SYMBOL(local_flush_tlb_page);
*/
#ifdef CONFIG_SMP
+static int amp;
+
+#ifdef CONFIG_44x
+void __init early_init_mmu_44x(void)
+{
+ unsigned long root = of_get_flat_dt_root();
+ if (of_flat_dt_is_compatible(root, ibm,47x-AMP))
+ amp = 1;
+}
+#endif /* CONFIG_44x */
+
static DEFINE_RAW_SPINLOCK(tlbivax_lock);
static int mm_is_core_local(struct mm_struct *mm)
@@ -232,7 +244,7 @@ void __flush_tlb_page(struct mm_struct *mm, unsigned long
vmaddr,
cpu_mask = mm_cpumask(mm);
if (!mm_is_core_local(mm)) {
/* If broadcast tlbivax is supported, use it */
- if (mmu_has_feature(MMU_FTR_USE_TLBIVAX_BCAST)) {
+ if (!amp mmu_has_feature(MMU_FTR_USE_TLBIVAX_BCAST)) {
int lock = mmu_has_feature(MMU_FTR_LOCK_BCAST_INVAL);
if (lock)
raw_spin_lock(tlbivax_lock);
@@ -587,4 +599,11 @@ void setup_initial_memory_limit(phys_addr_t
first_memblock_base,
/* Finally limit subsequent allocations */
memblock_set_current_limit(first_memblock_base + ppc64_rma_size);
}
+#else /* ! CONFIG_PPC64 */
+void __init early_init_mmu(void)
+{
+#if defined(CONFIG_SMP) defined(CONFIG_44x)
+ early_init_mmu_44x();
+#endif
+}
#endif /* CONFIG_PPC64 */
--
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[PATCH 3/5] powerpc/47x: allow kernel to be loaded in higher physical memory
Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com
---
arch/powerpc/Kconfig |2 +-
arch/powerpc/configs/44x/iss476-smp_defconfig |6 ++--
arch/powerpc/kernel/head_44x.S| 42 -
arch/powerpc/mm/44x_mmu.c | 13 ++--
4 files changed, 48 insertions(+), 15 deletions(-)
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 7d69e9b..fa41026 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -827,7 +827,7 @@ config LOWMEM_CAM_NUM
config RELOCATABLE
bool Build a relocatable kernel (EXPERIMENTAL)
- depends on EXPERIMENTAL ADVANCED_OPTIONS FLATMEM FSL_BOOKE
+ depends on EXPERIMENTAL ADVANCED_OPTIONS FLATMEM (FSL_BOOKE ||
PPC_47x)
help
This builds a kernel image that is capable of running at the
location the kernel is loaded at (some alignment restrictions may
diff --git a/arch/powerpc/configs/44x/iss476-smp_defconfig
b/arch/powerpc/configs/44x/iss476-smp_defconfig
index 92f863a..a6eb6ad 100644
--- a/arch/powerpc/configs/44x/iss476-smp_defconfig
+++ b/arch/powerpc/configs/44x/iss476-smp_defconfig
@@ -3,8 +3,8 @@ CONFIG_SMP=y
CONFIG_EXPERIMENTAL=y
CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
+CONFIG_SPARSE_IRQ=y
CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SYSFS_DEPRECATED_V2=y
CONFIG_BLK_DEV_INITRD=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_EXPERT=y
@@ -21,10 +21,11 @@ CONFIG_ISS4xx=y
CONFIG_HZ_100=y
CONFIG_MATH_EMULATION=y
CONFIG_IRQ_ALL_CPUS=y
-CONFIG_SPARSE_IRQ=y
CONFIG_CMDLINE_BOOL=y
CONFIG_CMDLINE=root=/dev/issblk0
# CONFIG_PCI is not set
+CONFIG_ADVANCED_OPTIONS=y
+CONFIG_RELOCATABLE=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
@@ -67,7 +68,6 @@ CONFIG_EXT3_FS=y
# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
CONFIG_EXT3_FS_POSIX_ACL=y
CONFIG_EXT3_FS_SECURITY=y
-CONFIG_INOTIFY=y
CONFIG_PROC_KCORE=y
CONFIG_TMPFS=y
CONFIG_CRAMFS=y
diff --git a/arch/powerpc/kernel/head_44x.S b/arch/powerpc/kernel/head_44x.S
index cbb3436..1da9b7e 100644
--- a/arch/powerpc/kernel/head_44x.S
+++ b/arch/powerpc/kernel/head_44x.S
@@ -93,6 +93,30 @@ _ENTRY(_start);
bl early_init
+#ifdef CONFIG_RELOCATABLE
+ /*
+* r25 will contain RPN/ERPN for the start address of memory
+*
+* Add the difference between KERNELBASE and PAGE_OFFSET to the
+* start of physical memory to get kernstart_addr.
+*/
+ lis r3,kernstart_addr@ha
+ la r3,kernstart_addr@l(r3)
+
+ lis r4,KERNELBASE@h
+ ori r4,r4,KERNELBASE@l
+ lis r5,PAGE_OFFSET@h
+ ori r5,r5,PAGE_OFFSET@l
+ subfr4,r5,r4
+
+ rlwinm r6,r25,0,28,31 /* ERPN */
+ rlwinm r7,r25,0,0,3/* RPN - assuming 256 MB page size */
+ add r7,r7,r4
+
+ stw r6,0(r3)
+ stw r7,4(r3)
+#endif
+
/*
* Decide what sort of machine this is and initialize the MMU.
*/
@@ -1001,9 +1025,6 @@ clear_utlb_entry:
lis r3,PAGE_OFFSET@h
ori r3,r3,PAGE_OFFSET@l
- /* Kernel is at the base of RAM */
- li r4, 0/* Load the kernel physical address */
-
/* Load the kernel PID = 0 */
li r0,0
mtspr SPRN_PID,r0
@@ -1013,9 +1034,8 @@ clear_utlb_entry:
clrrwi r3,r3,12/* Mask off the effective page number */
ori r3,r3,PPC47x_TLB0_VALID | PPC47x_TLB0_256M
- /* Word 1 */
- clrrwi r4,r4,12/* Mask off the real page number */
- /* ERPN is 0 for first 4GB page */
+ /* Word 1 - use r25. RPN is the same as the original entry */
+
/* Word 2 */
li r5,0
ori r5,r5,PPC47x_TLB2_S_RWX
@@ -1026,7 +1046,7 @@ clear_utlb_entry:
/* We write to way 0 and bolted 0 */
lis r0,0x8800
tlbwe r3,r0,0
- tlbwe r4,r0,1
+ tlbwe r25,r0,1
tlbwe r5,r0,2
/*
@@ -1124,7 +1144,13 @@ head_start_common:
lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */
mtspr SPRN_IVPR,r4
- addis r22,r22,KERNELBASE@h
+ /*
+* If the kernel was loaded at a non-zero 256 MB page, we need to
+* mask off the most significant 4 bits to get the relative address
+* from the start of physical memory
+*/
+ rlwinm r22,r22,0,4,31
+ addis r22,r22,PAGE_OFFSET@h
mtlrr22
isync
blr
diff --git a/arch/powerpc/mm/44x_mmu.c b/arch/powerpc/mm/44x_mmu.c
index 024acab..f60e006 100644
--- a/arch/powerpc/mm/44x_mmu.c
+++ b/arch/powerpc/mm/44x_mmu.c
@@ -186,10 +186,11 @@ void __init MMU_init_hw(void)
unsigned long __init mmu_mapin_ram(unsigned long top)
{
unsigned long addr;
+ unsigned long memstart = memstart_addr ~(PPC_PIN_SIZE - 1);
/* Pin in enough TLBs to cover any lowmem not covered by the
* initial 256M
Re: Run 'usermode-agent' cause kernel panic on Powerpc
On Tue, 2010-12-07 at 14:48 +0800, xufeng zhang wrote:
Hi Dave,
I have a question with the below patch you made before:
powerpc/booke: Add support for advanced debug registers
From: Dave Kleikamp sha...@linux.vnet.ibm.com
Based on patches originally written by Torez Smith.
-
I meet a kernel panic problem while running 'usermode-agent' on PowerPC
Oops: Exception in kernel mode, sig: 5 [#1]
PREEMPT LTT NESTING LEVEL : 0
MPC8536 DS
last sysfs file:
/sys/devices/f300.soc/f3003100.i2c/i2c-1/i2c-dev/i2c-1/dev
Modules linked in:
NIP: c00081a0 LR: c03a9560 CTR: c003547c
REGS: ef11bf10 TRAP: 2002 Not tainted (2.6.34.6-WR4.0.0.0_standard)
MSR: 00021000 ME,CE CR: 44000624 XER:
TASK = efc1de00[752] 'usermode-agent' THREAD: ef63e000
GPR00: cc00cc00 ef63fe60 efc1de00 efc1de00 efc1f700 c04c8000 00258560
GPR08: ffda8a00 4000 1fda c050 49eaebbd 1008b654 3ff8a900
GPR16: eed84c40 c03b4570 c04ee4d0 c04ca870 ef63e03c
GPR24: c04f7ee8 c04ee4c0 0004 c04ca440 ef63e000 efc1f700 c04ca440
efc1de00
NIP [c00081a0] __switch_to+0xac/0x104
LR [c03a9560] schedule+0x20c/0x3f4
Call Trace:
[ef63fe60] [efc1f700] 0xefc1f700 (unreliable)
[ef63fe70] [c03a9560] schedule+0x20c/0x3f4
[ef63fec0] [c00429e0] do_wait+0x1a4/0x278
[ef63fef0] [c0042b44] sys_wait4+0x90/0xf8
[ef63ff40] [c00106d4] ret_from_syscall+0x0/0x4
--
Actually, this problem is caused by enabling On Chip Debugging, when On
Chip Debugging is enabled, we enable MSR_DE as below:
#define MSR_KERNEL (MSR_ME|MSR_RI|MSR_CE|MSR_DE)
If I comment out mtspr(SPRN_DBCR0, thread-dbcr0); in
prime_debug_regs() function,
then it will be ok.
Here is my analysis for this problem:
Run 'usermode-agent' application will set Internal Debug Mode(IDM) and
Instruction Complete Debug Event(ICMP)flags for thread.
As MSR_DE is enabled, when execute context switching in prime_debug_regs(),
thread-dbcr0 would write to SPRN_DBCR0 register.
So this will enable Instruction Complete Debug Event interrupt, and it
will cause a kernel-mode
exception right now, it will be handled in native_DebugException(), then
kernel detected
this exception not happens in user-mode, lastly kernel call die() and
kill current process.
So my question is could I just comment out mtspr(SPRN_DBCR0,
thread-dbcr0); in prime_debug_regs()?
I'm sure whether or not it will impose a bad impact on debugging.
I believe it would have such an impact. I don't see that user-mode
debugging would be enabled at all.
Maybe something like this untested patch:
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index 84906d3..0e7d1cf 100644
--- a/arch/powerpc/kernel/process.c
+++ b/arch/powerpc/kernel/process.c
@@ -323,6 +323,13 @@ static void set_debug_reg_defaults(struct thread_struct
*thread)
static void prime_debug_regs(struct thread_struct *thread)
{
+ /*
+* If we're setting up debug events for user space, make sure they
+* don't fire in kernel space before we get to user space
+*/
+ if (thread-dbcr0 DBCR0_IDM)
+ mtmsr(mfmsr() ~MSR_DE);
+
mtspr(SPRN_IAC1, thread-iac1);
mtspr(SPRN_IAC2, thread-iac2);
#if CONFIG_PPC_ADV_DEBUG_IACS 2
--
Dave Kleikamp
IBM Linux Technology Center
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Re: [PATCH 2/2] ppc: lazy flush_tlb_mm for nohash architectures
On Thu, 2010-10-14 at 11:52 +1100, Benjamin Herrenschmidt wrote:
On Fri, 2010-09-24 at 13:01 -0500, Dave Kleikamp wrote:
On PPC_MMU_NOHASH processors that support a large number of contexts,
implement a lazy flush_tlb_mm() that switches to a free context, marking
the old one stale. The tlb is only flushed when no free contexts are
available.
The lazy tlb flushing is controlled by the global variable tlb_lazy_flush
which is set during init, dependent upon MMU_FTR_TYPE_47x.
Unless I'm mistaken, there are some issues with that patch... sorry for
the late review, I've been away for a couple of weeks.
+int tlb_lazy_flush;
+static int tlb_needs_flush[NR_CPUS];
+static unsigned long *context_available_map;
+static unsigned int nr_stale_contexts;
Now I understand what you're doing here, but wouldn't it have been
possible to re-use the existing stale map concept or do you reckon it
would have been too messy ?
I didn't like the implementation of a per-core stale map. The existing
implementation flushes the core's tlb, but only clears a specific entry
from the stale map. It's dealing with the stale contexts one at a time,
where the new function is accumulating many stale contexts, with the
intent to do a single tlb flush per core.
Since I originally intended the new function only to be enabled on the
47x, I left the context-stealing code as untouched as possible thinking
it wouldn't be exercised in 47x-land. This was probably narrow-minded,
and I should look at either 1) aligning the context-stealing code closer
to the new lazy flush code, or 2) dropping this code on the floor and
picking back up the new design that we worked on last year.
At the very least, the old style stale map code and new style stale
TLB code should be more in sync, you may end up flushing the TLB
twice...
yeah. if we enable this for 440, it is more likely to be an issue than
on 476.
@@ -189,6 +220,38 @@ static void context_check_map(void)
static void context_check_map(void) { }
#endif
+/*
+ * On architectures that support a large number of contexts, the tlb
+ * can be flushed lazily by picking a new context and making the stale
+ * context unusable until a lazy tlb flush has been issued.
+ *
+ * context_available_map keeps track of both active and stale contexts,
+ * while context_map continues to track only active contexts. When the
+ * lazy tlb flush is triggered, context_map is copied to
+ * context_available_map, making the once-stale contexts available again
+ */
+static void recycle_stale_contexts(void)
+{
+ if (nr_free_contexts == 0 nr_stale_contexts 0) {
Do an early return and avoid the indentation instead ?
Yeah, that makes sense.
+ unsigned int cpu = smp_processor_id();
+ unsigned int i;
+
+ pr_hard([%d] recycling stale contexts\n, cpu);
+ /* Time to flush the TLB's */
+ memcpy(context_available_map, context_map, CTX_MAP_SIZE);
+ nr_free_contexts = nr_stale_contexts;
+ nr_stale_contexts = 0;
+ for_each_online_cpu(i) {
+ if ((i cpu_first_thread_in_core(cpu)) ||
+ (i cpu_last_thread_in_core(cpu)))
+ tlb_needs_flush[i] = 1;
+ else
+ tlb_needs_flush[i] = 0; /* This core */
+ }
+ _tlbil_all();
+ }
+}
+
void switch_mmu_context(struct mm_struct *prev, struct mm_struct *next)
{
unsigned int i, id, cpu = smp_processor_id();
@@ -197,6 +260,8 @@ void switch_mmu_context(struct mm_struct *prev, struct
mm_struct *next)
/* No lockless fast path .. yet */
raw_spin_lock(context_lock);
+ flush_recycled_contexts(cpu);
+
Ok so here's the nasty one I think. You need to make sure that whenever
you pick something off the context_available_map, you've done the above
first within the same context_lock section right ? At least before you
actually -use- said context.
right.
So far so good ... but steal_context can drop the lock iirc. So you may
need to re-flush there. Not sure that can happen in practice but better
safe than sorry. I would have preferred seeing that flush near the end
of the function to avoid such problem.
I can fix this. For 476, I don't think that even if steal_context()
could be called, it wouldn't drop the lock. But then again, if we
enable this for other architectures, it may be a possibility.
Then, you can end up in cases where you flush the TLB, but your context
is marked stale due to stealing, and flush again. That's one of the
reason I wonder if we can consolidate a bit the two orthogonal
staleness concepts we have now.
Granted, stealing on 47x is unlikely, but I have reasons to think that
this lazy flushing will benefit 440 too.
pr_hard([%d] activating context for mm @%p, active=%d, id=%d,
cpu, next, next
[RFC PATCH v3] 476: Set CCR2[DSTI] to prevent isync from flushing shadow TLB
Josh, don't pick this up yet. It needs a bit more testing, but I think I got it right this time. When the DSTI (Disable Shadow TLB Invalidate) bit is set in the CCR2 register, the isync command does not flush the shadow TLB (iTLB dTLB). However, since the shadow TLB does not contain context information, we want the shadow TLB flushed in situations where we are switching context. In those situations, we explicitly clear the DSTI bit before performing isync, and set it again afterward. We also need to do the same when we perform isync after explicitly flushing the TLB. The 476 requires an isync following a write to certain SPRs in order for their changes to be effective. Such is the case with the DSTI bit, so the first isync may not be affected by an immediate change to CCR2, but a second isync instruction will repect the setting. Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com --- arch/powerpc/include/asm/reg_booke.h |4 arch/powerpc/kernel/head_44x.S| 28 arch/powerpc/mm/tlb_nohash_low.S | 24 +++- arch/powerpc/platforms/44x/misc_44x.S | 28 4 files changed, 83 insertions(+), 1 deletions(-) diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h index 667a498..a7ecbfe 100644 --- a/arch/powerpc/include/asm/reg_booke.h +++ b/arch/powerpc/include/asm/reg_booke.h @@ -120,6 +120,7 @@ #define SPRN_TLB3CFG 0x2B3 /* TLB 3 Config Register */ #define SPRN_EPR 0x2BE /* External Proxy Register */ #define SPRN_CCR1 0x378 /* Core Configuration Register 1 */ +#define SPRN_CCR2_476 0x379 /* Core Configuration Register 2 (476)*/ #define SPRN_ZPR 0x3B0 /* Zone Protection Register (40x) */ #define SPRN_MAS7 0x3B0 /* MMU Assist Register 7 */ #define SPRN_MMUCR 0x3B2 /* MMU Control Register */ @@ -188,6 +189,9 @@ #defineCCR1_DPC0x0100 /* Disable L1 I-Cache/D-Cache parity checking */ #defineCCR1_TCS0x0080 /* Timer Clock Select */ +/* Bit definitions for CCR2. */ +#define CCR2_476_DSTI 0x0800 /* Disable Shadow TLB Invalidate */ + /* Bit definitions for the MCSR. */ #define MCSR_MCS 0x8000 /* Machine Check Summary */ #define MCSR_IB0x4000 /* Instruction PLB Error */ diff --git a/arch/powerpc/kernel/head_44x.S b/arch/powerpc/kernel/head_44x.S index 562305b..df1ef80 100644 --- a/arch/powerpc/kernel/head_44x.S +++ b/arch/powerpc/kernel/head_44x.S @@ -38,6 +38,7 @@ #include asm/ppc_asm.h #include asm/asm-offsets.h #include asm/synch.h +#include asm/bug.h #include head_booke.h @@ -703,8 +704,29 @@ _GLOBAL(set_context) stw r4, 0x4(r5) #endif mtspr SPRN_PID,r3 +BEGIN_MMU_FTR_SECTION + b 1f +END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_47x) isync /* Force context change */ blr +1: +#ifdef CONFIG_PPC_47x + mfspr r10,SPRN_CCR2_476 + rlwinm r11,r10,0,~CCR2_476_DSTI + mtspr SPRN_CCR2_476,r11 + /* +* The first isync may not respect the change to CCR2, but its +* completion will ensure that the second isync does. +*/ + isync + isync /* Force context change */ + mtspr SPRN_CCR2_476,r10 + isync +#else /* CONFIG_PPC_47x */ +2: trap + EMIT_BUG_ENTRY 2b,__FILE__,__LINE__,0; +#endif /* CONFIG_PPC_47x */ + blr /* * Init CPU state. This is called at boot time or for secondary CPUs @@ -1083,6 +1105,12 @@ clear_utlb_entry: isync #endif /* CONFIG_PPC_EARLY_DEBUG_44x */ + mfspr r3,SPRN_CCR2_476 + /* With CCR2(DSTI) set, isync does not invalidate the shadow TLB */ + orisr3,r3,ccr2_476_d...@h + mtspr SPRN_CCR2_476,r3 + isync + /* Establish the interrupt vector offsets */ SET_IVOR(0, CriticalInput); SET_IVOR(1, MachineCheckA); diff --git a/arch/powerpc/mm/tlb_nohash_low.S b/arch/powerpc/mm/tlb_nohash_low.S index b9d9fed..8e318ed 100644 --- a/arch/powerpc/mm/tlb_nohash_low.S +++ b/arch/powerpc/mm/tlb_nohash_low.S @@ -112,6 +112,16 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_47x) clrrwi r4,r3,12/* get an EPN for the hashing with V = 0 */ ori r4,r4,PPC47x_TLBE_SIZE tlbwe r4,r7,0 /* write it */ + mfspr r8,SPRN_CCR2_476 + rlwinm r9,r8,0,~CCR2_476_DSTI + mtspr SPRN_CCR2_476,r9 + /* +* The first isync may not respect the change to CCR2, but its +* completion will ensure that the second isync does. +*/ + isync + isync + mtspr SPRN_CCR2_476,r8 isync wrtee r10 blr @@ -180,7 +190,13 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_47x) lwz r8,0(r10) /* Load boltmap entry */ addir10,r10,4 /* Next word */ b 1b /* Then loop */ -1
Re: [PATCH 1/2] v2 476: Set CCR2[DSTI] to prevent isync from flushing shadow TLB
Josh, Please pull this patch. I just found a bone-headed mistake that makes the whole patch a no-op. I'll need to fix it and put it through a bit of testing before I can re-submit it. The other patch in this series should be okay. Thanks, Shaggy On Mon, 2010-09-27 at 16:56 -0500, Dave Kleikamp wrote: When the DSTI (Disable Shadow TLB Invalidate) bit is set in the CCR2 register, the isync command does not flush the shadow TLB (iTLB dTLB). However, since the shadow TLB does not contain context information, we want the shadow TLB flushed in situations where we are switching context. In those situations, we explicitly clear the DSTI bit before performing isync, and set it again afterward. We also need to do the same when we perform isync after explicitly flushing the TLB. Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com --- arch/powerpc/include/asm/reg_booke.h |4 arch/powerpc/kernel/head_44x.S| 25 + arch/powerpc/mm/tlb_nohash_low.S | 14 +- arch/powerpc/platforms/44x/misc_44x.S | 26 ++ 4 files changed, 68 insertions(+), 1 deletions(-) --- snip --- --- a/arch/powerpc/kernel/head_44x.S +++ b/arch/powerpc/kernel/head_44x.S Not only is this in the wrong place (non-47x initialization) but ... @@ -861,6 +877,15 @@ skpinv: addir4,r4,1 /* Increment */ isync #endif /* CONFIG_PPC_EARLY_DEBUG_44x */ +BEGIN_MMU_FTR_SECTION + mfspr r3,SPRN_CCR2_476 + /* With CCR2(DSTI) set, isync does not invalidate the shadow TLB */ + orisr3,r3,ccr2_476_d...@h + rlwinm r3,r3,0,~CCR2_476_DSTI ^^^ This instruction doesn't belong at all. It clears the bit right after setting it. This one was just introduced removing the config option, but it was in the wrong place all along. + mtspr SPRN_CCR2_476,r3 + isync +END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_47x) + /* Establish the interrupt vector offsets */ SET_IVOR(0, CriticalInput); SET_IVOR(1, MachineCheck); I wasn't diligent enough checking a year-old patch that I got back to work on. The code is very similar in two places and the patch applied to the wrong section. Thanks, Shaggy -- Dave Kleikamp IBM Linux Technology Center ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 1/2] 476: Set CCR2[DSTI] to prevent isync from flushing shadow TLB
On Mon, 2010-09-27 at 11:04 -0400, Josh Boyer wrote: On Fri, Sep 24, 2010 at 01:01:36PM -0500, Dave Kleikamp wrote: When the DSTI (Disable Shadow TLB Invalidate) bit is set in the CCR2 register, the isync command does not flush the shadow TLB (iTLB dTLB). However, since the shadow TLB does not contain context information, we want the shadow TLB flushed in situations where we are switching context. In those situations, we explicitly clear the DSTI bit before performing isync, and set it again afterward. We also need to do the same when we perform isync after explicitly flushing the TLB. Th setting of the DSTI bit is dependent on CONFIG_PPC_47x_DISABLE_SHADOW_TLB_INVALIDATE. When we are confident that the feature works as expected, the option can probably be removed. You're defaulting it to 'y' in the Kconfig. Technically someone could turn it off I guess, but practice mostly shows that nobody mucks with the defaults. Do you want it to default 'n' for now if you aren't confident in it just quite yet? I think I made it a config option at Ben's request when I first started this work last year, before being sidetracked by other priorities. I could either remove the option, or default it to 'n'. It might be best to just hard-code the behavior to make sure it's exercised, since there's no 47x hardware in production yet, but we can give Ben a chance to weigh in with his opinion. (Linus also has some kind of gripe with new options being default 'y', but I don't recall all the details and I doubt he'd care about something in low-level PPC code.) josh -- Dave Kleikamp IBM Linux Technology Center ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 1/2] 476: Set CCR2[DSTI] to prevent isync from flushing shadow TLB
On Tue, 2010-09-28 at 07:10 +1000, Benjamin Herrenschmidt wrote: On Mon, 2010-09-27 at 10:26 -0500, Dave Kleikamp wrote: I think I made it a config option at Ben's request when I first started this work last year, before being sidetracked by other priorities. I could either remove the option, or default it to 'n'. It might be best to just hard-code the behavior to make sure it's exercised, since there's no 47x hardware in production yet, but we can give Ben a chance to weigh in with his opinion. You can remove the option I suppose. It was useful to have it during early bringup but probably not anymore. Thanks, Ben. I'll resend it without the config option. Shaggy -- Dave Kleikamp IBM Linux Technology Center ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 1/2] v2 476: Set CCR2[DSTI] to prevent isync from flushing shadow TLB
When the DSTI (Disable Shadow TLB Invalidate) bit is set in the CCR2 register, the isync command does not flush the shadow TLB (iTLB dTLB). However, since the shadow TLB does not contain context information, we want the shadow TLB flushed in situations where we are switching context. In those situations, we explicitly clear the DSTI bit before performing isync, and set it again afterward. We also need to do the same when we perform isync after explicitly flushing the TLB. Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com --- arch/powerpc/include/asm/reg_booke.h |4 arch/powerpc/kernel/head_44x.S| 25 + arch/powerpc/mm/tlb_nohash_low.S | 14 +- arch/powerpc/platforms/44x/misc_44x.S | 26 ++ 4 files changed, 68 insertions(+), 1 deletions(-) diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h index 667a498..a7ecbfe 100644 --- a/arch/powerpc/include/asm/reg_booke.h +++ b/arch/powerpc/include/asm/reg_booke.h @@ -120,6 +120,7 @@ #define SPRN_TLB3CFG 0x2B3 /* TLB 3 Config Register */ #define SPRN_EPR 0x2BE /* External Proxy Register */ #define SPRN_CCR1 0x378 /* Core Configuration Register 1 */ +#define SPRN_CCR2_476 0x379 /* Core Configuration Register 2 (476)*/ #define SPRN_ZPR 0x3B0 /* Zone Protection Register (40x) */ #define SPRN_MAS7 0x3B0 /* MMU Assist Register 7 */ #define SPRN_MMUCR 0x3B2 /* MMU Control Register */ @@ -188,6 +189,9 @@ #defineCCR1_DPC0x0100 /* Disable L1 I-Cache/D-Cache parity checking */ #defineCCR1_TCS0x0080 /* Timer Clock Select */ +/* Bit definitions for CCR2. */ +#define CCR2_476_DSTI 0x0800 /* Disable Shadow TLB Invalidate */ + /* Bit definitions for the MCSR. */ #define MCSR_MCS 0x8000 /* Machine Check Summary */ #define MCSR_IB0x4000 /* Instruction PLB Error */ diff --git a/arch/powerpc/kernel/head_44x.S b/arch/powerpc/kernel/head_44x.S index 562305b..cd34afb 100644 --- a/arch/powerpc/kernel/head_44x.S +++ b/arch/powerpc/kernel/head_44x.S @@ -38,6 +38,7 @@ #include asm/ppc_asm.h #include asm/asm-offsets.h #include asm/synch.h +#include asm/bug.h #include head_booke.h @@ -703,8 +704,23 @@ _GLOBAL(set_context) stw r4, 0x4(r5) #endif mtspr SPRN_PID,r3 +BEGIN_MMU_FTR_SECTION + b 1f +END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_47x) isync /* Force context change */ blr +1: +#ifdef CONFIG_PPC_47x + mfspr r10,SPRN_CCR2_476 + rlwinm r11,r10,0,~CCR2_476_DSTI + mtspr SPRN_CCR2_476,r11 + isync /* Force context change */ + mtspr SPRN_CCR2_476,r10 +#else /* CONFIG_PPC_47x */ +2: trap + EMIT_BUG_ENTRY 2b,__FILE__,__LINE__,0; +#endif /* CONFIG_PPC_47x */ + blr /* * Init CPU state. This is called at boot time or for secondary CPUs @@ -861,6 +877,15 @@ skpinv:addir4,r4,1 /* Increment */ isync #endif /* CONFIG_PPC_EARLY_DEBUG_44x */ +BEGIN_MMU_FTR_SECTION + mfspr r3,SPRN_CCR2_476 + /* With CCR2(DSTI) set, isync does not invalidate the shadow TLB */ + orisr3,r3,ccr2_476_d...@h + rlwinm r3,r3,0,~CCR2_476_DSTI + mtspr SPRN_CCR2_476,r3 + isync +END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_47x) + /* Establish the interrupt vector offsets */ SET_IVOR(0, CriticalInput); SET_IVOR(1, MachineCheck); diff --git a/arch/powerpc/mm/tlb_nohash_low.S b/arch/powerpc/mm/tlb_nohash_low.S index b9d9fed..f28fb52 100644 --- a/arch/powerpc/mm/tlb_nohash_low.S +++ b/arch/powerpc/mm/tlb_nohash_low.S @@ -112,7 +112,11 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_47x) clrrwi r4,r3,12/* get an EPN for the hashing with V = 0 */ ori r4,r4,PPC47x_TLBE_SIZE tlbwe r4,r7,0 /* write it */ + mfspr r8,SPRN_CCR2_476 + rlwinm r9,r8,0,~CCR2_476_DSTI + mtspr SPRN_CCR2_476,r9 isync + mtspr SPRN_CCR2_476,r8 wrtee r10 blr #else /* CONFIG_PPC_47x */ @@ -180,7 +184,11 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_47x) lwz r8,0(r10) /* Load boltmap entry */ addir10,r10,4 /* Next word */ b 1b /* Then loop */ -1: isync /* Sync shadows */ +1: mfspr r9,SPRN_CCR2_476 + rlwinm r10,r9,0,~CCR2_476_DSTI + mtspr SPRN_CCR2_476,r10 + isync /* Sync shadows */ + mtspr SPRN_CCR2_476,r9 wrtee r11 #else /* CONFIG_PPC_47x */ 1: trap @@ -203,7 +211,11 @@ _GLOBAL(_tlbivax_bcast) isync /* tlbivax 0,r3 - use .long to avoid binutils deps */ .long 0x7c000624 | (r3 11) + mfspr r8,SPRN_CCR2_476 + rlwinm r9,r8,0,~CCR2_476_DSTI + mtspr SPRN_CCR2_476,r9
[PATCH 0/2] powerpc/47x TLB optimization patches
These two patches reduce the frequency that the tlb caches are flushed in hardware. Both the normal tlb cache and the shadow tlb cache, which separates the tlbs for data and instruction access (dTLB and iTLB). Dave Kleikamp (2): 476: Set CCR2[DSTI] to prevent isync from flushing shadow TLB ppc: lazy flush_tlb_mm for nohash architectures arch/powerpc/include/asm/reg_booke.h |4 + arch/powerpc/kernel/head_44x.S| 25 ++ arch/powerpc/mm/mmu_context_nohash.c | 154 ++--- arch/powerpc/mm/mmu_decl.h|8 ++ arch/powerpc/mm/tlb_nohash.c | 28 +- arch/powerpc/mm/tlb_nohash_low.S | 14 +++- arch/powerpc/platforms/44x/Kconfig|7 ++ arch/powerpc/platforms/44x/misc_44x.S | 26 ++ 8 files changed, 249 insertions(+), 17 deletions(-) -- 1.7.2.2 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 1/2] 476: Set CCR2[DSTI] to prevent isync from flushing shadow TLB
When the DSTI (Disable Shadow TLB Invalidate) bit is set in the CCR2 register, the isync command does not flush the shadow TLB (iTLB dTLB). However, since the shadow TLB does not contain context information, we want the shadow TLB flushed in situations where we are switching context. In those situations, we explicitly clear the DSTI bit before performing isync, and set it again afterward. We also need to do the same when we perform isync after explicitly flushing the TLB. Th setting of the DSTI bit is dependent on CONFIG_PPC_47x_DISABLE_SHADOW_TLB_INVALIDATE. When we are confident that the feature works as expected, the option can probably be removed. Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com --- arch/powerpc/include/asm/reg_booke.h |4 arch/powerpc/kernel/head_44x.S| 25 + arch/powerpc/mm/tlb_nohash_low.S | 14 +- arch/powerpc/platforms/44x/Kconfig|7 +++ arch/powerpc/platforms/44x/misc_44x.S | 26 ++ 5 files changed, 75 insertions(+), 1 deletions(-) diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h index 667a498..a7ecbfe 100644 --- a/arch/powerpc/include/asm/reg_booke.h +++ b/arch/powerpc/include/asm/reg_booke.h @@ -120,6 +120,7 @@ #define SPRN_TLB3CFG 0x2B3 /* TLB 3 Config Register */ #define SPRN_EPR 0x2BE /* External Proxy Register */ #define SPRN_CCR1 0x378 /* Core Configuration Register 1 */ +#define SPRN_CCR2_476 0x379 /* Core Configuration Register 2 (476)*/ #define SPRN_ZPR 0x3B0 /* Zone Protection Register (40x) */ #define SPRN_MAS7 0x3B0 /* MMU Assist Register 7 */ #define SPRN_MMUCR 0x3B2 /* MMU Control Register */ @@ -188,6 +189,9 @@ #defineCCR1_DPC0x0100 /* Disable L1 I-Cache/D-Cache parity checking */ #defineCCR1_TCS0x0080 /* Timer Clock Select */ +/* Bit definitions for CCR2. */ +#define CCR2_476_DSTI 0x0800 /* Disable Shadow TLB Invalidate */ + /* Bit definitions for the MCSR. */ #define MCSR_MCS 0x8000 /* Machine Check Summary */ #define MCSR_IB0x4000 /* Instruction PLB Error */ diff --git a/arch/powerpc/kernel/head_44x.S b/arch/powerpc/kernel/head_44x.S index 562305b..0c1b118 100644 --- a/arch/powerpc/kernel/head_44x.S +++ b/arch/powerpc/kernel/head_44x.S @@ -703,8 +703,23 @@ _GLOBAL(set_context) stw r4, 0x4(r5) #endif mtspr SPRN_PID,r3 +BEGIN_MMU_FTR_SECTION + b 1f +END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_47x) isync /* Force context change */ blr +1: +#ifdef CONFIG_PPC_47x + mfspr r10,SPRN_CCR2_476 + rlwinm r11,r10,0,~CCR2_476_DSTI + mtspr SPRN_CCR2_476,r11 + isync /* Force context change */ + mtspr SPRN_CCR2_476,r10 +#else /* CONFIG_PPC_47x */ +2: trap + EMIT_BUG_ENTRY 2b,__FILE__,__LINE__,0; +#endif /* CONFIG_PPC_47x */ + blr /* * Init CPU state. This is called at boot time or for secondary CPUs @@ -861,6 +876,16 @@ skpinv:addir4,r4,1 /* Increment */ isync #endif /* CONFIG_PPC_EARLY_DEBUG_44x */ + mfspr r3,SPRN_CCR2_476 +#ifdef CONFIG_PPC_47x_DISABLE_SHADOW_TLB_INVALIDATE + /* With CCR2(DSTI) set, isync does not invalidate the shadow TLB */ + orisr3,r3,ccr2_476_d...@h +#else + rlwinm r3,r3,0,~CCR2_476_DSTI +#endif + mtspr SPRN_CCR2_476,r3 + isync + /* Establish the interrupt vector offsets */ SET_IVOR(0, CriticalInput); SET_IVOR(1, MachineCheck); diff --git a/arch/powerpc/mm/tlb_nohash_low.S b/arch/powerpc/mm/tlb_nohash_low.S index b9d9fed..f28fb52 100644 --- a/arch/powerpc/mm/tlb_nohash_low.S +++ b/arch/powerpc/mm/tlb_nohash_low.S @@ -112,7 +112,11 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_47x) clrrwi r4,r3,12/* get an EPN for the hashing with V = 0 */ ori r4,r4,PPC47x_TLBE_SIZE tlbwe r4,r7,0 /* write it */ + mfspr r8,SPRN_CCR2_476 + rlwinm r9,r8,0,~CCR2_476_DSTI + mtspr SPRN_CCR2_476,r9 isync + mtspr SPRN_CCR2_476,r8 wrtee r10 blr #else /* CONFIG_PPC_47x */ @@ -180,7 +184,11 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_47x) lwz r8,0(r10) /* Load boltmap entry */ addir10,r10,4 /* Next word */ b 1b /* Then loop */ -1: isync /* Sync shadows */ +1: mfspr r9,SPRN_CCR2_476 + rlwinm r10,r9,0,~CCR2_476_DSTI + mtspr SPRN_CCR2_476,r10 + isync /* Sync shadows */ + mtspr SPRN_CCR2_476,r9 wrtee r11 #else /* CONFIG_PPC_47x */ 1: trap @@ -203,7 +211,11 @@ _GLOBAL(_tlbivax_bcast) isync /* tlbivax 0,r3 - use .long to avoid binutils deps */ .long 0x7c000624 | (r3 11) + mfspr
[PATCH 2/2] ppc: lazy flush_tlb_mm for nohash architectures
On PPC_MMU_NOHASH processors that support a large number of contexts,
implement a lazy flush_tlb_mm() that switches to a free context, marking
the old one stale. The tlb is only flushed when no free contexts are
available.
The lazy tlb flushing is controlled by the global variable tlb_lazy_flush
which is set during init, dependent upon MMU_FTR_TYPE_47x.
Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com
---
arch/powerpc/mm/mmu_context_nohash.c | 154 +++---
arch/powerpc/mm/mmu_decl.h |8 ++
arch/powerpc/mm/tlb_nohash.c | 28 +-
3 files changed, 174 insertions(+), 16 deletions(-)
diff --git a/arch/powerpc/mm/mmu_context_nohash.c
b/arch/powerpc/mm/mmu_context_nohash.c
index ddfd7ad..87c7dc2 100644
--- a/arch/powerpc/mm/mmu_context_nohash.c
+++ b/arch/powerpc/mm/mmu_context_nohash.c
@@ -17,10 +17,6 @@
* TODO:
*
* - The global context lock will not scale very well
- * - The maps should be dynamically allocated to allow for processors
- * that support more PID bits at runtime
- * - Implement flush_tlb_mm() by making the context stale and picking
- * a new one
* - More aggressively clear stale map bits and maybe find some way to
* also clear mm-cpu_vm_mask bits when processes are migrated
*/
@@ -52,6 +48,8 @@
#include asm/mmu_context.h
#include asm/tlbflush.h
+#include mmu_decl.h
+
static unsigned int first_context, last_context;
static unsigned int next_context, nr_free_contexts;
static unsigned long *context_map;
@@ -59,9 +57,31 @@ static unsigned long *stale_map[NR_CPUS];
static struct mm_struct **context_mm;
static DEFINE_RAW_SPINLOCK(context_lock);
+int tlb_lazy_flush;
+static int tlb_needs_flush[NR_CPUS];
+static unsigned long *context_available_map;
+static unsigned int nr_stale_contexts;
+
#define CTX_MAP_SIZE \
(sizeof(unsigned long) * (last_context / BITS_PER_LONG + 1))
+/*
+ * if another cpu recycled the stale contexts, we need to flush
+ * the local TLB, so that we may re-use those contexts
+ */
+void flush_recycled_contexts(int cpu)
+{
+ int i;
+
+ if (tlb_needs_flush[cpu]) {
+ pr_hard([%d] flushing tlb\n, cpu);
+ _tlbil_all();
+ for (i = cpu_first_thread_in_core(cpu);
+i = cpu_last_thread_in_core(cpu); i++) {
+ tlb_needs_flush[i] = 0;
+ }
+ }
+}
/* Steal a context from a task that has one at the moment.
*
@@ -147,7 +167,7 @@ static unsigned int steal_context_up(unsigned int id)
pr_hardcont( | steal %d from 0x%p, id, mm);
/* Flush the TLB for that context */
- local_flush_tlb_mm(mm);
+ __local_flush_tlb_mm(mm);
/* Mark this mm has having no context anymore */
mm-context.id = MMU_NO_CONTEXT;
@@ -161,13 +181,19 @@ static unsigned int steal_context_up(unsigned int id)
#ifdef DEBUG_MAP_CONSISTENCY
static void context_check_map(void)
{
- unsigned int id, nrf, nact;
+ unsigned int id, nrf, nact, nstale;
- nrf = nact = 0;
+ nrf = nact = nstale = 0;
for (id = first_context; id = last_context; id++) {
int used = test_bit(id, context_map);
- if (!used)
- nrf++;
+ int allocated = tlb_lazy_flush
+ test_bit(id, context_available_map);
+ if (!used) {
+ if (allocated)
+ nstale++;
+ else
+ nrf++;
+ }
if (used != (context_mm[id] != NULL))
pr_err(MMU: Context %d is %s and MM is %p !\n,
id, used ? used : free, context_mm[id]);
@@ -179,6 +205,11 @@ static void context_check_map(void)
nr_free_contexts, nrf);
nr_free_contexts = nrf;
}
+ if (nstale != nr_stale_contexts) {
+ pr_err(MMU: Stale context count out of sync ! (%d vs %d)\n,
+ nr_stale_contexts, nstale);
+ nr_stale_contexts = nstale;
+ }
if (nact num_online_cpus())
pr_err(MMU: More active contexts than CPUs ! (%d vs %d)\n,
nact, num_online_cpus());
@@ -189,6 +220,38 @@ static void context_check_map(void)
static void context_check_map(void) { }
#endif
+/*
+ * On architectures that support a large number of contexts, the tlb
+ * can be flushed lazily by picking a new context and making the stale
+ * context unusable until a lazy tlb flush has been issued.
+ *
+ * context_available_map keeps track of both active and stale contexts,
+ * while context_map continues to track only active contexts. When the
+ * lazy tlb flush is triggered, context_map is copied to
+ * context_available_map, making the once-stale contexts available again
+ */
+static void recycle_stale_contexts(void
[PATCH 1/4] powerpc/47x: Make sure mcsr is cleared before enabling machine check interrupts
Clear the machine check syndrom register before enabling machine check interrupts. The initial state of the tlb can lead to parity errors being flagged early after a cold boot. Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com --- arch/powerpc/kernel/head_44x.S |4 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/kernel/head_44x.S b/arch/powerpc/kernel/head_44x.S index 5ab484e..562305b 100644 --- a/arch/powerpc/kernel/head_44x.S +++ b/arch/powerpc/kernel/head_44x.S @@ -113,6 +113,10 @@ _ENTRY(_start); stw r5, 0(r4) /* Save abatron_pteptrs at a fixed location */ stw r6, 0(r5) + /* Clear the Machine Check Syndrome Register */ + li r0,0 + mtspr SPRN_MCSR,r0 + /* Let's move on */ lis r4,start_ker...@h ori r4,r4,start_ker...@l -- 1.7.1 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 0/4] *** SUBJECT HERE ***
Josh, Here are some bug fixes for the powerpc-4xx tree. It'd be nice if they could make it into 2.6.46. Thanks, Shaggy Dave Kleikamp (4): powerpc/47x: Make sure mcsr is cleared before enabling machine check interrupts powerpc/47x: Remove redundant line from cputable.c powerpc/4xx: Index interrupt stacks by physical cpu powerpc/47x: Add an isync before the tlbivax instruction arch/powerpc/kernel/cputable.c |1 - arch/powerpc/kernel/head_44x.S |4 arch/powerpc/kernel/irq.c| 15 --- arch/powerpc/kernel/setup_32.c |9 + arch/powerpc/mm/tlb_nohash_low.S |1 + 5 files changed, 18 insertions(+), 12 deletions(-) ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 4/4] powerpc/47x: Add an isync before the tlbivax instruction
Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com --- arch/powerpc/mm/tlb_nohash_low.S |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/mm/tlb_nohash_low.S b/arch/powerpc/mm/tlb_nohash_low.S index cfa7682..b9d9fed 100644 --- a/arch/powerpc/mm/tlb_nohash_low.S +++ b/arch/powerpc/mm/tlb_nohash_low.S @@ -200,6 +200,7 @@ _GLOBAL(_tlbivax_bcast) rlwimi r5,r4,0,16,31 wrteei 0 mtspr SPRN_MMUCR,r5 + isync /* tlbivax 0,r3 - use .long to avoid binutils deps */ .long 0x7c000624 | (r3 11) isync -- 1.7.1 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 3/4] powerpc/4xx: Index interrupt stacks by physical cpu
The interrupt stacks need to be indexed by the physical cpu since the
critical, debug and machine check handlers use the contents of SPRN_PIR to
index the critirq_ctx, dbgirq_ctx, and mcheckirq_ctx arrays.
Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com
---
arch/powerpc/kernel/irq.c | 15 ---
arch/powerpc/kernel/setup_32.c |9 +
2 files changed, 13 insertions(+), 11 deletions(-)
diff --git a/arch/powerpc/kernel/irq.c b/arch/powerpc/kernel/irq.c
index d3ce67c..52e9c95 100644
--- a/arch/powerpc/kernel/irq.c
+++ b/arch/powerpc/kernel/irq.c
@@ -446,22 +446,23 @@ struct thread_info *mcheckirq_ctx[NR_CPUS] __read_mostly;
void exc_lvl_ctx_init(void)
{
struct thread_info *tp;
- int i;
+ int i, hw_cpu;
for_each_possible_cpu(i) {
- memset((void *)critirq_ctx[i], 0, THREAD_SIZE);
- tp = critirq_ctx[i];
+ hw_cpu = get_hard_smp_processor_id(i);
+ memset((void *)critirq_ctx[hw_cpu], 0, THREAD_SIZE);
+ tp = critirq_ctx[hw_cpu];
tp-cpu = i;
tp-preempt_count = 0;
#ifdef CONFIG_BOOKE
- memset((void *)dbgirq_ctx[i], 0, THREAD_SIZE);
- tp = dbgirq_ctx[i];
+ memset((void *)dbgirq_ctx[hw_cpu], 0, THREAD_SIZE);
+ tp = dbgirq_ctx[hw_cpu];
tp-cpu = i;
tp-preempt_count = 0;
- memset((void *)mcheckirq_ctx[i], 0, THREAD_SIZE);
- tp = mcheckirq_ctx[i];
+ memset((void *)mcheckirq_ctx[hw_cpu], 0, THREAD_SIZE);
+ tp = mcheckirq_ctx[hw_cpu];
tp-cpu = i;
tp-preempt_count = HARDIRQ_OFFSET;
#endif
diff --git a/arch/powerpc/kernel/setup_32.c b/arch/powerpc/kernel/setup_32.c
index a10ffc8..93666f9 100644
--- a/arch/powerpc/kernel/setup_32.c
+++ b/arch/powerpc/kernel/setup_32.c
@@ -258,17 +258,18 @@ static void __init irqstack_early_init(void)
#if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
static void __init exc_lvl_early_init(void)
{
- unsigned int i;
+ unsigned int i, hw_cpu;
/* interrupt stacks must be in lowmem, we get that for free on ppc32
* as the memblock is limited to lowmem by MEMBLOCK_REAL_LIMIT */
for_each_possible_cpu(i) {
- critirq_ctx[i] = (struct thread_info *)
+ hw_cpu = get_hard_smp_processor_id(i);
+ critirq_ctx[hw_cpu] = (struct thread_info *)
__va(memblock_alloc(THREAD_SIZE, THREAD_SIZE));
#ifdef CONFIG_BOOKE
- dbgirq_ctx[i] = (struct thread_info *)
+ dbgirq_ctx[hw_cpu] = (struct thread_info *)
__va(memblock_alloc(THREAD_SIZE, THREAD_SIZE));
- mcheckirq_ctx[i] = (struct thread_info *)
+ mcheckirq_ctx[hw_cpu] = (struct thread_info *)
__va(memblock_alloc(THREAD_SIZE, THREAD_SIZE));
#endif
}
--
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[PATCH 2/4] powerpc/47x: Remove redundant line from cputable.c
There are two entries for .cpu_user_features in
arch/powerpc/kernel/cputable.c. Remove the one that doesn't belong
Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com
---
arch/powerpc/kernel/cputable.c |1 -
1 files changed, 0 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index 65e2b4e..1f9123f 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -1826,7 +1826,6 @@ static struct cpu_spec __initdata cpu_specs[] = {
.cpu_features = CPU_FTRS_47X,
.cpu_user_features = COMMON_USER_BOOKE |
PPC_FEATURE_HAS_FPU,
- .cpu_user_features = COMMON_USER_BOOKE,
.mmu_features = MMU_FTR_TYPE_47x |
MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_LOCK_BCAST_INVAL,
.icache_bsize = 32,
--
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Re: [PATCH 0/4] Some 47x patches for the powerpc-4xx tree
Sorry! Forgot to change the subject. Shaggy On Wed, 2010-08-18 at 11:44 -0500, Dave Kleikamp wrote: Josh, Here are some bug fixes for the powerpc-4xx tree. It'd be nice if they could make it into 2.6.46. Thanks, Shaggy Dave Kleikamp (4): powerpc/47x: Make sure mcsr is cleared before enabling machine check interrupts powerpc/47x: Remove redundant line from cputable.c powerpc/4xx: Index interrupt stacks by physical cpu powerpc/47x: Add an isync before the tlbivax instruction arch/powerpc/kernel/cputable.c |1 - arch/powerpc/kernel/head_44x.S |4 arch/powerpc/kernel/irq.c| 15 --- arch/powerpc/kernel/setup_32.c |9 + arch/powerpc/mm/tlb_nohash_low.S |1 + 5 files changed, 18 insertions(+), 12 deletions(-) -- Dave Kleikamp IBM Linux Technology Center ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] powerpc: fix userspace build of ptrace.h
On Sun, 2010-05-09 at 17:27 +1000, Benjamin Herrenschmidt wrote: On Sun, 2010-05-09 at 08:59 +0200, Sam Ravnborg wrote: From ff056c080d2b0b93bac07ad71125fee701919f5e Mon Sep 17 00:00:00 2001 From: Sam Ravnborg s...@ravnborg.org Date: Sun, 9 May 2010 08:52:31 +0200 Subject: [PATCH] powerpc: fix userspace build of ptrace.h Build of ptrace.h failed for assembly because it pulls in stdint.h. Use exportable types (__u32, __u64) to avoid the dependency on stdint.h. Signed-off-by: Sam Ravnborg s...@ravnborg.org Cc: Andrey Volkov avol...@varma-el.com Cc: Dave Kleikamp sha...@linux.vnet.ibm.com Cc: Benjamin Herrenschmidt b...@kernel.crashing.org --- A better fix is to remove the use of stdint like the following patch does. Note - I have not even build tested this patch! Ack, thanks, I'll test and apply. Acked-by: Dave Kleikamp sha...@linux.vnet.ibm.com -- Dave Kleikamp IBM Linux Technology Center ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: Fix [e]glibc build process
On Sat, 2010-05-08 at 23:56 +0400, Andrey Volkov wrote:
This patch fix [e]glibc build process destruction (more precisely _assembler_
is die when try to compile getcontext.S since stdint.h coldn't be assembled)
intruduced by patch:
commit: 162d92dfb79a0b5fc03380b8819fa5f870ebf1e
Date: Mon, 8 Feb 2010 11:51:05 + (11:51 +)
from: Dave Kleikamp
Signed-off-by: Andrey Volkov avol...@varma-el.com
---
arch/powerpc/include/asm/ptrace.h |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/include/asm/ptrace.h
b/arch/powerpc/include/asm/ptrace.h
index 9e2d84c..025912b 100644
--- a/arch/powerpc/include/asm/ptrace.h
+++ b/arch/powerpc/include/asm/ptrace.h
@@ -27,8 +27,10 @@
#ifdef __KERNEL__
#include linux/types.h
#else
+#ifndef __ASSEMBLY__
#include stdint.h
#endif
+#endif
#ifndef __ASSEMBLY__
Assembly code won't need to pull in linux/types.h either, so this would
be simpler:
Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com
diff --git a/arch/powerpc/include/asm/ptrace.h
b/arch/powerpc/include/asm/ptrace.h
index 9e2d84c..0ed710e 100644
--- a/arch/powerpc/include/asm/ptrace.h
+++ b/arch/powerpc/include/asm/ptrace.h
@@ -24,14 +24,14 @@
* 2 of the License, or (at your option) any later version.
*/
+#ifndef __ASSEMBLY__
+
#ifdef __KERNEL__
#include linux/types.h
#else
#include stdint.h
#endif
-#ifndef __ASSEMBLY__
-
struct pt_regs {
unsigned long gpr[32];
unsigned long nip;
--
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Re: [PATCH 04/13] powerpc/476: add machine check handler for 47x core
On Wed, 2010-05-05 at 08:59 -0400, Josh Boyer wrote:
On Wed, May 05, 2010 at 08:27:01AM -0400, Josh Boyer wrote:
+int machine_check_47x(struct pt_regs *regs)
+{
+ unsigned long reason = get_mc_reason(regs);
+ u32 mcsr;
+
+ printk(KERN_ERR Machine check in kernel mode.\n);
+ if (reason ESR_IMCP) {
+ printk(KERN_ERR
+ Instruction Synchronous Machine Check exception\n);
+ mtspr(SPRN_ESR, reason ~ESR_IMCP);
+ return 0;
+ }
+ mcsr = mfspr(SPRN_MCSR);
+ if (mcsr MCSR_IB)
+ printk(KERN_ERR Instruction Read PLB Error\n);
+ if (mcsr MCSR_DRB)
+ printk(KERN_ERR Data Read PLB Error\n);
+ if (mcsr MCSR_DWB)
+ printk(KERN_ERR Data Write PLB Error\n);
+ if (mcsr MCSR_TLBP)
+ printk(KERN_ERR TLB Parity Error\n);
+ if (mcsr MCSR_ICP) {
+ flush_instruction_cache();
+ printk(KERN_ERR I-Cache Parity Error\n);
+ }
+ if (mcsr MCSR_DCSP)
+ printk(KERN_ERR D-Cache Search Parity Error\n);
+ if (mcsr PPC47x_MCSR_GPR)
+ printk(KERN_ERR GPR Parity Error\n);
+ if (mcsr PPC47x_MCSR_FPR)
+ printk(KERN_ERR FPR Parity Error\n);
+ if (mcsr PPC47x_MCSR_IPR)
+ printk(KERN_ERR Machine Check exception is imprecise\n);
This function isn't guarded by CONFIG_PPC_47x, however the defines for
PPC47x_MCSR_* are in include/asm/reg_booke.h. They were added that way in
patch
4. As it stands, we get this when trying to build for plain 44x:
CC arch/powerpc/kernel/traps.o
arch/powerpc/kernel/traps.c: In function 'machine_check_47x':
arch/powerpc/kernel/traps.c:411: error: 'PPC47x_MCSR_GPR' undeclared (first
use in this function)
arch/powerpc/kernel/traps.c:411: error: (Each undeclared identifier is
reported only once
arch/powerpc/kernel/traps.c:411: error: for each function it appears in.)
arch/powerpc/kernel/traps.c:413: error: 'PPC47x_MCSR_FPR' undeclared (first
use in this function)
arch/powerpc/kernel/traps.c:415: error: 'PPC47x_MCSR_IPR' undeclared (first
use in this function)
make[1]: *** [arch/powerpc/kernel/traps.o] Error 1
make: *** [arch/powerpc/kernel] Error 2
make: *** Waiting for unfinished jobs
We should probably guard this function behind CONFIG_PPC_47x, right? If so,
I
can fix that up locally quickly enough.
Actually, that won't work unless we wrap the .machine_check addition in
cputable
as well. That looks ugly. I'm guessing the easiest and cleanest fix is to
not guard the #defines for those regs in reg_booke.h. Anyone have problems
with
that?
I have no problems with that. Sorry for not being diligent and building
these patches with other configs.
Thanks,
Shaggy
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Re: [PATCH 06/13] powerpc/4xx: Simple platform for the ISS 4xx simulator
On Wed, 2010-05-05 at 11:11 -0400, Josh Boyer wrote:
On Fri, Mar 05, 2010 at 01:45:54PM -0700, Dave Kleikamp wrote:
+config ISS4xx
+bool ISS 4xx Simulator
+depends on (44x || 40x)
+default n
+select 405GP if 40x
+select 440GP if 44x !PPC_47x
+select PPC_FPU
+select OF_RTC
+help
+ This option enables support for the IBM ISS simulation environment
This looks like how we want to do this, however...
+/* We can have either UICs or MPICs */
+static void __init iss4xx_init_irq(void)
+{
+struct device_node *np;
+
+/* Find top level interrupt controller */
+for_each_node_with_property(np, interrupt-controller) {
+if (of_get_property(np, interrupts, NULL) == NULL)
+break;
+}
+if (np == NULL)
+panic(Can't find top level interrupt controller);
+
+/* Check type and do appropriate initialization */
+if (of_device_is_compatible(np, ibm,uic)) {
+uic_init_tree();
+ppc_md.get_irq = uic_get_irq;
+} else if (of_device_is_compatible(np, chrp,open-pic)) {
+/* The MPIC driver will get everything it needs from the
+ * device-tree, just pass 0 to all arguments
+ */
+struct mpic *mpic = mpic_alloc(np, 0, MPIC_PRIMARY, 0, 0,
+MPIC );
+BUG_ON(mpic == NULL);
+mpic_init(mpic);
+ppc_md.get_irq = mpic_get_irq;
+} else
+panic(Unrecognized top level interrupt controller);
+}
.. on non-476 builds we get link errors:
arch/powerpc/platforms/built-in.o: In function `as1_writeb':
(.init.text+0x5d4): undefined reference to `mpic_alloc'
arch/powerpc/platforms/built-in.o: In function `as1_writeb':
(.init.text+0x5e4): undefined reference to `mpic_init'
arch/powerpc/platforms/built-in.o: In function `as1_writeb':
(.init.text+0x5ea): undefined reference to `mpic_get_irq'
arch/powerpc/platforms/built-in.o: In function `as1_writeb':
(.init.text+0x5ee): undefined reference to `mpic_get_irq'
make: *** [.tmp_vmlinux1] Error 1
because we don't have CONFIG_MPIC turned on for these. I'd suggest we guard
the mpic else chunk in this file behind CONFIG_MPIC. Agreed?
Yeah. That's reasonable.
I'm less worried about the mpic references that are already guarded behind the
CONFIG_SMP sections. Nobody has been crazy enough to make an SMP 440 or 460
SoC
yet, so CONFIG_SMP should only get selected for 476, and that already selects
MPIC in the Kconfig.
josh
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Re: [RFC Patch 2/2] PPC64-HWBKPT: Implement hw-breakpoints for PPC64
On Mon, 2010-03-29 at 17:01 +0530, K.Prasad wrote: On Fri, Mar 26, 2010 at 04:11:45PM -0500, Dave Kleikamp wrote: On Tue, 2010-03-23 at 19:37 +0530, K.Prasad wrote: plain text document attachment (ppc64_hbkpt_02) Implement perf-events based hw-breakpoint interfaces for PPC64 processors. These interfaces help arbitrate requests from various users and schedules them as appropriate. Signed-off-by: K.Prasad pra...@linux.vnet.ibm.com SNIP Index: linux-2.6.ppc64_test/arch/powerpc/include/asm/cputable.h === --- linux-2.6.ppc64_test.orig/arch/powerpc/include/asm/cputable.h +++ linux-2.6.ppc64_test/arch/powerpc/include/asm/cputable.h @@ -511,6 +511,13 @@ static inline int cpu_has_feature(unsign feature); } +#define CPU_FTR_HAS_DABR (defined(CONFIG_PPC64) \ + !defined(CONFIG_PPC_ADV_DEBUG_REGS)) +#ifdef CPU_FTR_HAS_DABR +/* Number of physical HW breakpoint registers */ +#define HBP_NUM 1 +#endif + #endif /* !__ASSEMBLY__ */ #endif /* __KERNEL__ */ These new defines don't really correlate to the cpu table. One would expect cpu_has_feature(CPU_FTR_HAS_DABR) to have meaning, but it would have to be defined similar to the other CPU_FTR_ constants, and or-ed with CPU_FTRS_ALWAYS (when appropriate). The code can be changed as below: #if (defined(CONFIG_PPC64) !defined(CONFIG_PPC_ADV_DEBUG_REGS)) #define CPU_FTR_HAS_DABR 1 /* Number of physical HW breakpoint registers */ #define HBP_NUM 1 #endif However, a config option CONFIG_PPC_BOOK3S_64 (I just found) whose scope includes only 64-bit server processors (having one DABR) to be the most suitable. I think it must be used in lieu of introducing a new CPU_FTR_HAS_DABR definition in cputable.h Similarly, I would expect the cpu_spec structure to have a new field, hbp_num, which is initialized in cputable.c. Maybe a longer name would be better, num_hw_brkpts? There are a few issues with such an approach: i) Two such fields would be required in 'struct cpu_spec' - one for instruction breakpoints and other for data. ii) As pointed out by you below, hbp_num or num_hw_brkpts would always be assigned to the compile time constant HBP_NUM (hence a variable is not required to store it). iii) HBP_NUM still cannot be entirely removed as it is used by generic kernel/hw_breakpoint.c code (and is used by x86 code as well). I think the simplest approach would be to have the following entry in cputable.h (and get away with the rest of the additions seen in patch ver XV) #ifdef CONFIG_PPC_BOOK3S_64 #define HBP_NUM 1 #endif The next version of the patch should contain changes to that effect (assuming I hear no objections). I just don't think this belongs in cputable.h. Why not put this in hw_breakpoint.h? -- David Kleikamp IBM Linux Technology Center ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [RFC Patch 2/2] PPC64-HWBKPT: Implement hw-breakpoints for PPC64
On Tue, 2010-03-23 at 19:37 +0530, K.Prasad wrote: plain text document attachment (ppc64_hbkpt_02) Implement perf-events based hw-breakpoint interfaces for PPC64 processors. These interfaces help arbitrate requests from various users and schedules them as appropriate. Signed-off-by: K.Prasad pra...@linux.vnet.ibm.com SNIP Index: linux-2.6.ppc64_test/arch/powerpc/include/asm/cputable.h === --- linux-2.6.ppc64_test.orig/arch/powerpc/include/asm/cputable.h +++ linux-2.6.ppc64_test/arch/powerpc/include/asm/cputable.h @@ -511,6 +511,13 @@ static inline int cpu_has_feature(unsign feature); } +#define CPU_FTR_HAS_DABR (defined(CONFIG_PPC64) \ + !defined(CONFIG_PPC_ADV_DEBUG_REGS)) +#ifdef CPU_FTR_HAS_DABR +/* Number of physical HW breakpoint registers */ +#define HBP_NUM 1 +#endif + #endif /* !__ASSEMBLY__ */ #endif /* __KERNEL__ */ These new defines don't really correlate to the cpu table. One would expect cpu_has_feature(CPU_FTR_HAS_DABR) to have meaning, but it would have to be defined similar to the other CPU_FTR_ constants, and or-ed with CPU_FTRS_ALWAYS (when appropriate). Similarly, I would expect the cpu_spec structure to have a new field, hbp_num, which is initialized in cputable.c. Maybe a longer name would be better, num_hw_brkpts? When I added the PPC_ADV_DEBUG config options for the bookE features, I didn't see an immediate need to clutter the cputable since their values are fixed at compile time. We should be consistent with these, but unless we are going to determine any of these at run-time, I don't know that they belong in the cpu table. Thanks, Shaggy -- David Kleikamp IBM Linux Technology Center ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 05/13] powerpc/476: Add isync after loading mmu and debug spr's
On Sun, 2010-03-07 at 15:08 -0800, Hollis Blanchard wrote: On Fri, Mar 5, 2010 at 12:43 PM, Dave Kleikamp sha...@linux.vnet.ibm.com wrote: powerpc/476: Add isync after loading mmu and debug spr's From: Dave Kleikamp sha...@linux.vnet.ibm.com 476 requires an isync after loading MMU and debug related SPR's. Some of these are in performance-critical paths and may need to be optimized, but initially, we're playing it safe. Why is there sometimes #ifdef CONFIG_PPC_47x, sometimes not, and never the cputable infrastructure which was intended for this sort of thing? The places without an ifdef are either in cpu initialization code, where the cost of an isync is insignificant or, in one case, in 47x-specific code. I was having problems trying to get the cputable infrastructure compiling in inline assembly in the *.c files, but I could have used that in some places. Currently, one can't build with CONFIG_PPC_47x for a non-47x cpu, and we want to re-evaluate whether we can get by without these isyncs. So basically, I plan to clean this up somehow by the time we have a working unified 44x/47x binary kernel. Thanks, Shaggy -- David Kleikamp IBM Linux Technology Center ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [RFC: PATCH 08/13] powerpc/476: define specific cpu table entry for DD1 and DD1.1 cores
On Fri, 2010-03-05 at 03:15 -0600, Kumar Gala wrote: On Mar 4, 2010, at 11:06 AM, Hollis Blanchard wrote: On Mon, Mar 1, 2010 at 11:13 AM, Dave Kleikamp sha...@linux.vnet.ibm.com wrote: powerpc/476: define specific cpu table entry for DD1 and DD1.1 cores From: Benjamin Herrenschmidt b...@kernel.crashing.org There are still some unstable bits on the DD1 and DD1.1 cores. Don't use the FPU or the tlbivax operation. Define CPU_FTR_476_DD1 and CPU_FTR_476_DD1_1 for additional workarounds in later patches. The DD1 core requires workarounds triggered by both CPU_FTR_476_DD1 and CPU_FTR_476_DD1_1. the DD1.1 core only needs CPU_FTR_476_DD1_1 defined. Isn't the policy generally not to commit workarounds for early/errataful hardware which will not be seen in the real world? Otherwise, every new half-broken core could burn a bunch of feature bits... -Hollis I'm with Hollis. Cluttering the code with non-production errata could get very ugly as well as burning feature bits up like made. Ben's going to make the decision on whether or not these patches should be included into mainline. I'd be happy maintaining them separately if not. I'm separating out the DD1 workaround from the others, since it's less likely that one will be needed long-term. Thanks, Shaggy -- David Kleikamp IBM Linux Technology Center ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 02/13] powerpc/44x: break out cpu init code into stand-alone function
powerpc/44x: break out cpu init code into stand-alone function From: Dave Kleikamp sha...@linux.vnet.ibm.com The 47x platform supports multiple cores and shares code with 44x. Break out code that is common for initializing the primary and secondary cpus into a function which can be called for both. Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com --- arch/powerpc/kernel/head_44x.S | 330 +--- 1 files changed, 171 insertions(+), 159 deletions(-) diff --git a/arch/powerpc/kernel/head_44x.S b/arch/powerpc/kernel/head_44x.S index 711368b..39be049 100644 --- a/arch/powerpc/kernel/head_44x.S +++ b/arch/powerpc/kernel/head_44x.S @@ -69,165 +69,7 @@ _ENTRY(_start); mr r27,r7 li r24,0 /* CPU number */ -/* - * In case the firmware didn't do it, we apply some workarounds - * that are good for all 440 core variants here - */ - mfspr r3,SPRN_CCR0 - rlwinm r3,r3,0,0,27/* disable icache prefetch */ - isync - mtspr SPRN_CCR0,r3 - isync - sync - -/* - * Set up the initial MMU state - * - * We are still executing code at the virtual address - * mappings set by the firmware for the base of RAM. - * - * We first invalidate all TLB entries but the one - * we are running from. We then load the KERNELBASE - * mappings so we can begin to use kernel addresses - * natively and so the interrupt vector locations are - * permanently pinned (necessary since Book E - * implementations always have translation enabled). - * - * TODO: Use the known TLB entry we are running from to - * determine which physical region we are located - * in. This can be used to determine where in RAM - * (on a shared CPU system) or PCI memory space - * (on a DRAMless system) we are located. - * For now, we assume a perfect world which means - * we are located at the base of DRAM (physical 0). - */ - -/* - * Search TLB for entry that we are currently using. - * Invalidate all entries but the one we are using. - */ - /* Load our current PID-MMUCR TID and MSR IS-MMUCR STS */ - mfspr r3,SPRN_PID /* Get PID */ - mfmsr r4 /* Get MSR */ - andi. r4,r4,msr...@l /* TS=1? */ - beq wmmucr /* If not, leave STS=0 */ - orisr3,r3,ppc44x_mmucr_...@h/* Set STS=1 */ -wmmucr:mtspr SPRN_MMUCR,r3 /* Put MMUCR */ - sync - - bl invstr /* Find our address */ -invstr:mflrr5 /* Make it accessible */ - tlbsx r23,0,r5/* Find entry we are in */ - li r4,0/* Start at TLB entry 0 */ - li r3,0/* Set PAGEID inval value */ -1: cmpwr23,r4 /* Is this our entry? */ - beq skpinv /* If so, skip the inval */ - tlbwe r3,r4,PPC44x_TLB_PAGEID /* If not, inval the entry */ -skpinv:addir4,r4,1 /* Increment */ - cmpwi r4,64 /* Are we done? */ - bne 1b /* If not, repeat */ - isync /* If so, context change */ - -/* - * Configure and load pinned entry into TLB slot 63. - */ - - lis r3,page_off...@h - ori r3,r3,page_off...@l - - /* Kernel is at the base of RAM */ - li r4, 0/* Load the kernel physical address */ - - /* Load the kernel PID = 0 */ - li r0,0 - mtspr SPRN_PID,r0 - sync - - /* Initialize MMUCR */ - li r5,0 - mtspr SPRN_MMUCR,r5 - sync - - /* pageid fields */ - clrrwi r3,r3,10/* Mask off the effective page number */ - ori r3,r3,PPC44x_TLB_VALID | PPC44x_TLB_256M - - /* xlat fields */ - clrrwi r4,r4,10/* Mask off the real page number */ - /* ERPN is 0 for first 4GB page */ - - /* attrib fields */ - /* Added guarded bit to protect against speculative loads/stores */ - li r5,0 - ori r5,r5,(PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX | PPC44x_TLB_G) - -li r0,63/* TLB slot 63 */ - - tlbwe r3,r0,PPC44x_TLB_PAGEID /* Load the pageid fields */ - tlbwe r4,r0,PPC44x_TLB_XLAT /* Load the translation fields */ - tlbwe r5,r0,PPC44x_TLB_ATTRIB /* Load the attrib/access fields */ - - /* Force context change */ - mfmsr r0 - mtspr SPRN_SRR1, r0 - lis r0,3...@h - ori r0,r0,3...@l - mtspr SPRN_SRR0,r0 - sync - rfi - - /* If necessary, invalidate original entry we used */ -3: cmpwi
[PATCH 03/13] powerpc/47x: Base ppc476 support
powerpc/47x: Base ppc476 support
From: Dave Kleikamp sha...@linux.vnet.ibm.com
This patch adds the base support for the 476 processor. The code was
primarily written by Ben Herrenschmidt and Torez Smith, but I've been
maintaining it for a while.
The goal is to have a single binary that will run on 44x and 47x, but
we still have some details to work out. The biggest is that the L1 cache
line size differs on the two platforms, but it's currently a compile-time
option.
Signed-off-by: Benjamin Herrenschmidt b...@kernel.crashing.org
Signed-off-by: Torez Smith lnxto...@linux.vnet.ibm.com
Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/cache.h |6
arch/powerpc/include/asm/cputable.h|4
arch/powerpc/include/asm/mmu-44x.h | 51 +++
arch/powerpc/include/asm/mmu.h |1
arch/powerpc/include/asm/reg.h |1
arch/powerpc/include/asm/reg_booke.h | 26 ++
arch/powerpc/kernel/cputable.c | 13 +
arch/powerpc/kernel/entry_32.S |5
arch/powerpc/kernel/head_44x.S | 502 +++-
arch/powerpc/kernel/misc_32.S |9 -
arch/powerpc/kernel/smp.c |8 +
arch/powerpc/mm/44x_mmu.c | 144 +
arch/powerpc/mm/mmu_context_nohash.c |8 +
arch/powerpc/mm/mmu_decl.h |7
arch/powerpc/mm/tlb_nohash_low.S | 118 +++-
arch/powerpc/platforms/44x/Kconfig |9 +
arch/powerpc/platforms/Kconfig.cputype |5
17 files changed, 873 insertions(+), 44 deletions(-)
diff --git a/arch/powerpc/include/asm/cache.h b/arch/powerpc/include/asm/cache.h
index 81de6eb..725634f 100644
--- a/arch/powerpc/include/asm/cache.h
+++ b/arch/powerpc/include/asm/cache.h
@@ -12,8 +12,12 @@
#define L1_CACHE_SHIFT 6
#define MAX_COPY_PREFETCH 4
#elif defined(CONFIG_PPC32)
-#define L1_CACHE_SHIFT 5
#define MAX_COPY_PREFETCH 4
+#if defined(CONFIG_PPC_47x)
+#define L1_CACHE_SHIFT 7
+#else
+#define L1_CACHE_SHIFT 5
+#endif
#else /* CONFIG_PPC64 */
#define L1_CACHE_SHIFT 7
#endif
diff --git a/arch/powerpc/include/asm/cputable.h
b/arch/powerpc/include/asm/cputable.h
index 80f315e..75b774e 100644
--- a/arch/powerpc/include/asm/cputable.h
+++ b/arch/powerpc/include/asm/cputable.h
@@ -365,6 +365,7 @@ extern const char *powerpc_base_platform;
#define CPU_FTRS_44X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN |
CPU_FTR_NOEXECUTE)
#define CPU_FTRS_440x6 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN |
CPU_FTR_NOEXECUTE | \
CPU_FTR_INDEXED_DCR)
+#define CPU_FTRS_47X (CPU_FTRS_440x6)
#define CPU_FTRS_E200 (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \
CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \
CPU_FTR_UNIFIED_ID_CACHE | CPU_FTR_NOEXECUTE)
@@ -453,6 +454,9 @@ enum {
#ifdef CONFIG_44x
CPU_FTRS_44X | CPU_FTRS_440x6 |
#endif
+#ifdef CONFIG_PPC_47x
+ CPU_FTRS_47X |
+#endif
#ifdef CONFIG_E200
CPU_FTRS_E200 |
#endif
diff --git a/arch/powerpc/include/asm/mmu-44x.h
b/arch/powerpc/include/asm/mmu-44x.h
index 0372669..bf52d70 100644
--- a/arch/powerpc/include/asm/mmu-44x.h
+++ b/arch/powerpc/include/asm/mmu-44x.h
@@ -40,7 +40,7 @@
#define PPC44x_TLB_I 0x0400 /* Caching is inhibited */
#define PPC44x_TLB_M 0x0200 /* Memory is coherent */
#define PPC44x_TLB_G 0x0100 /* Memory is guarded */
-#define PPC44x_TLB_E 0x0080 /* Memory is guarded */
+#define PPC44x_TLB_E 0x0080 /* Memory is little endian */
#define PPC44x_TLB_PERM_MASK 0x003f
#define PPC44x_TLB_UX 0x0020 /* User execution */
@@ -53,6 +53,52 @@
/* Number of TLB entries */
#define PPC44x_TLB_SIZE64
+/* 47x bits */
+#define PPC47x_MMUCR_TID 0x
+#define PPC47x_MMUCR_STS 0x0001
+
+/* Page identification fields */
+#define PPC47x_TLB0_EPN_MASK 0xf000 /* Effective Page Number */
+#define PPC47x_TLB0_VALID 0x0800 /* Valid flag */
+#define PPC47x_TLB0_TS 0x0400 /* Translation address space */
+#define PPC47x_TLB0_4K 0x
+#define PPC47x_TLB0_16K0x0010
+#define PPC47x_TLB0_64K0x0030
+#define PPC47x_TLB0_1M 0x0070
+#define PPC47x_TLB0_16M0x00f0
+#define PPC47x_TLB0_256M 0x01f0
+#define PPC47x_TLB0_1G 0x03f0
+#define PPC47x_TLB0_BOLTED_R 0x0008 /* tlbre only */
+
+/* Translation fields */
+#define PPC47x_TLB1_RPN_MASK 0xf000 /* Real Page Number */
+#define PPC47x_TLB1_ERPN_MASK 0x03ff
+
+/* Storage attribute and access control fields */
+#define PPC47x_TLB2_ATTR_MASK 0x0003ff80
+#define PPC47x_TLB2_IL1I 0x0002 /* Memory is guarded */
+#define PPC47x_TLB2_IL1D 0x0001 /* Memory is guarded */
+#define PPC47x_TLB2_U0
[PATCH 01/13] powerpc/booke: Add Stack Marking support to Booke Exception Prolog
powerpc/booke: Add Stack Marking support to Booke Exception Prolog From: Torez Smith lnxto...@linux.vnet.ibm.com This patch adds a marker to the exception stack frame to aid in debugging. It's already inserted on other platforms and xmon recognizes it and identifies exception frames when showing stack traces. Signed-off-by: Torez Smith lnxto...@linux.vnet.ibm.com Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com --- arch/powerpc/kernel/head_booke.h |4 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/kernel/head_booke.h b/arch/powerpc/kernel/head_booke.h index 50504ae..a0bf158 100644 --- a/arch/powerpc/kernel/head_booke.h +++ b/arch/powerpc/kernel/head_booke.h @@ -1,6 +1,7 @@ #ifndef __HEAD_BOOKE_H__ #define __HEAD_BOOKE_H__ +#include asm/ptrace.h/* for STACK_FRAME_REGS_MARKER */ /* * Macros used for common Book-e exception handling */ @@ -48,6 +49,9 @@ stw r10,0(r11); \ rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\ stw r0,GPR0(r11);\ + lis r10, stack_frame_regs_mar...@ha;/* exception frame marker */ \ + addir10, r10, stack_frame_regs_mar...@l; \ + stw r10, 8(r11); \ SAVE_4GPRS(3, r11); \ SAVE_2GPRS(7, r11) -- Dave Kleikamp IBM Linux Technology Center ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 05/13] powerpc/476: Add isync after loading mmu and debug spr's
powerpc/476: Add isync after loading mmu and debug spr's
From: Dave Kleikamp sha...@linux.vnet.ibm.com
476 requires an isync after loading MMU and debug related SPR's. Some of
these are in performance-critical paths and may need to be optimized, but
initially, we're playing it safe.
Signed-off-by: Torez Smith lnxto...@linux.vnet.ibm.com
Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com
---
arch/powerpc/kernel/head_44x.S |8
arch/powerpc/kernel/kprobes.c|3 +++
arch/powerpc/kernel/process.c|3 +++
arch/powerpc/kernel/traps.c |6 ++
arch/powerpc/mm/44x_mmu.c|1 +
arch/powerpc/mm/tlb_nohash_low.S |3 +++
6 files changed, 24 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/kernel/head_44x.S b/arch/powerpc/kernel/head_44x.S
index 1acd175..992e9d5 100644
--- a/arch/powerpc/kernel/head_44x.S
+++ b/arch/powerpc/kernel/head_44x.S
@@ -464,6 +464,9 @@ finish_tlb_load_44x:
lwz r11,PGDIR(r11)
mfspr r12,SPRN_PID/* Get PID */
4: mtspr SPRN_MMUCR,r12 /* Set MMUCR */
+#ifdef CONFIG_PPC_47x
+ isync
+#endif
/* Mask of required permission bits. Note that while we
* do copy ESR:ST to _PAGE_RW position as trying to write
@@ -561,6 +564,9 @@ finish_tlb_load_44x:
lwz r11,PGDIR(r11)
mfspr r12,SPRN_PID/* Get PID */
4: mtspr SPRN_MMUCR,r12 /* Set MMUCR */
+#ifdef CONFIG_PPC_47x
+ isync
+#endif
/* Make up the required permissions */
li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
@@ -1031,6 +1037,7 @@ clear_utlb_entry:
mtspr SPRN_USPCR,r3
LOAD_REG_IMMEDIATE(r3, 0x12345670)
mtspr SPRN_ISPCR,r3
+ isync /* 476 needs this */
/* Force context change */
mfmsr r0
@@ -1116,6 +1123,7 @@ head_start_common:
/* Establish the interrupt vector base */
lis r4,interrupt_b...@h /* IVPR only uses the high 16-bits */
mtspr SPRN_IVPR,r4
+ isync /* 476 needs this */
addis r22,r22,kernelb...@h
mtlrr22
diff --git a/arch/powerpc/kernel/kprobes.c b/arch/powerpc/kernel/kprobes.c
index c932978..7fec5db 100644
--- a/arch/powerpc/kernel/kprobes.c
+++ b/arch/powerpc/kernel/kprobes.c
@@ -113,6 +113,9 @@ static void __kprobes prepare_singlestep(struct kprobe *p,
struct pt_regs *regs)
#ifdef CONFIG_BOOKE
regs-msr = ~MSR_CE;
mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) | DBCR0_IC | DBCR0_IDM);
+#ifdef CONFIG_PPC_47x
+ isync();
+#endif
#endif
/*
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index 7b816da..15ee756 100644
--- a/arch/powerpc/kernel/process.c
+++ b/arch/powerpc/kernel/process.c
@@ -286,6 +286,9 @@ int set_dabr(unsigned long dabr)
/* XXX should we have a CPU_FTR_HAS_DABR ? */
#if defined(CONFIG_BOOKE)
mtspr(SPRN_DAC1, dabr);
+#ifdef CONFIG_PPC_47x
+ isync();
+#endif
#elif defined(CONFIG_PPC_BOOK3S)
mtspr(SPRN_DABR, dabr);
#endif
diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
index 21ed77b..9957c44 100644
--- a/arch/powerpc/kernel/traps.c
+++ b/arch/powerpc/kernel/traps.c
@@ -1080,6 +1080,9 @@ void __kprobes DebugException(struct pt_regs *regs,
unsigned long debug_status)
mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) ~DBCR0_BT);
/* Clear the BT event */
mtspr(SPRN_DBSR, DBSR_BT);
+#ifdef CONFIG_PPC_47x
+ isync();
+#endif
/* Do the single step trick only when coming from userspace */
if (user_mode(regs)) {
@@ -1102,6 +1105,9 @@ void __kprobes DebugException(struct pt_regs *regs,
unsigned long debug_status)
mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) ~DBCR0_IC);
/* Clear the instruction completion event */
mtspr(SPRN_DBSR, DBSR_IC);
+#ifdef CONFIG_PPC_47x
+ isync();
+#endif
if (notify_die(DIE_SSTEP, single_step, regs, 5,
5, SIGTRAP) == NOTIFY_STOP) {
diff --git a/arch/powerpc/mm/44x_mmu.c b/arch/powerpc/mm/44x_mmu.c
index d8c6efb..a5f082a 100644
--- a/arch/powerpc/mm/44x_mmu.c
+++ b/arch/powerpc/mm/44x_mmu.c
@@ -156,6 +156,7 @@ static void __cpuinit ppc47x_pin_tlb(unsigned int virt,
unsigned int phys)
virt, phys, bolted);
mtspr(SPRN_MMUCR, 0);
+ isync();
__asm__ __volatile__(
tlbwe %2,%3,0\n
diff --git a/arch/powerpc/mm/tlb_nohash_low.S b/arch/powerpc/mm/tlb_nohash_low.S
index e925cb5..7c890f7 100644
--- a/arch/powerpc/mm/tlb_nohash_low.S
+++ b/arch/powerpc/mm/tlb_nohash_low.S
@@ -92,6 +92,9 @@ _GLOBAL(__tlbil_va)
*/
wrteei 0
mtspr SPRN_MMUCR,r5
+#ifdef CONFIG_PPC_47x
+ isync
+#endif
tlbsx. r6,0,r3
bne 10f
sync
--
Dave Kleikamp
IBM Linux Technology Center
[PATCH 07/13] powerpc/47x: defconfig for 476 on the iss 4xx simulator
powerpc/47x: defconfig for 476 on the iss 4xx simulator From: Dave Kleikamp sha...@linux.vnet.ibm.com Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com --- arch/powerpc/configs/44x/iss476-smp_defconfig | 1026 + 1 files changed, 1026 insertions(+), 0 deletions(-) create mode 100644 arch/powerpc/configs/44x/iss476-smp_defconfig diff --git a/arch/powerpc/configs/44x/iss476-smp_defconfig b/arch/powerpc/configs/44x/iss476-smp_defconfig new file mode 100644 index 000..8683cbc --- /dev/null +++ b/arch/powerpc/configs/44x/iss476-smp_defconfig @@ -0,0 +1,1026 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.33 +# Thu Mar 4 11:50:12 2010 +# +# CONFIG_PPC64 is not set + +# +# Processor support +# +# CONFIG_PPC_BOOK3S_32 is not set +# CONFIG_PPC_85xx is not set +# CONFIG_PPC_8xx is not set +# CONFIG_40x is not set +CONFIG_44x=y +# CONFIG_E200 is not set +CONFIG_PPC_FPU=y +CONFIG_4xx=y +CONFIG_BOOKE=y +CONFIG_PTE_64BIT=y +CONFIG_PHYS_64BIT=y +CONFIG_PPC_MMU_NOHASH=y +CONFIG_PPC_MMU_NOHASH_32=y +# CONFIG_PPC_MM_SLICES is not set +CONFIG_SMP=y +CONFIG_NR_CPUS=4 +# CONFIG_NOT_COHERENT_CACHE is not set +CONFIG_PPC32=y +CONFIG_WORD_SIZE=32 +CONFIG_ARCH_PHYS_ADDR_T_64BIT=y +CONFIG_MMU=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set +# CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK is not set +CONFIG_IRQ_PER_CPU=y +CONFIG_NR_IRQS=512 +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +CONFIG_ARCH_HAS_ILOG2_U32=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_FIND_NEXT_BIT=y +# CONFIG_ARCH_NO_VIRT_TO_BUS is not set +CONFIG_PPC=y +CONFIG_EARLY_PRINTK=y +CONFIG_GENERIC_NVRAM=y +CONFIG_SCHED_OMIT_FRAME_POINTER=y +CONFIG_ARCH_MAY_HAVE_PC_FDC=y +CONFIG_PPC_OF=y +CONFIG_OF=y +CONFIG_PPC_UDBG_16550=y +CONFIG_GENERIC_TBSYNC=y +CONFIG_AUDIT_ARCH=y +CONFIG_GENERIC_BUG=y +CONFIG_DTC=y +# CONFIG_DEFAULT_UIMAGE is not set +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_PPC_DCR_NATIVE=y +# CONFIG_PPC_DCR_MMIO is not set +CONFIG_PPC_DCR=y +CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y +CONFIG_DEFCONFIG_LIST=/lib/modules/$UNAME_RELEASE/.config +CONFIG_CONSTRUCTORS=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION= +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_TINY_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_GROUP_SCHED=y +CONFIG_FAIR_GROUP_SCHED=y +# CONFIG_RT_GROUP_SCHED is not set +CONFIG_USER_SCHED=y +# CONFIG_CGROUP_SCHED is not set +# CONFIG_CGROUPS is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +# CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE= +CONFIG_RD_GZIP=y +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_RD_LZO is not set +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EMBEDDED=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_ALL=y +CONFIG_KALLSYMS_EXTRA_PASS=y +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_HAVE_PERF_EVENTS=y + +# +# Kernel Performance Events And Counters +# +CONFIG_PERF_EVENTS=y +CONFIG_EVENT_PROFILE=y +# CONFIG_PERF_COUNTERS is not set +# CONFIG_DEBUG_PERF_USE_VMALLOC is not set +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +CONFIG_PROFILING=y +CONFIG_TRACEPOINTS=y +CONFIG_OPROFILE=y +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_HAVE_IOREMAP_PROT=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_USE_GENERIC_SMP_HELPERS=y +CONFIG_HAVE_DMA_API_DEBUG=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +# CONFIG_SLOW_WORK is not set +# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set
[PATCH 08/13] powerpc/476: define specific cpu table entry DD1.1 core
powerpc/476: define specific cpu table entry DD1.1 core
From: Benjamin Herrenschmidt b...@kernel.crashing.org
There are still some unstable bits in the DD1.1 cores. Don't use
the FPU or the tlbivax operation. Define CPU_FTR_476_DD1_1 for additional
workarounds in later patches.
The DD1 core requires an additional workaround that will be addressed
in a separate patch, which may not need to be picked up into the
mainline kernel.
Signed-off-by: Benjamin Herrenschmidt b...@kernel.crashing.org
Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/cputable.h |1 +
arch/powerpc/kernel/cputable.c | 26 --
2 files changed, 21 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/include/asm/cputable.h
b/arch/powerpc/include/asm/cputable.h
index 9fff628..7c5d490 100644
--- a/arch/powerpc/include/asm/cputable.h
+++ b/arch/powerpc/include/asm/cputable.h
@@ -153,6 +153,7 @@ extern const char *powerpc_base_platform;
#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x2000)
#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x4000)
#define CPU_FTR_NO_DPM ASM_CONST(0x8000)
+#define CPU_FTR_476_DD1_1 ASM_CONST(0x0001)
#define CPU_FTR_NEED_COHERENT ASM_CONST(0x0002)
#define CPU_FTR_NO_BTICASM_CONST(0x0004)
#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0010)
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index a06e6d3..cb9e6b7 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -1701,15 +1701,15 @@ static struct cpu_spec __initdata cpu_specs[] = {
.machine_check = machine_check_440A,
.platform = ppc440,
},
- { /* 476 core */
+ { /* 476 DD1.1 core */
.pvr_mask = 0x,
- .pvr_value = 0x11a5,
+ .pvr_value = 0x11a52040,
.cpu_name = 476,
- .cpu_features = CPU_FTRS_47X,
- .cpu_user_features = COMMON_USER_BOOKE |
- PPC_FEATURE_HAS_FPU,
+ .cpu_features = CPU_FTRS_47X | CPU_FTR_476_DD1_1 |
+ CPU_FTR_FPU_UNAVAILABLE,
+ .cpu_user_features = COMMON_USER_BOOKE,
.mmu_features = MMU_FTR_TYPE_47x |
- MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_LOCK_BCAST_INVAL,
+ MMU_FTR_LOCK_BCAST_INVAL,
.icache_bsize = 32,
.dcache_bsize = 128,
.machine_check = machine_check_47x,
@@ -1724,6 +1724,20 @@ static struct cpu_spec __initdata cpu_specs[] = {
PPC_FEATURE_HAS_FPU,
.cpu_user_features = COMMON_USER_BOOKE,
.mmu_features = MMU_FTR_TYPE_47x |
+ MMU_FTR_LOCK_BCAST_INVAL,
+ .icache_bsize = 32,
+ .dcache_bsize = 128,
+ .machine_check = machine_check_47x,
+ .platform = ppc470,
+ },
+ { /* 476 others */
+ .pvr_mask = 0x,
+ .pvr_value = 0x11a52000,
+ .cpu_name = 476,
+ .cpu_features = CPU_FTRS_47X,
+ .cpu_user_features = COMMON_USER_BOOKE |
+ PPC_FEATURE_HAS_FPU,
+ .mmu_features = MMU_FTR_TYPE_47x |
MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_LOCK_BCAST_INVAL,
.icache_bsize = 32,
.dcache_bsize = 128,
--
Dave Kleikamp
IBM Linux Technology Center
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[PATCH 06/13] powerpc/4xx: Simple platform for the ISS 4xx simulator
powerpc/4xx: Simple platform for the ISS 4xx simulator
From: Torez Smith lnxto...@linux.vnet.ibm.com
This is a trivial 4xx plaform that uses the new simple bsp from
Josh and is handy to use in simulators such as ISS or even Mambo
who don't properly implement most of the actual devices in the
SoC but really only the core.
Signed-off-by: Torez Smith lnxto...@linux.vnet.ibm.com
Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com
---
arch/powerpc/boot/Makefile|5 +
arch/powerpc/boot/dts/iss4xx-mpic.dts | 155 +++
arch/powerpc/boot/dts/iss4xx.dts | 116 +++
arch/powerpc/boot/treeboot-iss4xx.c | 56 +++
arch/powerpc/boot/wrapper |3 +
arch/powerpc/include/asm/reg.h|3 +
arch/powerpc/kernel/cputable.c| 15 +++
arch/powerpc/kernel/head_44x.S|2
arch/powerpc/platforms/44x/Kconfig| 11 ++
arch/powerpc/platforms/44x/Makefile |1
arch/powerpc/platforms/44x/iss4xx.c | 165 +
11 files changed, 531 insertions(+), 1 deletions(-)
create mode 100644 arch/powerpc/boot/dts/iss4xx-mpic.dts
create mode 100644 arch/powerpc/boot/dts/iss4xx.dts
create mode 100644 arch/powerpc/boot/treeboot-iss4xx.c
create mode 100644 arch/powerpc/platforms/44x/iss4xx.c
diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile
index bb2465b..997196e 100644
--- a/arch/powerpc/boot/Makefile
+++ b/arch/powerpc/boot/Makefile
@@ -44,6 +44,7 @@ $(obj)/cuboot-taishan.o: BOOTCFLAGS += -mcpu=405
$(obj)/cuboot-katmai.o: BOOTCFLAGS += -mcpu=405
$(obj)/cuboot-acadia.o: BOOTCFLAGS += -mcpu=405
$(obj)/treeboot-walnut.o: BOOTCFLAGS += -mcpu=405
+$(obj)/treeboot-iss4xx.o: BOOTCFLAGS += -mcpu=405
$(obj)/virtex405-head.o: BOOTAFLAGS += -mcpu=405
@@ -77,7 +78,7 @@ src-plat := of.c cuboot-52xx.c cuboot-824x.c cuboot-83xx.c
cuboot-85xx.c holly.c
cuboot-warp.c cuboot-85xx-cpm2.c cuboot-yosemite.c simpleboot.c
\
virtex405-head.S virtex.c redboot-83xx.c cuboot-sam440ep.c \
cuboot-acadia.c cuboot-amigaone.c cuboot-kilauea.c \
- gamecube-head.S gamecube.c wii-head.S wii.c
+ gamecube-head.S gamecube.c wii-head.S wii.c treeboot-iss4xx.c
src-boot := $(src-wlib) $(src-plat) empty.c
src-boot := $(addprefix $(obj)/, $(src-boot))
@@ -206,6 +207,8 @@ image-$(CONFIG_TAISHAN) +=
cuImage.taishan
image-$(CONFIG_KATMAI) += cuImage.katmai
image-$(CONFIG_WARP) += cuImage.warp
image-$(CONFIG_YOSEMITE) += cuImage.yosemite
+image-$(CONFIG_ISS4xx) += treeImage.iss4xx \
+ treeImage.iss4xx-mpic
# Board ports in arch/powerpc/platform/8xx/Kconfig
image-$(CONFIG_MPC86XADS) += cuImage.mpc866ads
diff --git a/arch/powerpc/boot/dts/iss4xx-mpic.dts
b/arch/powerpc/boot/dts/iss4xx-mpic.dts
new file mode 100644
index 000..23e9d9b
--- /dev/null
+++ b/arch/powerpc/boot/dts/iss4xx-mpic.dts
@@ -0,0 +1,155 @@
+/*
+ * Device Tree Source for IBM Embedded PPC 476 Platform
+ *
+ * Copyright 2010 Torez Smith, IBM Corporation.
+ *
+ * Based on earlier code:
+ * Copyright (c) 2006, 2007 IBM Corp.
+ * Josh Boyer jwbo...@linux.vnet.ibm.com, David Gibson d...@au1.ibm.com
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed as is without
+ * any warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+
+/memreserve/ 0x01f0 0x0010;
+
+/ {
+ #address-cells = 2;
+ #size-cells = 1;
+ model = ibm,iss-4xx;
+ compatible = ibm,iss-4xx;
+ dcr-parent = {/cpus/c...@0};
+
+ aliases {
+ serial0 = UART0;
+ };
+
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ c...@0 {
+ device_type = cpu;
+ model = PowerPC,4xx; // real CPU changed in sim
+ reg = 0;
+ clock-frequency = 1; // 100Mhz :-)
+ timebase-frequency = 1;
+ i-cache-line-size = 32;
+ d-cache-line-size = 32;
+ i-cache-size = 32768;
+ d-cache-size = 32768;
+ dcr-controller;
+ dcr-access-method = native;
+ status = ok;
+ };
+ c...@1 {
+ device_type = cpu;
+ model = PowerPC,4xx; // real CPU changed in sim
+ reg = 1;
+ clock-frequency = 1; // 100Mhz :-)
+ timebase-frequency = 1;
+ i-cache-line-size = 32;
+ d-cache-line-size = 32;
+ i-cache-size = 32768
[PATCH 09/13] powerpc/476: Workaround for dcbf/dcbz workaround on DD1
powerpc/476: Workaround for dcbf/dcbz workaround on DD1 From: Benjamin Herrenschmidt b...@kernel.crashing.org On the DD1.1 core, the dcbf and dcbz instructions need to be preceded and followed by an lwsync. We must trap user-space to ensure that this occurs there too. Signed-off-by: Benjamin Herrenschmidt b...@kernel.crashing.org Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com --- arch/powerpc/include/asm/asm-compat.h | 10 +++ arch/powerpc/include/asm/ppc-opcode.h |4 +++ arch/powerpc/include/asm/reg_booke.h |9 +++ arch/powerpc/kernel/entry_32.S| 35 +++--- arch/powerpc/kernel/head_44x.S|9 +++ arch/powerpc/kernel/misc_32.S | 32 ++- arch/powerpc/kernel/traps.c | 45 + arch/powerpc/lib/copy_32.S|7 - 8 files changed, 145 insertions(+), 6 deletions(-) diff --git a/arch/powerpc/include/asm/asm-compat.h b/arch/powerpc/include/asm/asm-compat.h index 8f0fe79..bee05ec 100644 --- a/arch/powerpc/include/asm/asm-compat.h +++ b/arch/powerpc/include/asm/asm-compat.h @@ -64,6 +64,16 @@ #define PPC405_ERR77(ra,rb) #define PPC405_ERR77_SYNC #endif + +#ifdef CONFIG_PPC_47x +#define PPC476_ERR_DCBx() \ + BEGIN_FTR_SECTION; \ + lwsync; \ + END_FTR_SECTION_IFSET(CPU_FTR_476_DD1_1) +#else +#define PPC476_ERR_DCBx() +#endif /* CONFIG_PPC_47x */ + #endif #endif /* _ASM_POWERPC_ASM_COMPAT_H */ diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h index ef9aa84..629b1fe 100644 --- a/arch/powerpc/include/asm/ppc-opcode.h +++ b/arch/powerpc/include/asm/ppc-opcode.h @@ -19,6 +19,10 @@ #define PPC_INST_DCBA 0x7c0005ec #define PPC_INST_DCBA_MASK 0xfc0007fe #define PPC_INST_DCBAL 0x7c2005ec +#define PPC_INST_DCBF 0x7cac +#define PPC_INST_DCBF_MASK 0xfc0007fe +#define PPC_INST_DCBZ 0x7c0007ec +#define PPC_INST_DCBZ_MASK 0xfc0007fe #define PPC_INST_DCBZL 0x7c2007ec #define PPC_INST_ISEL 0x7c1e #define PPC_INST_ISEL_MASK 0xfc3e diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h index ee61a9d..8153093 100644 --- a/arch/powerpc/include/asm/reg_booke.h +++ b/arch/powerpc/include/asm/reg_booke.h @@ -276,6 +276,8 @@ #define ESR_IMCN 0x4000 /* Instr. Machine Check - Non-config */ #define ESR_IMCB 0x2000 /* Instr. Machine Check - Bus error */ #define ESR_IMCT 0x1000 /* Instr. Machine Check - Timeout */ +#define ESR_POT1 0x2000 /* 476 - IOCR1 trap */ +#define ESR_POT2 0x1000 /* 476 - IOCR2 trap */ #define ESR_PIL0x0800 /* Program Exception - Illegal */ #define ESR_PPR0x0400 /* Program Exception - Privileged */ #define ESR_PTR0x0200 /* Program Exception - Trap */ @@ -535,6 +537,13 @@ #define MMUBE1_VBE30x0004 #define MMUBE1_VBE40x0002 #define MMUBE1_VBE50x0001 +#define SPRN_IOCCR 860 +#defineIOCCR_IOCR1EN 0x8000 +#defineIOCCR_IOCR1M0x4000 +#defineIOCCR_IOCR2EN 0x2000 +#defineIOCCR_IOCR2M0x1000 +#define SPRN_IOCR1 861 +#define SPRN_IOCR2 862 #endif /* __ASM_POWERPC_REG_BOOKE_H__ */ #endif /* __KERNEL__ */ diff --git a/arch/powerpc/kernel/entry_32.S b/arch/powerpc/kernel/entry_32.S index ed4aeb9..57b7893 100644 --- a/arch/powerpc/kernel/entry_32.S +++ b/arch/powerpc/kernel/entry_32.S @@ -142,6 +142,12 @@ transfer_to_handler: addir2,r12,-THREAD tovirt(r2,r2) /* set r2 to current */ beq 2f /* if from user, fix up THREAD.regs */ +#ifdef CONFIG_PPC_47x +BEGIN_FTR_SECTION + li r11,0 + mtspr SPRN_IOCCR,r11 +END_FTR_SECTION_IFSET(CPU_FTR_476_DD1_1) +#endif /* CONFIG_PPC_47x */ addir11,r1,STACK_FRAME_OVERHEAD stw r11,PT_REGS(r12) #if defined(CONFIG_40x) || defined(CONFIG_BOOKE) @@ -280,6 +286,12 @@ stack_ovf: 0: _GLOBAL(DoSyscall) +#ifdef CONFIG_PPC_47x +BEGIN_FTR_SECTION + li r11,0 + mtspr SPRN_IOCCR,r11 +END_FTR_SECTION_IFSET(CPU_FTR_476_DD1_1) +#endif /* CONFIG_PPC_47x */ stw r3,ORIG_GPR3(r1) li r12,0 stw r12,RESULT(r1) @@ -381,6 +393,16 @@ BEGIN_MMU_FTR_SECTION 1: END_MMU_FTR_SECTION_IFCLR(MMU_FTR_TYPE_47x) #endif /* CONFIG_44x */ +#ifdef CONFIG_PPC_47x +BEGIN_FTR_SECTION + lwz r7,_MSR(r1) + andi. r5,r7,MSR_PR + beq 11f + lis r4,(IOCCR_IOCR1EN|IOCCR_IOCR2EN)@h + mtspr SPRN_IOCCR
[PATCH 10/13] powerpc/476: Add isync to the top of all exception handlers for DD1.1 core
powerpc/476: Add isync to the top of all exception handlers for DD1.1 core From: Dave Kleikamp sha...@linux.vnet.ibm.com Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com --- arch/powerpc/include/asm/asm-compat.h |7 ++- arch/powerpc/kernel/head_booke.h |3 ++- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/include/asm/asm-compat.h b/arch/powerpc/include/asm/asm-compat.h index bee05ec..1890fbf 100644 --- a/arch/powerpc/include/asm/asm-compat.h +++ b/arch/powerpc/include/asm/asm-compat.h @@ -70,8 +70,13 @@ BEGIN_FTR_SECTION; \ lwsync; \ END_FTR_SECTION_IFSET(CPU_FTR_476_DD1_1) -#else +#define PPC476_ERR_ISYNC() \ + BEGIN_FTR_SECTION; \ + isync; \ + END_FTR_SECTION_IFSET(CPU_FTR_476_DD1_1) +#else /* ! CONFIG_PPC_47x */ #define PPC476_ERR_DCBx() +#define PPC476_ERR_ISYNC() #endif /* CONFIG_PPC_47x */ #endif diff --git a/arch/powerpc/kernel/head_booke.h b/arch/powerpc/kernel/head_booke.h index a0bf158..c6f5dcd 100644 --- a/arch/powerpc/kernel/head_booke.h +++ b/arch/powerpc/kernel/head_booke.h @@ -164,7 +164,8 @@ */ #defineSTART_EXCEPTION(label) \ .align 5; \ -label: +label: \ + PPC476_ERR_ISYNC() #define FINISH_EXCEPTION(func) \ bl transfer_to_handler_full; \ -- Dave Kleikamp IBM Linux Technology Center ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 11/13] powerpc/476: Software workaround to fix dcr read/write sequencing.
powerpc/476: Software workaround to fix dcr read/write sequencing.
From: Dave Kleikamp sha...@linux.vnet.ibm.com
Copy the register containing the dcr address to a spr before mfdcrx or
mtdcrx instruction. SPRN_SPRG_WSCRATCH_CRIT seems safe enough to use
as a dummy register, as it is only otherwise used by critical interrupts,
and we don't care if what we write is overwritten.
Ideally, would only do this when CPU_FTR_476_DD1_1 is set, but I'm not
getting the feature macros working in inlined assembler. The dummy store
is pretty cheap though, so I'm doing it unconditionally for 47x.
Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/dcr-native.h | 24 ++--
1 files changed, 22 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/include/asm/dcr-native.h
b/arch/powerpc/include/asm/dcr-native.h
index 7d2e623..768ce50 100644
--- a/arch/powerpc/include/asm/dcr-native.h
+++ b/arch/powerpc/include/asm/dcr-native.h
@@ -50,14 +50,34 @@ extern unsigned int __mfdcr(unsigned int reg);
static inline unsigned int mfdcrx(unsigned int reg)
{
unsigned int ret;
- asm volatile(.long 0x7c000206 | (%0 21) | (%1 16)
+ asm volatile(
+#ifdef CONFIG_PPC_47x
+ /*
+* Workaround: move reg to an spr prior to mfdcrx instruction
+*/
+/* __stringify(BEGIN_FTR_SECTION) */
+mtspr __stringify(SPRN_SPRG_WSCRATCH_CRIT),%1;
+/* __stringify(END_FTR_SECTION_IFSET(CPU_FTR_476_DD1_1)) */
+#endif
+.long 0x7c000206 | (%0 21) | (%1 16)
: =r (ret) : r (reg));
return ret;
}
static inline void mtdcrx(unsigned int reg, unsigned int val)
{
- asm volatile(.long 0x7c000306 | (%0 21) | (%1 16)
+ asm volatile(
+#ifdef CONFIG_PPC_47x
+ /*
+* Workaround: move reg to an spr prior to mtdcrx instruction.
+* (Would love to get the FTR_SECTION macros working for
+* inlined assembler -- shaggy)
+*/
+/* __stringify(BEGIN_FTR_SECTION) */
+mtspr __stringify(SPRN_SPRG_WSCRATCH_CRIT),%1;
+/* __stringify(END_FTR_SECTION_IFSET(CPU_FTR_476_DD1_1)) */
+#endif
+.long 0x7c000306 | (%0 21) | (%1 16)
: : r (val), r (reg));
}
--
Dave Kleikamp
IBM Linux Technology Center
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[PATCH 12/13] powerpc/476: Workaround for DD1.1: Issue lwsync after mtpid
powerpc/476: Workaround for DD1.1: Issue lwsync after mtpid From: Dave Kleikamp sha...@linux.vnet.ibm.com Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com --- arch/powerpc/include/asm/asm-compat.h |2 ++ arch/powerpc/kernel/head_44x.S|1 + 2 files changed, 3 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/include/asm/asm-compat.h b/arch/powerpc/include/asm/asm-compat.h index 1890fbf..fd16e3a 100644 --- a/arch/powerpc/include/asm/asm-compat.h +++ b/arch/powerpc/include/asm/asm-compat.h @@ -70,12 +70,14 @@ BEGIN_FTR_SECTION; \ lwsync; \ END_FTR_SECTION_IFSET(CPU_FTR_476_DD1_1) +#define PPC476_ERR_MTPID PPC476_ERR_DCBx #define PPC476_ERR_ISYNC() \ BEGIN_FTR_SECTION; \ isync; \ END_FTR_SECTION_IFSET(CPU_FTR_476_DD1_1) #else /* ! CONFIG_PPC_47x */ #define PPC476_ERR_DCBx() +#define PPC476_ERR_MTPID() #define PPC476_ERR_ISYNC() #endif /* CONFIG_PPC_47x */ diff --git a/arch/powerpc/kernel/head_44x.S b/arch/powerpc/kernel/head_44x.S index a96796d..c27b0cd 100644 --- a/arch/powerpc/kernel/head_44x.S +++ b/arch/powerpc/kernel/head_44x.S @@ -705,6 +705,7 @@ _GLOBAL(set_context) stw r4, 0x4(r5) #endif mtspr SPRN_PID,r3 + PPC476_ERR_MTPID() isync /* Force context change */ blr -- Dave Kleikamp IBM Linux Technology Center ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 13/13] powerpc/476: Add dci instruction to async interrupt handlers on DD1 core
powerpc/476: Add dci instruction to async interrupt handlers on DD1 core
From: Dave Kleikamp sha...@linux.vnet.ibm.com
Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/asm-compat.h |5 +
arch/powerpc/include/asm/cputable.h |1 +
arch/powerpc/kernel/cputable.c| 14 ++
arch/powerpc/kernel/head_booke.h |3 +++
4 files changed, 23 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/include/asm/asm-compat.h
b/arch/powerpc/include/asm/asm-compat.h
index fd16e3a..43e9d1b 100644
--- a/arch/powerpc/include/asm/asm-compat.h
+++ b/arch/powerpc/include/asm/asm-compat.h
@@ -71,6 +71,10 @@
lwsync; \
END_FTR_SECTION_IFSET(CPU_FTR_476_DD1_1)
#define PPC476_ERR_MTPID PPC476_ERR_DCBx
+#define PPC476_ERR_DCI() \
+ BEGIN_FTR_SECTION; \
+ dci;\
+ END_FTR_SECTION_IFSET(CPU_FTR_476_DD1)
#define PPC476_ERR_ISYNC() \
BEGIN_FTR_SECTION; \
isync; \
@@ -78,6 +82,7 @@
#else /* ! CONFIG_PPC_47x */
#define PPC476_ERR_DCBx()
#define PPC476_ERR_MTPID()
+#define PPC476_ERR_DCI()
#define PPC476_ERR_ISYNC()
#endif /* CONFIG_PPC_47x */
diff --git a/arch/powerpc/include/asm/cputable.h
b/arch/powerpc/include/asm/cputable.h
index 7c5d490..1cf38fb 100644
--- a/arch/powerpc/include/asm/cputable.h
+++ b/arch/powerpc/include/asm/cputable.h
@@ -156,6 +156,7 @@ extern const char *powerpc_base_platform;
#define CPU_FTR_476_DD1_1 ASM_CONST(0x0001)
#define CPU_FTR_NEED_COHERENT ASM_CONST(0x0002)
#define CPU_FTR_NO_BTICASM_CONST(0x0004)
+#define CPU_FTR_476_DD1ASM_CONST(0x0008)
#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0010)
#define CPU_FTR_PPC_LE ASM_CONST(0x0020)
#define CPU_FTR_REAL_LEASM_CONST(0x0040)
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index cb9e6b7..e91bb2e 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -1701,6 +1701,20 @@ static struct cpu_spec __initdata cpu_specs[] = {
.machine_check = machine_check_440A,
.platform = ppc440,
},
+ { /* 476 DD1 core - needs DD1.1 feature as well */
+ .pvr_mask = 0x,
+ .pvr_value = 0x11a5,
+ .cpu_name = 476,
+ .cpu_features = CPU_FTRS_47X | CPU_FTR_476_DD1 |
+ CPU_FTR_476_DD1_1 | CPU_FTR_FPU_UNAVAILABLE,
+ .cpu_user_features = COMMON_USER_BOOKE,
+ .mmu_features = MMU_FTR_TYPE_47x |
+ MMU_FTR_LOCK_BCAST_INVAL,
+ .icache_bsize = 32,
+ .dcache_bsize = 128,
+ .machine_check = machine_check_47x,
+ .platform = ppc470,
+ },
{ /* 476 DD1.1 core */
.pvr_mask = 0x,
.pvr_value = 0x11a52040,
diff --git a/arch/powerpc/kernel/head_booke.h b/arch/powerpc/kernel/head_booke.h
index c6f5dcd..c8e38c8 100644
--- a/arch/powerpc/kernel/head_booke.h
+++ b/arch/powerpc/kernel/head_booke.h
@@ -174,12 +174,14 @@ label:
\
#define EXCEPTION(n, label, hdlr, xfer)\
START_EXCEPTION(label); \
+ PPC476_ERR_DCI(); \
NORMAL_EXCEPTION_PROLOG;\
addir3,r1,STACK_FRAME_OVERHEAD; \
xfer(n, hdlr)
#define CRITICAL_EXCEPTION(n, label, hdlr) \
START_EXCEPTION(label); \
+ PPC476_ERR_DCI(); \
CRITICAL_EXCEPTION_PROLOG; \
addir3,r1,STACK_FRAME_OVERHEAD; \
EXC_XFER_TEMPLATE(hdlr, n+2, (MSR_KERNEL ~(MSR_ME|MSR_DE|MSR_CE)), \
@@ -379,6 +381,7 @@ label:
\
#define DECREMENTER_EXCEPTION\
START_EXCEPTION(Decrementer) \
+ PPC476_ERR_DCI(); \
NORMAL_EXCEPTION_PROLOG; \
lis r0,tsr_...@h; /* Setup the DEC interrupt mask */\
mtspr SPRN_TSR,r0
Re: [RFC: PATCH 01/13] powerpc/booke: Add Stack Marking support to Booke Exception Prolog
On Tue, 2010-03-02 at 08:50 -0600, Kumar Gala wrote: On Mar 1, 2010, at 1:13 PM, Dave Kleikamp wrote: powerpc/booke: Add Stack Marking support to Booke Exception Prolog From: Torez Smith lnxto...@linux.vnet.ibm.com Signed-off-by: Torez Smith lnxto...@linux.vnet.ibm.com Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com --- arch/powerpc/kernel/head_booke.h |5 + 1 files changed, 5 insertions(+), 0 deletions(-) Can this be explained further as to what this gets us or does. Yeah. Sorry about that. This is a debugging aid that identifies an exception on the stack. xmon recognizes the marker and identifies the exception frame in the stack trace. Other sub-architectures have it, but bookE is currently missing it. Ben, Torez, Is there any reason this patch is re-defining STACK_FRAME_REGS_MARKER rather than including asm/ptrace.h? Thanks, Shaggy -- David Kleikamp IBM Linux Technology Center ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH] powerpc/booke: Fix breakpoint/watchpoint one-shot behavior
Another fix for the extended ptrace patches in the -next tree.
The handling of breakpoints and watchpoints is inconsistent. When a
breakpoint or watchpoint is hit, the interrupt handler is clearing the
proper bits in the dbcr* registers, but leaving the dac* and iac* registers
alone. The ptrace code to delete the break/watchpoints checks the dac* and
iac* registers for zero to determine if they are enabled. Instead, they
should check the dbcr* bits.
Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com
---
arch/powerpc/kernel/ptrace.c | 12 ++--
1 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/kernel/ptrace.c b/arch/powerpc/kernel/ptrace.c
index 0efa2e3..ed2cfe1 100644
--- a/arch/powerpc/kernel/ptrace.c
+++ b/arch/powerpc/kernel/ptrace.c
@@ -940,7 +940,7 @@ static int del_instruction_bp(struct task_struct *child,
int slot)
{
switch (slot) {
case 1:
- if (child-thread.iac1 == 0)
+ if ((child-thread.dbcr0 DBCR0_IAC1) == 0)
return -ENOENT;
if (dbcr_iac_range(child) DBCR_IAC12MODE) {
@@ -952,7 +952,7 @@ static int del_instruction_bp(struct task_struct *child,
int slot)
child-thread.dbcr0 = ~DBCR0_IAC1;
break;
case 2:
- if (child-thread.iac2 == 0)
+ if ((child-thread.dbcr0 DBCR0_IAC2) == 0)
return -ENOENT;
if (dbcr_iac_range(child) DBCR_IAC12MODE)
@@ -963,7 +963,7 @@ static int del_instruction_bp(struct task_struct *child,
int slot)
break;
#if CONFIG_PPC_ADV_DEBUG_IACS 2
case 3:
- if (child-thread.iac3 == 0)
+ if ((child-thread.dbcr0 DBCR0_IAC3) == 0)
return -ENOENT;
if (dbcr_iac_range(child) DBCR_IAC34MODE) {
@@ -975,7 +975,7 @@ static int del_instruction_bp(struct task_struct *child,
int slot)
child-thread.dbcr0 = ~DBCR0_IAC3;
break;
case 4:
- if (child-thread.iac4 == 0)
+ if ((child-thread.dbcr0 DBCR0_IAC4) == 0)
return -ENOENT;
if (dbcr_iac_range(child) DBCR_IAC34MODE)
@@ -1054,7 +1054,7 @@ static int set_dac(struct task_struct *child, struct
ppc_hw_breakpoint *bp_info)
static int del_dac(struct task_struct *child, int slot)
{
if (slot == 1) {
- if (child-thread.dac1 == 0)
+ if ((dbcr_dac(child) (DBCR_DAC1R | DBCR_DAC1W)) == 0)
return -ENOENT;
child-thread.dac1 = 0;
@@ -1070,7 +1070,7 @@ static int del_dac(struct task_struct *child, int slot)
child-thread.dvc1 = 0;
#endif
} else if (slot == 2) {
- if (child-thread.dac2 == 0)
+ if ((dbcr_dac(child) (DBCR_DAC2R | DBCR_DAC2W)) == 0)
return -ENOENT;
#ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
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[RFC: PATCH 00/13] powerpc/47x: Support for 476 core
These patches add support for the 476 core. The goal is to have a single binary that will run on both 44x and 47x, but we still have some details to work out. The biggest is that the L1 cache line size differs on the two platforms, but it's currently a compile-time option. The code was originally written by Ben Herrenschmidt and Torez Smith, but I've been maintaining it. I'll take responsibility for the content, but I can't take all the credit. The first patch is a generic bookE feature. Patches 2-5 add base 47x support. Patches 6 7 add a platform to support the ISS simulator, and patches 8-13 add workarounds for DD1 and DD1.1 hardware bugs. -- Dave Kleikamp IBM Linux Technology Center ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[RFC: PATCH 02/13] powerpc/44x: break out cpu init code into stand-alone function
powerpc/44x: break out cpu init code into stand-alone function From: Dave Kleikamp sha...@linux.vnet.ibm.com The 47x platform supports multiple cores and shares code with 44x. Break out code that is common for initializing the primary and secondary cpus into a function which can be called for both. Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com --- arch/powerpc/kernel/head_44x.S | 330 +--- 1 files changed, 171 insertions(+), 159 deletions(-) diff --git a/arch/powerpc/kernel/head_44x.S b/arch/powerpc/kernel/head_44x.S index 711368b..39be049 100644 --- a/arch/powerpc/kernel/head_44x.S +++ b/arch/powerpc/kernel/head_44x.S @@ -69,165 +69,7 @@ _ENTRY(_start); mr r27,r7 li r24,0 /* CPU number */ -/* - * In case the firmware didn't do it, we apply some workarounds - * that are good for all 440 core variants here - */ - mfspr r3,SPRN_CCR0 - rlwinm r3,r3,0,0,27/* disable icache prefetch */ - isync - mtspr SPRN_CCR0,r3 - isync - sync - -/* - * Set up the initial MMU state - * - * We are still executing code at the virtual address - * mappings set by the firmware for the base of RAM. - * - * We first invalidate all TLB entries but the one - * we are running from. We then load the KERNELBASE - * mappings so we can begin to use kernel addresses - * natively and so the interrupt vector locations are - * permanently pinned (necessary since Book E - * implementations always have translation enabled). - * - * TODO: Use the known TLB entry we are running from to - * determine which physical region we are located - * in. This can be used to determine where in RAM - * (on a shared CPU system) or PCI memory space - * (on a DRAMless system) we are located. - * For now, we assume a perfect world which means - * we are located at the base of DRAM (physical 0). - */ - -/* - * Search TLB for entry that we are currently using. - * Invalidate all entries but the one we are using. - */ - /* Load our current PID-MMUCR TID and MSR IS-MMUCR STS */ - mfspr r3,SPRN_PID /* Get PID */ - mfmsr r4 /* Get MSR */ - andi. r4,r4,msr...@l /* TS=1? */ - beq wmmucr /* If not, leave STS=0 */ - orisr3,r3,ppc44x_mmucr_...@h/* Set STS=1 */ -wmmucr:mtspr SPRN_MMUCR,r3 /* Put MMUCR */ - sync - - bl invstr /* Find our address */ -invstr:mflrr5 /* Make it accessible */ - tlbsx r23,0,r5/* Find entry we are in */ - li r4,0/* Start at TLB entry 0 */ - li r3,0/* Set PAGEID inval value */ -1: cmpwr23,r4 /* Is this our entry? */ - beq skpinv /* If so, skip the inval */ - tlbwe r3,r4,PPC44x_TLB_PAGEID /* If not, inval the entry */ -skpinv:addir4,r4,1 /* Increment */ - cmpwi r4,64 /* Are we done? */ - bne 1b /* If not, repeat */ - isync /* If so, context change */ - -/* - * Configure and load pinned entry into TLB slot 63. - */ - - lis r3,page_off...@h - ori r3,r3,page_off...@l - - /* Kernel is at the base of RAM */ - li r4, 0/* Load the kernel physical address */ - - /* Load the kernel PID = 0 */ - li r0,0 - mtspr SPRN_PID,r0 - sync - - /* Initialize MMUCR */ - li r5,0 - mtspr SPRN_MMUCR,r5 - sync - - /* pageid fields */ - clrrwi r3,r3,10/* Mask off the effective page number */ - ori r3,r3,PPC44x_TLB_VALID | PPC44x_TLB_256M - - /* xlat fields */ - clrrwi r4,r4,10/* Mask off the real page number */ - /* ERPN is 0 for first 4GB page */ - - /* attrib fields */ - /* Added guarded bit to protect against speculative loads/stores */ - li r5,0 - ori r5,r5,(PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX | PPC44x_TLB_G) - -li r0,63/* TLB slot 63 */ - - tlbwe r3,r0,PPC44x_TLB_PAGEID /* Load the pageid fields */ - tlbwe r4,r0,PPC44x_TLB_XLAT /* Load the translation fields */ - tlbwe r5,r0,PPC44x_TLB_ATTRIB /* Load the attrib/access fields */ - - /* Force context change */ - mfmsr r0 - mtspr SPRN_SRR1, r0 - lis r0,3...@h - ori r0,r0,3...@l - mtspr SPRN_SRR0,r0 - sync - rfi - - /* If necessary, invalidate original entry we used */ -3: cmpwi
[RFC: PATCH 01/13] powerpc/booke: Add Stack Marking support to Booke Exception Prolog
powerpc/booke: Add Stack Marking support to Booke Exception Prolog From: Torez Smith lnxto...@linux.vnet.ibm.com Signed-off-by: Torez Smith lnxto...@linux.vnet.ibm.com Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com --- arch/powerpc/kernel/head_booke.h |5 + 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/kernel/head_booke.h b/arch/powerpc/kernel/head_booke.h index 50504ae..80d47f4 100644 --- a/arch/powerpc/kernel/head_booke.h +++ b/arch/powerpc/kernel/head_booke.h @@ -1,6 +1,8 @@ #ifndef __HEAD_BOOKE_H__ #define __HEAD_BOOKE_H__ +#define STACK_FRAME_REGS_MARKERASM_CONST(0x72656773) + /* * Macros used for common Book-e exception handling */ @@ -48,6 +50,9 @@ stw r10,0(r11); \ rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\ stw r0,GPR0(r11);\ + lis r10, stack_frame_regs_mar...@ha;/* exception frame marker */ \ + addir10, r10, stack_frame_regs_mar...@l; \ + stw r10, 8(r11); \ SAVE_4GPRS(3, r11); \ SAVE_2GPRS(7, r11) -- Dave Kleikamp IBM Linux Technology Center ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[RFC: PATCH 03/13] powerpc/47x: Base ppc476 support
powerpc/47x: Base ppc476 support
From: Dave Kleikamp sha...@linux.vnet.ibm.com
This patch adds the base support for the 476 processor. The code was
primarily written by Ben Herrenschmidt and Torez Smith, but I've been
maintaining it for a while.
The goal is to have a single binary that will run on 44x and 47x, but
we still have some details to work out. The biggest is that the L1 cache
line size differs on the two platforms, but it's currently a compile-time
option.
Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/cache.h |6
arch/powerpc/include/asm/cputable.h|4
arch/powerpc/include/asm/mmu-44x.h | 51 +++
arch/powerpc/include/asm/mmu.h |1
arch/powerpc/include/asm/reg.h |1
arch/powerpc/include/asm/reg_booke.h | 26 ++
arch/powerpc/kernel/cputable.c | 13 +
arch/powerpc/kernel/entry_32.S |5
arch/powerpc/kernel/head_44x.S | 502 +++-
arch/powerpc/kernel/misc_32.S |9 -
arch/powerpc/kernel/smp.c |8 +
arch/powerpc/mm/44x_mmu.c | 144 +
arch/powerpc/mm/mmu_context_nohash.c |8 +
arch/powerpc/mm/mmu_decl.h |7
arch/powerpc/mm/tlb_nohash_low.S | 118 +++-
arch/powerpc/platforms/44x/Kconfig | 37 ++
arch/powerpc/platforms/Kconfig.cputype |5
17 files changed, 888 insertions(+), 57 deletions(-)
diff --git a/arch/powerpc/include/asm/cache.h b/arch/powerpc/include/asm/cache.h
index 81de6eb..725634f 100644
--- a/arch/powerpc/include/asm/cache.h
+++ b/arch/powerpc/include/asm/cache.h
@@ -12,8 +12,12 @@
#define L1_CACHE_SHIFT 6
#define MAX_COPY_PREFETCH 4
#elif defined(CONFIG_PPC32)
-#define L1_CACHE_SHIFT 5
#define MAX_COPY_PREFETCH 4
+#if defined(CONFIG_PPC_47x)
+#define L1_CACHE_SHIFT 7
+#else
+#define L1_CACHE_SHIFT 5
+#endif
#else /* CONFIG_PPC64 */
#define L1_CACHE_SHIFT 7
#endif
diff --git a/arch/powerpc/include/asm/cputable.h
b/arch/powerpc/include/asm/cputable.h
index 80f315e..75b774e 100644
--- a/arch/powerpc/include/asm/cputable.h
+++ b/arch/powerpc/include/asm/cputable.h
@@ -365,6 +365,7 @@ extern const char *powerpc_base_platform;
#define CPU_FTRS_44X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN |
CPU_FTR_NOEXECUTE)
#define CPU_FTRS_440x6 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN |
CPU_FTR_NOEXECUTE | \
CPU_FTR_INDEXED_DCR)
+#define CPU_FTRS_47X (CPU_FTRS_440x6)
#define CPU_FTRS_E200 (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \
CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \
CPU_FTR_UNIFIED_ID_CACHE | CPU_FTR_NOEXECUTE)
@@ -453,6 +454,9 @@ enum {
#ifdef CONFIG_44x
CPU_FTRS_44X | CPU_FTRS_440x6 |
#endif
+#ifdef CONFIG_PPC_47x
+ CPU_FTRS_47X |
+#endif
#ifdef CONFIG_E200
CPU_FTRS_E200 |
#endif
diff --git a/arch/powerpc/include/asm/mmu-44x.h
b/arch/powerpc/include/asm/mmu-44x.h
index 0372669..bf52d70 100644
--- a/arch/powerpc/include/asm/mmu-44x.h
+++ b/arch/powerpc/include/asm/mmu-44x.h
@@ -40,7 +40,7 @@
#define PPC44x_TLB_I 0x0400 /* Caching is inhibited */
#define PPC44x_TLB_M 0x0200 /* Memory is coherent */
#define PPC44x_TLB_G 0x0100 /* Memory is guarded */
-#define PPC44x_TLB_E 0x0080 /* Memory is guarded */
+#define PPC44x_TLB_E 0x0080 /* Memory is little endian */
#define PPC44x_TLB_PERM_MASK 0x003f
#define PPC44x_TLB_UX 0x0020 /* User execution */
@@ -53,6 +53,52 @@
/* Number of TLB entries */
#define PPC44x_TLB_SIZE64
+/* 47x bits */
+#define PPC47x_MMUCR_TID 0x
+#define PPC47x_MMUCR_STS 0x0001
+
+/* Page identification fields */
+#define PPC47x_TLB0_EPN_MASK 0xf000 /* Effective Page Number */
+#define PPC47x_TLB0_VALID 0x0800 /* Valid flag */
+#define PPC47x_TLB0_TS 0x0400 /* Translation address space */
+#define PPC47x_TLB0_4K 0x
+#define PPC47x_TLB0_16K0x0010
+#define PPC47x_TLB0_64K0x0030
+#define PPC47x_TLB0_1M 0x0070
+#define PPC47x_TLB0_16M0x00f0
+#define PPC47x_TLB0_256M 0x01f0
+#define PPC47x_TLB0_1G 0x03f0
+#define PPC47x_TLB0_BOLTED_R 0x0008 /* tlbre only */
+
+/* Translation fields */
+#define PPC47x_TLB1_RPN_MASK 0xf000 /* Real Page Number */
+#define PPC47x_TLB1_ERPN_MASK 0x03ff
+
+/* Storage attribute and access control fields */
+#define PPC47x_TLB2_ATTR_MASK 0x0003ff80
+#define PPC47x_TLB2_IL1I 0x0002 /* Memory is guarded */
+#define PPC47x_TLB2_IL1D 0x0001 /* Memory is guarded */
+#define PPC47x_TLB2_U0 0x8000 /* User 0 */
+#define PPC47x_TLB2_U1 0x4000 /* User 1 */
+#define PPC47x_TLB2_U2
[RFC: PATCH 04/13] powerpc/476: add machine check handler for 47x core
powerpc/476: add machine check handler for 47x core
From: Dave Kleikamp sha...@linux.vnet.ibm.com
The 47x core's MCSR varies from 44x, so it needs it's own machine check
handler.
Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/cputable.h |1 +
arch/powerpc/include/asm/reg_booke.h |2 +-
arch/powerpc/kernel/cputable.c |1 +
arch/powerpc/kernel/traps.c | 38 ++
4 files changed, 41 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/include/asm/cputable.h
b/arch/powerpc/include/asm/cputable.h
index 75b774e..9fff628 100644
--- a/arch/powerpc/include/asm/cputable.h
+++ b/arch/powerpc/include/asm/cputable.h
@@ -72,6 +72,7 @@ extern int machine_check_4xx(struct pt_regs *regs);
extern int machine_check_440A(struct pt_regs *regs);
extern int machine_check_e500(struct pt_regs *regs);
extern int machine_check_e200(struct pt_regs *regs);
+extern int machine_check_47x(struct pt_regs *regs);
/* NOTE WELL: Update identify_cpu() if fields are added or removed! */
struct cpu_spec {
diff --git a/arch/powerpc/include/asm/reg_booke.h
b/arch/powerpc/include/asm/reg_booke.h
index ee61a9d..a9245b9 100644
--- a/arch/powerpc/include/asm/reg_booke.h
+++ b/arch/powerpc/include/asm/reg_booke.h
@@ -194,7 +194,7 @@
#ifdef CONFIG_PPC_47x
#define PPC47x_MCSR_GPR0x0100 /* GPR parity error */
#define PPC47x_MCSR_FPR0x0080 /* FPR parity error */
-#define PPC47x_MCSR_IPR0x0040 /* Imprecise Machine Check Exception
*/
+#define PPC47x_MCSR_IMP0x0040 /* Imprecise Machine Check Exception
*/
#endif
#ifdef CONFIG_E500
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index 338ac47..7b2a67c 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -1712,6 +1712,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_LOCK_BCAST_INVAL,
.icache_bsize = 32,
.dcache_bsize = 128,
+ .machine_check = machine_check_47x,
.platform = ppc470,
},
{ /* default match */
diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
index d069ff8..66617b6 100644
--- a/arch/powerpc/kernel/traps.c
+++ b/arch/powerpc/kernel/traps.c
@@ -376,6 +376,44 @@ int machine_check_440A(struct pt_regs *regs)
}
return 0;
}
+
+int machine_check_47x(struct pt_regs *regs)
+{
+ unsigned long reason = get_mc_reason(regs);
+
+ printk(Machine check in kernel mode.\n);
+ if (reason ESR_IMCP){
+ printk(Instruction Synchronous Machine Check exception\n);
+ mtspr(SPRN_ESR, reason ~ESR_IMCP);
+ }
+ else {
+ u32 mcsr = mfspr(SPRN_MCSR);
+ if (mcsr MCSR_IB)
+ printk(Instruction Read PLB Error\n);
+ if (mcsr MCSR_DRB)
+ printk(Data Read PLB Error\n);
+ if (mcsr MCSR_DWB)
+ printk(Data Write PLB Error\n);
+ if (mcsr MCSR_TLBP)
+ printk(TLB Parity Error\n);
+ if (mcsr MCSR_ICP){
+ flush_instruction_cache();
+ printk(I-Cache Parity Error\n);
+ }
+ if (mcsr MCSR_DCSP)
+ printk(D-Cache Search Parity Error\n);
+ if (mcsr PPC47x_MCSR_GPR)
+ printk(GPR Parity Error\n);
+ if (mcsr PPC47x_MCSR_FPR)
+ printk(FPR Parity Error\n);
+ if (mcsr PPC47x_MCSR_IMP)
+ printk(Machine Check exception is imprecise\n);
+
+ /* Clear MCSR */
+ mtspr(SPRN_MCSR, mcsr);
+ }
+ return 0;
+}
#elif defined(CONFIG_E500)
int machine_check_e500(struct pt_regs *regs)
{
--
Dave Kleikamp
IBM Linux Technology Center
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[RFC: PATCH 06/13] powerpc/4xx: Simple platform for the ISS 4xx simulator
powerpc/4xx: Simple platform for the ISS 4xx simulator
From: Torez Smith lnxto...@linux.vnet.ibm.com
This is a trivial 4xx plaform that uses the new simple bsp from
Josh and is handy to use in simulators such as ISS or even Mambo
who don't properly implement most of the actual devices in the
SoC but really only the core.
Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com
---
arch/powerpc/boot/Makefile|5 +
arch/powerpc/boot/dts/iss4xx-mpic.dts | 155 +++
arch/powerpc/boot/dts/iss4xx.dts | 116 +++
arch/powerpc/boot/treeboot-iss4xx.c | 56 +++
arch/powerpc/boot/wrapper |3 +
arch/powerpc/include/asm/reg.h|3 +
arch/powerpc/kernel/cputable.c| 15 +++
arch/powerpc/kernel/head_44x.S|2
arch/powerpc/platforms/44x/Kconfig| 11 ++
arch/powerpc/platforms/44x/Makefile |1
arch/powerpc/platforms/44x/iss4xx.c | 165 +
11 files changed, 531 insertions(+), 1 deletions(-)
create mode 100644 arch/powerpc/boot/dts/iss4xx-mpic.dts
create mode 100644 arch/powerpc/boot/dts/iss4xx.dts
create mode 100644 arch/powerpc/boot/treeboot-iss4xx.c
create mode 100644 arch/powerpc/platforms/44x/iss4xx.c
diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile
index bb2465b..997196e 100644
--- a/arch/powerpc/boot/Makefile
+++ b/arch/powerpc/boot/Makefile
@@ -44,6 +44,7 @@ $(obj)/cuboot-taishan.o: BOOTCFLAGS += -mcpu=405
$(obj)/cuboot-katmai.o: BOOTCFLAGS += -mcpu=405
$(obj)/cuboot-acadia.o: BOOTCFLAGS += -mcpu=405
$(obj)/treeboot-walnut.o: BOOTCFLAGS += -mcpu=405
+$(obj)/treeboot-iss4xx.o: BOOTCFLAGS += -mcpu=405
$(obj)/virtex405-head.o: BOOTAFLAGS += -mcpu=405
@@ -77,7 +78,7 @@ src-plat := of.c cuboot-52xx.c cuboot-824x.c cuboot-83xx.c
cuboot-85xx.c holly.c
cuboot-warp.c cuboot-85xx-cpm2.c cuboot-yosemite.c simpleboot.c
\
virtex405-head.S virtex.c redboot-83xx.c cuboot-sam440ep.c \
cuboot-acadia.c cuboot-amigaone.c cuboot-kilauea.c \
- gamecube-head.S gamecube.c wii-head.S wii.c
+ gamecube-head.S gamecube.c wii-head.S wii.c treeboot-iss4xx.c
src-boot := $(src-wlib) $(src-plat) empty.c
src-boot := $(addprefix $(obj)/, $(src-boot))
@@ -206,6 +207,8 @@ image-$(CONFIG_TAISHAN) +=
cuImage.taishan
image-$(CONFIG_KATMAI) += cuImage.katmai
image-$(CONFIG_WARP) += cuImage.warp
image-$(CONFIG_YOSEMITE) += cuImage.yosemite
+image-$(CONFIG_ISS4xx) += treeImage.iss4xx \
+ treeImage.iss4xx-mpic
# Board ports in arch/powerpc/platform/8xx/Kconfig
image-$(CONFIG_MPC86XADS) += cuImage.mpc866ads
diff --git a/arch/powerpc/boot/dts/iss4xx-mpic.dts
b/arch/powerpc/boot/dts/iss4xx-mpic.dts
new file mode 100644
index 000..23e9d9b
--- /dev/null
+++ b/arch/powerpc/boot/dts/iss4xx-mpic.dts
@@ -0,0 +1,155 @@
+/*
+ * Device Tree Source for IBM Embedded PPC 476 Platform
+ *
+ * Copyright 2010 Torez Smith, IBM Corporation.
+ *
+ * Based on earlier code:
+ * Copyright (c) 2006, 2007 IBM Corp.
+ * Josh Boyer jwbo...@linux.vnet.ibm.com, David Gibson d...@au1.ibm.com
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed as is without
+ * any warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+
+/memreserve/ 0x01f0 0x0010;
+
+/ {
+ #address-cells = 2;
+ #size-cells = 1;
+ model = ibm,iss-4xx;
+ compatible = ibm,iss-4xx;
+ dcr-parent = {/cpus/c...@0};
+
+ aliases {
+ serial0 = UART0;
+ };
+
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ c...@0 {
+ device_type = cpu;
+ model = PowerPC,4xx; // real CPU changed in sim
+ reg = 0;
+ clock-frequency = 1; // 100Mhz :-)
+ timebase-frequency = 1;
+ i-cache-line-size = 32;
+ d-cache-line-size = 32;
+ i-cache-size = 32768;
+ d-cache-size = 32768;
+ dcr-controller;
+ dcr-access-method = native;
+ status = ok;
+ };
+ c...@1 {
+ device_type = cpu;
+ model = PowerPC,4xx; // real CPU changed in sim
+ reg = 1;
+ clock-frequency = 1; // 100Mhz :-)
+ timebase-frequency = 1;
+ i-cache-line-size = 32;
+ d-cache-line-size = 32;
+ i-cache-size = 32768;
+ d-cache-size = 32768
[RFC: PATCH 05/13] powerpc/476: Add isync after loading mmu and debug spr's
powerpc/476: Add isync after loading mmu and debug spr's
From: Dave Kleikamp sha...@linux.vnet.ibm.com
476 requires an isync after loading MMU and debug related SPR's. Some of
these are in performance-critical paths and may need to be optimized, but
initially, we're playing it safe.
Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com
---
arch/powerpc/kernel/head_44x.S |8
arch/powerpc/kernel/kprobes.c|3 +++
arch/powerpc/kernel/process.c|3 +++
arch/powerpc/kernel/traps.c |6 ++
arch/powerpc/mm/44x_mmu.c|1 +
arch/powerpc/mm/tlb_nohash_low.S |3 +++
6 files changed, 24 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/kernel/head_44x.S b/arch/powerpc/kernel/head_44x.S
index 1acd175..992e9d5 100644
--- a/arch/powerpc/kernel/head_44x.S
+++ b/arch/powerpc/kernel/head_44x.S
@@ -464,6 +464,9 @@ finish_tlb_load_44x:
lwz r11,PGDIR(r11)
mfspr r12,SPRN_PID/* Get PID */
4: mtspr SPRN_MMUCR,r12 /* Set MMUCR */
+#ifdef CONFIG_PPC_47x
+ isync
+#endif
/* Mask of required permission bits. Note that while we
* do copy ESR:ST to _PAGE_RW position as trying to write
@@ -561,6 +564,9 @@ finish_tlb_load_44x:
lwz r11,PGDIR(r11)
mfspr r12,SPRN_PID/* Get PID */
4: mtspr SPRN_MMUCR,r12 /* Set MMUCR */
+#ifdef CONFIG_PPC_47x
+ isync
+#endif
/* Make up the required permissions */
li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
@@ -1031,6 +1037,7 @@ clear_utlb_entry:
mtspr SPRN_USPCR,r3
LOAD_REG_IMMEDIATE(r3, 0x12345670)
mtspr SPRN_ISPCR,r3
+ isync /* 476 needs this */
/* Force context change */
mfmsr r0
@@ -1116,6 +1123,7 @@ head_start_common:
/* Establish the interrupt vector base */
lis r4,interrupt_b...@h /* IVPR only uses the high 16-bits */
mtspr SPRN_IVPR,r4
+ isync /* 476 needs this */
addis r22,r22,kernelb...@h
mtlrr22
diff --git a/arch/powerpc/kernel/kprobes.c b/arch/powerpc/kernel/kprobes.c
index c932978..7fec5db 100644
--- a/arch/powerpc/kernel/kprobes.c
+++ b/arch/powerpc/kernel/kprobes.c
@@ -113,6 +113,9 @@ static void __kprobes prepare_singlestep(struct kprobe *p,
struct pt_regs *regs)
#ifdef CONFIG_BOOKE
regs-msr = ~MSR_CE;
mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) | DBCR0_IC | DBCR0_IDM);
+#ifdef CONFIG_PPC_47x
+ isync();
+#endif
#endif
/*
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index 7b816da..15ee756 100644
--- a/arch/powerpc/kernel/process.c
+++ b/arch/powerpc/kernel/process.c
@@ -286,6 +286,9 @@ int set_dabr(unsigned long dabr)
/* XXX should we have a CPU_FTR_HAS_DABR ? */
#if defined(CONFIG_BOOKE)
mtspr(SPRN_DAC1, dabr);
+#ifdef CONFIG_PPC_47x
+ isync();
+#endif
#elif defined(CONFIG_PPC_BOOK3S)
mtspr(SPRN_DABR, dabr);
#endif
diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
index 66617b6..47169f6 100644
--- a/arch/powerpc/kernel/traps.c
+++ b/arch/powerpc/kernel/traps.c
@@ -1078,6 +1078,9 @@ void __kprobes DebugException(struct pt_regs *regs,
unsigned long debug_status)
mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) ~DBCR0_BT);
/* Clear the BT event */
mtspr(SPRN_DBSR, DBSR_BT);
+#ifdef CONFIG_PPC_47x
+ isync();
+#endif
/* Do the single step trick only when coming from userspace */
if (user_mode(regs)) {
@@ -1100,6 +1103,9 @@ void __kprobes DebugException(struct pt_regs *regs,
unsigned long debug_status)
mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) ~DBCR0_IC);
/* Clear the instruction completion event */
mtspr(SPRN_DBSR, DBSR_IC);
+#ifdef CONFIG_PPC_47x
+ isync();
+#endif
if (notify_die(DIE_SSTEP, single_step, regs, 5,
5, SIGTRAP) == NOTIFY_STOP) {
diff --git a/arch/powerpc/mm/44x_mmu.c b/arch/powerpc/mm/44x_mmu.c
index d8c6efb..a5f082a 100644
--- a/arch/powerpc/mm/44x_mmu.c
+++ b/arch/powerpc/mm/44x_mmu.c
@@ -156,6 +156,7 @@ static void __cpuinit ppc47x_pin_tlb(unsigned int virt,
unsigned int phys)
virt, phys, bolted);
mtspr(SPRN_MMUCR, 0);
+ isync();
__asm__ __volatile__(
tlbwe %2,%3,0\n
diff --git a/arch/powerpc/mm/tlb_nohash_low.S b/arch/powerpc/mm/tlb_nohash_low.S
index e925cb5..7c890f7 100644
--- a/arch/powerpc/mm/tlb_nohash_low.S
+++ b/arch/powerpc/mm/tlb_nohash_low.S
@@ -92,6 +92,9 @@ _GLOBAL(__tlbil_va)
*/
wrteei 0
mtspr SPRN_MMUCR,r5
+#ifdef CONFIG_PPC_47x
+ isync
+#endif
tlbsx. r6,0,r3
bne 10f
sync
--
Dave Kleikamp
IBM Linux Technology Center
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[RFC: PATCH 07/13] powerpc/47x: defconfig for 476 on the iss 4xx simulator
powerpc/47x: defconfig for 476 on the iss 4xx simulator From: Dave Kleikamp sha...@linux.vnet.ibm.com Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com --- arch/powerpc/configs/44x/iss476-smp_defconfig | 1023 + 1 files changed, 1023 insertions(+), 0 deletions(-) create mode 100644 arch/powerpc/configs/44x/iss476-smp_defconfig diff --git a/arch/powerpc/configs/44x/iss476-smp_defconfig b/arch/powerpc/configs/44x/iss476-smp_defconfig new file mode 100644 index 000..681c0d7 --- /dev/null +++ b/arch/powerpc/configs/44x/iss476-smp_defconfig @@ -0,0 +1,1023 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.33-rc7 +# Tue Feb 9 16:40:35 2010 +# +# CONFIG_PPC64 is not set + +# +# Processor support +# +# CONFIG_PPC_BOOK3S_32 is not set +# CONFIG_PPC_85xx is not set +# CONFIG_PPC_8xx is not set +# CONFIG_40x is not set +CONFIG_44x=y +# CONFIG_E200 is not set +CONFIG_PPC_FPU=y +CONFIG_4xx=y +CONFIG_BOOKE=y +CONFIG_PTE_64BIT=y +CONFIG_PHYS_64BIT=y +CONFIG_PPC_MMU_NOHASH=y +CONFIG_PPC_MMU_NOHASH_32=y +# CONFIG_PPC_MM_SLICES is not set +CONFIG_SMP=y +CONFIG_NR_CPUS=4 +# CONFIG_NOT_COHERENT_CACHE is not set +CONFIG_PPC32=y +CONFIG_WORD_SIZE=32 +CONFIG_ARCH_PHYS_ADDR_T_64BIT=y +CONFIG_MMU=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set +# CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK is not set +CONFIG_IRQ_PER_CPU=y +CONFIG_NR_IRQS=512 +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +CONFIG_ARCH_HAS_ILOG2_U32=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_FIND_NEXT_BIT=y +# CONFIG_ARCH_NO_VIRT_TO_BUS is not set +CONFIG_PPC=y +CONFIG_EARLY_PRINTK=y +CONFIG_GENERIC_NVRAM=y +CONFIG_SCHED_OMIT_FRAME_POINTER=y +CONFIG_ARCH_MAY_HAVE_PC_FDC=y +CONFIG_PPC_OF=y +CONFIG_OF=y +CONFIG_PPC_UDBG_16550=y +CONFIG_GENERIC_TBSYNC=y +CONFIG_AUDIT_ARCH=y +CONFIG_GENERIC_BUG=y +CONFIG_DTC=y +# CONFIG_DEFAULT_UIMAGE is not set +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_PPC_DCR_NATIVE=y +# CONFIG_PPC_DCR_MMIO is not set +CONFIG_PPC_DCR=y +CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y +CONFIG_PPC_ADV_DEBUG_REGS=y +CONFIG_PPC_ADV_DEBUG_IACS=4 +CONFIG_PPC_ADV_DEBUG_DACS=2 +CONFIG_PPC_ADV_DEBUG_DVCS=2 +CONFIG_PPC_ADV_DEBUG_DAC_RANGE=y +CONFIG_DEFCONFIG_LIST=/lib/modules/$UNAME_RELEASE/.config +CONFIG_CONSTRUCTORS=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION= +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_TINY_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_GROUP_SCHED=y +CONFIG_FAIR_GROUP_SCHED=y +# CONFIG_RT_GROUP_SCHED is not set +CONFIG_USER_SCHED=y +# CONFIG_CGROUP_SCHED is not set +# CONFIG_CGROUPS is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +# CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE= +CONFIG_RD_GZIP=y +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_RD_LZO is not set +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EMBEDDED=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_ALL=y +CONFIG_KALLSYMS_EXTRA_PASS=y +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_HAVE_PERF_EVENTS=y + +# +# Kernel Performance Events And Counters +# +CONFIG_PERF_EVENTS=y +CONFIG_EVENT_PROFILE=y +# CONFIG_PERF_COUNTERS is not set +# CONFIG_DEBUG_PERF_USE_VMALLOC is not set +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +CONFIG_PROFILING=y +CONFIG_TRACEPOINTS=y +CONFIG_OPROFILE=y +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_HAVE_IOREMAP_PROT=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_USE_GENERIC_SMP_HELPERS=y +CONFIG_HAVE_DMA_API_DEBUG=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +# CONFIG_SLOW_WORK is not set +# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y
[RFC: PATCH 08/13] powerpc/476: define specific cpu table entry for DD1 and DD1.1 cores
powerpc/476: define specific cpu table entry for DD1 and DD1.1 cores
From: Benjamin Herrenschmidt b...@kernel.crashing.org
There are still some unstable bits on the DD1 and DD1.1 cores. Don't use
the FPU or the tlbivax operation. Define CPU_FTR_476_DD1 and
CPU_FTR_476_DD1_1 for additional workarounds in later patches.
The DD1 core requires workarounds triggered by both CPU_FTR_476_DD1
and CPU_FTR_476_DD1_1. the DD1.1 core only needs CPU_FTR_476_DD1_1
defined.
Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/cputable.h |2 ++
arch/powerpc/kernel/cputable.c | 38 ++-
2 files changed, 35 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/include/asm/cputable.h
b/arch/powerpc/include/asm/cputable.h
index 9fff628..d28eaf7 100644
--- a/arch/powerpc/include/asm/cputable.h
+++ b/arch/powerpc/include/asm/cputable.h
@@ -153,8 +153,10 @@ extern const char *powerpc_base_platform;
#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x2000)
#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x4000)
#define CPU_FTR_NO_DPM ASM_CONST(0x8000)
+#define CPU_FTR_476_DD1ASM_CONST(0x0001)
#define CPU_FTR_NEED_COHERENT ASM_CONST(0x0002)
#define CPU_FTR_NO_BTICASM_CONST(0x0004)
+#define CPU_FTR_476_DD1_1 ASM_CONST(0x0008)
#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0010)
#define CPU_FTR_PPC_LE ASM_CONST(0x0020)
#define CPU_FTR_REAL_LEASM_CONST(0x0040)
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index a06e6d3..0ea9134 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -1701,15 +1701,29 @@ static struct cpu_spec __initdata cpu_specs[] = {
.machine_check = machine_check_440A,
.platform = ppc440,
},
- { /* 476 core */
+ { /* 476 DD1 core - needs DD1.1 feature as well */
.pvr_mask = 0x,
.pvr_value = 0x11a5,
.cpu_name = 476,
- .cpu_features = CPU_FTRS_47X,
- .cpu_user_features = COMMON_USER_BOOKE |
- PPC_FEATURE_HAS_FPU,
+ .cpu_features = CPU_FTRS_47X | CPU_FTR_476_DD1 |
+ CPU_FTR_476_DD1_1 | CPU_FTR_FPU_UNAVAILABLE,
+ .cpu_user_features = COMMON_USER_BOOKE,
.mmu_features = MMU_FTR_TYPE_47x |
- MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_LOCK_BCAST_INVAL,
+ MMU_FTR_LOCK_BCAST_INVAL,
+ .icache_bsize = 32,
+ .dcache_bsize = 128,
+ .machine_check = machine_check_47x,
+ .platform = ppc470,
+ },
+ { /* 476 DD1.1 core */
+ .pvr_mask = 0x,
+ .pvr_value = 0x11a5,
+ .cpu_name = 476,
+ .cpu_features = CPU_FTRS_47X | CPU_FTR_476_DD1_1 |
+ CPU_FTR_FPU_UNAVAILABLE,
+ .cpu_user_features = COMMON_USER_BOOKE,
+ .mmu_features = MMU_FTR_TYPE_47x |
+ MMU_FTR_LOCK_BCAST_INVAL,
.icache_bsize = 32,
.dcache_bsize = 128,
.machine_check = machine_check_47x,
@@ -1724,6 +1738,20 @@ static struct cpu_spec __initdata cpu_specs[] = {
PPC_FEATURE_HAS_FPU,
.cpu_user_features = COMMON_USER_BOOKE,
.mmu_features = MMU_FTR_TYPE_47x |
+ MMU_FTR_LOCK_BCAST_INVAL,
+ .icache_bsize = 32,
+ .dcache_bsize = 128,
+ .machine_check = machine_check_47x,
+ .platform = ppc470,
+ },
+ { /* 476 others */
+ .pvr_mask = 0x,
+ .pvr_value = 0x11a5,
+ .cpu_name = 476,
+ .cpu_features = CPU_FTRS_47X,
+ .cpu_user_features = COMMON_USER_BOOKE |
+ PPC_FEATURE_HAS_FPU,
+ .mmu_features = MMU_FTR_TYPE_47x |
MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_LOCK_BCAST_INVAL,
.icache_bsize = 32,
.dcache_bsize = 128,
--
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IBM Linux Technology Center
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[RFC: PATCH 10/13] powerpc/476: Add isync to the top of all exception handlers for DD1.1 core
powerpc/476: Add isync to the top of all exception handlers for DD1.1 core From: Dave Kleikamp sha...@linux.vnet.ibm.com Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com --- arch/powerpc/include/asm/asm-compat.h |7 ++- arch/powerpc/kernel/head_booke.h |3 ++- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/include/asm/asm-compat.h b/arch/powerpc/include/asm/asm-compat.h index bee05ec..1890fbf 100644 --- a/arch/powerpc/include/asm/asm-compat.h +++ b/arch/powerpc/include/asm/asm-compat.h @@ -70,8 +70,13 @@ BEGIN_FTR_SECTION; \ lwsync; \ END_FTR_SECTION_IFSET(CPU_FTR_476_DD1_1) -#else +#define PPC476_ERR_ISYNC() \ + BEGIN_FTR_SECTION; \ + isync; \ + END_FTR_SECTION_IFSET(CPU_FTR_476_DD1_1) +#else /* ! CONFIG_PPC_47x */ #define PPC476_ERR_DCBx() +#define PPC476_ERR_ISYNC() #endif /* CONFIG_PPC_47x */ #endif diff --git a/arch/powerpc/kernel/head_booke.h b/arch/powerpc/kernel/head_booke.h index 80d47f4..6b1ad61 100644 --- a/arch/powerpc/kernel/head_booke.h +++ b/arch/powerpc/kernel/head_booke.h @@ -165,7 +165,8 @@ */ #defineSTART_EXCEPTION(label) \ .align 5; \ -label: +label: \ + PPC476_ERR_ISYNC() #define FINISH_EXCEPTION(func) \ bl transfer_to_handler_full; \ -- Dave Kleikamp IBM Linux Technology Center ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[RFC: PATCH 09/13] powerpc/476: Workaround for dcbf/dcbz workaround on DD1
powerpc/476: Workaround for dcbf/dcbz workaround on DD1 From: Benjamin Herrenschmidt b...@kernel.crashing.org On the DD1.1 core, the dcbf and dcbz instructions need to be preceded and followed by an lwsync. We must trap user-space to ensure that this occurs there too. Signed-off-by: Benjamin Herrenschmidt b...@kernel.crashing.org Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com --- arch/powerpc/include/asm/asm-compat.h | 10 +++ arch/powerpc/include/asm/ppc-opcode.h |4 +++ arch/powerpc/include/asm/reg_booke.h |9 +++ arch/powerpc/kernel/entry_32.S| 35 +++--- arch/powerpc/kernel/head_44x.S|9 +++ arch/powerpc/kernel/misc_32.S | 32 ++- arch/powerpc/kernel/traps.c | 45 + arch/powerpc/lib/copy_32.S|7 - 8 files changed, 145 insertions(+), 6 deletions(-) diff --git a/arch/powerpc/include/asm/asm-compat.h b/arch/powerpc/include/asm/asm-compat.h index 8f0fe79..bee05ec 100644 --- a/arch/powerpc/include/asm/asm-compat.h +++ b/arch/powerpc/include/asm/asm-compat.h @@ -64,6 +64,16 @@ #define PPC405_ERR77(ra,rb) #define PPC405_ERR77_SYNC #endif + +#ifdef CONFIG_PPC_47x +#define PPC476_ERR_DCBx() \ + BEGIN_FTR_SECTION; \ + lwsync; \ + END_FTR_SECTION_IFSET(CPU_FTR_476_DD1_1) +#else +#define PPC476_ERR_DCBx() +#endif /* CONFIG_PPC_47x */ + #endif #endif /* _ASM_POWERPC_ASM_COMPAT_H */ diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h index ef9aa84..629b1fe 100644 --- a/arch/powerpc/include/asm/ppc-opcode.h +++ b/arch/powerpc/include/asm/ppc-opcode.h @@ -19,6 +19,10 @@ #define PPC_INST_DCBA 0x7c0005ec #define PPC_INST_DCBA_MASK 0xfc0007fe #define PPC_INST_DCBAL 0x7c2005ec +#define PPC_INST_DCBF 0x7cac +#define PPC_INST_DCBF_MASK 0xfc0007fe +#define PPC_INST_DCBZ 0x7c0007ec +#define PPC_INST_DCBZ_MASK 0xfc0007fe #define PPC_INST_DCBZL 0x7c2007ec #define PPC_INST_ISEL 0x7c1e #define PPC_INST_ISEL_MASK 0xfc3e diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h index a9245b9..bca3fba 100644 --- a/arch/powerpc/include/asm/reg_booke.h +++ b/arch/powerpc/include/asm/reg_booke.h @@ -276,6 +276,8 @@ #define ESR_IMCN 0x4000 /* Instr. Machine Check - Non-config */ #define ESR_IMCB 0x2000 /* Instr. Machine Check - Bus error */ #define ESR_IMCT 0x1000 /* Instr. Machine Check - Timeout */ +#define ESR_POT1 0x2000 /* 476 - IOCR1 trap */ +#define ESR_POT2 0x1000 /* 476 - IOCR2 trap */ #define ESR_PIL0x0800 /* Program Exception - Illegal */ #define ESR_PPR0x0400 /* Program Exception - Privileged */ #define ESR_PTR0x0200 /* Program Exception - Trap */ @@ -535,6 +537,13 @@ #define MMUBE1_VBE30x0004 #define MMUBE1_VBE40x0002 #define MMUBE1_VBE50x0001 +#define SPRN_IOCCR 860 +#defineIOCCR_IOCR1EN 0x8000 +#defineIOCCR_IOCR1M0x4000 +#defineIOCCR_IOCR2EN 0x2000 +#defineIOCCR_IOCR2M0x1000 +#define SPRN_IOCR1 861 +#define SPRN_IOCR2 862 #endif /* __ASM_POWERPC_REG_BOOKE_H__ */ #endif /* __KERNEL__ */ diff --git a/arch/powerpc/kernel/entry_32.S b/arch/powerpc/kernel/entry_32.S index ed4aeb9..57b7893 100644 --- a/arch/powerpc/kernel/entry_32.S +++ b/arch/powerpc/kernel/entry_32.S @@ -142,6 +142,12 @@ transfer_to_handler: addir2,r12,-THREAD tovirt(r2,r2) /* set r2 to current */ beq 2f /* if from user, fix up THREAD.regs */ +#ifdef CONFIG_PPC_47x +BEGIN_FTR_SECTION + li r11,0 + mtspr SPRN_IOCCR,r11 +END_FTR_SECTION_IFSET(CPU_FTR_476_DD1_1) +#endif /* CONFIG_PPC_47x */ addir11,r1,STACK_FRAME_OVERHEAD stw r11,PT_REGS(r12) #if defined(CONFIG_40x) || defined(CONFIG_BOOKE) @@ -280,6 +286,12 @@ stack_ovf: 0: _GLOBAL(DoSyscall) +#ifdef CONFIG_PPC_47x +BEGIN_FTR_SECTION + li r11,0 + mtspr SPRN_IOCCR,r11 +END_FTR_SECTION_IFSET(CPU_FTR_476_DD1_1) +#endif /* CONFIG_PPC_47x */ stw r3,ORIG_GPR3(r1) li r12,0 stw r12,RESULT(r1) @@ -381,6 +393,16 @@ BEGIN_MMU_FTR_SECTION 1: END_MMU_FTR_SECTION_IFCLR(MMU_FTR_TYPE_47x) #endif /* CONFIG_44x */ +#ifdef CONFIG_PPC_47x +BEGIN_FTR_SECTION + lwz r7,_MSR(r1) + andi. r5,r7,MSR_PR + beq 11f + lis r4,(IOCCR_IOCR1EN|IOCCR_IOCR2EN)@h + mtspr SPRN_IOCCR
[RFC: PATCH 12/13] powerpc/476: Workaround for DD1.1: Issue lwsync after mtpid
powerpc/476: Workaround for DD1.1: Issue lwsync after mtpid From: Dave Kleikamp sha...@linux.vnet.ibm.com Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com --- arch/powerpc/include/asm/asm-compat.h |2 ++ arch/powerpc/kernel/head_44x.S|1 + 2 files changed, 3 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/include/asm/asm-compat.h b/arch/powerpc/include/asm/asm-compat.h index 1890fbf..fd16e3a 100644 --- a/arch/powerpc/include/asm/asm-compat.h +++ b/arch/powerpc/include/asm/asm-compat.h @@ -70,12 +70,14 @@ BEGIN_FTR_SECTION; \ lwsync; \ END_FTR_SECTION_IFSET(CPU_FTR_476_DD1_1) +#define PPC476_ERR_MTPID PPC476_ERR_DCBx #define PPC476_ERR_ISYNC() \ BEGIN_FTR_SECTION; \ isync; \ END_FTR_SECTION_IFSET(CPU_FTR_476_DD1_1) #else /* ! CONFIG_PPC_47x */ #define PPC476_ERR_DCBx() +#define PPC476_ERR_MTPID() #define PPC476_ERR_ISYNC() #endif /* CONFIG_PPC_47x */ diff --git a/arch/powerpc/kernel/head_44x.S b/arch/powerpc/kernel/head_44x.S index a96796d..c27b0cd 100644 --- a/arch/powerpc/kernel/head_44x.S +++ b/arch/powerpc/kernel/head_44x.S @@ -705,6 +705,7 @@ _GLOBAL(set_context) stw r4, 0x4(r5) #endif mtspr SPRN_PID,r3 + PPC476_ERR_MTPID() isync /* Force context change */ blr -- Dave Kleikamp IBM Linux Technology Center ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[RFC: PATCH 11/13] powerpc/476: Software workaround to fix dcr read/write sequencing.
powerpc/476: Software workaround to fix dcr read/write sequencing.
From: Dave Kleikamp sha...@linux.vnet.ibm.com
Copy the register containing the dcr address to a spr before mfdcrx or
mtdcrx instruction. SPRN_SPRG_WSCRATCH_CRIT seems safe enough to use
as a dummy register, as it is only otherwise used by critical interrupts,
and we don't care if what we write is overwritten.
Ideally, would only do this when CPU_FTR_476_DD1_1 is set, but I'm not
getting the feature macros working in inlined assembler. The dummy store
is pretty cheap though, so I'm doing it unconditionally for 47x.
Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/dcr-native.h | 24 ++--
1 files changed, 22 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/include/asm/dcr-native.h
b/arch/powerpc/include/asm/dcr-native.h
index 7d2e623..768ce50 100644
--- a/arch/powerpc/include/asm/dcr-native.h
+++ b/arch/powerpc/include/asm/dcr-native.h
@@ -50,14 +50,34 @@ extern unsigned int __mfdcr(unsigned int reg);
static inline unsigned int mfdcrx(unsigned int reg)
{
unsigned int ret;
- asm volatile(.long 0x7c000206 | (%0 21) | (%1 16)
+ asm volatile(
+#ifdef CONFIG_PPC_47x
+ /*
+* Workaround: move reg to an spr prior to mfdcrx instruction
+*/
+/* __stringify(BEGIN_FTR_SECTION) */
+mtspr __stringify(SPRN_SPRG_WSCRATCH_CRIT),%1;
+/* __stringify(END_FTR_SECTION_IFSET(CPU_FTR_476_DD1_1)) */
+#endif
+.long 0x7c000206 | (%0 21) | (%1 16)
: =r (ret) : r (reg));
return ret;
}
static inline void mtdcrx(unsigned int reg, unsigned int val)
{
- asm volatile(.long 0x7c000306 | (%0 21) | (%1 16)
+ asm volatile(
+#ifdef CONFIG_PPC_47x
+ /*
+* Workaround: move reg to an spr prior to mtdcrx instruction.
+* (Would love to get the FTR_SECTION macros working for
+* inlined assembler -- shaggy)
+*/
+/* __stringify(BEGIN_FTR_SECTION) */
+mtspr __stringify(SPRN_SPRG_WSCRATCH_CRIT),%1;
+/* __stringify(END_FTR_SECTION_IFSET(CPU_FTR_476_DD1_1)) */
+#endif
+.long 0x7c000306 | (%0 21) | (%1 16)
: : r (val), r (reg));
}
--
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[RFC: PATCH 13/13] powerpc/476: Add dci instruction to async interrupt handlers on DD1 core
powerpc/476: Add dci instruction to async interrupt handlers on DD1 core From: Dave Kleikamp sha...@linux.vnet.ibm.com Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com --- arch/powerpc/include/asm/asm-compat.h |5 + arch/powerpc/kernel/head_booke.h |3 +++ 2 files changed, 8 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/include/asm/asm-compat.h b/arch/powerpc/include/asm/asm-compat.h index fd16e3a..43e9d1b 100644 --- a/arch/powerpc/include/asm/asm-compat.h +++ b/arch/powerpc/include/asm/asm-compat.h @@ -71,6 +71,10 @@ lwsync; \ END_FTR_SECTION_IFSET(CPU_FTR_476_DD1_1) #define PPC476_ERR_MTPID PPC476_ERR_DCBx +#define PPC476_ERR_DCI() \ + BEGIN_FTR_SECTION; \ + dci;\ + END_FTR_SECTION_IFSET(CPU_FTR_476_DD1) #define PPC476_ERR_ISYNC() \ BEGIN_FTR_SECTION; \ isync; \ @@ -78,6 +82,7 @@ #else /* ! CONFIG_PPC_47x */ #define PPC476_ERR_DCBx() #define PPC476_ERR_MTPID() +#define PPC476_ERR_DCI() #define PPC476_ERR_ISYNC() #endif /* CONFIG_PPC_47x */ diff --git a/arch/powerpc/kernel/head_booke.h b/arch/powerpc/kernel/head_booke.h index 6b1ad61..d247c1c 100644 --- a/arch/powerpc/kernel/head_booke.h +++ b/arch/powerpc/kernel/head_booke.h @@ -175,12 +175,14 @@ label: \ #define EXCEPTION(n, label, hdlr, xfer)\ START_EXCEPTION(label); \ + PPC476_ERR_DCI(); \ NORMAL_EXCEPTION_PROLOG;\ addir3,r1,STACK_FRAME_OVERHEAD; \ xfer(n, hdlr) #define CRITICAL_EXCEPTION(n, label, hdlr) \ START_EXCEPTION(label); \ + PPC476_ERR_DCI(); \ CRITICAL_EXCEPTION_PROLOG; \ addir3,r1,STACK_FRAME_OVERHEAD; \ EXC_XFER_TEMPLATE(hdlr, n+2, (MSR_KERNEL ~(MSR_ME|MSR_DE|MSR_CE)), \ @@ -380,6 +382,7 @@ label: \ #define DECREMENTER_EXCEPTION\ START_EXCEPTION(Decrementer) \ + PPC476_ERR_DCI(); \ NORMAL_EXCEPTION_PROLOG; \ lis r0,tsr_...@h; /* Setup the DEC interrupt mask */\ mtspr SPRN_TSR,r0;/* Clear the DEC interrupt */ \ -- Dave Kleikamp IBM Linux Technology Center ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [RFC: PATCH 03/13] powerpc/47x: Base ppc476 support
On Mon, 2010-03-01 at 15:19 -0500, Josh Boyer wrote:
Overall I'm just going to trust you that things aren't broken on 47x :)
A few minor comments below. Also, if Torez and Benh contributed to this code,
then their S-o-b lines should be included as well (same goes for any other
patch).
Right, wanted to make sure they approved of the current state of the
patches. They'll go through Ben anyway.
On Mon, Mar 01, 2010 at 12:13:15PM -0700, Dave Kleikamp wrote:
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index bc8dd53..4af1c28 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -813,6 +813,7 @@
#define PVR_403GC 0x00200200
#define PVR_403GCX 0x00201400
#define PVR_405GP 0x4011
+#define PVR_476 0x11a52000
Is that really needed? None of the 44x CPUs have a PVR value here.
init_cpu_state() checks the PVR against the high-order word of PVR_476
to determine whether the cpu is 44x or 47x, as we eventually want the
same kernel to run on either platform. It's either defined here, or
hardcoded there.
#define PVR_STB03XXX0x4031
#define PVR_NP405H 0x4141
#define PVR_NP405L 0x4161
snip
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index 2fc82ba..338ac47 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -1701,6 +1701,19 @@ static struct cpu_spec __initdata cpu_specs[] = {
.machine_check = machine_check_440A,
.platform = ppc440,
},
+{ /* 476 core */
+.pvr_mask = 0x,
+.pvr_value = 0x11a5,
Could we use PVR_476 here (if it's going to stay).
I guess it could, but it would be inconsistent with the rest of the cpu
table. Also, I'm adding new values for DD1 and DD1.1 (and maybe someday
DD2) that differ in the low-order word, but the logic in init_cpu_state
only uses the high-order bits in PVR_476, so I don't intend to add new
values for those
+.cpu_name = 476,
+.cpu_features = CPU_FTRS_47X,
+.cpu_user_features = COMMON_USER_BOOKE |
+PPC_FEATURE_HAS_FPU,
+.mmu_features = MMU_FTR_TYPE_47x |
+MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_LOCK_BCAST_INVAL,
+.icache_bsize = 32,
+.dcache_bsize = 128,
+.platform = ppc470,
+},
snip
diff --git a/arch/powerpc/platforms/44x/Kconfig
b/arch/powerpc/platforms/44x/Kconfig
index 7486bff..1dfc1c1 100644
--- a/arch/powerpc/platforms/44x/Kconfig
+++ b/arch/powerpc/platforms/44x/Kconfig
@@ -1,6 +1,17 @@
+config PPC_44x_46x
+bool Support for 44x and 46x variants
+depends on 44x
+default n
Why do this? All it seems to do is add a bunch of churn to the Kconfig here.
If the intention was to try and prevent selecting both 44x and 47x kernel
options, then maybe I could see that. However nothing prevents both from
being
enabled.
I'm not really sure about this. If Ben doesn't convince me there's a
reason for it, I think I'll remove it.
Maybe PPC_47x should:
depends on !PPC_44x_46x 44x
Eventually, we want to resolve compiler-time differences in these
platforms and have a binary kernel that could run on both 44x and 47x,
so we'd just have to rip this out later. I'm not convinced we want this
at all. We may want something for the time being to keep from breaking
47x from being accidentally selected, but I'm not sure this is the best
thing.
josh
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Re: [RFC: PATCH 04/13] powerpc/476: add machine check handler for 47x core
On Mon, 2010-03-01 at 15:08 -0600, Olof Johansson wrote:
On Mon, Mar 01, 2010 at 05:13:23AM -0700, Dave Kleikamp wrote:
powerpc/476: add machine check handler for 47x core
From: Dave Kleikamp sha...@linux.vnet.ibm.com
The 47x core's MCSR varies from 44x, so it needs it's own machine check
handler.
--- a/arch/powerpc/kernel/traps.c
+++ b/arch/powerpc/kernel/traps.c
@@ -376,6 +376,44 @@ int machine_check_440A(struct pt_regs *regs)
}
return 0;
}
+
+int machine_check_47x(struct pt_regs *regs)
+{
+ unsigned long reason = get_mc_reason(regs);
+
+ printk(Machine check in kernel mode.\n);
It's quite possible that the other machine check handlers don't have
printk KERN_-levels on them but it would be a good idea to use them here.
Right. As it's new code, it should be as correct as possible.
+ if (reason ESR_IMCP){
+ printk(Instruction Synchronous Machine Check exception\n);
+ mtspr(SPRN_ESR, reason ~ESR_IMCP);
+ }
+ else {
} else {
Or, rather, add an early return above and you can just remove one level of
indentation below.
agreed.
Thanks,
Shaggy
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Re: [RFC: PATCH 06/13] powerpc/4xx: Simple platform for the ISS 4xx simulator
On Mon, 2010-03-01 at 15:29 -0500, Josh Boyer wrote: On Mon, Mar 01, 2010 at 12:16:00PM -0700, Dave Kleikamp wrote: diff --git a/arch/powerpc/platforms/44x/Kconfig b/arch/powerpc/platforms/44x/Kconfig index 1dfc1c1..915c295 100644 --- a/arch/powerpc/platforms/44x/Kconfig +++ b/arch/powerpc/platforms/44x/Kconfig @@ -162,6 +162,17 @@ config YOSEMITE help This option enables support for the AMCC PPC440EP evaluation board. +config ISS4xx +bool ISS 4xx Simulator +depends on (44x || 40x) +default n +select 405GP if 40x +select 440GP if 44x Won't that now build a 44x_46x kernel due to the 'select 440GP' there? If so, doesn't that cause issues for 476? Confused... I hadn't really noticed this because it's been working. When both 44GP and PPC_47x are defined, it doesn't cause any problems for the 476. It's not right though. Thanks, Shaggy -- David Kleikamp IBM Linux Technology Center ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [RFC: PATCH 08/13] powerpc/476: define specific cpu table entry for DD1 and DD1.1 cores
On Mon, 2010-03-01 at 15:24 -0500, Josh Boyer wrote: On Mon, Mar 01, 2010 at 02:13:52PM -0500, Dave Kleikamp wrote: powerpc/476: define specific cpu table entry for DD1 and DD1.1 cores From: Benjamin Herrenschmidt b...@kernel.crashing.org There are still some unstable bits on the DD1 and DD1.1 cores. Don't use the FPU or the tlbivax operation. Define CPU_FTR_476_DD1 and CPU_FTR_476_DD1_1 for additional workarounds in later patches. The DD1 core requires workarounds triggered by both CPU_FTR_476_DD1 and CPU_FTR_476_DD1_1. the DD1.1 core only needs CPU_FTR_476_DD1_1 defined. DD1, DD1.1, and all others have the same PVR value? How do you tell which core version you have? I seemed to have lost the change to the DD1.1 PVR value. I originally coded it this way while I was waiting to find out what it was. DD1.1 is 0x11A52040. I don't know a value for the future versions, so that will have to be filled in later. Actually, I should probably use 0x11A52000, since that's what's defined in reg.h. Thanks, Shaggy -- David Kleikamp IBM Linux Technology Center ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH] powerpc/booke: Fix a couple typos in the advanced ptrace code
powerpc/booke: Fix a couple typos in the advanced ptrace code
Found and fixed a couple typos in the advanced ptrace patches.
(These patches are currently in benh's next tree.)
Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com
Cc: Benjamin Herrenschmidt b...@kernel.crashing.org
Cc: linuxppc-dev list linuxppc-...@ozlabs.org
---
diff --git a/arch/powerpc/include/asm/reg_booke.h
b/arch/powerpc/include/asm/reg_booke.h
index 126cb05..96c2ce8 100644
--- a/arch/powerpc/include/asm/reg_booke.h
+++ b/arch/powerpc/include/asm/reg_booke.h
@@ -421,8 +421,8 @@
/* Bit definitions related to the DBCR2. */
#define DBCR2_DAC1US 0xC000 /* Data Addr Cmp 1 Sup/User */
#define DBCR2_DAC1ER 0x3000 /* Data Addr Cmp 1 Eff/Real */
-#define DBCR2_DAC2US 0x /* Data Addr Cmp 2 Sup/User */
-#define DBCR2_DAC2ER 0x /* Data Addr Cmp 2 Eff/Real */
+#define DBCR2_DAC2US 0x0C00 /* Data Addr Cmp 2 Sup/User */
+#define DBCR2_DAC2ER 0x0300 /* Data Addr Cmp 2 Eff/Real */
#define DBCR2_DAC12M 0x0080 /* DAC 1-2 range enable */
#define DBCR2_DAC12MM 0x0040 /* DAC 1-2 Mask mode*/
#define DBCR2_DAC12MX 0x00C0 /* DAC 1-2 range eXclusive */
diff --git a/arch/powerpc/kernel/ptrace.c b/arch/powerpc/kernel/ptrace.c
index d9b0586..0efa2e3 100644
--- a/arch/powerpc/kernel/ptrace.c
+++ b/arch/powerpc/kernel/ptrace.c
@@ -1070,7 +1070,7 @@ static int del_dac(struct task_struct *child, int
slot)
child-thread.dvc1 = 0;
#endif
} else if (slot == 2) {
- if (child-thread.dac1 == 0)
+ if (child-thread.dac2 == 0)
return -ENOENT;
#ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 00/04] powerpc/booke: Expose advanced debug registers through extended ptrace interface
; p.addr_mode = PPC_BREAKPOINT_MODE_EXACT; p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE; p.addr= (uint64_t) address; p.addr2 = 0; p.condition_value = 0; - set a watchpoint which triggers only with a specific value p.version = PPC_DEBUG_CURRENT_VERSION; p.trigger_type= PPC_BREAKPOINT_TRIGGER_READ; p.addr_mode = PPC_BREAKPOINT_MODE_EXACT; p.condition_mode = PPC_BREAKPOINT_CONDITION_AND | PPC_BREAKPOINT_CONDITION_BE_ALL; p.addr= (uint64_t) address; p.addr2 = 0; p.condition_value = (uint64_t) condition; - set a ranged hardware breakpoint p.version = PPC_DEBUG_CURRENT_VERSION; p.trigger_type= PPC_BREAKPOINT_TRIGGER_EXECUTE; p.addr_mode = PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE; p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE; p.addr= (uint64_t) begin_range; p.addr2 = (uint64_t) end_range; p.condition_value = 0; 3. PTRACE_DELHWDEBUG Takes an integer which identifies an existing breakpoint or watchpoint (i.e., the value returned from PTRACE_SETHWDEBUG), and deletes the corresponding breakpoint or watchpoint.. -- Dave Kleikamp IBM Linux Technology Center ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 03/04] powerpc/booke: Add definitions for advanced debug registers
powerpc/booke: Add definitions for advanced debug registers
From: Dave Kleikamp sha...@linux.vnet.ibm.com
Based on patches originally written by Torez Smith.
This patch adds additional definitions for BookE Debug Registers
to the reg_booke.h header file.
Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com
Acked-by: David Gibson d...@au1.ibm.com
Cc: Torez Smith lnxto...@linux.vnet.ibm.com
Cc: Benjamin Herrenschmidt b...@kernel.crashing.org
Cc: Josh Boyer jwbo...@linux.vnet.ibm.com
Cc: Kumar Gala ga...@kernel.crashing.org
Cc: Sergio Durigan Junior sergi...@br.ibm.com
Cc: Thiago Jung Bauermann bauer...@br.ibm.com
Cc: linuxppc-dev list linuxppc-...@ozlabs.org
---
arch/powerpc/include/asm/processor.h | 36 -
arch/powerpc/include/asm/reg_booke.h | 96 ++
2 files changed, 129 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/include/asm/processor.h
b/arch/powerpc/include/asm/processor.h
index 9eed29e..221ba62 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -161,9 +161,41 @@ struct thread_struct {
#ifdef CONFIG_PPC32
void*pgdir; /* root of page-table tree */
#endif
-#if defined(CONFIG_4xx) || defined (CONFIG_BOOKE)
- unsigned long dbcr0; /* debug control register values */
+#ifdef CONFIG_PPC_ADV_DEBUG_REGS
+ /*
+* The following help to manage the use of Debug Control Registers
+* om the BookE platforms.
+*/
+ unsigned long dbcr0;
unsigned long dbcr1;
+#ifdef CONFIG_BOOKE
+ unsigned long dbcr2;
+#endif
+ /*
+* The stored value of the DBSR register will be the value at the
+* last debug interrupt. This register can only be read from the
+* user (will never be written to) and has value while helping to
+* describe the reason for the last debug trap. Torez
+*/
+ unsigned long dbsr;
+ /*
+* The following will contain addresses used by debug applications
+* to help trace and trap on particular address locations.
+* The bits in the Debug Control Registers above help define which
+* of the following registers will contain valid data and/or addresses.
+*/
+ unsigned long iac1;
+ unsigned long iac2;
+#if CONFIG_PPC_ADV_DEBUG_IACS 2
+ unsigned long iac3;
+ unsigned long iac4;
+#endif
+ unsigned long dac1;
+ unsigned long dac2;
+#if CONFIG_PPC_ADV_DEBUG_DVCS 0
+ unsigned long dvc1;
+ unsigned long dvc2;
+#endif
#endif
/* FP and VSX 0-31 register set */
double fpr[32][TS_FPRWIDTH];
diff --git a/arch/powerpc/include/asm/reg_booke.h
b/arch/powerpc/include/asm/reg_booke.h
index 3bf7835..8808d30 100644
--- a/arch/powerpc/include/asm/reg_booke.h
+++ b/arch/powerpc/include/asm/reg_booke.h
@@ -248,6 +248,8 @@
#define DBSR_RET 0x8000 /* Return Debug Event */
#define DBSR_CIRPT 0x0040 /* Critical Interrupt Taken Event */
#define DBSR_CRET 0x0020 /* Critical Return Debug Event */
+#define DBSR_IAC12ATS 0x0002 /* Instr Address Compare 1/2 Toggle */
+#define DBSR_IAC34ATS 0x0001 /* Instr Address Compare 3/4 Toggle */
#endif
#ifdef CONFIG_40x
#define DBSR_IC0x8000 /* Instruction Completion */
@@ -313,6 +315,38 @@
#define DBCR0_IA12T0x8000 /* Instr Addr 1-2 range Toggle */
#define DBCR0_IA34T0x4000 /* Instr Addr 3-4 range Toggle */
#define DBCR0_FT 0x0001 /* Freeze Timers on debug event */
+
+#define dbcr_iac_range(task) ((task)-thread.dbcr0)
+#define DBCR_IAC12IDBCR0_IA12 /* Range Inclusive */
+#define DBCR_IAC12X(DBCR0_IA12 | DBCR0_IA12X) /* Range Exclusive */
+#define DBCR_IAC12MODE (DBCR0_IA12 | DBCR0_IA12X) /* IAC 1-2 Mode Bits */
+#define DBCR_IAC34IDBCR0_IA34 /* Range Inclusive */
+#define DBCR_IAC34X(DBCR0_IA34 | DBCR0_IA34X) /* Range Exclusive */
+#define DBCR_IAC34MODE (DBCR0_IA34 | DBCR0_IA34X) /* IAC 3-4 Mode Bits */
+
+/* Bit definitions related to the DBCR1. */
+#define DBCR1_DAC1R0x8000 /* DAC1 Read Debug Event */
+#define DBCR1_DAC2R0x4000 /* DAC2 Read Debug Event */
+#define DBCR1_DAC1W0x2000 /* DAC1 Write Debug Event */
+#define DBCR1_DAC2W0x1000 /* DAC2 Write Debug Event */
+
+#define dbcr_dac(task) ((task)-thread.dbcr1)
+#define DBCR_DAC1R DBCR1_DAC1R
+#define DBCR_DAC1W DBCR1_DAC1W
+#define DBCR_DAC2R DBCR1_DAC2R
+#define DBCR_DAC2W DBCR1_DAC2W
+
+/*
+ * Are there any active Debug Events represented in the
+ * Debug Control Registers?
+ */
+#define DBCR0_ACTIVE_EVENTS(DBCR0_ICMP | DBCR0_IAC1 | DBCR0_IAC2 | \
+DBCR0_IAC3 | DBCR0_IAC4)
+#define DBCR1_ACTIVE_EVENTS(DBCR1_DAC1R | DBCR1_DAC2R
Re: [RFC:PATCH 00/03] powerpc: Expose BookE debug registers through extended ptrace interface
On Mon, 2010-01-18 at 16:34 -0600, Dave Kleikamp wrote: On Thu, 2009-12-10 at 20:23 -0600, Kumar Gala wrote: Is GDB smart enough to deal w/no condition_regs? On some Book-E devices we have 2 IACs, 2 DACs, and 0 DVCs. Does it need to be in the features? I wasn't aware that the bookE devices had varying numbers of these registers. I guess I will have to make it a runtime option. Kumar, Can you tell me which bookE processors have 2 IAC's, and which have no DVC's? I think we still may be able to make these compile-time options as long no two cpus that run on the same binary kernel vary in the number of registers. Right now I know the 403 only has 2 IAC's, and I don't intend to expose the DVC's for the 40x processors anyway. If they don't need to be run-time configurable, I think it would be cleaner to define the number of each type of register in CONFIG_ flags and put the logic into the Kconfig files. Thanks, Shaggy -- David Kleikamp IBM Linux Technology Center ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[RFC:PATCH 00/03] powerpc: Expose BookE debug registers through extended ptrace interface
) address; p.addr2 = 0; p.condition_value = 0; - set a watchpoint which triggers only with a specific value p.version = PPC_DEBUG_CURRENT_VERSION; p.trigger_type= PPC_BREAKPOINT_TRIGGER_READ; p.addr_mode = PPC_BREAKPOINT_MODE_EXACT; p.condition_mode = PPC_BREAKPOINT_CONDITION_AND | PPC_BREAKPOINT_CONDITION_BE_ALL; p.addr= (uint64_t) address; p.addr2 = 0; p.condition_value = (uint64_t) condition; - set a ranged hardware breakpoint p.version = PPC_DEBUG_CURRENT_VERSION; p.trigger_type= PPC_BREAKPOINT_TRIGGER_EXECUTE; p.addr_mode = PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE; p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE; p.addr= (uint64_t) begin_range; p.addr2 = (uint64_t) end_range; p.condition_value = 0; 3. PTRACE_DELHWDEBUG Takes an integer which identifies an existing breakpoint or watchpoint (i.e., the value returned from PTRACE_SETHWDEBUG), and deletes the corresponding breakpoint or watchpoint.. -- Dave Kleikamp IBM Linux Technology Center ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[RFC:PATCH 01/03] powerpc: Extended ptrace interface
powerpc: Extended ptrace interface
From: Torez Smith lnxto...@linux.vnet.ibm.com
Add a new extended ptrace interface so that user-space has a single
interface for powerpc, without having to know the specific layout
of the debug registers.
Implement:
PPC_PTRACE_GETHWDEBUGINFO
PPC_PTRACE_SETHWDEBUG
PPC_PTRACE_DELHWDEBUG
Signed-off-by: Torez Smith lnxto...@linux.vnet.ibm.com
Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com
Acked-by: David Gibson d...@au1.ibm.com
Cc: Benjamin Herrenschmidt b...@kernel.crashing.org
Cc: Josh Boyer jwbo...@linux.vnet.ibm.com
Cc: Kumar Gala ga...@kernel.crashing.org
Cc: Sergio Durigan Junior sergi...@br.ibm.com
Cc: Thiago Jung Bauermann bauer...@br.ibm.com
Cc: linuxppc-dev list linuxppc-...@ozlabs.org
---
Documentation/powerpc/ptrace.txt | 134 +
arch/powerpc/include/asm/ptrace.h | 77 +
arch/powerpc/kernel/ptrace.c | 90 +
3 files changed, 301 insertions(+), 0 deletions(-)
create mode 100644 Documentation/powerpc/ptrace.txt
diff --git a/Documentation/powerpc/ptrace.txt b/Documentation/powerpc/ptrace.txt
new file mode 100644
index 000..f4a5499
--- /dev/null
+++ b/Documentation/powerpc/ptrace.txt
@@ -0,0 +1,134 @@
+GDB intends to support the following hardware debug features of BookE
+processors:
+
+4 hardware breakpoints (IAC)
+2 hardware watchpoints (read, write and read-write) (DAC)
+2 value conditions for the hardware watchpoints (DVC)
+
+For that, we need to extend ptrace so that GDB can query and set these
+resources. Since we're extending, we're trying to create an interface
+that's extendable and that covers both BookE and server processors, so
+that GDB doesn't need to special-case each of them. We added the
+following 3 new ptrace requests.
+
+1. PTRACE_PPC_GETHWDEBUGINFO
+
+Query for GDB to discover the hardware debug features. The main info to
+be returned here is the minimum alignment for the hardware watchpoints.
+BookE processors don't have restrictions here, but server processors have
+an 8-byte alignment restriction for hardware watchpoints. We'd like to avoid
+adding special cases to GDB based on what it sees in AUXV.
+
+Since we're at it, we added other useful info that the kernel can return to
+GDB: this query will return the number of hardware breakpoints, hardware
+watchpoints and whether it supports a range of addresses and a condition.
+The query will fill the following structure provided by the requesting process:
+
+struct ppc_debug_info {
+ unit32_t version;
+ unit32_t num_instruction_bps;
+ unit32_t num_data_bps;
+ unit32_t num_condition_regs;
+ unit32_t data_bp_alignment;
+ unit32_t sizeof_condition; /* size of the DVC register */
+ uint64_t features; /* bitmask of the individual flags */
+};
+
+features will have bits indicating whether there is support for:
+
+#define PPC_DEBUG_FEATURE_INSN_BP_RANGE0x1
+#define PPC_DEBUG_FEATURE_INSN_BP_MASK 0x2
+#define PPC_DEBUG_FEATURE_DATA_BP_RANGE0x4
+#define PPC_DEBUG_FEATURE_DATA_BP_MASK 0x8
+
+2. PTRACE_SETHWDEBUG
+
+Sets a hardware breakpoint or watchpoint, according to the provided structure:
+
+struct ppc_hw_breakpoint {
+uint32_t version;
+#define PPC_BREAKPOINT_TRIGGER_EXECUTE 0x1
+#define PPC_BREAKPOINT_TRIGGER_READ 0x2
+#define PPC_BREAKPOINT_TRIGGER_WRITE0x4
+uint32_t trigger_type; /* only some combinations allowed */
+#define PPC_BREAKPOINT_MODE_EXACT 0x0
+#define PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE 0x1
+#define PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE 0x2
+#define PPC_BREAKPOINT_MODE_MASK0x3
+uint32_t addr_mode; /* address match mode */
+
+#define PPC_BREAKPOINT_CONDITION_MODE 0x3
+#define PPC_BREAKPOINT_CONDITION_NONE 0x0
+#define PPC_BREAKPOINT_CONDITION_AND0x1
+#define PPC_BREAKPOINT_CONDITION_EXACT 0x1/* different name for the same
thing as above */
+#define PPC_BREAKPOINT_CONDITION_OR 0x2
+#define PPC_BREAKPOINT_CONDITION_AND_OR 0x3
+#define PPC_BREAKPOINT_CONDITION_BE_ALL 0x00ff /* byte enable bits */
+#define PPC_BREAKPOINT_CONDITION_BE(n) (1((n)+16))
+uint32_t condition_mode; /* break/watchpoint condition flags */
+
+uint64_t addr;
+uint64_t addr2;
+uint64_t condition_value;
+};
+
+A request specifies one event, not necessarily just one register to be set.
+For instance, if the request is for a watchpoint with a condition, both the
+DAC and DVC registers will be set in the same request.
+
+With this GDB can ask for all kinds of hardware breakpoints and watchpoints
+that the BookE supports. COMEFROM breakpoints available in server processors
+are not contemplated, but that is out of the scope of this work.
+
+ptrace will return an integer (handle) uniquely identifying the breakpoint or
+watchpoint just created. This integer will be used
[RFC:PATCH 03/03] powerpc: Add support for BookE Debug Reg. traps, exceptions and ptrace
powerpc: Add support for BookE Debug Reg. traps, exceptions and ptrace
From: Torez Smith lnxto...@linux.vnet.ibm.com
This patch defines context switch and trap related functionality
for BookE specific Debug Registers. It adds support to ptrace()
for setting and getting BookE related Debug Registers
Signed-off-by: Torez Smith lnxto...@linux.vnet.ibm.com
Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com
Cc: Benjamin Herrenschmidt b...@kernel.crashing.org
Cc: Josh Boyer jwbo...@linux.vnet.ibm.com
Cc: Kumar Gala ga...@kernel.crashing.org
Cc: Sergio Durigan Junior sergi...@br.ibm.com
Cc: Thiago Jung Bauermann bauer...@br.ibm.com
Cc: David Gibson d...@au1.ibm.com
Cc: linuxppc-dev list linuxppc-...@ozlabs.org
---
arch/powerpc/include/asm/system.h |5
arch/powerpc/kernel/process.c | 105 +++--
arch/powerpc/kernel/ptrace.c | 453 ++---
arch/powerpc/kernel/signal.c |6
arch/powerpc/kernel/signal_32.c |8 -
arch/powerpc/kernel/traps.c | 91 ++-
6 files changed, 587 insertions(+), 81 deletions(-)
diff --git a/arch/powerpc/include/asm/system.h
b/arch/powerpc/include/asm/system.h
index bb8e006..0634e79 100644
--- a/arch/powerpc/include/asm/system.h
+++ b/arch/powerpc/include/asm/system.h
@@ -112,8 +112,13 @@ static inline int debugger_fault_handler(struct pt_regs
*regs) { return 0; }
#endif
extern int set_dabr(unsigned long dabr);
+#if (defined(CONFIG_40x) || defined(CONFIG_BOOKE))
+extern void do_send_trap(struct pt_regs *regs, unsigned long address,
+unsigned long error_code, int signal_code, int brkpt);
+#else
extern void do_dabr(struct pt_regs *regs, unsigned long address,
unsigned long error_code);
+#endif
extern void print_backtrace(unsigned long *);
extern void show_regs(struct pt_regs * regs);
extern void flush_instruction_cache(void);
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index c930ac3..9f4919a 100644
--- a/arch/powerpc/kernel/process.c
+++ b/arch/powerpc/kernel/process.c
@@ -245,6 +245,24 @@ void discard_lazy_cpu_state(void)
}
#endif /* CONFIG_SMP */
+#if (defined(CONFIG_40x) || defined(CONFIG_BOOKE))
+void do_send_trap(struct pt_regs *regs, unsigned long address,
+ unsigned long error_code, int signal_code, int breakpt)
+{
+ siginfo_t info;
+
+ if (notify_die(DIE_DABR_MATCH, dabr_match, regs, error_code,
+ 11, SIGSEGV) == NOTIFY_STOP)
+ return;
+
+ /* Deliver the signal to userspace */
+ info.si_signo = SIGTRAP;
+ info.si_errno = breakpt;/* breakpoint or watchpoint id */
+ info.si_code = signal_code;
+ info.si_addr = (void __user *)address;
+ force_sig_info(SIGTRAP, info, current);
+}
+#else /* !(defined(CONFIG_40x) || defined(CONFIG_BOOKE)) */
void do_dabr(struct pt_regs *regs, unsigned long address,
unsigned long error_code)
{
@@ -257,12 +275,6 @@ void do_dabr(struct pt_regs *regs, unsigned long address,
if (debugger_dabr_match(regs))
return;
- /* Clear the DAC and struct entries. One shot trigger */
-#if defined(CONFIG_BOOKE)
- mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) ~(DBSR_DAC1R | DBSR_DAC1W
- | DBCR0_IDM));
-#endif
-
/* Clear the DABR */
set_dabr(0);
@@ -273,9 +285,73 @@ void do_dabr(struct pt_regs *regs, unsigned long address,
info.si_addr = (void __user *)address;
force_sig_info(SIGTRAP, info, current);
}
+#endif
static DEFINE_PER_CPU(unsigned long, current_dabr);
+#if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
+/*
+ * Set the debug registers back to their default safe values.
+ */
+static void set_debug_reg_defaults(struct thread_struct *thread)
+{
+ thread-iac1 = thread-iac2 = thread-iac3 = thread-iac4 = 0;
+ thread-dac1 = thread-dac2 = 0;
+ thread-dvc1 = thread-dvc2 = 0;
+ thread-dbcr0 = 0;
+#ifdef CONFIG_BOOKE
+ /*
+* Force User/Supervisor bits to b11 (user-only MSR[PR]=1)
+*/
+ thread-dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US | \
+ DBCR1_IAC3US | DBCR1_IAC4US;
+ /*
+* Force Data Address Compare User/Supervisor bits to be User-only
+* (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0.
+*/
+ thread-dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US;
+#else
+ thread-dbcr1 = 0;
+#endif
+}
+
+static void prime_debug_regs(struct thread_struct *thread)
+{
+ mtspr(SPRN_IAC1, thread-iac1);
+ mtspr(SPRN_IAC2, thread-iac2);
+ mtspr(SPRN_IAC3, thread-iac3);
+ mtspr(SPRN_IAC4, thread-iac4);
+ mtspr(SPRN_DAC1, thread-dac1);
+ mtspr(SPRN_DAC2, thread-dac2);
+ mtspr(SPRN_DVC1, thread-dvc1);
+ mtspr(SPRN_DVC2, thread-dvc2);
+ mtspr(SPRN_DBCR0, thread-dbcr0);
+ mtspr(SPRN_DBCR1, thread-dbcr1);
+#ifdef
[RFC:PATCH 02/03] powerpc: Add definitions for Debug Registers on BookE Platforms
powerpc: Add definitions for Debug Registers on BookE Platforms
From: Torez Smith lnxto...@linux.vnet.ibm.com
This patch adds additional definitions for BookE Debug Registers
to the reg_booke.h header file.
Signed-off-by: Torez Smith lnxto...@linux.vnet.ibm.com
Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com
Acked-by: David Gibson d...@au1.ibm.com
Cc: Benjamin Herrenschmidt b...@kernel.crashing.org
Cc: Josh Boyer jwbo...@linux.vnet.ibm.com
Cc: Kumar Gala ga...@kernel.crashing.org
Cc: Sergio Durigan Junior sergi...@br.ibm.com
Cc: Thiago Jung Bauermann bauer...@br.ibm.com
Cc: linuxppc-dev list linuxppc-...@ozlabs.org
---
arch/powerpc/include/asm/processor.h | 32 +++
arch/powerpc/include/asm/reg_booke.h | 96 ++
2 files changed, 125 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/include/asm/processor.h
b/arch/powerpc/include/asm/processor.h
index 9eed29e..ab0ee94 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -161,9 +161,37 @@ struct thread_struct {
#ifdef CONFIG_PPC32
void*pgdir; /* root of page-table tree */
#endif
-#if defined(CONFIG_4xx) || defined (CONFIG_BOOKE)
- unsigned long dbcr0; /* debug control register values */
+#if defined(CONFIG_40x) || defined(CONFIG_BOOKE)
+ /*
+* The following help to manage the use of Debug Control Registers
+* om the BookE platforms.
+*/
+ unsigned long dbcr0;
unsigned long dbcr1;
+#ifdef CONFIG_BOOKE
+ unsigned long dbcr2;
+#endif
+ /*
+* The stored value of the DBSR register will be the value at the
+* last debug interrupt. This register can only be read from the
+* user (will never be written to) and has value while helping to
+* describe the reason for the last debug trap. Torez
+*/
+ unsigned long dbsr;
+ /*
+* The following will contain addresses used by debug applications
+* to help trace and trap on particular address locations.
+* The bits in the Debug Control Registers above help define which
+* of the following registers will contain valid data and/or addresses.
+*/
+ unsigned long iac1;
+ unsigned long iac2;
+ unsigned long iac3;
+ unsigned long iac4;
+ unsigned long dac1;
+ unsigned long dac2;
+ unsigned long dvc1;
+ unsigned long dvc2;
#endif
/* FP and VSX 0-31 register set */
double fpr[32][TS_FPRWIDTH];
diff --git a/arch/powerpc/include/asm/reg_booke.h
b/arch/powerpc/include/asm/reg_booke.h
index 3bf7835..8808d30 100644
--- a/arch/powerpc/include/asm/reg_booke.h
+++ b/arch/powerpc/include/asm/reg_booke.h
@@ -248,6 +248,8 @@
#define DBSR_RET 0x8000 /* Return Debug Event */
#define DBSR_CIRPT 0x0040 /* Critical Interrupt Taken Event */
#define DBSR_CRET 0x0020 /* Critical Return Debug Event */
+#define DBSR_IAC12ATS 0x0002 /* Instr Address Compare 1/2 Toggle */
+#define DBSR_IAC34ATS 0x0001 /* Instr Address Compare 3/4 Toggle */
#endif
#ifdef CONFIG_40x
#define DBSR_IC0x8000 /* Instruction Completion */
@@ -313,6 +315,38 @@
#define DBCR0_IA12T0x8000 /* Instr Addr 1-2 range Toggle */
#define DBCR0_IA34T0x4000 /* Instr Addr 3-4 range Toggle */
#define DBCR0_FT 0x0001 /* Freeze Timers on debug event */
+
+#define dbcr_iac_range(task) ((task)-thread.dbcr0)
+#define DBCR_IAC12IDBCR0_IA12 /* Range Inclusive */
+#define DBCR_IAC12X(DBCR0_IA12 | DBCR0_IA12X) /* Range Exclusive */
+#define DBCR_IAC12MODE (DBCR0_IA12 | DBCR0_IA12X) /* IAC 1-2 Mode Bits */
+#define DBCR_IAC34IDBCR0_IA34 /* Range Inclusive */
+#define DBCR_IAC34X(DBCR0_IA34 | DBCR0_IA34X) /* Range Exclusive */
+#define DBCR_IAC34MODE (DBCR0_IA34 | DBCR0_IA34X) /* IAC 3-4 Mode Bits */
+
+/* Bit definitions related to the DBCR1. */
+#define DBCR1_DAC1R0x8000 /* DAC1 Read Debug Event */
+#define DBCR1_DAC2R0x4000 /* DAC2 Read Debug Event */
+#define DBCR1_DAC1W0x2000 /* DAC1 Write Debug Event */
+#define DBCR1_DAC2W0x1000 /* DAC2 Write Debug Event */
+
+#define dbcr_dac(task) ((task)-thread.dbcr1)
+#define DBCR_DAC1R DBCR1_DAC1R
+#define DBCR_DAC1W DBCR1_DAC1W
+#define DBCR_DAC2R DBCR1_DAC2R
+#define DBCR_DAC2W DBCR1_DAC2W
+
+/*
+ * Are there any active Debug Events represented in the
+ * Debug Control Registers?
+ */
+#define DBCR0_ACTIVE_EVENTS(DBCR0_ICMP | DBCR0_IAC1 | DBCR0_IAC2 | \
+DBCR0_IAC3 | DBCR0_IAC4)
+#define DBCR1_ACTIVE_EVENTS(DBCR1_DAC1R | DBCR1_DAC2R | \
+DBCR1_DAC1W | DBCR1_DAC2W)
+#define DBCR_ACTIVE_EVENTS(dbcr0, dbcr1) (((dbcr0
Re: [RFC:PATCH 02/03] powerpc: Add definitions for Debug Registers on BookE Platforms
On Fri, 2009-12-11 at 11:53 +1100, David Gibson wrote: On Thu, Dec 10, 2009 at 01:57:21PM -0200, Dave Kleikamp wrote: powerpc: Add definitions for Debug Registers on BookE Platforms From: Torez Smith lnxto...@linux.vnet.ibm.com This patch adds additional definitions for BookE Debug Registers to the reg_booke.h header file. Signed-off-by: Torez Smith lnxto...@linux.vnet.ibm.com Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com arch/powerpc/include/asm/processor.h | 30 +- arch/powerpc/include/asm/reg_booke.h | 176 +- 2 files changed, 178 insertions(+), 28 deletions(-) [snip] + /* +* The following will contain addresses used by debug applications +* to help trace and trap on particular address locations. +* The bits in the Debug Control Registers above help define which +* of the following registers will contain valid data and/or addresses. +*/ + unsigned long iac1; + unsigned long iac2; + unsigned long iac3; + unsigned long iac4; + unsigned long dac1; + unsigned long dac2; + unsigned long dvc1; + unsigned long dvc2; I think you'd make the logic in patch 3 substantially easier, if you defined these as unsigned long iac[4]; unsigned long dac[2]; unsigned long dvc[2]; instead of as individual structure members. I've cleaned up the logic a bit without having to change this. Any further simplification of the code would also involve abstracting the #defines further and I'm not sure it would make anything more clear. [snip] + +#define dbcr_iac_range(task) ((task)-thread.dbcr0) Hrm, I think the way these macros work to do the 40x vs. BookE abstration is kind of ugly. But an unequivocally better way doesn't immediately occur to me. I haven't changed this. I don't have a better solution. Shaggy -- David Kleikamp IBM Linux Technology Center ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [RFC:PATCH 03/03] powerpc: Add support for BookE Debug Reg. traps, exceptions and ptrace
On Fri, 2009-12-11 at 14:26 +1100, David Gibson wrote:
On Thu, Dec 10, 2009 at 01:57:27PM -0200, Dave Kleikamp wrote:
powerpc: Add support for BookE Debug Reg. traps, exceptions and ptrace
From: Torez Smith lnxto...@linux.vnet.ibm.com
This patch defines context switch and trap related functionality
for BookE specific Debug Registers. It adds support to ptrace()
for setting and getting BookE related Debug Registers
[snip]
+#if !(defined(CONFIG_40x) || defined(CONFIG_BOOKE))
void do_dabr(struct pt_regs *regs, unsigned long address,
unsigned long error_code)
{
@@ -257,12 +275,6 @@ void do_dabr(struct pt_regs *regs, unsigned long
address,
if (debugger_dabr_match(regs))
return;
- /* Clear the DAC and struct entries. One shot trigger */
-#if defined(CONFIG_BOOKE)
- mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) ~(DBSR_DAC1R | DBSR_DAC1W
- | DBCR0_IDM));
-#endif
-
/* Clear the DABR */
set_dabr(0);
Uh.. does this imply we're keeping the one-shot behaviour for
new-style breakpoints? To me the interface really suggests they're
persistent, although dealing with the semantics of that at signal time
can get curly.
I've left it as one-shot. The gdb guys seem happy with that.
[snip]
int set_dabr(unsigned long dabr)
{
__get_cpu_var(current_dabr) = dabr;
@@ -284,7 +358,7 @@ int set_dabr(unsigned long dabr)
return ppc_md.set_dabr(dabr);
/* XXX should we have a CPU_FTR_HAS_DABR ? */
-#if defined(CONFIG_BOOKE)
+#if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
mtspr(SPRN_DAC1, dabr);
Uh.. this would seem to be wrong. set_dabr(0) is called from the
debug exception - but nowadays that could be tiggered by a DAC other
than DAC1.
Right now, the only place left that set_dabr() is called for BOOKE or
40x is from xmon. I think that's already a problem in that it doesn't
play nicely with ptrace and it fails to set DBCR0_DAC1R or DBCR0_DAC1W.
We probably need an independent patch for that.
[snip]
+#else
/* As described above, it was assumed 3 bits were passed with the data
* address, but we will assume only the mode bits will be passed
* as to not cause alignment restrictions for DAC-based processors.
*/
/* DAC's hold the whole address without any mode flags */
- task-thread.dabr = data ~0x3UL;
-
- if (task-thread.dabr == 0) {
- task-thread.dbcr0 = ~(DBSR_DAC1R | DBSR_DAC1W | DBCR0_IDM);
- task-thread.regs-msr = ~MSR_DE;
+ task-thread.dac1 = data ~0x3UL;
+
+ if (task-thread.dac1 == 0) {
+ dbcr_dac(task) = ~(DBCR_DAC1R | DBCR_DAC1W);
+ if (!DBCR_ACTIVE_EVENTS(task-thread.dbcr0,
+ task-thread.dbcr1)) {
+ task-thread.regs-msr = ~MSR_DE;
+ task-thread.dbcr0 = ~DBCR0_IDM;
+ }
return 0;
}
Ok, so effectively the old ptrace method of setting the DABR acts as a
bypass to set DAC1, rather than having the old interface being
implemented via the new interface. This has some weirdness - you can
clobber a new-style breakpoint in DAC1 using the old interface, for
example. Still, it might be the simplest approach for a first cut.
I really didn't consider a program using both the old and new interface.
What *is* a problem though, is that this means that the SIGTRAP will
always give a slot number, even for a breakpoint established using the
old interface. Part of the idea of encoding the registered breakpoint
number in the siginfo was to be able to distinguish between old-style
and new-style breakpoints at trap time.
Do we realistically expect both the old and new style breakpoints to be
used together? I'm having trouble visualizing the scenerio.
[snip]
+ int slot;
+
+ if (byte_enable (condition_mode == 0))
+ return -EINVAL;
+
+ if (bp_info-addr = TASK_SIZE)
+ return -EIO;
+
+ if ((dbcr_dac(child) (DBCR_DAC1R | DBCR_DAC1W)) == 0) {
+ if (bp_info-trigger_type PPC_BREAKPOINT_TRIGGER_READ)
+ dbcr_dac(child) |= DBCR_DAC1R;
+ if (bp_info-trigger_type PPC_BREAKPOINT_TRIGGER_WRITE)
+ dbcr_dac(child) |= DBCR_DAC1W;
+ child-thread.dac1 = (unsigned long)bp_info-addr;
+#ifdef CONFIG_BOOKE
Better to have a runtime feature bit test here, than use an #ifdef to
distinguish the 40x and BookE cases. Plus, you should return an error
if the user attempts to use a feature not supported on this hardware,
which doesn't seem to happen here.
I'll take a look at making this a runtime feature.
Shaggy
--
David Kleikamp
IBM Linux Technology Center
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Re: [RFC:PATCH 00/03] powerpc: Expose BookE debug registers through extended ptrace interface
On Thu, 2009-12-10 at 20:45 -0600, Kumar Gala wrote: What do we do in EDM mode? We need a flag somewhere to determine if HW supports conveying DBCR0[EDM] and if it does which of the ptrace calls fails? I really don't have a good answer to this. I'm open to any and all advice. Shaggy -- David Kleikamp IBM Linux Technology Center ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
