Re: [PATCH 1/3] powerpc/mpic: add irq_set_wake support
On Mar 18, 2013, at 9:41 AM, Benjamin Herrenschmidt wrote:
> On Mon, 2013-03-18 at 09:28 +, Wang Dongsheng-B40534 wrote:
>> Hi Benjamin & Kumar,
>>
>> I am not sure who can apply these patches...
>>
>> Could you apply these patches?
>
> I can but I need somebody to review them, I don't have the bandwidth nor
> am I familiar with the FSL changes to the MPIC.
>
> Cheers,
> Ben.
I'd ask for Scott's ack/signoff on these patches for ben or I to accept them.
- k
>
>> Thanks.
>>
>> [1/3] powerpc/mpic: add irq_set_wake support
>> http://patchwork.ozlabs.org/patch/226034/
>>
>> [2/3] powerpc/mpic: add global timer support
>> http://patchwork.ozlabs.org/patch/226035/
>>
>> [3/3] powerpc/fsl: add MPIC timer wakeup support
>> http://patchwork.ozlabs.org/patch/226036/
>>
>>> -Original Message-
>>> From: Wang Dongsheng-B40534
>>> Sent: Friday, March 08, 2013 3:39 PM
>>> To: Wood Scott-B07421; Gala Kumar-B11780
>>> Cc: linuxppc-dev@lists.ozlabs.org; Wang Dongsheng-B40534
>>> Subject: [PATCH 1/3] powerpc/mpic: add irq_set_wake support
>>>
>>> Add irq_set_wake support. Just add IRQF_NO_SUSPEND to desc->action->flag.
>>> So the wake up interrupt will not be disable in suspend_device_irqs.
>>>
>>> Signed-off-by: Wang Dongsheng
>>> ---
>>> arch/powerpc/sysdev/mpic.c | 15 +++
>>> 1 files changed, 15 insertions(+), 0 deletions(-)
>>>
>>> diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
>>> index 3b2efd4..10e474e 100644
>>> --- a/arch/powerpc/sysdev/mpic.c
>>> +++ b/arch/powerpc/sysdev/mpic.c
>>> @@ -920,6 +920,18 @@ int mpic_set_irq_type(struct irq_data *d, unsigned
>>> int flow_type)
>>> return IRQ_SET_MASK_OK_NOCOPY;
>>> }
>>>
>>> +static int mpic_irq_set_wake(struct irq_data *d, unsigned int on) {
>>> + struct irq_desc *desc = container_of(d, struct irq_desc, irq_data);
>>> +
>>> + if (on)
>>> + desc->action->flags |= IRQF_NO_SUSPEND;
>>> + else
>>> + desc->action->flags &= ~IRQF_NO_SUSPEND;
>>> +
>>> + return 0;
>>> +}
>>> +
>>> void mpic_set_vector(unsigned int virq, unsigned int vector) {
>>> struct mpic *mpic = mpic_from_irq(virq); @@ -957,6 +969,7 @@ static
>>> struct irq_chip mpic_irq_chip = {
>>> .irq_unmask = mpic_unmask_irq,
>>> .irq_eoi= mpic_end_irq,
>>> .irq_set_type = mpic_set_irq_type,
>>> + .irq_set_wake = mpic_irq_set_wake,
>>> };
>>>
>>> #ifdef CONFIG_SMP
>>> @@ -971,6 +984,7 @@ static struct irq_chip mpic_tm_chip = {
>>> .irq_mask = mpic_mask_tm,
>>> .irq_unmask = mpic_unmask_tm,
>>> .irq_eoi= mpic_end_irq,
>>> + .irq_set_wake = mpic_irq_set_wake,
>>> };
>>>
>>> #ifdef CONFIG_MPIC_U3_HT_IRQS
>>> @@ -981,6 +995,7 @@ static struct irq_chip mpic_irq_ht_chip = {
>>> .irq_unmask = mpic_unmask_ht_irq,
>>> .irq_eoi= mpic_end_ht_irq,
>>> .irq_set_type = mpic_set_irq_type,
>>> + .irq_set_wake = mpic_irq_set_wake,
>>> };
>>> #endif /* CONFIG_MPIC_U3_HT_IRQS */
>>>
>>> --
>>> 1.7.5.1
>>
>
>
>
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Re: [PATCH]qonverge/usb: Add first usb controller node
On Feb 28, 2013, at 2:46 AM, Ramneek Mehresh wrote: > Add first usb controller node for qonverge qoriq platforms like > B4860, etc > > Signed-off-by: Ramneek Mehresh > --- > Applies on git://git.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git > (branch next) > > arch/powerpc/boot/dts/fsl/qonverge-usb2-dr-0.dtsi | 41 +++ > 1 file changed, 41 insertions(+) > create mode 100644 arch/powerpc/boot/dts/fsl/qonverge-usb2-dr-0.dtsi applied to next - k ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] mmc: sdhci-pltfm: Fix timeout on t4240's sdhci controller
On Mar 7, 2013, at 8:57 PM, Chunhe Lan wrote: > On 03/08/2013 12:30 AM, Gala Kumar-B11780 wrote: >> On Mar 7, 2013, at 2:05 AM, Chunhe Lan wrote: >> >>> This patch fixes timeout problems on t4240's sdhci controller: >>> >>> mmc0: Too large timeout requested for CMD25! >>> mmc0: Too large timeout requested for CMD25! >>> mmc0: Too large timeout requested for CMD25! >>> >>> Signed-off-by: Chunhe Lan >>> --- >>> drivers/mmc/host/sdhci-pltfm.c |1 + >>> 1 files changed, 1 insertions(+), 0 deletions(-) >>> >>> diff --git a/drivers/mmc/host/sdhci-pltfm.c b/drivers/mmc/host/sdhci-pltfm.c >>> index 3145a78..9db7b12 100644 >>> --- a/drivers/mmc/host/sdhci-pltfm.c >>> +++ b/drivers/mmc/host/sdhci-pltfm.c >>> @@ -94,6 +94,7 @@ void sdhci_get_of_property(struct platform_device *pdev) >>> >>> if (of_device_is_compatible(np, "fsl,p2020-esdhc") || >>> of_device_is_compatible(np, "fsl,p1010-esdhc") || >>> + of_device_is_compatible(np, "fsl,t4240-esdhc") || >>> of_device_is_compatible(np, "fsl,mpc8536-esdhc")) >>> host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; >>> >>> -- >>> 1.7.6.5 >>> >> >> Why does this occur? Is it a board issue? Is it a silicon issue? Is it >> due to some erratum? Why T4 only? > It would be the property of T4 hardware, and please see below the patch > which locates > the mail list of freescale: > > eSDHC: mmc:host host need long time to generate command complete interrupt > > According to Spec 2.0, command complete interrupt will generate within 150 > SD-CLK. > But this was not enough on T4240 board. So give it sufficient time to detect > command > timeout. 1000 * HZ will be enough, this value was test on all T4 board, all > worked well. > > Signed-off-by: Jerry Huang > Signed-off-by: Haijun Zhang I still don't understand the explanation of the issue on T4. Why doesn't P4080, P5020, etc suffer from the issue? - k ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] edac/85xx: Add PCIe error interrupt edac support
On Mar 8, 2013, at 2:32 AM, Chunhe Lan wrote:
> Adding pcie error interrupt edac support for mpc85xx, p3041, p4080,
> and p5020. The mpc85xx uses the legacy interrupt report mechanism -
> the error interrupts are reported directly to mpic. While, the p3041/
> p4080/p5020 attaches the most of error interrupts to interrupt zero.
> And report error interrupts to mpic via interrupt 0.
>
> This patch can handle both of them.
>
> Signed-off-by: Chunhe Lan
> ---
> drivers/edac/mpc85xx_edac.c | 169 ---
> drivers/edac/mpc85xx_edac.h |7 ++
> 2 files changed, 165 insertions(+), 11 deletions(-)
Does this also work on T4 / PCIe controller rev3.0?
>
> diff --git a/drivers/edac/mpc85xx_edac.c b/drivers/edac/mpc85xx_edac.c
> index 42a840d..085b6b3 100644
> --- a/drivers/edac/mpc85xx_edac.c
> +++ b/drivers/edac/mpc85xx_edac.c
> @@ -1,5 +1,6 @@
> /*
> * Freescale MPC85xx Memory Controller kenel module
> + * Copyright (c) 2013 Freescale Semiconductor, Inc.
> *
> * Author: Dave Jiang
> *
> @@ -196,6 +197,120 @@ static void mpc85xx_pci_check(struct edac_pci_ctl_info
> *pci)
> edac_pci_handle_npe(pci, pci->ctl_name);
> }
>
> +static void mpc85xx_pcie_check(struct edac_pci_ctl_info *pci)
> +{
> + struct mpc85xx_pci_pdata *pdata = pci->pvt_info;
> + u32 err_detect;
> +
> + err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR);
> +
> + pr_err("PCIE error(s) detected\n");
> + pr_err("PCIE ERR_DR register: 0x%08x\n", err_detect);
> + pr_err("PCIE ERR_CAP_STAT register: 0x%08x\n",
> + in_be32(pdata->pci_vbase + MPC85XX_PCI_GAS_TIMR));
> + pr_err("PCIE ERR_CAP_R0 register: 0x%08x\n",
> + in_be32(pdata->pci_vbase + MPC85XX_PCIE_ERR_CAP_R0));
> + pr_err("PCIE ERR_CAP_R1 register: 0x%08x\n",
> + in_be32(pdata->pci_vbase + MPC85XX_PCIE_ERR_CAP_R1));
> + pr_err("PCIE ERR_CAP_R2 register: 0x%08x\n",
> + in_be32(pdata->pci_vbase + MPC85XX_PCIE_ERR_CAP_R2));
> + pr_err("PCIE ERR_CAP_R3 register: 0x%08x\n",
> + in_be32(pdata->pci_vbase + MPC85XX_PCIE_ERR_CAP_R3));
> +
> + /* clear error bits */
> + out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect);
> +}
> +
> +/*
> + * This function is for error interrupt ORed mechanism.
> + * This mechanism attaches most functions' error interrupts to interrupt 0.
> + * And report error interrupt to mpic via interrupt 0.
> + * EIMR0 - Error Interrupt Mask Register 0.
> + *
> + * This function check whether the device support error interrupt ORed
> + * mechanism via device tree. If supported, umask pcie error interrupt
> + * bit in EIMR0.
> + */
> +static int mpc85xx_err_int_en(struct platform_device *op)
> +{
> + u32 *int_cell;
> + struct device_node *np;
> + void __iomem *mpic_base;
> + u32 reg_tmp;
> + u32 int_len;
> + struct resource r;
> + int res;
> +
> + if (!op->dev.of_node)
> + return -EINVAL;
> +
> + /*
> + * Unmask pcie error interrupt bit in EIMR0.
> + * Extend interrupt specifier has 4 cells.
> + * For the 3rd cell:
> + * 0 -- normal interrupt;
> + * 1 -- error interrupt.
> + */
> + int_cell = (u32 *)of_get_property(op->dev.of_node, "interrupts",
> + &int_len);
> + if ((int_len/sizeof(u32)) == 4) {
> + /* soc has error interrupt integration handling mechanism */
> + if (*(int_cell + 2) == 1) {
> + np = of_find_node_by_type(NULL, "open-pic");
> +
> + if (of_address_to_resource(np, 0, &r)) {
> + pr_err("%s: Failed to map mpic regs\n",
> + __func__);
> + of_node_put(np);
> + res = -ENOMEM;
> + goto err;
> + }
> +
> + if (!request_mem_region(r.start, r.end - r.start + 1,
> + "mpic")) {
> + pr_err("%s: Error when requesting mem region\n",
> + __func__);
> + res = -EBUSY;
> + goto err;
> + }
> +
> + mpic_base = ioremap(r.start, r.end - r.start + 1);
> + if (!mpic_base) {
> + pr_err("%s: Unable to map mpic regs\n",
> + __func__);
> + res = -ENOMEM;
> + goto err_ioremap;
> + }
> +
> + reg_tmp = in_be32(mpic_base + MPC85XX_MPIC_EIMR0);
> + out_be32(mpic_base + MPC85XX_MPIC_EIMR0, reg_tmp &
> + ~(1 << (31 - *(int_cell + 3;
> + iounm
Re: [PATCH] mmc: sdhci-pltfm: Fix timeout on t4240's sdhci controller
On Mar 7, 2013, at 2:05 AM, Chunhe Lan wrote: > This patch fixes timeout problems on t4240's sdhci controller: > > mmc0: Too large timeout requested for CMD25! > mmc0: Too large timeout requested for CMD25! > mmc0: Too large timeout requested for CMD25! > > Signed-off-by: Chunhe Lan > --- > drivers/mmc/host/sdhci-pltfm.c |1 + > 1 files changed, 1 insertions(+), 0 deletions(-) > > diff --git a/drivers/mmc/host/sdhci-pltfm.c b/drivers/mmc/host/sdhci-pltfm.c > index 3145a78..9db7b12 100644 > --- a/drivers/mmc/host/sdhci-pltfm.c > +++ b/drivers/mmc/host/sdhci-pltfm.c > @@ -94,6 +94,7 @@ void sdhci_get_of_property(struct platform_device *pdev) > > if (of_device_is_compatible(np, "fsl,p2020-esdhc") || > of_device_is_compatible(np, "fsl,p1010-esdhc") || > + of_device_is_compatible(np, "fsl,t4240-esdhc") || > of_device_is_compatible(np, "fsl,mpc8536-esdhc")) > host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; > > -- > 1.7.6.5 > Why does this occur? Is it a board issue? Is it a silicon issue? Is it due to some erratum? Why T4 only? - k ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] bsc9131:l2sram: Add compatible string for BSC9131 platform
On Feb 19, 2013, at 3:14 AM, Harninder Rai wrote: > Signed-off-by: Harninder Rai > --- > arch/powerpc/sysdev/fsl_85xx_l2ctlr.c |1 + > 1 files changed, 1 insertions(+), 0 deletions(-) applied to next - k ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] bsc9131/dts: Correct typo in SDHC device node
On Feb 19, 2013, at 3:13 AM, Harninder Rai wrote: > BSC9131RDB doesn't have SDHC enabled. As a result of this typo, > the node was not getting disabled from the device tree which was > leading to linux hang during bootup > > Signed-off-by: Harninder Rai > --- > arch/powerpc/boot/dts/bsc9131rdb.dtsi |2 +- > 1 files changed, 1 insertions(+), 1 deletions(-) applied to next - k ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] bsc913x:defconfig: Add new defconfig file for BSC913x platforms
On Feb 19, 2013, at 3:14 AM, Harninder Rai wrote: > BSC913x are heterogeneous platforms having DSP and PowerPC. > * Lot of new IPs like AIC (Antenna Interface Controller), RF (radio) etc > * Such IPs are not present in any other 85xx platform > * Lot of optimizations related to ethernet/ASF (Application Specific Fastpath) > are enabled in this config > * IPC for inter-domain communication (DSP and PA) is present > > Signed-off-by: Harninder Rai > --- > arch/powerpc/configs/qoriq_sdk_asf_term_defconfig | 209 + > 1 files changed, 209 insertions(+), 0 deletions(-) > create mode 100644 arch/powerpc/configs/qoriq_sdk_asf_term_defconfig I'm ignoring this as this is clearly meant for FSL SDK and not upstream. - k ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] powerpc/85xx: dts - add ranges property for SEC
On Feb 18, 2013, at 6:29 PM, Po Liu wrote: > This facilitates getting the physical address of the SEC node. > > Signed-off-by: Liu po > --- > arch/powerpc/boot/dts/fsl/pq3-sec4.4-0.dtsi |1 + > 1 files changed, 1 insertions(+), 0 deletions(-) Why are you reposting this, I already applied it: http://git.kernel.org/?p=linux/kernel/git/galak/powerpc.git;a=commit;h=db29cd3c4497e7edf9176284ba7cf3cec1814c7a - k ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] [v2] powerpc/fsl: remove extraneous DIU platform functions
On Jan 17, 2013, at 5:26 PM, Timur Tabi wrote: > From: Timur Tabi > > The Freescale DIU driver was recently updated to not require every DIU > platform function, so now we can remove the unneeded functions from > some boards. > > Signed-off-by: Timur Tabi > --- > arch/powerpc/platforms/512x/mpc512x_shared.c |5 --- > arch/powerpc/platforms/85xx/p1022_ds.c | 38 -- > arch/powerpc/platforms/85xx/p1022_rdk.c | 12 > 3 files changed, 0 insertions(+), 55 deletions(-) applied to next - k ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 2/2] powerpc/85xx: describe the PAMU topology in the device tree
On Jan 17, 2013, at 4:34 PM, Timur Tabi wrote: > From: Timur Tabi > > The PAMU caches use the LIODNs to determine which cache lines hold the > entries for the corresponding LIODs. The LIODNs must therefore be > carefully assigned to avoid cache thrashing -- two active LIODs with > LIODNs that put them in the same cache line. > > Currently, LIODNs are statically assigned by U-Boot, but this has > limitations. LIODNs are assigned even for devices that may be disabled > or unused by the kernel. Static assignments also do not allow for device > drivers which may know which LIODs can be used simultaneously. In > other words, we really should assign LIODNs dynamically in Linux. > > To do that, we need to describe the PAMU device and cache topologies in > the device trees. > > Signed-off-by: Timur Tabi > --- > .../devicetree/bindings/powerpc/fsl/guts.txt | 14 ++- > .../devicetree/bindings/powerpc/fsl/pamu.txt | 142 > arch/powerpc/boot/dts/fsl/p2041si-post.dtsi| 87 +++-- > arch/powerpc/boot/dts/fsl/p3041si-post.dtsi| 87 +++-- > arch/powerpc/boot/dts/fsl/p4080si-post.dtsi| 68 +- > arch/powerpc/boot/dts/fsl/p5020si-post.dtsi| 92 +++-- > arch/powerpc/boot/dts/fsl/p5040si-post.dtsi| 92 +++-- > 7 files changed, 533 insertions(+), 49 deletions(-) > create mode 100644 Documentation/devicetree/bindings/powerpc/fsl/pamu.txt applied to next - k ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 1/2] powerpc/85xx: fix various PCI node compatible strings
On Jan 17, 2013, at 4:34 PM, Timur Tabi wrote: > From: Timur Tabi > > Fix and/or improve the compatible strings of the PCI device tree nodes for > some Freescale SOCs. This fixes some issues and improves consistency among > the SOCs. > > Specifically: > > 1) The P1022 has a v1 PCIe controller, so the compatible property should just > say "fsl,mpc8548-pcie". U-Boot does not look for "fsl,p1022-pcie", so it > wasn't fixing up the node. > > 2) The P4080 has a v2.1 PCIe controller, so add that version-specific string > to the device tree. Update the kernel to also look for that string. > Currently, the kernel looks for "fsl,p4080-pcie" specifically, but > eventually that check should be deleted. > > 3) The P1010 device tree claims compatibility with v2.2 and v2.3, but that's > redundant. No other device tree does this. Remove the v2.2 string. > > 4) The kernel looks for both "fsl,p1023-pcie" and "fsl,qoriq-pcie-v2.2", > even though the P1023 device trees has always included both strings. Remove > the search for "fsl,p1023-pcie". > > Signed-off-by: Timur Tabi > --- > arch/powerpc/boot/dts/fsl/p1010si-post.dtsi |4 ++-- > arch/powerpc/boot/dts/fsl/p1022si-post.dtsi |6 +++--- > arch/powerpc/boot/dts/fsl/p4080si-post.dtsi |6 +++--- > arch/powerpc/sysdev/fsl_pci.c | 15 ++- > 4 files changed, 18 insertions(+), 13 deletions(-) applied to next - k ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 2/2] powerpc/85xx: describe the PAMU topology in the device tree
On Jan 17, 2013, at 4:34 PM, Timur Tabi wrote: > From: Timur Tabi > > The PAMU caches use the LIODNs to determine which cache lines hold the > entries for the corresponding LIODs. The LIODNs must therefore be > carefully assigned to avoid cache thrashing -- two active LIODs with > LIODNs that put them in the same cache line. > > Currently, LIODNs are statically assigned by U-Boot, but this has > limitations. LIODNs are assigned even for devices that may be disabled > or unused by the kernel. Static assignments also do not allow for device > drivers which may know which LIODs can be used simultaneously. In > other words, we really should assign LIODNs dynamically in Linux. > > To do that, we need to describe the PAMU device and cache topologies in > the device trees. > > Signed-off-by: Timur Tabi > --- > .../devicetree/bindings/powerpc/fsl/guts.txt | 14 ++- > .../devicetree/bindings/powerpc/fsl/pamu.txt | 142 > arch/powerpc/boot/dts/fsl/p2041si-post.dtsi| 87 +++-- > arch/powerpc/boot/dts/fsl/p3041si-post.dtsi| 87 +++-- > arch/powerpc/boot/dts/fsl/p4080si-post.dtsi| 68 +- > arch/powerpc/boot/dts/fsl/p5020si-post.dtsi| 92 +++-- > arch/powerpc/boot/dts/fsl/p5040si-post.dtsi| 92 +++-- > 7 files changed, 533 insertions(+), 49 deletions(-) > create mode 100644 Documentation/devicetree/bindings/powerpc/fsl/pamu.txt Scott, Stuart, does this have your guys Ack? - k ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] powerpc/mpc85xx: Change spin table to cached memory
On Sep 29, 2012, at 6:44 PM, York Sun wrote: > ePAPR v1.1 requires the spin table to be in cached memory. So we need > to change the call argument of ioremap to enable cache and coherence. > We also flush the cache after writing to spin table to keep it compatible > with previous cache-inhibit spin table. Flushing before and after > accessing spin table is recommended by ePAPR. > > Signed-off-by: York Sun > Acked-by: Timur Tabi > --- > This patch applies to > git://git.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git next branch. > > arch/powerpc/platforms/85xx/smp.c | 49 +++-- > 1 file changed, 36 insertions(+), 13 deletions(-) applied to next - k ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 1/3] edac: Use ccsr_pci structure instead of hardcoded define
On Sep 27, 2012, at 2:02 PM, Chunhe Lan wrote: > There are some differences of register offset and definition between > pci and pcie error management registers. While, some other pci/pcie > error management registers are nearly the same. > > To merge pci and pcie edac code into one, it is easier to use ccsr_pci > structure than the hardcoded define. So remove the hardcoded define and > add pci/pcie error management register in ccsr_pci structure. > > Signed-off-by: Chunhe Lan > --- > arch/powerpc/sysdev/fsl_pci.h | 46 +--- > drivers/edac/mpc85xx_edac.h | 12 +- > 2 files changed, 40 insertions(+), 18 deletions(-) This patch breaks building the kernel. You can't remove the defines MPC85XX_PCI_ERR_* and not change the code that uses them - k ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 3/3] edac/85xx: Enable the EDAC PCI err driver by device_initcall
On Sep 27, 2012, at 11:09 AM, Scott Wood wrote:
> On 09/27/2012 02:02:03 PM, Chunhe Lan wrote:
>> Original process of call:
>> The mpc85xx_pci_err_probe function completes to been registered
>> and enabled of EDAC PCI err driver at the latter time stage of
>> kernel boot in the mpc85xx_edac.c.
>> Current process of call:
>> The mpc85xx_pci_err_probe function completes to been registered
>> and enabled of EDAC PCI err driver at the first time stage of
>> kernel boot in the fsl_pci.c.
>> So in this case the following error messages appear in the boot log:
>>PCI: Probing PCI hardware
>>pci :00:00.0: ignoring class b20 (doesn't match header type 01)
>>PCIE error(s) detected
>>PCIE ERR_DR register: 0x0002
>>PCIE ERR_CAP_STAT register: 0x8001
>>PCIE ERR_CAP_R0 register: 0x0800
>>PCIE ERR_CAP_R1 register: 0x
>>PCIE ERR_CAP_R2 register: 0x
>>PCIE ERR_CAP_R3 register: 0x
>> Because the EDAC PCI err driver is registered and enabled earlier than
>> original point of call. But at this point of time, PCI hardware is not
>> probed and initialized, and it is in unknowable state.
>> So, move enable function into mpc85xx_pci_err_en which is called at the
>> middle time stage of kernel boot and after PCI hardware is probed and
>> initialized by device_initcall in the fsl_pci.c.
>> Signed-off-by: Chunhe Lan
>> ---
>> arch/powerpc/sysdev/fsl_pci.c | 12 ++
>> arch/powerpc/sysdev/fsl_pci.h |5
>> drivers/edac/mpc85xx_edac.c | 47
>> 3 files changed, 50 insertions(+), 14 deletions(-)
>> diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
>> index 3d6f4d8..a591965 100644
>> --- a/arch/powerpc/sysdev/fsl_pci.c
>> +++ b/arch/powerpc/sysdev/fsl_pci.c
>> @@ -904,4 +904,16 @@ static int __init fsl_pci_init(void)
>> return platform_driver_register(&fsl_pci_driver);
>> }
>> arch_initcall(fsl_pci_init);
>> +
>> +static int __init fsl_pci_err_en(void)
>> +{
>> +struct device_node *np;
>> +
>> +for_each_node_by_type(np, "pci")
>> +if (of_match_node(pci_ids, np))
>> +mpc85xx_pci_err_en(np);
>> +
>> +return 0;
>> +}
>> +device_initcall(fsl_pci_err_en);
>
> Why can't you call this from the normal PCIe controller init, instead of
> searching for the node independently?
Don't we have this now with mpc85xx_pci_err_probe() ??
- k
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Re: [PATCH] p1023rds_defconfig: Add USB support
On Sep 14, 2012, at 2:57 PM, Chunhe Lan wrote: > Signed-off-by: Chunhe Lan > --- > arch/powerpc/configs/85xx/p1023rds_defconfig |6 ++ > 1 files changed, 6 insertions(+), 0 deletions(-) applied to next - k ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH v2 2/2] powerpc/mpic: add global timer support
On Aug 10, 2012, at 2:40 PM, Scott Wood wrote:
> On 08/10/2012 12:54 AM, dongsheng.w...@freescale.com wrote:
>> +static const struct of_device_id mpic_timer_ids[] = {
>> +{ .compatible = "open-pic,global-timer", },
>> +{ .compatible = "fsl,global-timer", },
>> +{},
>> +};
>> +
>> +static int __init mpic_timer_init(void)
>> +{
>> +struct device_node *np = NULL;
>> +
>> +for_each_node_by_type(np, "open-pic")
>> +if (of_match_node(mpic_timer_ids, np))
>> +group_init(np);
>> +
>> +if (list_empty(&group_list))
>> +return -ENODEV;
>> +
>> +return 0;
>> +}
>> +arch_initcall(mpic_timer_init);
>>
>
> Where do you distinguish an FSL timer from an openpic timer? I thought
> openpic timers didn't support cascading.
in group_init()
+ if (of_device_is_compatible(np, "fsl,global-timer"))
+ priv->flags |= FSL_GLOBAL_TIMER;
+
- k
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Re: [PATCH v2 1/2] powerpc/mpic: Add Open-PIC global timer document
On Aug 10, 2012, at 12:53 AM,
wrote:
> From: Wang Dongsheng
>
> Add a description of the OPEN-PIC global timer in the OPEN-PIC document.
>
> Moidfy mpic-timer document. 1.Add a TFRR register region. This register
> is written by software to report the clocking frequency of the PIC timers.
> 2.Add a device_type. The global timer in line with the OPEN-PIC specification.
>
> Signed-off-by: Wang Dongsheng
> Signed-off-by: Li Yang
> ---
> Documentation/devicetree/bindings/open-pic.txt | 46
Let's separate out the open-pic.txt timer binding change into its own patch
from the FSL timer binding & dtsi updates.
> .../devicetree/bindings/powerpc/fsl/mpic-timer.txt | 21 +
> arch/powerpc/boot/dts/fsl/pq3-mpic-timer-B.dtsi|7 ++-
> arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi|7 ++-
> 4 files changed, 66 insertions(+), 15 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/open-pic.txt
> b/Documentation/devicetree/bindings/open-pic.txt
> index 909a902..045c2e9 100644
> --- a/Documentation/devicetree/bindings/open-pic.txt
> +++ b/Documentation/devicetree/bindings/open-pic.txt
> @@ -92,6 +92,52 @@ Example 2:
>
> * References
>
> +* Open PIC global timers
> +
> +Required properties:
> +- compatible: "open-pic,global-timer"
> +
> +- reg : Contains two regions. The first is the timer frequency reporting
> + register for the group. The second is the main timer register bank
> + (GTCCR, GTBCR, GTVPR, GTDR).
> +
> +- available-ranges: use style section to define which
> + timer interrupts can be used. This property is optional; without this,
> + all timers within the group can be used.
> +
> +- interrupts: one interrupt per timer in the group, in order, starting
> + with timer zero. If available-ranges is present, only the interrupts
> + that correspond to available timers shall be present.
> +
If we are going to require device_type property it should be in the binding.
Based on the comments in ePAPR, I recommend dropping device_type from the timer
binding.
> +* Examples
> +
> +Example 1:
> +
> + /* Note that this requires #interrupt-cells to be 4 */
> + timer: timer@010f0 {
> + compatible = "open-pic,global-timer";
> + device_type = "open-pic";
> + reg = <0x010f0 4 0x01100 0x100>;
> +
> + /* Another AMP partition is using timer */
> + available-ranges = <2 2>;
> +
> + interrupts = <2 0 3 0
> + 3 0 3 0>;
> + };
> +
> +Example 2:
> +
> + timer: timer@010f0 {
> + compatible = "open-pic,global-timer";
> + device_type = "open-pic";
> + reg = <0x010f0 4 0x01100 0x100>;
> + interrupts = <0 0 3 0
> + 1 0 3 0
> + 2 0 3 0
> + 3 0 3 0>;
> + };
> +
> [1] Power.org (TM) Standard for Embedded Power Architecture (TM) Platform
> Requirements (ePAPR), Version 1.0, July 2008.
> (http://www.power.org/resources/downloads/Power_ePAPR_APPROVED_v1.0.pdf)
> diff --git a/Documentation/devicetree/bindings/powerpc/fsl/mpic-timer.txt
> b/Documentation/devicetree/bindings/powerpc/fsl/mpic-timer.txt
> index df41958..5aafca0 100644
> --- a/Documentation/devicetree/bindings/powerpc/fsl/mpic-timer.txt
> +++ b/Documentation/devicetree/bindings/powerpc/fsl/mpic-timer.txt
> @@ -1,13 +1,14 @@
> * Freescale MPIC timers
>
> Required properties:
> -- compatible: "fsl,mpic-global-timer"
> +- compatible: "fsl,global-timer"
Why are renaming?.. also use of fsl,global-timer is to generic of a name for
the this.
>
> -- reg : Contains two regions. The first is the main timer register bank
> - (GTCCRxx, GTBCRxx, GTVPRxx, GTDRxx). The second is the timer control
> +- reg : Contains three regions. The first is the timer frequency reporting
> + register (TFRRx) for the group. The second is the main timer register
> + bank (GTCCRxx, GTBCRxx, GTVPRxx, GTDRxx). The third is the timer control
> register (TCRx) for the group.
>
> -- fsl,available-ranges: use style section to define which
> +- available-ranges: use style section to define which
> timer interrupts can be used. This property is optional; without this,
> all timers within the group can be used.
>
> @@ -18,19 +19,21 @@ Required properties:
> Example:
> /* Note that this requires #interrupt-cells to be 4 */
> timer0: timer@41100 {
> - compatible = "fsl,mpic-global-timer";
> - reg = <0x41100 0x100 0x41300 4>;
> + compatible = "fsl,global-timer";
> + device_type = "open-pic";
> + reg = <0x410f0 4 0x41100 0x100 0x41300 4>;
>
> /* Another AMP partition is using timers 0 and 1 */
> - fsl,available-ranges = <2 2>;
> + available-ranges = <2 2>;
>
> interrupts = <2 0 3 0
> 3 0 3 0>;
> };
>
> time
Re: [PATCH V5 3/3] powerpc/fsl-pci: Unify pci/pcie initialization code
>>> As I explained before, this has to be done globally, not from the >>> probe function, so we can assign a default primary bus if there >>> isn't any ISA. >>> There are bugs in the Linux PPC PCI code relating to not having >>> any primary bus. >>> >>> -Scott >> >> In my way of searching ISA you can also assign a default primary bus >> in board specific files. > > That was meant for when the board file had an alternate way of > searching for the primary bus (e.g. look for i8259), not as a > replacement for the mechanism that guarantees there's a primary bus. > > You are causing a regression in the qemu_e500.c platform. Can we fix the qemu device tree to address the problem if we do make it a rule to use the ISA node to indicate the primary bus? >>> >>> No. There is no ISA, and we're not going to lie and say there is. >> >> But we can assign a default primary for qemu. > > Not in the device tree. What other mechanism do you propose? And why > do you want to fix it only for QEMU and not other boards, where things > happen to work but not as designed? > > Kumar, can you speak up here as maintainer so we can stop going back and > forth endlessly? I'd rather we stick with the code that works for this purpose at this point. That would be Scott's current upstream code. Lets get the other aspects of this patchset closed (SWIOTLB, conversion to platform driver, PM, etc.). The primary bus code Scott wrote does NOT need to change at this point. - k ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Upstream patch status?? (v3.6-rc1 out)
Guys, As v3.6-rc1 is now out we really need to get some of these simpler patches upstream and accepted NOW. Please provide status updates if the patch is upstream already let me know. [P1025RDB] (some major differences between upstream and internal P1025RDB support) powerpc/85xx: Add Quicc Engine support for p1025rdb P1025RDB Zhicheng Fan powerpc/dts: Add ucc uart support for p1025rdb P1025RDB Zhicheng Fan powerpc/dts: Add dts for p1025rdb board P1025RDBZhicheng Fan [P1022DS] (this is trivial, please take 10m and get this updated and submitted) powerpc/mpc85xx: p1022ds support the MTD for NOR and NAND flash P1022DS Jerry Huang [DTS] (Stuart, can you help and close) powerpc/e5500: Add power isa properties to comply with ePAPR 1.1EPAPR Liu Yu powerpc/e500mc: Add power isa properties to comply with ePAPR 1.1 EPAPR Liu Yu powerpc/e500v2: Add power isa properties to comply with ePAPR 1.1 EPAPR Liu Yu [MSI] (I think upstream, Timur please verify) powerpc/fsl: add MSI support for the Freescale hypervisor KVM/HV Timur Tabi [CORE] powerpc/booke: Re-organize debug code COREKumar Gala [USB] (Again, this is trivial and spend 10m and send upstream) usb/fsl: fixed USB wakeup USB Zhao Chenhui [LBC] mtd: elbc nand: use drvdata to only remove the relevant chipLBC Scott Wood [SATA] libata-pmp: add schedule timeout to support some PMP cards SATA Jerry Huang fsl-sata: workaround to fix the exception of link layer SATAQiang Liu - k ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] [v2] powerpc/85xx: clean up FPGA device tree nodes for Freecsale QorIQ boards
I pulling the p3060qds bit out so drop that change from next patch. - k On Sep 15, 2011, at 11:31 AM, "Tabi Timur-B04825" wrote: > Kumar Gala wrote: >> What happened to looking at pixis vs ngpixis ? > > Doh, I knew I was forgetting something. > > -- > Timur Tabi > Linux kernel developer at Freescale ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
