Hi,

I am new to this mail list and this is my first post, I apologize if I break 
some rules.

Description of the problem:
We incorporated Freescale MPC8548E CPU, PLX PEX8648 PCIe switch and Altera FPGA 
into our solution.
FPGA has one prefetchable 64-bit BAR 0 and 32-bit non-prefetchable Bar2.It was 
recognized successfully,as well as the PCIe switch.
But there are resources collisions on the upstream bridge and the downstream 
bridge connected to FPGA.
the startup log, as well the device tree, is shown below.

My question is: 
am I missing something in the device tree that standa for the PCIe switch?
Do I need to code in the Linux kernel to fix this problem?

================================ startup log 
=======================================================
pci 0000:01:00.0: device not available because of BAR 0 [0xb0000000-0xb001ffff] 
collisions
pci 0000:01:00.0: device not available because of BAR 8 [0xb0000000-0xb00fffff] 
collisions
pci 0000:01:00.0: device not available because of BAR 9 [0xa0000000-0xa0ffffff] 
collisions
pci 0000:02:08.0: device not available because of BAR 8 [0xb0000000-0xb00fffff] 
collisions
pci 0000:02:08.0: device not available because of BAR 9 [0xa0000000-0xa0ffffff] 
collisions 

================================ device tree regarding PCIe 
========================================
        pci2: p...@e000a000 {
                cell-index = <2>;
                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                interrupt-map = <

                        /* IDSEL 0x0 (PEX) */
                        00000 0x0 0x0 0x1 &mpic 0x0 0x1
                        00000 0x0 0x0 0x2 &mpic 0x1 0x1
                        00000 0x0 0x0 0x3 &mpic 0x2 0x1
                        00000 0x0 0x0 0x4 &mpic 0x3 0x1>;

                interrupt-parent = <&mpic>;
                interrupts = <26 2>;
                bus-range = <0 255>;
                ranges = <0x2000000 0x0 0x10000000 0xb0000000 0x0 0x10000000
                        0x43000000 0x0 0x0 0xa0000000 0x0 0x10000000
                          0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>;

              //ranges = empty;
                clock-frequency = <33333333>;
                #interrupt-cells = <1>;
                #size-cells = <2>;
                #address-cells = <3>;
                reg = <0xe000a000 0x1000>;
                compatible = "fsl,mpc8548-pcie";
                device_type = "pci";
                p...@0 {
                        reg = <0x0 0x0 0x0 0x0 0x0>;
                        #size-cells = <2>;
                        #address-cells = <3>;
                        device_type = "pci";
                        //ranges = empty;
                        ranges = <0x2000000 0x0 0x10000000
                                  0x20000000 0x0 0x0
                                  0x0 0x10000000

                            0x43000000 0x0 0xa0000000
                                  0x43000000 0x0 0xa0000000
                                  0x0 0x10000000

                                  0x1000000 0x0 0x0
                                  0x1000000 0x0 0x0
                                  0x0 0x100000>;
                                  
                };
        };
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