RE: [PATCHv5] clk: ppc-corenet: rename to qoriq and add CLK_OF_DECLARE support

2014-10-14 Thread Jingchang Lu 
Hi, Scott and Mike,
  
  Could you please help review this patch. Thanks.

Best Regards,
Jingchang

-Original Message-
From: Jingchang Lu [mailto:jingchang...@freescale.com]
Sent: Friday, October 10, 2014 5:15 PM
To: mturque...@linaro.org
Cc: Wood Scott-B07421; linuxppc-dev@lists.ozlabs.org; linux-
ker...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; Lu
Jingchang-B35083
Subject: [PATCHv5] clk: ppc-corenet: rename to qoriq and add
CLK_OF_DECLARE support

The IP is shared by PPC and ARM, this renames it to qoriq for better
represention, and this also adds the CLK_OF_DECLARE support for being
initialized by of_clk_init() on ARM.

Signed-off-by: Jingchang Lu jingchang...@freescale.com
---
changes in v5:
 update drivers/cpufreq/Kconfig.powerpc to slect the renamed config option.

changes in v4:
 remove corenet literals omitted in v3 remove.

changes in v3:
 generate the patch with -M -C option

changes in v2:
 rename the driver name to ppc-qoriq.c for shared on PPC and ARM.

 drivers/clk/Kconfig| 10 -
 drivers/clk/Makefile   |  2 +-
 drivers/clk/{clk-ppc-corenet.c = clk-qoriq.c} | 29 +++--
-
 drivers/cpufreq/Kconfig.powerpc|  2 +-
 4 files changed, 24 insertions(+), 19 deletions(-)  rename
drivers/clk/{clk-ppc-corenet.c = clk-qoriq.c} (89%)

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index
455fd17..4706a9f 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -101,12 +101,12 @@ config COMMON_CLK_AXI_CLKGEN
 Support for the Analog Devices axi-clkgen pcore clock generator
for Xilinx
 FPGAs. It is commonly used in Analog Devices' reference designs.

-config CLK_PPC_CORENET
-  bool Clock driver for PowerPC corenet platforms
-  depends on PPC_E500MC  OF
+config CLK_QORIQ
+  bool Clock driver for Freescale QorIQ platforms
+  depends on (PPC_E500MC || ARM)  OF
   ---help---
-This adds the clock driver support for Freescale PowerPC corenet
-platforms using common clock framework.
+This adds the clock driver support for Freescale QorIQ platforms
+using common clock framework.

 config COMMON_CLK_XGENE
   bool Clock driver for APM XGene SoC
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index
d5fba5b..4ff94cd 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -30,7 +30,7 @@ obj-$(CONFIG_ARCH_MOXART)+= clk-moxart.o
 obj-$(CONFIG_ARCH_NOMADIK)+= clk-nomadik.o
 obj-$(CONFIG_ARCH_NSPIRE) += clk-nspire.o
 obj-$(CONFIG_COMMON_CLK_PALMAS)   += clk-palmas.o
-obj-$(CONFIG_CLK_PPC_CORENET) += clk-ppc-corenet.o
+obj-$(CONFIG_CLK_QORIQ)   += clk-qoriq.o
 obj-$(CONFIG_COMMON_CLK_RK808)+= clk-rk808.o
 obj-$(CONFIG_COMMON_CLK_S2MPS11)  += clk-s2mps11.o
 obj-$(CONFIG_COMMON_CLK_SI5351)   += clk-si5351.o
diff --git a/drivers/clk/clk-ppc-corenet.c b/drivers/clk/clk-qoriq.c
similarity index 89% rename from drivers/clk/clk-ppc-corenet.c rename to
drivers/clk/clk-qoriq.c index 8e58edf..48cb923 100644
--- a/drivers/clk/clk-ppc-corenet.c
+++ b/drivers/clk/clk-qoriq.c
@@ -5,7 +5,7 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  *
- * clock driver for Freescale PowerPC corenet SoCs.
+ * clock driver for Freescale QorIQ SoCs.
  */
 #include linux/clk-provider.h
 #include linux/io.h
@@ -155,7 +155,7 @@ static void __init core_pll_init(struct device_node
*np)

   base = of_iomap(np, 0);
   if (!base) {
-  pr_err(clk-ppc: iomap error\n);
+  pr_err(clk-qoriq: iomap error\n);
   return;
   }

@@ -252,7 +252,7 @@ static void __init sysclk_init(struct device_node
*node)
   u32 rate;

   if (!np) {
-  pr_err(ppc-clk: could not get parent node\n);
+  pr_err(qoriq-clk: could not get parent node\n);
   return;
   }

@@ -278,30 +278,35 @@ static const struct of_device_id clk_match[]
__initconst = {
   {}
 };

-static int __init ppc_corenet_clk_probe(struct platform_device *pdev)
+static int __init qoriq_clk_probe(struct platform_device *pdev)
 {
   of_clk_init(clk_match);

   return 0;
 }

-static const struct of_device_id ppc_clk_ids[] __initconst = {
+static const struct of_device_id qoriq_clk_ids[] __initconst = {
   { .compatible = fsl,qoriq-clockgen-1.0, },
   { .compatible = fsl,qoriq-clockgen-2.0, },
   {}
 };

-static struct platform_driver ppc_corenet_clk_driver __initdata = {
+static struct platform_driver qoriq_clk_driver __initdata = {
   .driver = {
-  .name = ppc_corenet_clock,
+  .name = qoriq_clock,
   .owner = THIS_MODULE,
-  .of_match_table = ppc_clk_ids,
+  .of_match_table = qoriq_clk_ids,
   },
-  .probe = ppc_corenet_clk_probe,
+  .probe

[PATCHv5] clk: ppc-corenet: rename to qoriq and add CLK_OF_DECLARE support

2014-10-10 Thread Jingchang Lu 
The IP is shared by PPC and ARM, this renames it to qoriq for better
represention, and this also adds the CLK_OF_DECLARE support for being
initialized by of_clk_init() on ARM.

Signed-off-by: Jingchang Lu jingchang...@freescale.com
---
changes in v5:
 update drivers/cpufreq/Kconfig.powerpc to slect the renamed config option.

changes in v4:
 remove corenet literals omitted in v3 remove.

changes in v3:
 generate the patch with -M -C option

changes in v2:
 rename the driver name to ppc-qoriq.c for shared on PPC and ARM.

 drivers/clk/Kconfig| 10 -
 drivers/clk/Makefile   |  2 +-
 drivers/clk/{clk-ppc-corenet.c = clk-qoriq.c} | 29 +++---
 drivers/cpufreq/Kconfig.powerpc|  2 +-
 4 files changed, 24 insertions(+), 19 deletions(-)
 rename drivers/clk/{clk-ppc-corenet.c = clk-qoriq.c} (89%)

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 455fd17..4706a9f 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -101,12 +101,12 @@ config COMMON_CLK_AXI_CLKGEN
  Support for the Analog Devices axi-clkgen pcore clock generator for 
Xilinx
  FPGAs. It is commonly used in Analog Devices' reference designs.
 
-config CLK_PPC_CORENET
-   bool Clock driver for PowerPC corenet platforms
-   depends on PPC_E500MC  OF
+config CLK_QORIQ
+   bool Clock driver for Freescale QorIQ platforms
+   depends on (PPC_E500MC || ARM)  OF
---help---
- This adds the clock driver support for Freescale PowerPC corenet
- platforms using common clock framework.
+ This adds the clock driver support for Freescale QorIQ platforms
+ using common clock framework.
 
 config COMMON_CLK_XGENE
bool Clock driver for APM XGene SoC
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index d5fba5b..4ff94cd 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -30,7 +30,7 @@ obj-$(CONFIG_ARCH_MOXART) += clk-moxart.o
 obj-$(CONFIG_ARCH_NOMADIK) += clk-nomadik.o
 obj-$(CONFIG_ARCH_NSPIRE)  += clk-nspire.o
 obj-$(CONFIG_COMMON_CLK_PALMAS)+= clk-palmas.o
-obj-$(CONFIG_CLK_PPC_CORENET)  += clk-ppc-corenet.o
+obj-$(CONFIG_CLK_QORIQ)+= clk-qoriq.o
 obj-$(CONFIG_COMMON_CLK_RK808) += clk-rk808.o
 obj-$(CONFIG_COMMON_CLK_S2MPS11)   += clk-s2mps11.o
 obj-$(CONFIG_COMMON_CLK_SI5351)+= clk-si5351.o
diff --git a/drivers/clk/clk-ppc-corenet.c b/drivers/clk/clk-qoriq.c
similarity index 89%
rename from drivers/clk/clk-ppc-corenet.c
rename to drivers/clk/clk-qoriq.c
index 8e58edf..48cb923 100644
--- a/drivers/clk/clk-ppc-corenet.c
+++ b/drivers/clk/clk-qoriq.c
@@ -5,7 +5,7 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  *
- * clock driver for Freescale PowerPC corenet SoCs.
+ * clock driver for Freescale QorIQ SoCs.
  */
 #include linux/clk-provider.h
 #include linux/io.h
@@ -155,7 +155,7 @@ static void __init core_pll_init(struct device_node *np)
 
base = of_iomap(np, 0);
if (!base) {
-   pr_err(clk-ppc: iomap error\n);
+   pr_err(clk-qoriq: iomap error\n);
return;
}
 
@@ -252,7 +252,7 @@ static void __init sysclk_init(struct device_node *node)
u32 rate;
 
if (!np) {
-   pr_err(ppc-clk: could not get parent node\n);
+   pr_err(qoriq-clk: could not get parent node\n);
return;
}
 
@@ -278,30 +278,35 @@ static const struct of_device_id clk_match[] __initconst 
= {
{}
 };
 
-static int __init ppc_corenet_clk_probe(struct platform_device *pdev)
+static int __init qoriq_clk_probe(struct platform_device *pdev)
 {
of_clk_init(clk_match);
 
return 0;
 }
 
-static const struct of_device_id ppc_clk_ids[] __initconst = {
+static const struct of_device_id qoriq_clk_ids[] __initconst = {
{ .compatible = fsl,qoriq-clockgen-1.0, },
{ .compatible = fsl,qoriq-clockgen-2.0, },
{}
 };
 
-static struct platform_driver ppc_corenet_clk_driver __initdata = {
+static struct platform_driver qoriq_clk_driver __initdata = {
.driver = {
-   .name = ppc_corenet_clock,
+   .name = qoriq_clock,
.owner = THIS_MODULE,
-   .of_match_table = ppc_clk_ids,
+   .of_match_table = qoriq_clk_ids,
},
-   .probe = ppc_corenet_clk_probe,
+   .probe = qoriq_clk_probe,
 };
 
-static int __init ppc_corenet_clk_init(void)
+static int __init qoriq_clk_init(void)
 {
-   return platform_driver_register(ppc_corenet_clk_driver);
+   return platform_driver_register(qoriq_clk_driver);
 }
-subsys_initcall(ppc_corenet_clk_init);
+subsys_initcall(qoriq_clk_init);
+
+CLK_OF_DECLARE(qoriq_core_pll_v1, fsl,qoriq-core-pll-1.0, core_pll_init);
+CLK_OF_DECLARE(qoriq_core_pll_v2

RE: [PATCHv4] clk: ppc-corenet: rename to ppc-qoriq and add CLK_OF_DECLARE support

2014-09-28 Thread Jingchang Lu 
-Original Message-
From: Tudor Laurentiu-B10716
Sent: Thursday, September 25, 2014 8:56 PM
To: Lu Jingchang-B35083; mturque...@linaro.org
Cc: Wood Scott-B07421; linuxppc-dev@lists.ozlabs.org; linux-
ker...@vger.kernel.org; linux-arm-ker...@lists.infradead.org
Subject: Re: [PATCHv4] clk: ppc-corenet: rename to ppc-qoriq and add
CLK_OF_DECLARE support

Hi Jingchang,

On 09/23/2014 09:46 AM, Jingchang Lu wrote:
 The IP is shared by PPC and ARM, this renames it to qoriq for better
 represention, and this also adds the CLK_OF_DECLARE support for being
 initialized by of_clk_init() on ARM.


I think you need to also update drivers/cpufreq/Kconfig.powerpc to use the
renamed config option.


Thanks, I will update that selected config option of CLK_PPC_CORENET.

Best Regards,
Jingchang
---
Best Regards, Laurentiu


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RE: [PATCHv4] clk: ppc-corenet: rename to ppc-qoriq and add CLK_OF_DECLARE support

2014-09-25 Thread Jingchang Lu 
Hi, Scott and Mike,
  
  Could you please help review this patch and give an ACK if ok. Thanks.

Best Regards,
Jingchang

-Original Message-
From: Jingchang Lu [mailto:jingchang...@freescale.com]
Sent: Tuesday, September 23, 2014 2:47 PM
To: mturque...@linaro.org
Cc: Wood Scott-B07421; linuxppc-dev@lists.ozlabs.org; linux-
ker...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; Lu
Jingchang-B35083
Subject: [PATCHv4] clk: ppc-corenet: rename to ppc-qoriq and add
CLK_OF_DECLARE support

The IP is shared by PPC and ARM, this renames it to qoriq for better
represention, and this also adds the CLK_OF_DECLARE support for being
initialized by of_clk_init() on ARM.

Signed-off-by: Jingchang Lu jingchang...@freescale.com
---
changes in v4:
 remove corenet literals omitted in v3 remove.

changes in v3:
 generate the patch with -M -C option

changes in v2:
 rename the driver name to ppc-qoriq.c for shared on PPC and ARM.

 drivers/clk/Kconfig|  9 +
 drivers/clk/Makefile   |  2 +-
 drivers/clk/{clk-ppc-corenet.c = clk-qoriq.c} | 27 +++--
-
 3 files changed, 22 insertions(+), 16 deletions(-)  rename
drivers/clk/{clk-ppc-corenet.c = clk-qoriq.c} (89%)

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index
85131ae..f5f76cb 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -92,12 +92,13 @@ config COMMON_CLK_AXI_CLKGEN
 Support for the Analog Devices axi-clkgen pcore clock generator
for Xilinx
 FPGAs. It is commonly used in Analog Devices' reference designs.

-config CLK_PPC_CORENET
-  bool Clock driver for PowerPC corenet platforms
-  depends on PPC_E500MC  OF
+config CLK_QORIQ
+  bool Clock driver for PowerPC corenet and compatible ARM-based
platforms
+  depends on (PPC_E500MC || ARM)  OF
   ---help---
 This adds the clock driver support for Freescale PowerPC corenet
-platforms using common clock framework.
+platforms and compatible Freescale ARM based platforms using
common
+clock framework.

 config COMMON_CLK_XGENE
   bool Clock driver for APM XGene SoC
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index
27c542b..20f42e9 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -29,7 +29,7 @@ obj-$(CONFIG_ARCH_MOXART)+= clk-moxart.o
 obj-$(CONFIG_ARCH_NOMADIK)+= clk-nomadik.o
 obj-$(CONFIG_ARCH_NSPIRE) += clk-nspire.o
 obj-$(CONFIG_COMMON_CLK_PALMAS)   += clk-palmas.o
-obj-$(CONFIG_CLK_PPC_CORENET) += clk-ppc-corenet.o
+obj-$(CONFIG_CLK_QORIQ)   += clk-qoriq.o
 obj-$(CONFIG_COMMON_CLK_S2MPS11)  += clk-s2mps11.o
 obj-$(CONFIG_COMMON_CLK_SI5351)   += clk-si5351.o
 obj-$(CONFIG_COMMON_CLK_SI570)+= clk-si570.o
diff --git a/drivers/clk/clk-ppc-corenet.c b/drivers/clk/clk-qoriq.c
similarity index 89% rename from drivers/clk/clk-ppc-corenet.c rename to
drivers/clk/clk-qoriq.c index 8e58edf..cba8abe 100644
--- a/drivers/clk/clk-ppc-corenet.c
+++ b/drivers/clk/clk-qoriq.c
@@ -155,7 +155,7 @@ static void __init core_pll_init(struct device_node
*np)

   base = of_iomap(np, 0);
   if (!base) {
-  pr_err(clk-ppc: iomap error\n);
+  pr_err(clk-qoriq: iomap error\n);
   return;
   }

@@ -252,7 +252,7 @@ static void __init sysclk_init(struct device_node
*node)
   u32 rate;

   if (!np) {
-  pr_err(ppc-clk: could not get parent node\n);
+  pr_err(qoriq-clk: could not get parent node\n);
   return;
   }

@@ -278,30 +278,35 @@ static const struct of_device_id clk_match[]
__initconst = {
   {}
 };

-static int __init ppc_corenet_clk_probe(struct platform_device *pdev)
+static int __init qoriq_clk_probe(struct platform_device *pdev)
 {
   of_clk_init(clk_match);

   return 0;
 }

-static const struct of_device_id ppc_clk_ids[] __initconst = {
+static const struct of_device_id qoriq_clk_ids[] __initconst = {
   { .compatible = fsl,qoriq-clockgen-1.0, },
   { .compatible = fsl,qoriq-clockgen-2.0, },
   {}
 };

-static struct platform_driver ppc_corenet_clk_driver __initdata = {
+static struct platform_driver qoriq_clk_driver __initdata = {
   .driver = {
-  .name = ppc_corenet_clock,
+  .name = qoriq_clock,
   .owner = THIS_MODULE,
-  .of_match_table = ppc_clk_ids,
+  .of_match_table = qoriq_clk_ids,
   },
-  .probe = ppc_corenet_clk_probe,
+  .probe = qoriq_clk_probe,
 };

-static int __init ppc_corenet_clk_init(void)
+static int __init qoriq_clk_init(void)
 {
-  return platform_driver_register(ppc_corenet_clk_driver);
+  return platform_driver_register(qoriq_clk_driver);
 }
-subsys_initcall(ppc_corenet_clk_init);
+subsys_initcall(qoriq_clk_init);
+
+CLK_OF_DECLARE(qoriq_core_pll_v1, fsl,qoriq-core-pll-1.0,
+core_pll_init

[PATCHv4] clk: ppc-corenet: rename to ppc-qoriq and add CLK_OF_DECLARE support

2014-09-23 Thread Jingchang Lu 
The IP is shared by PPC and ARM, this renames it to qoriq for better
represention, and this also adds the CLK_OF_DECLARE support for being
initialized by of_clk_init() on ARM.

Signed-off-by: Jingchang Lu jingchang...@freescale.com
---
changes in v4:
 remove corenet literals omitted in v3 remove.

changes in v3:
 generate the patch with -M -C option

changes in v2:
 rename the driver name to ppc-qoriq.c for shared on PPC and ARM.

 drivers/clk/Kconfig|  9 +
 drivers/clk/Makefile   |  2 +-
 drivers/clk/{clk-ppc-corenet.c = clk-qoriq.c} | 27 +++---
 3 files changed, 22 insertions(+), 16 deletions(-)
 rename drivers/clk/{clk-ppc-corenet.c = clk-qoriq.c} (89%)

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 85131ae..f5f76cb 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -92,12 +92,13 @@ config COMMON_CLK_AXI_CLKGEN
  Support for the Analog Devices axi-clkgen pcore clock generator for 
Xilinx
  FPGAs. It is commonly used in Analog Devices' reference designs.
 
-config CLK_PPC_CORENET
-   bool Clock driver for PowerPC corenet platforms
-   depends on PPC_E500MC  OF
+config CLK_QORIQ
+   bool Clock driver for PowerPC corenet and compatible ARM-based 
platforms
+   depends on (PPC_E500MC || ARM)  OF
---help---
  This adds the clock driver support for Freescale PowerPC corenet
- platforms using common clock framework.
+ platforms and compatible Freescale ARM based platforms using common
+ clock framework.
 
 config COMMON_CLK_XGENE
bool Clock driver for APM XGene SoC
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 27c542b..20f42e9 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -29,7 +29,7 @@ obj-$(CONFIG_ARCH_MOXART) += clk-moxart.o
 obj-$(CONFIG_ARCH_NOMADIK) += clk-nomadik.o
 obj-$(CONFIG_ARCH_NSPIRE)  += clk-nspire.o
 obj-$(CONFIG_COMMON_CLK_PALMAS)+= clk-palmas.o
-obj-$(CONFIG_CLK_PPC_CORENET)  += clk-ppc-corenet.o
+obj-$(CONFIG_CLK_QORIQ)+= clk-qoriq.o
 obj-$(CONFIG_COMMON_CLK_S2MPS11)   += clk-s2mps11.o
 obj-$(CONFIG_COMMON_CLK_SI5351)+= clk-si5351.o
 obj-$(CONFIG_COMMON_CLK_SI570) += clk-si570.o
diff --git a/drivers/clk/clk-ppc-corenet.c b/drivers/clk/clk-qoriq.c
similarity index 89%
rename from drivers/clk/clk-ppc-corenet.c
rename to drivers/clk/clk-qoriq.c
index 8e58edf..cba8abe 100644
--- a/drivers/clk/clk-ppc-corenet.c
+++ b/drivers/clk/clk-qoriq.c
@@ -155,7 +155,7 @@ static void __init core_pll_init(struct device_node *np)
 
base = of_iomap(np, 0);
if (!base) {
-   pr_err(clk-ppc: iomap error\n);
+   pr_err(clk-qoriq: iomap error\n);
return;
}
 
@@ -252,7 +252,7 @@ static void __init sysclk_init(struct device_node *node)
u32 rate;
 
if (!np) {
-   pr_err(ppc-clk: could not get parent node\n);
+   pr_err(qoriq-clk: could not get parent node\n);
return;
}
 
@@ -278,30 +278,35 @@ static const struct of_device_id clk_match[] __initconst 
= {
{}
 };
 
-static int __init ppc_corenet_clk_probe(struct platform_device *pdev)
+static int __init qoriq_clk_probe(struct platform_device *pdev)
 {
of_clk_init(clk_match);
 
return 0;
 }
 
-static const struct of_device_id ppc_clk_ids[] __initconst = {
+static const struct of_device_id qoriq_clk_ids[] __initconst = {
{ .compatible = fsl,qoriq-clockgen-1.0, },
{ .compatible = fsl,qoriq-clockgen-2.0, },
{}
 };
 
-static struct platform_driver ppc_corenet_clk_driver __initdata = {
+static struct platform_driver qoriq_clk_driver __initdata = {
.driver = {
-   .name = ppc_corenet_clock,
+   .name = qoriq_clock,
.owner = THIS_MODULE,
-   .of_match_table = ppc_clk_ids,
+   .of_match_table = qoriq_clk_ids,
},
-   .probe = ppc_corenet_clk_probe,
+   .probe = qoriq_clk_probe,
 };
 
-static int __init ppc_corenet_clk_init(void)
+static int __init qoriq_clk_init(void)
 {
-   return platform_driver_register(ppc_corenet_clk_driver);
+   return platform_driver_register(qoriq_clk_driver);
 }
-subsys_initcall(ppc_corenet_clk_init);
+subsys_initcall(qoriq_clk_init);
+
+CLK_OF_DECLARE(qoriq_core_pll_v1, fsl,qoriq-core-pll-1.0, core_pll_init);
+CLK_OF_DECLARE(qoriq_core_pll_v2, fsl,qoriq-core-pll-2.0, core_pll_init);
+CLK_OF_DECLARE(qoriq_core_mux_v1, fsl,qoriq-core-mux-1.0, core_mux_init);
+CLK_OF_DECLARE(qoriq_core_mux_v2, fsl,qoriq-core-mux-2.0, core_mux_init);
-- 
1.8.0

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[PATCHv3] clk: ppc-corenet: rename to ppc-qoriq and add CLK_OF_DECLARE support

2014-09-03 Thread Jingchang Lu 
The IP is shared on PPC and ARM, this rename it to qoriq for better
represention, and this also add the CLK_OF_DECLARE support for being
initialized by of_clk_init() on ARM.

Signed-off-by: Jingchang Lu jingchang...@freescale.com
---
changes in v3:
 generate the patch with -M -C option

changes in v2:
 rename the driver name to ppc-qoriq.c for shared on PPC and ARM.

 drivers/clk/Kconfig|  9 +
 drivers/clk/Makefile   |  2 +-
 drivers/clk/{clk-ppc-corenet.c = clk-qoriq.c} | 27 +++---
 3 files changed, 22 insertions(+), 16 deletions(-)
 rename drivers/clk/{clk-ppc-corenet.c = clk-qoriq.c} (88%)

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index cfd3af7..d7892b9 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -81,12 +81,13 @@ config COMMON_CLK_AXI_CLKGEN
  Support for the Analog Devices axi-clkgen pcore clock generator for 
Xilinx
  FPGAs. It is commonly used in Analog Devices' reference designs.
 
-config CLK_PPC_CORENET
-   bool Clock driver for PowerPC corenet platforms
-   depends on PPC_E500MC  OF
+config CLK_QORIQ
+   bool Clock driver for PowerPC corenet and compatible ARM-based 
platforms
+   depends on (PPC_E500MC || ARM)  OF
---help---
  This adds the clock driver support for Freescale PowerPC corenet
- platforms using common clock framework.
+ platforms and compatible Freescale ARM based platforms using common
+ clock framework.
 
 config COMMON_CLK_XGENE
bool Clock driver for APM XGene SoC
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index f537a0b..5ca4b72 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -27,7 +27,7 @@ obj-$(CONFIG_ARCH_MOXART) += clk-moxart.o
 obj-$(CONFIG_ARCH_NOMADIK) += clk-nomadik.o
 obj-$(CONFIG_ARCH_NSPIRE)  += clk-nspire.o
 obj-$(CONFIG_COMMON_CLK_PALMAS)+= clk-palmas.o
-obj-$(CONFIG_CLK_PPC_CORENET)  += clk-ppc-corenet.o
+obj-$(CONFIG_CLK_QORIQ)+= clk-qoriq.o
 obj-$(CONFIG_COMMON_CLK_S2MPS11)   += clk-s2mps11.o
 obj-$(CONFIG_COMMON_CLK_SI5351)+= clk-si5351.o
 obj-$(CONFIG_COMMON_CLK_SI570) += clk-si570.o
diff --git a/drivers/clk/clk-ppc-corenet.c b/drivers/clk/clk-qoriq.c
similarity index 88%
rename from drivers/clk/clk-ppc-corenet.c
rename to drivers/clk/clk-qoriq.c
index 8e58edf..5053f46 100644
--- a/drivers/clk/clk-ppc-corenet.c
+++ b/drivers/clk/clk-qoriq.c
@@ -155,7 +155,7 @@ static void __init core_pll_init(struct device_node *np)
 
base = of_iomap(np, 0);
if (!base) {
-   pr_err(clk-ppc: iomap error\n);
+   pr_err(clk-qoriq: iomap error\n);
return;
}
 
@@ -252,7 +252,7 @@ static void __init sysclk_init(struct device_node *node)
u32 rate;
 
if (!np) {
-   pr_err(ppc-clk: could not get parent node\n);
+   pr_err(qoriq-clk: could not get parent node\n);
return;
}
 
@@ -278,30 +278,35 @@ static const struct of_device_id clk_match[] __initconst 
= {
{}
 };
 
-static int __init ppc_corenet_clk_probe(struct platform_device *pdev)
+static int __init qoriq_corenet_clk_probe(struct platform_device *pdev)
 {
of_clk_init(clk_match);
 
return 0;
 }
 
-static const struct of_device_id ppc_clk_ids[] __initconst = {
+static const struct of_device_id qoriq_clk_ids[] __initconst = {
{ .compatible = fsl,qoriq-clockgen-1.0, },
{ .compatible = fsl,qoriq-clockgen-2.0, },
{}
 };
 
-static struct platform_driver ppc_corenet_clk_driver __initdata = {
+static struct platform_driver qoriq_corenet_clk_driver __initdata = {
.driver = {
-   .name = ppc_corenet_clock,
+   .name = qoriq_corenet_clock,
.owner = THIS_MODULE,
-   .of_match_table = ppc_clk_ids,
+   .of_match_table = qoriq_clk_ids,
},
-   .probe = ppc_corenet_clk_probe,
+   .probe = qoriq_corenet_clk_probe,
 };
 
-static int __init ppc_corenet_clk_init(void)
+static int __init qoriq_corenet_clk_init(void)
 {
-   return platform_driver_register(ppc_corenet_clk_driver);
+   return platform_driver_register(qoriq_corenet_clk_driver);
 }
-subsys_initcall(ppc_corenet_clk_init);
+subsys_initcall(qoriq_corenet_clk_init);
+
+CLK_OF_DECLARE(qoriq_core_pll_v1, fsl,qoriq-core-pll-1.0, core_pll_init);
+CLK_OF_DECLARE(qoriq_core_pll_v2, fsl,qoriq-core-pll-2.0, core_pll_init);
+CLK_OF_DECLARE(qoriq_core_mux_v1, fsl,qoriq-core-mux-1.0, core_mux_init);
+CLK_OF_DECLARE(qoriq_core_mux_v2, fsl,qoriq-core-mux-2.0, core_mux_init);
-- 
1.8.0

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RE: [RESEND] clk: ppc-corenet: Add Freescale ARM-based platforms CLK_OF_DECLARE support

2014-08-29 Thread Jingchang Lu 
-Original Message-
From: Wood Scott-B07421
Sent: Friday, August 29, 2014 12:26 AM
To: Lu Jingchang-B35083
Cc: mturque...@linaro.org; linuxppc-dev@lists.ozlabs.org; linux-
ker...@vger.kernel.org; linux-arm-ker...@lists.infradead.org
Subject: Re: [RESEND] clk: ppc-corenet: Add Freescale ARM-based platforms
CLK_OF_DECLARE support

On Thu, 2014-08-28 at 05:05 -0500, Lu Jingchang-B35083 wrote:
 -Original Message-
 From: Wood Scott-B07421
 Sent: Thursday, August 28, 2014 7:34 AM
 To: Lu Jingchang-B35083
 Cc: mturque...@linaro.org; linuxppc-dev@lists.ozlabs.org; linux-
 ker...@vger.kernel.org; linux-arm-ker...@lists.infradead.org
 Subject: Re: [RESEND] clk: ppc-corenet: Add Freescale ARM-based
 platforms CLK_OF_DECLARE support
 
 On Tue, 2014-08-26 at 21:19 -0500, Lu Jingchang-B35083 wrote:
  -Original Message-
  From: Wood Scott-B07421
  Sent: Wednesday, August 27, 2014 6:51 AM
  To: Lu Jingchang-B35083
  Cc: mturque...@linaro.org; linuxppc-dev@lists.ozlabs.org; linux-
  ker...@vger.kernel.org; linux-arm-ker...@lists.infradead.org
  Subject: Re: [RESEND] clk: ppc-corenet: Add Freescale ARM-based
  platforms CLK_OF_DECLARE support
  
  On Fri, 2014-08-22 at 17:34 +0800, Jingchang Lu wrote:
   +CLK_OF_DECLARE(ppc_core_pll_v1, fsl,qoriq-core-pll-1.0,
  core_pll_init);
   +CLK_OF_DECLARE(ppc_core_pll_v2, fsl,qoriq-core-pll-2.0,
  core_pll_init);
   +CLK_OF_DECLARE(ppc_core_mux_v1, fsl,qoriq-core-mux-1.0,
  core_mux_init);
   +CLK_OF_DECLARE(ppc_core_mux_v2, fsl,qoriq-core-mux-2.0,
  core_mux_init);
  
  What does this do that the existing platform driver and match
  table don't?  Why is it needed for ARM when PPC didn't need it?
  
  -Scott
  
  Common clk init on ARM platform is initialized earlier via
  of_clk_init() instead of driver probe method, the of_clk_init will
  walk a __clk_of_table to init each clk provider in the table, the
  CLK_OF_DECLARE() macro puts a supported clk in the __clk_of_table
  for it
 initializing on starup, and the clk system has added some common clk
 such as fixed-clk
  to this table already.
  So here I add our specific clk init declaration to consist this
  framework, and the driver probe function will not be needed on ARM.
 
 OK... Is there any reason why the new method won't work on PPC?
 
 PPC has little dependence on the clock tree but frequency, it will
 work well if adopted I think.

I'm just saying it seems redundant to have both.  Even on ARM, won't this
result in the clock getting registered twice (albeit with one of those
times being too late)?

Regardless of what dependence PPC has on the clock tree, what stops this
method of enumeration from working on PPC?  Is there anything required
other than inserting a call to of_clk_init(NULL) in the arch init code?

-Scott

The of_clk_init is an alternative way to the legacy driver. 
Latest ARM standard support a default call to of_clk_init(NULL) in its 
time_init().
So this is the general way for ARM-based platform.
The clk register layer can detect the twice registration of a same clk and
avoid the duplicate registration. The dtb should select the compatible for 
either,
but not both. On LS1021A the driver probe method will not be triggered.
And for support of of_clk_init on PPC, I think just add a call to it as ARM do
in time_init()[arch/arm/kernel/time.c] would be ok.



Best Regards,
Jingchang





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[PATCHv2] clk: ppc-corenet: rename to ppc-qoriq and add CLK_OF_DECLARE support

2014-08-29 Thread Jingchang Lu 
The IP is shared on PPC and ARM, this rename it to qoriq for better
represention, and this also add the CLK_OF_DECLARE support for being
initialized by of_clk_init() on ARM.

Signed-off-by: Jingchang Lu jingchang...@freescale.com
---
changes in v2:
 rename the driver name to ppc-qoriq.c for shared on PPC and ARM.

 drivers/clk/Kconfig   |   9 +-
 drivers/clk/Makefile  |   2 +-
 drivers/clk/clk-ppc-corenet.c | 307 -
 drivers/clk/clk-qoriq.c   | 312 ++
 4 files changed, 318 insertions(+), 312 deletions(-)
 delete mode 100644 drivers/clk/clk-ppc-corenet.c
 create mode 100644 drivers/clk/clk-qoriq.c

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index cfd3af7..d7892b9 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -81,12 +81,13 @@ config COMMON_CLK_AXI_CLKGEN
  Support for the Analog Devices axi-clkgen pcore clock generator for 
Xilinx
  FPGAs. It is commonly used in Analog Devices' reference designs.
 
-config CLK_PPC_CORENET
-   bool Clock driver for PowerPC corenet platforms
-   depends on PPC_E500MC  OF
+config CLK_QORIQ
+   bool Clock driver for PowerPC corenet and compatible ARM-based 
platforms
+   depends on (PPC_E500MC || ARM)  OF
---help---
  This adds the clock driver support for Freescale PowerPC corenet
- platforms using common clock framework.
+ platforms and compatible Freescale ARM based platforms using common
+ clock framework.
 
 config COMMON_CLK_XGENE
bool Clock driver for APM XGene SoC
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 312742c..c8f1f52 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -23,7 +23,7 @@ obj-$(CONFIG_ARCH_MOXART) += clk-moxart.o
 obj-$(CONFIG_ARCH_NOMADIK) += clk-nomadik.o
 obj-$(CONFIG_ARCH_NSPIRE)  += clk-nspire.o
 obj-$(CONFIG_COMMON_CLK_PALMAS)+= clk-palmas.o
-obj-$(CONFIG_CLK_PPC_CORENET)  += clk-ppc-corenet.o
+obj-$(CONFIG_CLK_QORIQ)+= clk-qoriq.o
 obj-$(CONFIG_COMMON_CLK_S2MPS11)   += clk-s2mps11.o
 obj-$(CONFIG_COMMON_CLK_SI5351)+= clk-si5351.o
 obj-$(CONFIG_COMMON_CLK_SI570) += clk-si570.o
diff --git a/drivers/clk/clk-ppc-corenet.c b/drivers/clk/clk-ppc-corenet.c
deleted file mode 100644
index 8e58edf..000
--- a/drivers/clk/clk-ppc-corenet.c
+++ /dev/null
@@ -1,307 +0,0 @@
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * clock driver for Freescale PowerPC corenet SoCs.
- */
-#include linux/clk-provider.h
-#include linux/io.h
-#include linux/kernel.h
-#include linux/module.h
-#include linux/of_address.h
-#include linux/of_platform.h
-#include linux/of.h
-#include linux/slab.h
-
-struct cmux_clk {
-   struct clk_hw hw;
-   void __iomem *reg;
-   u32 flags;
-};
-
-#define PLL_KILL   BIT(31)
-#defineCLKSEL_SHIFT27
-#define CLKSEL_ADJUST  BIT(0)
-#define to_cmux_clk(p) container_of(p, struct cmux_clk, hw)
-
-static unsigned int clocks_per_pll;
-
-static int cmux_set_parent(struct clk_hw *hw, u8 idx)
-{
-   struct cmux_clk *clk = to_cmux_clk(hw);
-   u32 clksel;
-
-   clksel = ((idx / clocks_per_pll)  2) + idx % clocks_per_pll;
-   if (clk-flags  CLKSEL_ADJUST)
-   clksel += 8;
-   clksel = (clksel  0xf)  CLKSEL_SHIFT;
-   iowrite32be(clksel, clk-reg);
-
-   return 0;
-}
-
-static u8 cmux_get_parent(struct clk_hw *hw)
-{
-   struct cmux_clk *clk = to_cmux_clk(hw);
-   u32 clksel;
-
-   clksel = ioread32be(clk-reg);
-   clksel = (clksel  CLKSEL_SHIFT)  0xf;
-   if (clk-flags  CLKSEL_ADJUST)
-   clksel -= 8;
-   clksel = (clksel  2) * clocks_per_pll + clksel % 4;
-
-   return clksel;
-}
-
-const struct clk_ops cmux_ops = {
-   .get_parent = cmux_get_parent,
-   .set_parent = cmux_set_parent,
-};
-
-static void __init core_mux_init(struct device_node *np)
-{
-   struct clk *clk;
-   struct clk_init_data init;
-   struct cmux_clk *cmux_clk;
-   struct device_node *node;
-   int rc, count, i;
-   u32 offset;
-   const char *clk_name;
-   const char **parent_names;
-
-   rc = of_property_read_u32(np, reg, offset);
-   if (rc) {
-   pr_err(%s: could not get reg property\n, np-name);
-   return;
-   }
-
-   /* get the input clock source count */
-   count = of_property_count_strings(np, clock-names);
-   if (count  0) {
-   pr_err(%s: get clock count error\n, np-name);
-   return;
-   }
-   parent_names = kzalloc((sizeof(char *) * count), GFP_KERNEL

RE: [RESEND] clk: ppc-corenet: Add Freescale ARM-based platforms CLK_OF_DECLARE support

2014-08-28 Thread Jingchang Lu 
-Original Message-
From: Wood Scott-B07421
Sent: Thursday, August 28, 2014 7:34 AM
To: Lu Jingchang-B35083
Cc: mturque...@linaro.org; linuxppc-dev@lists.ozlabs.org; linux-
ker...@vger.kernel.org; linux-arm-ker...@lists.infradead.org
Subject: Re: [RESEND] clk: ppc-corenet: Add Freescale ARM-based platforms
CLK_OF_DECLARE support

On Tue, 2014-08-26 at 21:19 -0500, Lu Jingchang-B35083 wrote:
 -Original Message-
 From: Wood Scott-B07421
 Sent: Wednesday, August 27, 2014 6:51 AM
 To: Lu Jingchang-B35083
 Cc: mturque...@linaro.org; linuxppc-dev@lists.ozlabs.org; linux-
 ker...@vger.kernel.org; linux-arm-ker...@lists.infradead.org
 Subject: Re: [RESEND] clk: ppc-corenet: Add Freescale ARM-based
 platforms CLK_OF_DECLARE support
 
 On Fri, 2014-08-22 at 17:34 +0800, Jingchang Lu wrote:
  +CLK_OF_DECLARE(ppc_core_pll_v1, fsl,qoriq-core-pll-1.0,
 core_pll_init);
  +CLK_OF_DECLARE(ppc_core_pll_v2, fsl,qoriq-core-pll-2.0,
 core_pll_init);
  +CLK_OF_DECLARE(ppc_core_mux_v1, fsl,qoriq-core-mux-1.0,
 core_mux_init);
  +CLK_OF_DECLARE(ppc_core_mux_v2, fsl,qoriq-core-mux-2.0,
 core_mux_init);
 
 What does this do that the existing platform driver and match table
 don't?  Why is it needed for ARM when PPC didn't need it?
 
 -Scott
 
 Common clk init on ARM platform is initialized earlier via
 of_clk_init() instead of driver probe method, the of_clk_init will
 walk a __clk_of_table to init each clk provider in the table, the
 CLK_OF_DECLARE() macro puts a supported clk in the __clk_of_table for it
initializing on starup, and the clk system has added some common clk such
as fixed-clk
 to this table already.
 So here I add our specific clk init declaration to consist this
 framework, and the driver probe function will not be needed on ARM.

OK... Is there any reason why the new method won't work on PPC?

PPC has little dependence on the clock tree but frequency, it will work well
if adopted I think.



Best Regards,
Jingchang



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RE: [RESEND] clk: ppc-corenet: Add Freescale ARM-based platforms CLK_OF_DECLARE support

2014-08-26 Thread Jingchang Lu 
-Original Message-
From: Wood Scott-B07421
Sent: Wednesday, August 27, 2014 6:51 AM
To: Lu Jingchang-B35083
Cc: mturque...@linaro.org; linuxppc-dev@lists.ozlabs.org; linux-
ker...@vger.kernel.org; linux-arm-ker...@lists.infradead.org
Subject: Re: [RESEND] clk: ppc-corenet: Add Freescale ARM-based platforms
CLK_OF_DECLARE support

On Fri, 2014-08-22 at 17:34 +0800, Jingchang Lu wrote:
 Signed-off-by: Jingchang Lu jingchang...@freescale.com
 ---
  drivers/clk/Kconfig   | 7 ---
  drivers/clk/clk-ppc-corenet.c | 5 +
  2 files changed, 9 insertions(+), 3 deletions(-)

 diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
 index cfd3af7..8784704 100644
 --- a/drivers/clk/Kconfig
 +++ b/drivers/clk/Kconfig
 @@ -82,11 +82,12 @@ config COMMON_CLK_AXI_CLKGEN
FPGAs. It is commonly used in Analog Devices' reference designs.

  config CLK_PPC_CORENET
 -bool Clock driver for PowerPC corenet platforms
 -depends on PPC_E500MC  OF
 +bool Clock driver for PowerPC corenet and compatible ARM-based
platforms
 +depends on (PPC_E500MC || ARM)  OF

Should the symbol and driver be renamed to something like CLK_FSL_QORIQ?

This name is better for sharing on ARM and PowerPC, I will rename them. Thanks.

 diff --git a/drivers/clk/clk-ppc-corenet.c b/drivers/clk/clk-ppc-
corenet.c
 index 8e58edf..7692cac 100644
 --- a/drivers/clk/clk-ppc-corenet.c
 +++ b/drivers/clk/clk-ppc-corenet.c
 @@ -305,3 +305,8 @@ static int __init ppc_corenet_clk_init(void)
  return platform_driver_register(ppc_corenet_clk_driver);
  }
  subsys_initcall(ppc_corenet_clk_init);
 +
 +CLK_OF_DECLARE(ppc_core_pll_v1, fsl,qoriq-core-pll-1.0,
core_pll_init);
 +CLK_OF_DECLARE(ppc_core_pll_v2, fsl,qoriq-core-pll-2.0,
core_pll_init);
 +CLK_OF_DECLARE(ppc_core_mux_v1, fsl,qoriq-core-mux-1.0,
core_mux_init);
 +CLK_OF_DECLARE(ppc_core_mux_v2, fsl,qoriq-core-mux-2.0,
core_mux_init);

What does this do that the existing platform driver and match table
don't?  Why is it needed for ARM when PPC didn't need it?

-Scott

Common clk init on ARM platform is initialized earlier via of_clk_init() 
instead of
driver probe method, the of_clk_init will walk a __clk_of_table to init each 
clk provider
in the table, the CLK_OF_DECLARE() macro puts a supported clk in the 
__clk_of_table for
it initializing on starup, and the clk system has added some common clk such as 
fixed-clk
to this table already.
So here I add our specific clk init declaration to consist this framework, and 
the driver
probe function will not be needed on ARM.



Best Regards,
Jingchang



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[RESEND] clk: ppc-corenet: Add Freescale ARM-based platforms CLK_OF_DECLARE support

2014-08-22 Thread Jingchang Lu 
Signed-off-by: Jingchang Lu jingchang...@freescale.com
---
 drivers/clk/Kconfig   | 7 ---
 drivers/clk/clk-ppc-corenet.c | 5 +
 2 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index cfd3af7..8784704 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -82,11 +82,12 @@ config COMMON_CLK_AXI_CLKGEN
  FPGAs. It is commonly used in Analog Devices' reference designs.
 
 config CLK_PPC_CORENET
-   bool Clock driver for PowerPC corenet platforms
-   depends on PPC_E500MC  OF
+   bool Clock driver for PowerPC corenet and compatible ARM-based 
platforms
+   depends on (PPC_E500MC || ARM)  OF
---help---
  This adds the clock driver support for Freescale PowerPC corenet
- platforms using common clock framework.
+ platforms and compatible Freescale ARM based platforms using common
+ clock framework.
 
 config COMMON_CLK_XGENE
bool Clock driver for APM XGene SoC
diff --git a/drivers/clk/clk-ppc-corenet.c b/drivers/clk/clk-ppc-corenet.c
index 8e58edf..7692cac 100644
--- a/drivers/clk/clk-ppc-corenet.c
+++ b/drivers/clk/clk-ppc-corenet.c
@@ -305,3 +305,8 @@ static int __init ppc_corenet_clk_init(void)
return platform_driver_register(ppc_corenet_clk_driver);
 }
 subsys_initcall(ppc_corenet_clk_init);
+
+CLK_OF_DECLARE(ppc_core_pll_v1, fsl,qoriq-core-pll-1.0, core_pll_init);
+CLK_OF_DECLARE(ppc_core_pll_v2, fsl,qoriq-core-pll-2.0, core_pll_init);
+CLK_OF_DECLARE(ppc_core_mux_v1, fsl,qoriq-core-mux-1.0, core_mux_init);
+CLK_OF_DECLARE(ppc_core_mux_v2, fsl,qoriq-core-mux-2.0, core_mux_init);
-- 
1.8.0

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