Re: [PATCH] powerpc: Add MPC837x PCIE controller RC mode support

2008-01-03 Thread Li Li 
On Thu, 2008-01-03 at 18:14 +0800, Arnd Bergmann wrote:

> After some more research, I noticed that the distinction between 
> primary and secondary host bridges will go away _anyway_, so 
> I guess we shouldn't worry about it too much.
> 
> On powerpc64, we already don't care, as the
> arch/powerpc/kernel/isa-bridge.c 
> code takes care of legacy I/O areas there, instead of the PCI code. 
> It's only needed on machines with legacy ISA devices (PC keyboard, 
> floppy, ...), and those can be converted to use the isa-bridge code 
> at some point.
> 

This is really a good new :)

- Tony

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Re: [PATCH] powerpc: Add MPC837x PCIE controller RC mode support

2008-01-03 Thread Li Li 
On Thu, 2008-01-03 at 16:14 +0800, Arnd Bergmann wrote:
> On Thursday 03 January 2008, Li Li wrote: 
> > > * The detection method for the primary bus is somewhat fragile, 
> > > because 
> > > we depend on the order of the nodes in the device tree, which is
> not 
> > > specified to have a meaning. /Maybe/ there could be a property in 
> > > (at most) one of the PCI host bridge nodes saying that this
> specific 
> > > bus 
> > > is the primary one. 
> > > 
> > 
> > Put this primary in code is more save than in dts. 
> > The dts lacks error checking function. If provide error dts such as
> two 
> > pci hosts both has primary property will occur chaos.
> 
> It's easy enough to just panic() if you find more than one primary
> bus, 
> since the information from the device tree is static enough that one 
> will know how to fix this after seeing the error.
> 

It is just a case. what about if do not find primary pci host.
The current code can prevent this potential error and make system
robust.

- Tony


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Re: [PATCH] powerpc: Add MPC837x PCIE controller RC mode support

2008-01-02 Thread Li Li 
On Wed, 2008-01-02 at 19:53 +0800, Arnd Bergmann wrote:
> On Wednesday 02 January 2008, Li Li wrote: 
> >  #ifdef CONFIG_PCI 
> > -   for_each_compatible_node(np, "pci", "fsl,mpc8349-pci") 
> > -   mpc83xx_add_bridge(np); 
> > +   for_each_compatible_node(np, "pci", "fsl,mpc8349-pci") { 
> > +   if (primary_pci_bus) { 
> > +   mpc83xx_add_bridge(np, PPC_83XX_PCI |
> PPC_83XX_PCI_PRIMARY); 
> > +   primary_pci_bus = 0; 
> > +   } else 
> > +   mpc83xx_add_bridge(np, PPC_83XX_PCI); 
> > +   } 
> > + 
> > +   for_each_compatible_node(np, "pci", "fsl,mpc8377-pcie") { 
> > +   if (primary_pci_bus) { 
> > +   mpc83xx_add_bridge(np, PPC_83XX_PCIE |
> PPC_83XX_PCI_PRIMARY); 
> > +   primary_pci_bus = 0; 
> > +   } else 
> > +   mpc83xx_add_bridge(np, PPC_83XX_PCIE); 
> > +   } 
> > + 
> > +   ppc_md.pci_exclude_device = mpc837x_exclude_device; 
> >  #endif
> 
> A few comments on how I think this can be improved:
> 
> * Instead of duplicating this code across all platforms, make a
> single 
> function that does the probing in one place (including the #ifdef 
> CONFIG_PCI).
> 

This code appears in 834x board in first and then copied from one board
to another. It is a legacy issue. :(
Yes. it is the time to remove this duplicates.

> * Better yet, get rid of mpc83xx_add_bridge and make it possible for
> the 
> mpc83xx code to use the of_pci_phb_driver from 
> arch/powerpc/kernel/of_platform.c. This used to be impossible because 
> of the differences  between 32 and 64 bit code for PCI probing, but 
> I think with the work than benh put into unifying the two, we should 
> be pretty close now.
> 

This is really a huge task and almost affects all exist boards. We need
more opinions in here. 


> * The detection method for the primary bus is somewhat fragile,
> because 
> we depend on the order of the nodes in the device tree, which is not 
> specified to have a meaning. /Maybe/ there could be a property in 
> (at most) one of the PCI host bridge nodes saying that this specific
> bus 
> is the primary one.
> 

Put this primary in code is more save than in dts.
The dts lacks error checking function. If provide error dts such as two
pci hosts both has primary property will occur chaos.

> * Since you are using exactly the same probing code for pci and pcie, 
> you may want to check for a more generic "compatible" property than 
> the specific model, so you can use the same code for both.
> 
> Arnd <><
> 

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Re: [PATCH] powerpc: Add MPC837x PCIE controller RC mode support

2008-01-02 Thread Li Li 
On Wed, 2008-01-02 at 23:23 +0800, Kumar Gala wrote:
> 
> On Jan 2, 2008, at 5:16 AM, Li Li wrote:
> 
> > * The MPC837x PCIE controller hardware resources and SerDes are  
> > initiated in u-boot. 
> > * Merge the MPC837x PCIE code into arch/powerpc/sysdev/fsl_pci.c 
> > * The MPC837x PCIE controller`s configure address bit field is
> uniqe: 
> >   bus number: bits 31-24 
> >   device number:  bits 23-19 
> >   function number:bits 18-16 
> >   ext reg number: bits 11-8 
> >   reg number: bits 7-2 
> > * Add mpc837x_exclude_device to fixup a controller bug.
> 
> what is the bug that is being worked around?
> 
For Type 0 configure transactions, the PCIE controller do not check the
device number bits and just assume the device number bits are 0.

- tony

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[PATCH] powerpc: Add MPC837x PCIE controller RC mode support

2008-01-02 Thread Li Li 
* The MPC837x PCIE controller hardware resources and SerDes are initiated in 
u-boot.
* Merge the MPC837x PCIE code into arch/powerpc/sysdev/fsl_pci.c
* The MPC837x PCIE controller`s configure address bit field is uniqe:
bus number: bits 31-24
device number:  bits 23-19
function number:bits 18-16
ext reg number: bits 11-8
reg number: bits 7-2
* Add mpc837x_exclude_device to fixup a controller bug.
* Add flag variant to mpc83xx_add_bridge function.

Signed-off-by: Tony Li <[EMAIL PROTECTED]>
---
 arch/powerpc/boot/dts/mpc8377_mds.dts |   54 --
 arch/powerpc/boot/dts/mpc8378_mds.dts |   54 --
 arch/powerpc/platforms/83xx/Kconfig   |2 +
 arch/powerpc/platforms/83xx/mpc8313_rdb.c |   10 ++-
 arch/powerpc/platforms/83xx/mpc832x_mds.c |   12 ++-
 arch/powerpc/platforms/83xx/mpc832x_rdb.c |   10 ++-
 arch/powerpc/platforms/83xx/mpc834x_itx.c |   10 ++-
 arch/powerpc/platforms/83xx/mpc834x_mds.c |   10 ++-
 arch/powerpc/platforms/83xx/mpc836x_mds.c |   12 ++-
 arch/powerpc/platforms/83xx/mpc837x_mds.c |   39 +++-
 arch/powerpc/platforms/83xx/mpc83xx.h |6 +-
 arch/powerpc/platforms/83xx/pci.c |   29 --
 arch/powerpc/sysdev/fsl_pci.c |  159 +
 arch/powerpc/sysdev/fsl_pci.h |3 +
 include/asm-powerpc/pci-bridge.h  |1 +
 include/linux/pci_ids.h   |4 +
 16 files changed, 375 insertions(+), 40 deletions(-)

diff --git a/arch/powerpc/boot/dts/mpc8377_mds.dts 
b/arch/powerpc/boot/dts/mpc8377_mds.dts
index 4402e39..4af3802 100644
--- a/arch/powerpc/boot/dts/mpc8377_mds.dts
+++ b/arch/powerpc/boot/dts/mpc8377_mds.dts
@@ -197,14 +197,6 @@
clock = ;
};
 
-   serdes2:[EMAIL PROTECTED] {
-   compatible = "fsl,serdes";
-   reg = ;
-   vdd-1v;
-   protocol = "pcie";
-   clock = ;
-   };
-
/* IPIC
 * interrupts cell = 
 * sense values match linux IORESOURCE_IRQ_* defines:
@@ -279,4 +271,50 @@
compatible = "fsl,mpc8349-pci";
device_type = "pci";
};
+
+   [EMAIL PROTECTED] {
+   interrupt-map-mask = ;
+   interrupt-map = <
+    0 0 1 &ipic 1 8
+    0 0 2 &ipic 1 8
+    0 0 3 &ipic 1 8
+    0 0 4 &ipic 1 8
+   >;
+   interrupt-parent = < &ipic >;
+   interrupts = <1 8>;
+   bus-range = <0 0>;
+   ranges = <0200 0 A000 A000 0 1000
+ 0100 0  B100 0 0080>;
+   clock-frequency = <0>;
+   #interrupt-cells = <1>;
+   #size-cells = <2>;
+   #address-cells = <3>;
+   reg = ;
+   compatible = "fsl,mpc8377-pcie";
+   device_type = "pci";
+   };
+
+   [EMAIL PROTECTED] {
+   interrupt-map-mask = ;
+   interrupt-map = <
+    0 0 1 &ipic 2 8
+    0 0 2 &ipic 2 8
+    0 0 3 &ipic 2 8
+    0 0 4 &ipic 2 8
+   >;
+   interrupt-parent = < &ipic >;
+   interrupts = <2 8>;
+   bus-range = <0 0>;
+   ranges = <0200 0 C000 C000 0 1000
+ 0100 0  D100 0 0080>;
+   clock-frequency = <0>;
+   #interrupt-cells = <1>;
+   #size-cells = <2>;
+   #address-cells = <3>;
+   reg = ;
+   compatible = "fsl,mpc8377-pcie";
+   device_type = "pci";
+   };
 };
diff --git a/arch/powerpc/boot/dts/mpc8378_mds.dts 
b/arch/powerpc/boot/dts/mpc8378_mds.dts
index 54171f4..de9d40c 100644
--- a/arch/powerpc/boot/dts/mpc8378_mds.dts
+++ b/arch/powerpc/boot/dts/mpc8378_mds.dts
@@ -179,14 +179,6 @@
clock = ;
};
 
-   serdes2:[EMAIL PROTECTED] {
-   compatible = "fsl,serdes";
-   reg = ;
-   vdd-1v;
-   protocol = "pcie";
-   clock = ;
-   };
-
/* IPIC
 * interrupts cell = 
 * sense values match linux IORESOURCE_IRQ_* defines:
@@ -261,4 +253,50 @@
compatible = "fsl,mpc8349-pci";
device_type = "pci";
};
+
+   [EMAIL PROTECTED] {
+   interrupt-map-mask = ;
+   interrupt-map = <
+    0 0 1 &ipic 1 8
+    0 0 2 &ipic 1 8
+

[patch] mpc83xx: Add MPC837x PCIE controller RC mode support

2007-12-19 Thread Li Li 
Initial the MPC837x PCIE controller.
Note that configue address bit field is not compatible with PCIE spec 10a.
Just map first 16M pci configure space which corresponding to a bus configure 
space at boot.


Signed-off-by: Tony Li <[EMAIL PROTECTED]>
---
 Makefile  |   17 ++-
 board/freescale/mpc837xemds/Makefile  |2 +-
 board/freescale/mpc837xemds/mpc837xemds.c |3 +
 board/freescale/mpc837xemds/pci.c |3 +-
 board/freescale/mpc837xemds/pcie.c|   95 +
 cpu/mpc83xx/Makefile  |2 +-
 cpu/mpc83xx/pcie.c|  315 +
 doc/README.mpc837xemds|6 +
 include/asm-ppc/immap_83xx.h  |  119 ++-
 include/configs/MPC837XEMDS.h |   23 ++-
 include/mpc83xx.h |   42 
 include/pci.h |4 +
 12 files changed, 619 insertions(+), 12 deletions(-)
 create mode 100644 board/freescale/mpc837xemds/pcie.c
 create mode 100644 cpu/mpc83xx/pcie.c

diff --git a/Makefile b/Makefile
index f8a038a..5934f77 100644
--- a/Makefile
+++ b/Makefile
@@ -1831,13 +1831,26 @@ MPC8360EMDS_SLAVE_config:   unconfig
@$(MKCONFIG) -a MPC8360EMDS ppc mpc83xx mpc8360emds freescale
 
 MPC837XEMDS_config \
-MPC837XEMDS_HOST_config:   unconfig
+MPC837XEMDS_HOST_config \
+MPC837XEMDS_PCIE_config \
+MPC837XEMDS_PCIE_X2_config:unconfig
@mkdir -p $(obj)include
@echo "" >$(obj)include/config.h ; \
if [ "$(findstring _HOST_,$@)" ] ; then \
echo -n "... PCI HOST " ; \
echo "#define CONFIG_PCI" >>$(obj)include/config.h ; \
-   fi ;
+   echo "#define CONFIG_PQ_MDS_PIB" >>$(obj)include/config.h ; \
+   fi ; \
+   if [ "$(findstring _PCIE_,$@)" ] ; then\
+   echo -n "... PCIE "; \
+   echo "#define CONFIG_PCI" >>$(obj)include/config.h ; \
+   echo "#define CONFIG_PCIE" >>$(obj)include/config.h ; \
+   fi; \
+   if [ "$(findstring _PCIE_X2_,$@)" ] ; then\
+   echo -n "_X2 "; \
+   echo "#define CONFIG_PCIE_X2" >>$(obj)include/config.h ; \
+   fi;
+
@$(MKCONFIG) -a MPC837XEMDS ppc mpc83xx mpc837xemds freescale
 
 sbc8349_config:unconfig
diff --git a/board/freescale/mpc837xemds/Makefile 
b/board/freescale/mpc837xemds/Makefile
index 3cffcfb..319ebc2 100644
--- a/board/freescale/mpc837xemds/Makefile
+++ b/board/freescale/mpc837xemds/Makefile
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
 
 LIB= $(obj)lib$(BOARD).a
 
-COBJS  := $(BOARD).o pci.o nand.o
+COBJS  := $(BOARD).o pci.o pcie.o nand.o
 
 SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS   := $(addprefix $(obj),$(COBJS))
diff --git a/board/freescale/mpc837xemds/mpc837xemds.c 
b/board/freescale/mpc837xemds/mpc837xemds.c
index 330e0e8..ff6f14a 100644
--- a/board/freescale/mpc837xemds/mpc837xemds.c
+++ b/board/freescale/mpc837xemds/mpc837xemds.c
@@ -48,6 +48,9 @@ int board_early_init_r(void)
 #ifdef CONFIG_PQ_MDS_PIB
pib_init();
 #endif
+#ifdef CONFIG_PCIE
+   pcie_init_board();
+#endif
return 0;
 }
 
diff --git a/board/freescale/mpc837xemds/pci.c 
b/board/freescale/mpc837xemds/pci.c
index ab90979..72e8dcc 100644
--- a/board/freescale/mpc837xemds/pci.c
+++ b/board/freescale/mpc837xemds/pci.c
@@ -59,7 +59,8 @@ void pci_init_board(void)
pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
 
udelay(2000);
-
+#if defined(CONFIG_PQ_MDS_PIB)
mpc83xx_pci_init(1, reg, 0);
+#endif
 }
 #endif /* CONFIG_PCI */
diff --git a/board/freescale/mpc837xemds/pcie.c 
b/board/freescale/mpc837xemds/pcie.c
new file mode 100644
index 000..474f848
--- /dev/null
+++ b/board/freescale/mpc837xemds/pcie.c
@@ -0,0 +1,95 @@
+/*
+ * Copyright (C) 2007 Freescale Semiconductor, Inc.
+ * Tony Li <[EMAIL PROTECTED]>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#if defined(CONFIG_PCIE)
+static struct pci_region pci_regions_0[] = {
+   {
+   bus_start: CFG_PCIE1_MEM_BASE,
+   phys_start: CFG_PCIE1_MEM_PHYS,
+   size: CFG_PCIE1_MEM_SIZE,
+   flags: PCI_REGION_MEM
+   },
+   {
+   bus_start: CFG_PCIE1_IO_BASE,
+   phys_start: CFG_PCIE1_IO_PHYS,
+   size: CFG_PCIE1_IO_SIZE,
+   flags: PCI_REGION_IO
+   }
+};
+
+static struct pci_region pci_regions_1[] = {
+   {
+   bus_start: CFG_PCIE2_MEM_BASE,
+   phys_start: CFG_PCIE2_MEM_PHYS,
+   size: CFG_PCIE2_MEM_SIZE,
+

[PATCH] powerpc: Add MPC837x PCIE RC mode support

2007-12-19 Thread Li Li 
The MPC837x PCIE controller hardware resources are initiated in u-boot.

Merge the MPC837x PCIE code into arch/powerpc/sysdev/fsl_pci.c

The MPC837x PCIE controller`s configure address bit field is uniqe:
bus number: bits 31-24
device number:  bits 23-19
function number:bits 18-16
ext reg number: bits 11-8
reg number: bits 7-2
This controller implements direct configure space access mode via outbound 
window.
Only map first 16M configure space at boot time. Remap the outbound window 
target address when 
want access another 16M configure space.

Add MPC837x PCIE controller specific fixup.

Add flag variant to mpc83xx_add_bridge function.

Signed-off-by: Tony Li <[EMAIL PROTECTED]>
---
 arch/powerpc/boot/dts/mpc8377_mds.dts |   54 --
 arch/powerpc/boot/dts/mpc8378_mds.dts |   54 --
 arch/powerpc/platforms/83xx/Kconfig   |2 +
 arch/powerpc/platforms/83xx/mpc8313_rdb.c |   10 ++-
 arch/powerpc/platforms/83xx/mpc832x_mds.c |   12 ++-
 arch/powerpc/platforms/83xx/mpc832x_rdb.c |   10 ++-
 arch/powerpc/platforms/83xx/mpc834x_itx.c |   10 ++-
 arch/powerpc/platforms/83xx/mpc834x_mds.c |   10 ++-
 arch/powerpc/platforms/83xx/mpc836x_mds.c |   12 ++-
 arch/powerpc/platforms/83xx/mpc837x_mds.c |   39 +++-
 arch/powerpc/platforms/83xx/mpc83xx.h |6 +-
 arch/powerpc/platforms/83xx/pci.c |   29 --
 arch/powerpc/sysdev/fsl_pci.c |  159 +
 arch/powerpc/sysdev/fsl_pci.h |3 +
 include/asm-powerpc/pci-bridge.h  |1 +
 include/linux/pci_ids.h   |4 +
 16 files changed, 375 insertions(+), 40 deletions(-)

diff --git a/arch/powerpc/boot/dts/mpc8377_mds.dts 
b/arch/powerpc/boot/dts/mpc8377_mds.dts
index 4402e39..5b6177a 100644
--- a/arch/powerpc/boot/dts/mpc8377_mds.dts
+++ b/arch/powerpc/boot/dts/mpc8377_mds.dts
@@ -197,14 +197,6 @@
clock = ;
};
 
-   serdes2:[EMAIL PROTECTED] {
-   compatible = "fsl,serdes";
-   reg = ;
-   vdd-1v;
-   protocol = "pcie";
-   clock = ;
-   };
-
/* IPIC
 * interrupts cell = 
 * sense values match linux IORESOURCE_IRQ_* defines:
@@ -279,4 +271,50 @@
compatible = "fsl,mpc8349-pci";
device_type = "pci";
};
+
+   [EMAIL PROTECTED] {
+   interrupt-map-mask = ;
+   interrupt-map = <
+    0 0 1 &ipic 1 8
+    0 0 2 &ipic 1 8
+    0 0 3 &ipic 1 8
+    0 0 4 &ipic 1 8
+   >;
+   interrupt-parent = < &ipic >;
+   interrupts = <1 8>;
+   bus-range = <0 0>;
+   ranges = <0200 0 A800 A800 0 1000
+ 0100 0  B800 0 0080>;
+   clock-frequency = <0>;
+   #interrupt-cells = <1>;
+   #size-cells = <2>;
+   #address-cells = <3>;
+   reg = ;
+   compatible = "fsl,mpc8377-pcie";
+   device_type = "pci";
+   };
+
+   [EMAIL PROTECTED] {
+   interrupt-map-mask = ;
+   interrupt-map = <
+    0 0 1 &ipic 2 8
+    0 0 2 &ipic 2 8
+    0 0 3 &ipic 2 8
+    0 0 4 &ipic 2 8
+   >;
+   interrupt-parent = < &ipic >;
+   interrupts = <2 8>;
+   bus-range = <0 0>;
+   ranges = <0200 0 C800 C800 0 1000
+ 0100 0  D800 0 0080>;
+   clock-frequency = <0>;
+   #interrupt-cells = <1>;
+   #size-cells = <2>;
+   #address-cells = <3>;
+   reg = ;
+   compatible = "fsl,mpc8377-pcie";
+   device_type = "pci";
+   };
 };
diff --git a/arch/powerpc/boot/dts/mpc8378_mds.dts 
b/arch/powerpc/boot/dts/mpc8378_mds.dts
index 54171f4..83ad974 100644
--- a/arch/powerpc/boot/dts/mpc8378_mds.dts
+++ b/arch/powerpc/boot/dts/mpc8378_mds.dts
@@ -179,14 +179,6 @@
clock = ;
};
 
-   serdes2:[EMAIL PROTECTED] {
-   compatible = "fsl,serdes";
-   reg = ;
-   vdd-1v;
-   protocol = "pcie";
-   clock = ;
-   };
-
/* IPIC
 * interrupts cell = 
 * sense values match linux IORESOURCE_IRQ_* defines:
@@ -261,4 +253,50 @@
compatible = "fsl,mpc8349-pci";
device_type = "pci";
};
+
+   [EMAIL PR

Re: [PATCH 2/2] powerpc: Add IPIC MSI support

2007-12-14 Thread Li Li 
On Fri, 2007-12-14 at 16:52 +0800, Kumar Gala wrote:
> 
> On Dec 14, 2007, at 2:47 AM, Li Tony wrote:
> 
> > 
> > Hi, 
> > 
> > I think it is possible to make common code to support both IPIC
> and  
> > MPIC. 
> > Currently, the MPIC has already implemented MSI which is different  
> > from IPIC and embedded into the mpic code body. 
> > If want to unifiy MSI code, we need to remove the current MPIC MSI  
> > implementation.
> 
> The MPIC is going to have to support several MSI styles (IBM/U3,  
> PaSemi, and FSL) since we all seem to handle it differently.
> 

Yes, you are right. I misunderstands here.

> > Micheal, what is your opinion ?? 
> > 
> > Jin is working on 86xx msi now.
> 
> What PCIe cards are you using to test MSIs?
> 

Intel PRO1000 PCIE network card and SysKonnect card.

> - k
> 
> >> -Original Message- 
> >> From: Kumar Gala [mailto:[EMAIL PROTECTED] 
> >> Sent: 2007年12月14日 13:45 
> >> To: Li Tony 
> >> Cc: Phillips Kim; [EMAIL PROTECTED]; linuxppc-dev 
> >> Subject: Re: [PATCH 2/2] powerpc: Add IPIC MSI support 
> >> 
> >> 
> >> On Dec 4, 2007, at 4:39 AM, Li Li wrote: 
> >> 
> >>> Modified based on discussion on list. 
> >>> 
> >>> 1. Adopt virq_to_hw routine 
> >>> 2. Correct a legacy bug 
> >>> 
> >>> Implements the IPIC MSI as two level interrupt controller. 
> >>> 
> >>> Signed-off-by: Tony Li <[EMAIL PROTECTED]> 
> >> 
> >> Tony, have you looked at the 85xx/86xx PCIe MSI mechanism? 
> >> The 2nd level PIC handling seems like its pretty similar 
> >> between IPIC and MPIC.  Would like to see if we could somehow 
> >> make the code common for to handle MSIs from both? 
> >> 
> >> - k 
> >>
> 

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[PATCH 2/2] powerpc: Add IPIC MSI support

2007-12-04 Thread Li Li 
Modified based on discussion on list.

1. Adopt virq_to_hw routine
2. Correct a legacy bug

Implements the IPIC MSI as two level interrupt controller.

Signed-off-by: Tony Li <[EMAIL PROTECTED]>
---
 arch/powerpc/boot/dts/mpc8377_mds.dts |   14 ++
 arch/powerpc/boot/dts/mpc8378_mds.dts |   14 ++
 arch/powerpc/boot/dts/mpc8379_mds.dts |   14 ++
 arch/powerpc/platforms/83xx/Kconfig   |6 +
 arch/powerpc/platforms/83xx/mpc837x_mds.c |7 +
 arch/powerpc/sysdev/Makefile  |1 +
 arch/powerpc/sysdev/ipic_msi.c|  359 +
 include/asm-powerpc/ipic_msi.h|   66 ++
 8 files changed, 481 insertions(+), 0 deletions(-)
 create mode 100644 arch/powerpc/sysdev/ipic_msi.c
 create mode 100644 include/asm-powerpc/ipic_msi.h

diff --git a/arch/powerpc/boot/dts/mpc8377_mds.dts 
b/arch/powerpc/boot/dts/mpc8377_mds.dts
index 8f54349..c11e529 100644
--- a/arch/powerpc/boot/dts/mpc8377_mds.dts
+++ b/arch/powerpc/boot/dts/mpc8377_mds.dts
@@ -210,6 +210,20 @@
#interrupt-cells = <2>;
reg = <700 100>;
};
+
+   [EMAIL PROTECTED] {
+   compatible = "fsl,ipic-msi";
+   reg = <7c0 40>;
+   interrupts = < 43 8
+  4  8
+  51 8
+  52 8
+  56 8
+  57 8
+  58 8
+  59 8 >;
+   interrupt-parent = < &ipic >;
+   };
};
 
[EMAIL PROTECTED] {
diff --git a/arch/powerpc/boot/dts/mpc8378_mds.dts 
b/arch/powerpc/boot/dts/mpc8378_mds.dts
index e09b0c5..7b0bf1b 100644
--- a/arch/powerpc/boot/dts/mpc8378_mds.dts
+++ b/arch/powerpc/boot/dts/mpc8378_mds.dts
@@ -192,6 +192,20 @@
#interrupt-cells = <2>;
reg = <700 100>;
};
+
+   [EMAIL PROTECTED] {
+   compatible = "fsl,ipic-msi";
+   reg = <7c0 40>;
+   interrupts = < 43 8
+  4  8
+  51 8
+  52 8
+  56 8
+  57 8
+  58 8
+  59 8 >;
+   interrupt-parent = < &ipic >;
+   };
};
 
[EMAIL PROTECTED] {
diff --git a/arch/powerpc/boot/dts/mpc8379_mds.dts 
b/arch/powerpc/boot/dts/mpc8379_mds.dts
index cdb4426..9fe4bd2 100644
--- a/arch/powerpc/boot/dts/mpc8379_mds.dts
+++ b/arch/powerpc/boot/dts/mpc8379_mds.dts
@@ -236,6 +236,20 @@
#interrupt-cells = <2>;
reg = <700 100>;
};
+
+   [EMAIL PROTECTED] {
+   compatible = "fsl,ipic-msi";
+   reg = <7c0 40>;
+   interrupts = < 43 8
+  4  8
+  51 8
+  52 8
+  56 8
+  57 8
+  58 8
+  59 8 >;
+   interrupt-parent = < &ipic >;
+   };
};
 
[EMAIL PROTECTED] {
diff --git a/arch/powerpc/platforms/83xx/Kconfig 
b/arch/powerpc/platforms/83xx/Kconfig
index 00154c5..4c51f78 100644
--- a/arch/powerpc/platforms/83xx/Kconfig
+++ b/arch/powerpc/platforms/83xx/Kconfig
@@ -88,6 +88,12 @@ config PPC_MPC837x
select FSL_SERDES
default y if MPC837x_MDS
 
+config IPIC_MSI
+   bool
+   depends on PCI_MSI
+   default y if PPC_MPC837x
+   default n
+
 config PPC_MPC83XX_PCIE
bool "MPC837X PCI Express support"
depends on PCIEPORTBUS && PPC_MPC837x
diff --git a/arch/powerpc/platforms/83xx/mpc837x_mds.c 
b/arch/powerpc/platforms/83xx/mpc837x_mds.c
index b1d3570..f68a7e9 100644
--- a/arch/powerpc/platforms/83xx/mpc837x_mds.c
+++ b/arch/powerpc/platforms/83xx/mpc837x_mds.c
@@ -17,6 +17,7 @@
 
 #include 
 #include 
+#include 
 #include 
 #include 
 
@@ -94,6 +95,12 @@ static void __init mpc837x_mds_init_IRQ(void)
 * in case the boot rom changed something on us.
 */
ipic_set_default_priority();
+
+   np = of_find_compatible_node(NULL, NULL, "fsl,ipic-msi");
+   if (!np)
+   return;
+
+   ipic_msi_init(np, ipic_msi_cascade);
 }
 
 /*
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index 99a77d7..5946b6a 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -25,6 +25,7 @@ ifeq ($(CONFIG_PPC_ME

[PATCH 1/2] powerpc: Add MPC837xE MDS PCIE RC mode support

2007-12-04 Thread Li Li 
Modified based on discussion in list.

1.Change the device node to pcie
2.Add PPC_83XX_PCI_PRIMARY flag
3.Rearrange the codes

The PCIE controller is initiated in u-boot.

Signed-off-by: Tony Li <[EMAIL PROTECTED]>
---
 arch/powerpc/boot/dts/mpc8377_mds.dts |   54 --
 arch/powerpc/boot/dts/mpc8378_mds.dts |   54 --
 arch/powerpc/platforms/83xx/Kconfig   |7 +
 arch/powerpc/platforms/83xx/mpc8313_rdb.c |   10 ++-
 arch/powerpc/platforms/83xx/mpc832x_mds.c |   12 ++-
 arch/powerpc/platforms/83xx/mpc832x_rdb.c |   10 ++-
 arch/powerpc/platforms/83xx/mpc834x_itx.c |   10 ++-
 arch/powerpc/platforms/83xx/mpc834x_mds.c |   10 ++-
 arch/powerpc/platforms/83xx/mpc836x_mds.c |   12 ++-
 arch/powerpc/platforms/83xx/mpc837x_mds.c |   19 +++-
 arch/powerpc/platforms/83xx/mpc83xx.h |6 +-
 arch/powerpc/platforms/83xx/pci.c |  174 +++--
 12 files changed, 338 insertions(+), 40 deletions(-)

diff --git a/arch/powerpc/boot/dts/mpc8377_mds.dts 
b/arch/powerpc/boot/dts/mpc8377_mds.dts
index 4402e39..8f54349 100644
--- a/arch/powerpc/boot/dts/mpc8377_mds.dts
+++ b/arch/powerpc/boot/dts/mpc8377_mds.dts
@@ -197,14 +197,6 @@
clock = ;
};
 
-   serdes2:[EMAIL PROTECTED] {
-   compatible = "fsl,serdes";
-   reg = ;
-   vdd-1v;
-   protocol = "pcie";
-   clock = ;
-   };
-
/* IPIC
 * interrupts cell = 
 * sense values match linux IORESOURCE_IRQ_* defines:
@@ -279,4 +271,50 @@
compatible = "fsl,mpc8349-pci";
device_type = "pci";
};
+
+   [EMAIL PROTECTED] {
+   interrupt-map-mask = ;
+   interrupt-map = <
+    0 0 1 &ipic 1 8
+    0 0 2 &ipic 1 8
+    0 0 3 &ipic 1 8
+    0 0 4 &ipic 1 8
+   >;
+   interrupt-parent = < &ipic >;
+   interrupts = <1 8>;
+   bus-range = <0 0>;
+   ranges = <0200 0 A800 A800 0 1000
+ 0100 0  B800 0 0080>;
+   clock-frequency = <0>;
+   #interrupt-cells = <1>;
+   #size-cells = <2>;
+   #address-cells = <3>;
+   reg = ;
+   compatible = "fsl,mpc8377-pcie";
+   device_type = "pci";
+   };
+
+   [EMAIL PROTECTED] {
+   interrupt-map-mask = ;
+   interrupt-map = <
+    0 0 1 &ipic 2 8
+    0 0 2 &ipic 2 8
+    0 0 3 &ipic 2 8
+    0 0 4 &ipic 2 8
+   >;
+   interrupt-parent = < &ipic >;
+   interrupts = <2 8>;
+   bus-range = <0 0>;
+   ranges = <0200 0 C800 C800 0 1000
+ 0100 0  D800 0 0080>;
+   clock-frequency = <0>;
+   #interrupt-cells = <1>;
+   #size-cells = <2>;
+   #address-cells = <3>;
+   reg = ;
+   compatible = "fsl,mpc8377-pcie";
+   device_type = "pci";
+   };
 };
diff --git a/arch/powerpc/boot/dts/mpc8378_mds.dts 
b/arch/powerpc/boot/dts/mpc8378_mds.dts
index 54171f4..e09b0c5 100644
--- a/arch/powerpc/boot/dts/mpc8378_mds.dts
+++ b/arch/powerpc/boot/dts/mpc8378_mds.dts
@@ -179,14 +179,6 @@
clock = ;
};
 
-   serdes2:[EMAIL PROTECTED] {
-   compatible = "fsl,serdes";
-   reg = ;
-   vdd-1v;
-   protocol = "pcie";
-   clock = ;
-   };
-
/* IPIC
 * interrupts cell = 
 * sense values match linux IORESOURCE_IRQ_* defines:
@@ -261,4 +253,50 @@
compatible = "fsl,mpc8349-pci";
device_type = "pci";
};
+
+   [EMAIL PROTECTED] {
+   interrupt-map-mask = ;
+   interrupt-map = <
+    0 0 1 &ipic 1 8
+    0 0 2 &ipic 1 8
+    0 0 3 &ipic 1 8
+    0 0 4 &ipic 1 8
+   >;
+   interrupt-parent = < &ipic >;
+   interrupts = <1 8>;
+   bus-range = <0 0>;
+   ranges = <0200 0 A800 A800 0 1000
+ 0100 0  B800 0 0080>;
+   clock-frequency = <0>;
+   #interrupt-cells = <1>;
+   #size-cells = <2>;
+   #address-cells = <3>;
+   reg = ;
+   compatible = "fsl,mpc8377-pcie";
+   devic

Re: [PATCH] Add IPIC MSI interrupt support

2007-12-04 Thread Li Li 
Yes. According to the PCI spec, a PCI device can request multi MSI
interrupts and require that interrupts are consecutive.
But it is ok if only allocate one to it.
Anyway, the hwirq should be allocated from bitmap instead of increment
by hand.

I will correct this and resend the patch.

- Tony

On Tue, 2007-12-04 at 15:51 +0800, Benjamin Herrenschmidt wrote:
> > I'm not sure what you mean? For MSI there is only one MSI per
> device, 
> > but this code is used also for MSI-X which supports > 1 MSI per
> device.
> 
> Or more specifically, for MSI, -linux- supports only one per device
> (in 
> theory, it's possible to have multiple MSI non-X but it's a mess).
> 
> > Either way we shouldn't be incrementing hwirq by hand, it's
> reassigned 
> > at the top of the loop. I think that's left over from old code that 
> > allocated nvec hwirqs in a block and then created virq mappings for
> each 
> > one, whereas the new code allocates each hwirq separately. 
> > 
> > cheers 
> > 
> > ___ 
> > Linuxppc-dev mailing list 
> > Linuxppc-dev@ozlabs.org 
> > https://ozlabs.org/mailman/listinfo/linuxppc-dev
> 

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Re: [PATCH] Add IPIC MSI interrupt support

2007-12-03 Thread Li Li 
On Tue, 2007-12-04 at 05:03 +0800, Benjamin Herrenschmidt wrote:
> 
> On Mon, 2007-12-03 at 17:07 +0800, Li Li wrote: 
> > 
> > In IPIC, the 8 MSI interrupts is handled as level intrrupt. 
> > I just provide a versatile in case it is changed.
> 
> Level ? Are you sure ? MSIs are by definition edge interrupts... Or
> do 
> you have some weird logic that asserts a level input until you go ack 
> something ? Sounds weird...
> 

The second one.
The MSI is edge interrupt. The 256 MSI interrupts are divided into 8
groups. Each group can generate a interrupt to core. This interrupts are
level and asserted untile ack MSI interrupt. A little weird.

> Ben.
> 
> 

- Tony


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Re: [PATCH] Add IPIC MSI interrupt support

2007-12-03 Thread Li Li 
Hi Michael,

I emulate mpic to write this IPIC MSI routines. :)


> > diff --git a/arch/powerpc/platforms/83xx/mpc837x_mds.c 
> > b/arch/powerpc/platforms/83xx/mpc837x_mds.c
> > index 6048f1b..dbea34b 100644
> > --- a/arch/powerpc/platforms/83xx/mpc837x_mds.c
> > +++ b/arch/powerpc/platforms/83xx/mpc837x_mds.c
> > @@ -17,6 +17,9 @@
> >  
> >  #include 
> >  #include 
> > +#if CONFIG_IPIC_MSI
> > +#include 
> > +#endif
> >  #include 
> >  #include 
> 
> I'd rather you just include it unconditionally.

Yes. that is ok for me.

> 
> > @@ -84,6 +87,14 @@ static void __init mpc837x_mds_init_IRQ(void)
> >  * in case the boot rom changed something on us.
> >  */
> > ipic_set_default_priority();
> > +
> > +#if CONFIG_IPIC_MSI
> > +   np = of_find_compatible_node(NULL, NULL, "fsl,ipic-msi");
> > +   if (!np)
> > +   return;
> > +
> > +   ipic_msi_init(np, ipic_msi_cascade);
> > +#endif
> 
> If you have a no-op version of ipic_msi_init() in your header file then
> you can remove the #ifdef in the C code - which I think is nicer.
> 

Seems you do not like #ifdef. :)  I agree it.
So, I move this #ifdef into header file.

> Why do you pass the handler into the init routine, rather than have the
> init routine just set the handler. Then you could make the handler
> static.
> 

In IPIC, the 8 MSI interrupts is handled as level intrrupt.
I just provide a versatile in case it is changed.

> >  }
> >  
> >  /*
> > diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
> > index 99a77d7..5946b6a 100644
> > --- a/arch/powerpc/sysdev/Makefile
> > +++ b/arch/powerpc/sysdev/Makefile
> > @@ -25,6 +25,7 @@ ifeq ($(CONFIG_PPC_MERGE),y)
> >  obj-$(CONFIG_PPC_INDIRECT_PCI) += indirect_pci.o
> >  obj-$(CONFIG_PPC_I8259)+= i8259.o
> >  obj-$(CONFIG_PPC_83xx) += ipic.o
> > +obj-$(CONFIG_IPIC_MSI) += ipic_msi.o
> >  obj-$(CONFIG_4xx)  += uic.o
> >  obj-$(CONFIG_XILINX_VIRTEX)+= xilinx_intc.o
> >  endif
> > diff --git a/arch/powerpc/sysdev/ipic_msi.c b/arch/powerpc/sysdev/ipic_msi.c
> > new file mode 100644
> > index 000..57758f7
> > --- /dev/null
> > +++ b/arch/powerpc/sysdev/ipic_msi.c
> > @@ -0,0 +1,359 @@
> > +/*
> > + * arch/powerpc/sysdev/ipic_msi.c
> > + *
> > + * IPIC MSI routines implementations.
> > + *
> > + * Auther: Tony Li <[EMAIL PROTECTED]>
> > + *
> > + * Copyright (c) 2007 Freescale Semiconductor, Inc.
> > + *
> > + * This program is free software; you can redistribute  it and/or modify it
> > + * under  the terms of  the GNU General  Public License as published by the
> > + * Free Software Foundation;  either version 2 of the  License, or (at your
> > + * option) any later version.
> > + */
> > +
> > +
> > +#include 
> > +#include 
> > +#include 
> > +
> > +#include 
> > +
> > +#define MSIR0  0x43
> > +#define MSIR1  0x4
> > +#define MSIR2  0x51
> > +#define MSIR3  0x52
> > +#define MSIR4  0x56
> > +#define MSIR5  0x57
> > +#define MSIR6  0x58
> > +#define MSIR7  0x59
> > +
> > +
> > +static struct ipic_msi *ipic_msi;
> > +static DEFINE_SPINLOCK(ipic_msi_lock);
> > +static DEFINE_SPINLOCK(ipic_msi_bitmap_lock);
> > +
> > +static inline u32 ipic_msi_read(volatile u32 __iomem *base, unsigned int 
> > reg)
> > +{
> > +   return in_be32(base + (reg >> 2));
> > +}
> > +
> > +static inline void ipic_msi_write(volatile u32 __iomem *base,
> > +   unsigned int reg, u32 value)
> > +{
> > +   out_be32(base + (reg >> 2), value);
> > +}
> > +
> > +static struct ipic_msi * ipic_msi_from_irq(unsigned int virq)
> > +{
> > +   return ipic_msi;
> > +}
> > +
> > +#defineipic_msi_irq_to_hw(virq)((unsigned 
> > int)irq_map[virq].hwirq)
> 
> What's wrong with virq_to_hw() ?
> 

viqr_to_hw is not __inline__.

> 
> > +static void ipic_msi_unmask(unsigned int virq)
> > +{
> > +   struct ipic_msi *msi = ipic_msi_from_irq(virq);
> > +   unsigned int src = ipic_msi_irq_to_hw(virq);
> > +   unsigned long flags;
> > +   u32 temp;
> > +
> > +   spin_lock_irqsave(&ipic_msi_lock, flags);
> > +   temp = ipic_msi_read(msi->regs, IPIC_MSIMR);
> > +   ipic_msi_write(msi->regs, IPIC_MSIMR,
> > +   temp & ~(1 << (src / msi->int_per_msir)));
> > +
> > +   spin_unlock_irqrestore(&ipic_msi_lock, flags);
> > +}
> > +
> > +static void ipic_msi_mask(unsigned int virq)
> > +{
> > +   struct ipic_msi *msi = ipic_msi_from_irq(virq);
> > +   unsigned int src = ipic_msi_irq_to_hw(virq);
> > +   unsigned long flags;
> > +   u32 temp;
> > +
> > +   spin_lock_irqsave(&ipic_msi_lock, flags);
> > +
> > +   temp = ipic_msi_read(msi->regs, IPIC_MSIMR);
> > +   ipic_msi_write(msi->regs, IPIC_MSIMR,
> > +   temp | (1 << (src / msi->int_per_msir)));
> > +
> > +   spin_unlock_irqrestore(&ipic_msi_lock, flags);
> > +}
> > +/*
> > + * We do not need this actually. The MSIR register has been read once
> > + * in ipic_msi_get_irq. So, this MSI interrupt has been acked
> > + */
> > +static void ipi

Re: [PATCH] Add IPIC MSI interrupt support

2007-12-02 Thread Li Li 
On Mon, 2007-12-03 at 09:52 +0800, David Gibson wrote:
> On Fri, Nov 30, 2007 at 11:48:39AM +0800, Li Li wrote: 
> > The IPIC MSI is introduced on MPC837x chip. 
> > Implements the IPIC MSI as two level interrupt controller. 
> > 
> > Signed-off-by: Tony Li <[EMAIL PROTECTED]> 
> > --- 
> >  arch/powerpc/boot/dts/mpc8377_mds.dts |   14 ++ 
> >  arch/powerpc/boot/dts/mpc8378_mds.dts |   14 ++ 
> >  arch/powerpc/boot/dts/mpc8379_mds.dts |   14 ++ 
> >  arch/powerpc/platforms/83xx/Kconfig   |6 + 
> >  arch/powerpc/platforms/83xx/mpc837x_mds.c |   11 + 
> >  arch/powerpc/sysdev/Makefile  |1 + 
> >  arch/powerpc/sysdev/ipic_msi.c|  359
> + 
> >  include/asm-powerpc/ipic_msi.h|   54 + 
> >  8 files changed, 473 insertions(+), 0 deletions(-) 
> >  create mode 100644 arch/powerpc/sysdev/ipic_msi.c 
> >  create mode 100644 include/asm-powerpc/ipic_msi.h 
> > 
> > diff --git a/arch/powerpc/boot/dts/mpc8377_mds.dts
> b/arch/powerpc/boot/dts/mpc8377_mds.dts 
> > index 1f7819e..1068fe2 100644 
> > --- a/arch/powerpc/boot/dts/mpc8377_mds.dts 
> > +++ b/arch/powerpc/boot/dts/mpc8377_mds.dts 
> > @@ -210,6 +210,20 @@ 
> >   #interrupt-cells = <2>; 
> >   reg = <700 100>; 
> >   }; 
> > + 
> > + [EMAIL PROTECTED] { 
> > + compatible = "fsl,ipic-msi"; 
> > + reg = <7c0 40>; 
> > + interrupts = < 43 8 
> > +4  8 
> > +51 8 
> > +52 8 
> > +56 8 
> > +57 8 
> > +58 8 
> > +59 8 >; 
> > + interrupt-parent = < &ipic >; 
> > + };
> 
> I'm not sure why the MSI needs a device node of its own.  What actual 
> piece of hardware is this representing?
> 

The IPIC MSI has its own registers which control the mask and ack of MSI
interrupt. Furthermore, IPIC MSI is the second level interrupt
coontorller which connected to IPIC, to compatible with IPIC OF routine
interface, we need a device node.

> -- 
> David Gibson| I'll have my music baroque, and my
> code 
> david AT gibson.dropbear.id.au  | minimalist, thank you.  NOT _the_
> _other_ 
> | _way_ _around_! 
> http://www.ozlabs.org/~dgibson
> 

- Tony

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Re: [PATCH] Add MPC837xEMDS PCIE RC mode support

2007-12-02 Thread Li Li 
On Fri, 2007-11-30 at 22:57 +0800, Gala Kumar wrote:
> 
> On Nov 30, 2007, at 3:37 AM, Li Li wrote:
> 
> > On Fri, 2007-11-30 at 17:05 +0800, Gala Kumar wrote: 
> >>>>> + 
> >>>>> + [EMAIL PROTECTED] { 
> >>>> 
> >>>> I agree w/Olof.  This should be [EMAIL PROTECTED] 
> >>>>> 
> >>>>> + interrupt-map-mask = ; 
> >>>>> + msi-available-ranges = <43 4 51 52 56 57 58 59>; 
> >>>>> + interrupt-map = < 
> >>>>> +  0 0 1 &ipic 1 8 
> >>>>> +  0 0 2 &ipic 1 8 
> >>>>> +  0 0 3 &ipic 1 8 
> >>>>> +  0 0 4 &ipic 1 8 
> >>>>> + >; 
> >>>>> + interrupt-parent = < &ipic >; 
> >>>>> + interrupts = <1 8>; 
> >>>>> + bus-range = <0 0>; 
> >>>>> + ranges = <0200 0 A800 A800 0 1000 
> >>>>> +   0100 0  B800 0
> 0080>; 
> >>>>> + clock-frequency = <0>; 
> >>>>> + #interrupt-cells = <1>; 
> >>>>> + #size-cells = <2>; 
> >>>>> + #address-cells = <3>; 
> >>>>> + reg =  >>>>> +a000 0800>; 
> >>>> 
> >>>> Shouldn't the reg size for the cfg space be 256M? 
> >>> 
> >>> 256M is a little too big for kernel. 
> >> 
> >> what do you mean too big?  Aren't you losing access to some 
> >> bus/dev/fn 
> >> than? 
> > 
> > If do it standard, a 256M config space, at least 256M mem space
> and  
> > 16M 
> > io space are needed for each PCIE controller. 
> > To allocate PCIE window, the window size only can be 512M or 1G. 
> > If we choose 1G space, two PCIE controller needs 2G space. 
> > We do not have 2G free physical space now. Usually, we use upper
> 128M 
> > configure space. So, we have to cut down the config space.
> 
> We'll cutting config space is problematic in that its a bug since
> you  
> might not be able to talk to a given device.
> 
> Is it possible to make the outbound window for cfg space 4k and
> change  
> the region of config space its looking at?
> 

I think that is possible but it means we have to reconfigure the PCIE
controller`s outbound window at every time we want do PCI config space
access in kernel. By now, all the PCIE controller is initialized on
u-boot which like PCI controller`s case.So it is a little not compatible
with the current kernel and u-boot assignment.

> >>>>> diff --git a/arch/powerpc/platforms/83xx/Kconfig
> b/arch/powerpc/ 
> >>>>> platforms/83xx/Kconfig 
> >>>>> index 0c61e7a..00154c5 100644 
> >>>>> --- a/arch/powerpc/platforms/83xx/Kconfig 
> >>>>> +++ b/arch/powerpc/platforms/83xx/Kconfig 
> >>>>> @@ -87,3 +87,10 @@ config PPC_MPC837x 
> >>>>> select PPC_INDIRECT_PCI 
> >>>>> select FSL_SERDES 
> >>>>> default y if MPC837x_MDS 
> >>>>> + 
> >>>>> +config PPC_MPC83XX_PCIE 
> >>>>> + bool "MPC837X PCI Express support" 
> >>>>> + depends on PCIEPORTBUS && PPC_MPC837x 
> >>>>> + default n 
> >>>>> + help 
> >>>>> +   Enables MPC837x PCI express RC mode 
> >>>> 
> >>>> This should be a hidden config that is just selected by 
> >> PPC_MPC837x 
> >>>> instead of a choice.  Also drop the depends on. 
> >>>> 
> >>> 
> >>> In the dts file, the PCIE is default enabled. So, we should
> provide 
> >>> another way to disable the PCIE. 
> >>> Modify and recompile the dts is a little unkind to user. 
> >> 
> >> Why do you something beyond CONFIG_PCI.  if you don't want PCIe
> but 
> >> do 
> >> want PCI the extra code for PCIe isn't going to kill you. 
> >> 
> > 
> > Here is a little complex. The MPC837xE board needs a carrier board
> to 
> > extend PCIE slot. If user does not populate carrier board onto  
> > MPC837xE 
> > board and

Re: [PATCH] Add MPC837xEMDS PCIE RC mode support

2007-11-30 Thread Li Li 
On Fri, 2007-11-30 at 17:05 +0800, Gala Kumar wrote:
> >>> + 
> >>> + [EMAIL PROTECTED] { 
> >> 
> >> I agree w/Olof.  This should be [EMAIL PROTECTED] 
> >>> 
> >>> + interrupt-map-mask = ; 
> >>> + msi-available-ranges = <43 4 51 52 56 57 58 59>; 
> >>> + interrupt-map = < 
> >>> +  0 0 1 &ipic 1 8 
> >>> +  0 0 2 &ipic 1 8 
> >>> +  0 0 3 &ipic 1 8 
> >>> +  0 0 4 &ipic 1 8 
> >>> + >; 
> >>> + interrupt-parent = < &ipic >; 
> >>> + interrupts = <1 8>; 
> >>> + bus-range = <0 0>; 
> >>> + ranges = <0200 0 A800 A800 0 1000 
> >>> +   0100 0  B800 0 0080>; 
> >>> + clock-frequency = <0>; 
> >>> + #interrupt-cells = <1>; 
> >>> + #size-cells = <2>; 
> >>> + #address-cells = <3>; 
> >>> + reg =  >>> +a000 0800>; 
> >> 
> >> Shouldn't the reg size for the cfg space be 256M? 
> > 
> > 256M is a little too big for kernel.
> 
> what do you mean too big?  Aren't you losing access to some
> bus/dev/fn  
> than?

If do it standard, a 256M config space, at least 256M mem space and 16M
io space are needed for each PCIE controller.
To allocate PCIE window, the window size only can be 512M or 1G.
If we choose 1G space, two PCIE controller needs 2G space.
We do not have 2G free physical space now. Usually, we use upper 128M
configure space. So, we have to cut down the config space.

> 
> >>> diff --git a/arch/powerpc/platforms/83xx/Kconfig b/arch/powerpc/ 
> >>> platforms/83xx/Kconfig 
> >>> index 0c61e7a..00154c5 100644 
> >>> --- a/arch/powerpc/platforms/83xx/Kconfig 
> >>> +++ b/arch/powerpc/platforms/83xx/Kconfig 
> >>> @@ -87,3 +87,10 @@ config PPC_MPC837x 
> >>>  select PPC_INDIRECT_PCI 
> >>>  select FSL_SERDES 
> >>>  default y if MPC837x_MDS 
> >>> + 
> >>> +config PPC_MPC83XX_PCIE 
> >>> + bool "MPC837X PCI Express support" 
> >>> + depends on PCIEPORTBUS && PPC_MPC837x 
> >>> + default n 
> >>> + help 
> >>> +   Enables MPC837x PCI express RC mode 
> >> 
> >> This should be a hidden config that is just selected by
> PPC_MPC837x 
> >> instead of a choice.  Also drop the depends on. 
> >> 
> > 
> > In the dts file, the PCIE is default enabled. So, we should provide 
> > another way to disable the PCIE. 
> > Modify and recompile the dts is a little unkind to user.
> 
> Why do you something beyond CONFIG_PCI.  if you don't want PCIe but
> do  
> want PCI the extra code for PCIe isn't going to kill you.
> 

Here is a little complex. The MPC837xE board needs a carrier board to
extend PCIE slot. If user does not populate carrier board onto MPC837xE
board and do PCIE scan, the system will halt.
I just want to provide a easy way to disable the PCIe other than modify
and recompile the dts.

> >>> diff --git a/arch/powerpc/platforms/83xx/mpc83xx.h
> b/arch/powerpc/ 
> >>> platforms/83xx/mpc83xx.h 
> >>> index b778cb4..2078da7 100644 
> >>> --- a/arch/powerpc/platforms/83xx/mpc83xx.h 
> >>> +++ b/arch/powerpc/platforms/83xx/mpc83xx.h 
> >>> @@ -43,12 +43,18 @@ 
> >>> #define PORTSCX_PTS_UTMI   0x 
> >>> #define PORTSCX_PTS_ULPI   0x8000 
> >>> 
> >>> +/* PCIE Registers */ 
> >>> +#define PEX_LTSSM_STAT   0x404 
> >>> +#define PEX_LTSSM_STAT_L00x16 
> >>> +#define PEX_GCLK_RATIO   0x440 
> >>> + 
> >> 
> >> just move these into the .c file. 

ok.

> >> 
> >>> 
> >>> /* 
> >>> * Declaration for the various functions exported by the 
> >>> * mpc83xx_* files. Mostly for use by mpc83xx_setup 
> >>> */ 
> >>> - 
> >>> -extern int mpc83xx_add_bridge(struct device_node *dev); 
> >>> +#define PPC_83XX_PCI 0x1 
> >>> +#define PPC_83XX_PCIE0x2 
> >>> +extern int mpc83xx_add_bridge(struct device_node *dev, int
> flags); 
> >>> extern void mpc83xx_restart(char *cmd); 
> >>> extern long mpc83xx_time_init(void); 
> >>> extern int mpc834x_usb_cfg(void); 
> >>> diff --git a/arch/powerpc/platforms/83xx/pci.c b/arch/powerpc/ 
> >>> platforms/83xx/pci.c 
> >>> index 80425d7..0b52b2e 100644 
> >>> --- a/arch/powerpc/platforms/83xx/pci.c 
> >>> +++ b/arch/powerpc/platforms/83xx/pci.c 
> >>> @@ -25,6 +25,8 @@ 
> >>> #include  
> >>> #include  
> >>> 
> >>> +#include "mpc83xx.h" 
> >>> + 
> >>> #undef DEBUG 
> >>> 
> >>> #ifdef DEBUG 
> >>> @@ -33,13 +35,157 @@ 
> >>> #define DBG(x...) 
> >>> #endif 
> >>> 
> >>> -int __init mpc83xx_add_bridge(struct device_node *dev) 
> >>> +#if defined(CONFIG_PPC_MPC83XX_PCIE) 
> >>> + 
> >>> +/* PCIE config space Read/Write routines */ 
> >> 
> >> should really be called something like mpc83xx_pciex_read_config 
> >>> 
> >>> +static int direct_read_config_pcie(struct pci_bus *bus, 
> >>> + uint devfn, int offset, int len, u32 *val) 
> >>> +{ 
> >>> + struc

Re: [PATCH] Add MPC837xEMDS PCIE RC mode support

2007-11-30 Thread Li Li 
On Fri, 2007-11-30 at 15:37 +0800, Gala Kumar wrote:
> 
> On Nov 29, 2007, at 9:45 PM, Li Li wrote:
> 
> > The PCIE controller is initiated in u-boot. 
> > 
> > This patch is based on Leo`s mpc837xe patches. 
> > 
> > 
> > Signed-off-by: Tony Li <[EMAIL PROTECTED]> 
> > --- 
> > arch/powerpc/boot/dts/mpc8377_mds.dts |   56 -- 
> > arch/powerpc/boot/dts/mpc8378_mds.dts |   56 -- 
> > arch/powerpc/platforms/83xx/Kconfig   |7 ++ 
> > arch/powerpc/platforms/83xx/mpc8313_rdb.c |2 +- 
> > arch/powerpc/platforms/83xx/mpc832x_mds.c |2 +- 
> > arch/powerpc/platforms/83xx/mpc832x_rdb.c |2 +- 
> > arch/powerpc/platforms/83xx/mpc834x_itx.c |2 +- 
> > arch/powerpc/platforms/83xx/mpc834x_mds.c |2 +- 
> > arch/powerpc/platforms/83xx/mpc836x_mds.c |2 +- 
> > arch/powerpc/platforms/83xx/mpc837x_mds.c |7 +- 
> > arch/powerpc/platforms/83xx/mpc83xx.h |   10 ++- 
> > arch/powerpc/platforms/83xx/pci.c |  166
>  
> > +++- 
> > 12 files changed, 283 insertions(+), 31 deletions(-) 
> > 
> > diff --git a/arch/powerpc/boot/dts/mpc8377_mds.dts b/arch/powerpc/ 
> > boot/dts/mpc8377_mds.dts 
> > index 4402e39..1f7819e 100644
> 
> > 
> > + 
> > + [EMAIL PROTECTED] {
> 
> I agree w/Olof.  This should be [EMAIL PROTECTED] 
> > 
> > + interrupt-map-mask = ; 
> > + msi-available-ranges = <43 4 51 52 56 57 58 59>; 
> > + interrupt-map = < 
> > +  0 0 1 &ipic 1 8 
> > +  0 0 2 &ipic 1 8 
> > +  0 0 3 &ipic 1 8 
> > +  0 0 4 &ipic 1 8 
> > + >; 
> > + interrupt-parent = < &ipic >; 
> > + interrupts = <1 8>; 
> > + bus-range = <0 0>; 
> > + ranges = <0200 0 A800 A800 0 1000 
> > +   0100 0  B800 0 0080>; 
> > + clock-frequency = <0>; 
> > + #interrupt-cells = <1>; 
> > + #size-cells = <2>; 
> > + #address-cells = <3>; 
> > + reg =  > +a000 0800>;
> 
> Shouldn't the reg size for the cfg space be 256M?

256M is a little too big for kernel.

> 
> 
> > diff --git a/arch/powerpc/platforms/83xx/Kconfig b/arch/powerpc/ 
> > platforms/83xx/Kconfig 
> > index 0c61e7a..00154c5 100644 
> > --- a/arch/powerpc/platforms/83xx/Kconfig 
> > +++ b/arch/powerpc/platforms/83xx/Kconfig 
> > @@ -87,3 +87,10 @@ config PPC_MPC837x 
> >   select PPC_INDIRECT_PCI 
> >   select FSL_SERDES 
> >   default y if MPC837x_MDS 
> > + 
> > +config PPC_MPC83XX_PCIE 
> > + bool "MPC837X PCI Express support" 
> > + depends on PCIEPORTBUS && PPC_MPC837x 
> > + default n 
> > + help 
> > +   Enables MPC837x PCI express RC mode
> 
> This should be a hidden config that is just selected by PPC_MPC837x  
> instead of a choice.  Also drop the depends on.
> 

In the dts file, the PCIE is default enabled. So, we should provide
another way to disable the PCIE.
Modify and recompile the dts is a little unkind to user.

> > diff --git a/arch/powerpc/platforms/83xx/mpc83xx.h b/arch/powerpc/ 
> > platforms/83xx/mpc83xx.h 
> > index b778cb4..2078da7 100644 
> > --- a/arch/powerpc/platforms/83xx/mpc83xx.h 
> > +++ b/arch/powerpc/platforms/83xx/mpc83xx.h 
> > @@ -43,12 +43,18 @@ 
> > #define PORTSCX_PTS_UTMI   0x 
> > #define PORTSCX_PTS_ULPI   0x8000 
> > 
> > +/* PCIE Registers */ 
> > +#define PEX_LTSSM_STAT   0x404 
> > +#define PEX_LTSSM_STAT_L00x16 
> > +#define PEX_GCLK_RATIO   0x440 
> > +
> 
> just move these into the .c file.
> 
> > 
> > /* 
> >  * Declaration for the various functions exported by the 
> >  * mpc83xx_* files. Mostly for use by mpc83xx_setup 
> >  */ 
> > - 
> > -extern int mpc83xx_add_bridge(struct device_node *dev); 
> > +#define PPC_83XX_PCI 0x1 
> > +#define PPC_83XX_PCIE0x2 
> > +extern int mpc83xx_add_bridge(struct device_node *dev, int flags); 
> > extern void mpc83xx_restart(char *cmd); 
> > extern long mpc83xx_time_init(void); 
> > extern int mpc834x_usb_cfg(void); 
> > diff --git a/arch/powerpc/platforms/83xx/pci.c b/arch/powerpc/

Re: [PATCH] Add MPC837xEMDS PCIE RC mode support

2007-11-29 Thread Li Li 
On Fri, 2007-11-30 at 12:14 +0800, Olof Johansson wrote:
> Hi,
> 
> On Fri, Nov 30, 2007 at 11:45:34AM +0800, Li Li wrote:
> 
> > + [EMAIL PROTECTED] {
> 
> Why call it pci2@ (and pci3@ below)? They are clearly identifiable
> with 
> their unit addresses anyway.
> 
> > +config PPC_MPC83XX_PCIE 
> > + bool "MPC837X PCI Express support" 
> > + depends on PCIEPORTBUS && PPC_MPC837x 
> > + default n 
> > + help 
> > +   Enables MPC837x PCI express RC mode
> 
> Why have a separate config option for this?
> 
> For systems where you don't want PCI-e configured, it should be left 
> out of the device tree instead.

It is easy to configure kernel than modify and recompile the dts.
The pcie is default enabled in dts.

> 
> 
> 
> -Olof
> 
- Tony

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[PATCH] Add IPIC MSI interrupt support

2007-11-29 Thread Li Li 
The IPIC MSI is introduced on MPC837x chip.
Implements the IPIC MSI as two level interrupt controller.

Signed-off-by: Tony Li <[EMAIL PROTECTED]>
---
 arch/powerpc/boot/dts/mpc8377_mds.dts |   14 ++
 arch/powerpc/boot/dts/mpc8378_mds.dts |   14 ++
 arch/powerpc/boot/dts/mpc8379_mds.dts |   14 ++
 arch/powerpc/platforms/83xx/Kconfig   |6 +
 arch/powerpc/platforms/83xx/mpc837x_mds.c |   11 +
 arch/powerpc/sysdev/Makefile  |1 +
 arch/powerpc/sysdev/ipic_msi.c|  359 +
 include/asm-powerpc/ipic_msi.h|   54 +
 8 files changed, 473 insertions(+), 0 deletions(-)
 create mode 100644 arch/powerpc/sysdev/ipic_msi.c
 create mode 100644 include/asm-powerpc/ipic_msi.h

diff --git a/arch/powerpc/boot/dts/mpc8377_mds.dts 
b/arch/powerpc/boot/dts/mpc8377_mds.dts
index 1f7819e..1068fe2 100644
--- a/arch/powerpc/boot/dts/mpc8377_mds.dts
+++ b/arch/powerpc/boot/dts/mpc8377_mds.dts
@@ -210,6 +210,20 @@
#interrupt-cells = <2>;
reg = <700 100>;
};
+
+   [EMAIL PROTECTED] {
+   compatible = "fsl,ipic-msi";
+   reg = <7c0 40>;
+   interrupts = < 43 8
+  4  8
+  51 8
+  52 8
+  56 8
+  57 8
+  58 8
+  59 8 >;
+   interrupt-parent = < &ipic >;
+   };
};
 
[EMAIL PROTECTED] {
diff --git a/arch/powerpc/boot/dts/mpc8378_mds.dts 
b/arch/powerpc/boot/dts/mpc8378_mds.dts
index 1503ae3..f12658f 100644
--- a/arch/powerpc/boot/dts/mpc8378_mds.dts
+++ b/arch/powerpc/boot/dts/mpc8378_mds.dts
@@ -192,6 +192,20 @@
#interrupt-cells = <2>;
reg = <700 100>;
};
+
+   [EMAIL PROTECTED] {
+   compatible = "fsl,ipic-msi";
+   reg = <7c0 40>;
+   interrupts = < 43 8
+  4  8
+  51 8
+  52 8
+  56 8
+  57 8
+  58 8
+  59 8 >;
+   interrupt-parent = < &ipic >;
+   };
};
 
[EMAIL PROTECTED] {
diff --git a/arch/powerpc/boot/dts/mpc8379_mds.dts 
b/arch/powerpc/boot/dts/mpc8379_mds.dts
index cdb4426..9fe4bd2 100644
--- a/arch/powerpc/boot/dts/mpc8379_mds.dts
+++ b/arch/powerpc/boot/dts/mpc8379_mds.dts
@@ -236,6 +236,20 @@
#interrupt-cells = <2>;
reg = <700 100>;
};
+
+   [EMAIL PROTECTED] {
+   compatible = "fsl,ipic-msi";
+   reg = <7c0 40>;
+   interrupts = < 43 8
+  4  8
+  51 8
+  52 8
+  56 8
+  57 8
+  58 8
+  59 8 >;
+   interrupt-parent = < &ipic >;
+   };
};
 
[EMAIL PROTECTED] {
diff --git a/arch/powerpc/platforms/83xx/Kconfig 
b/arch/powerpc/platforms/83xx/Kconfig
index 00154c5..4c51f78 100644
--- a/arch/powerpc/platforms/83xx/Kconfig
+++ b/arch/powerpc/platforms/83xx/Kconfig
@@ -88,6 +88,12 @@ config PPC_MPC837x
select FSL_SERDES
default y if MPC837x_MDS
 
+config IPIC_MSI
+   bool
+   depends on PCI_MSI
+   default y if PPC_MPC837x
+   default n
+
 config PPC_MPC83XX_PCIE
bool "MPC837X PCI Express support"
depends on PCIEPORTBUS && PPC_MPC837x
diff --git a/arch/powerpc/platforms/83xx/mpc837x_mds.c 
b/arch/powerpc/platforms/83xx/mpc837x_mds.c
index 6048f1b..dbea34b 100644
--- a/arch/powerpc/platforms/83xx/mpc837x_mds.c
+++ b/arch/powerpc/platforms/83xx/mpc837x_mds.c
@@ -17,6 +17,9 @@
 
 #include 
 #include 
+#if CONFIG_IPIC_MSI
+#include 
+#endif
 #include 
 #include 
 
@@ -84,6 +87,14 @@ static void __init mpc837x_mds_init_IRQ(void)
 * in case the boot rom changed something on us.
 */
ipic_set_default_priority();
+
+#if CONFIG_IPIC_MSI
+   np = of_find_compatible_node(NULL, NULL, "fsl,ipic-msi");
+   if (!np)
+   return;
+
+   ipic_msi_init(np, ipic_msi_cascade);
+#endif
 }
 
 /*
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index 99a77d7..5946b6a 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -25,6 +25,7 @@ ifeq ($(CONF

[PATCH] Add MPC837xEMDS PCIE RC mode support

2007-11-29 Thread Li Li 
The PCIE controller is initiated in u-boot.

This patch is based on Leo`s mpc837xe patches.


Signed-off-by: Tony Li <[EMAIL PROTECTED]>
---
 arch/powerpc/boot/dts/mpc8377_mds.dts |   56 --
 arch/powerpc/boot/dts/mpc8378_mds.dts |   56 --
 arch/powerpc/platforms/83xx/Kconfig   |7 ++
 arch/powerpc/platforms/83xx/mpc8313_rdb.c |2 +-
 arch/powerpc/platforms/83xx/mpc832x_mds.c |2 +-
 arch/powerpc/platforms/83xx/mpc832x_rdb.c |2 +-
 arch/powerpc/platforms/83xx/mpc834x_itx.c |2 +-
 arch/powerpc/platforms/83xx/mpc834x_mds.c |2 +-
 arch/powerpc/platforms/83xx/mpc836x_mds.c |2 +-
 arch/powerpc/platforms/83xx/mpc837x_mds.c |7 +-
 arch/powerpc/platforms/83xx/mpc83xx.h |   10 ++-
 arch/powerpc/platforms/83xx/pci.c |  166 +++-
 12 files changed, 283 insertions(+), 31 deletions(-)

diff --git a/arch/powerpc/boot/dts/mpc8377_mds.dts 
b/arch/powerpc/boot/dts/mpc8377_mds.dts
index 4402e39..1f7819e 100644
--- a/arch/powerpc/boot/dts/mpc8377_mds.dts
+++ b/arch/powerpc/boot/dts/mpc8377_mds.dts
@@ -197,14 +197,6 @@
clock = ;
};
 
-   serdes2:[EMAIL PROTECTED] {
-   compatible = "fsl,serdes";
-   reg = ;
-   vdd-1v;
-   protocol = "pcie";
-   clock = ;
-   };
-
/* IPIC
 * interrupts cell = 
 * sense values match linux IORESOURCE_IRQ_* defines:
@@ -279,4 +271,52 @@
compatible = "fsl,mpc8349-pci";
device_type = "pci";
};
+
+   [EMAIL PROTECTED] {
+   interrupt-map-mask = ;
+   msi-available-ranges = <43 4 51 52 56 57 58 59>;
+   interrupt-map = <
+    0 0 1 &ipic 1 8
+    0 0 2 &ipic 1 8
+    0 0 3 &ipic 1 8
+    0 0 4 &ipic 1 8
+   >;
+   interrupt-parent = < &ipic >;
+   interrupts = <1 8>;
+   bus-range = <0 0>;
+   ranges = <0200 0 A800 A800 0 1000
+ 0100 0  B800 0 0080>;
+   clock-frequency = <0>;
+   #interrupt-cells = <1>;
+   #size-cells = <2>;
+   #address-cells = <3>;
+   reg = ;
+   compatible = "fsl,mpc8377-pcie";
+   device_type = "pci";
+   };
+
+   [EMAIL PROTECTED] {
+   interrupt-map-mask = ;
+   msi-available-ranges = <43 4 51 52 56 57 58 59>;
+   interrupt-map = <
+    0 0 1 &ipic 2 8
+    0 0 2 &ipic 2 8
+    0 0 3 &ipic 2 8
+    0 0 4 &ipic 2 8
+   >;
+   interrupt-parent = < &ipic >;
+   interrupts = <2 8>;
+   bus-range = <0 0>;
+   ranges = <0200 0 C800 C800 0 1000
+ 0100 0  D800 0 0080>;
+   clock-frequency = <0>;
+   #interrupt-cells = <1>;
+   #size-cells = <2>;
+   #address-cells = <3>;
+   reg = ;
+   compatible = "fsl,mpc8377-pcie";
+   device_type = "pci";
+   };
 };
diff --git a/arch/powerpc/boot/dts/mpc8378_mds.dts 
b/arch/powerpc/boot/dts/mpc8378_mds.dts
index 54171f4..1503ae3 100644
--- a/arch/powerpc/boot/dts/mpc8378_mds.dts
+++ b/arch/powerpc/boot/dts/mpc8378_mds.dts
@@ -179,14 +179,6 @@
clock = ;
};
 
-   serdes2:[EMAIL PROTECTED] {
-   compatible = "fsl,serdes";
-   reg = ;
-   vdd-1v;
-   protocol = "pcie";
-   clock = ;
-   };
-
/* IPIC
 * interrupts cell = 
 * sense values match linux IORESOURCE_IRQ_* defines:
@@ -261,4 +253,52 @@
compatible = "fsl,mpc8349-pci";
device_type = "pci";
};
+
+   [EMAIL PROTECTED] {
+   interrupt-map-mask = ;
+   msi-available-ranges = <43 4 51 52 56 57 58 59>;
+   interrupt-map = <
+    0 0 1 &ipic 1 8
+    0 0 2 &ipic 1 8
+    0 0 3 &ipic 1 8
+    0 0 4 &ipic 1 8
+   >;
+   interrupt-parent = < &ipic >;
+   interrupts = <1 8>;
+   bus-range = <0 0>;
+   ranges = <0200 0 A800 A800 0 1000
+ 0100 0  B800 0 0080>;
+   clock-frequency = <0>;
+   #interrupt-cells = <1>;
+   #size-cells = <2>;
+   #addre