from:"Mike Wolf"

[PATCH] change where the kernel loads

2008-01-15 Thread Mike Wolf

When netbooting a kernel with an initrd or initramfs that makes
the image larger than 8 meg the firmware will kick out the kernel 
and go to the second boot device.  However when the mkzimage 
script is used to create the image instead of 'make zImage' then 
the kernel/initrd will netboot.  So this patch changes boot/zImage.lds
to load the kernel at the same location that the mkzimage would set.

This has been boot tested on POWER5, POWER5+, blades and POWER6
systems successfully.

signed off by:  Mike Wolf ([EMAIL PROTECTED])


--



--- linux-2.6.16.46-0.12.orig/arch/powerpc/boot/zImage.lds  2008-01-07 
14:51:05.0 -0600
+++ linux-2.6.16.46-0.12/arch/powerpc/boot/zImage.lds   2008-01-07 
14:31:14.0 -0600
@@ -2,7 +2,7 @@
 ENTRY(_zimage_start)
 SECTIONS
 {
-  . = (4*1024*1024);
+  . = (64*1024);
   _start = .;
   .text  :
   {


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Resend: [PATCH] oprofile support for Power 5++

2007-07-10 Thread Mike Wolf

The patch has not been included and there have been no comments so
I'm resending.

This patch adds a new oprofile cpu type for Power 5 revision 3 chips.
The new name is ppc64/power5++ and is used so that the performance
counters can be set up correctly.

Signed-off-by: Mike Wolf <[EMAIL PROTECTED]>

 
linux-2.6.18.ppc64.orig/arch/powerpc/kernel/cputable.c  2006-09-19 
22:42:06.0 -0500
+++ linux-2.6.18.ppc64/arch/powerpc/kernel/cputable.c   2007-06-11 
12:29:47.0 -0500
@@ -236,6 +236,21 @@
.oprofile_mmcra_sipr= MMCRA_SIPR,
.platform   = "power5",
},
+   {   /* Power5++ */
+   .pvr_mask   = 0xff00,
+   .pvr_value  = 0x003b0300,
+   .cpu_name   = "POWER5+ (gs)",
+   .cpu_features   = CPU_FTRS_POWER5,
+   .cpu_user_features  = COMMON_USER_POWER5_PLUS,
+   .icache_bsize   = 128,
+   .dcache_bsize   = 128,
+   .num_pmcs   = 6,
+   .oprofile_cpu_type  = "ppc64/power5++",
+   .oprofile_type  = PPC_OPROFILE_POWER4,
+   .oprofile_mmcra_sihv= MMCRA_SIHV,
+   .oprofile_mmcra_sipr= MMCRA_SIPR,
+   .platform   = "power5+",
+   },
{   /* Power5 GS */
.pvr_mask   = 0x,
.pvr_value  = 0x003b,

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Re: Resend: [PATCH] oprofile support for Power 5++

2007-07-10 Thread Mike Wolf

Michael Neuling wrote:
>> The patch has not been included and there have been no comments so
>> I'm resending.
>>
>> This patch adds a new oprofile cpu type for Power 5 revision 3 chips.
>> The new name is ppc64/power5++ and is used so that the performance
>> counters can be set up correctly.
>> 
>
> Does it make more sense to call this "ppc64/power5+rev3"?  
>   
This is a change to support new counter setup for oprofile.  It may be the
same if there is a revision 4 or 5 etc.  So since the internal name was ++
I followed that convention. 
> Mikey
>
>   
>> Signed-off-by: Mike Wolf <[EMAIL PROTECTED]>
>>
>>  
>> linux-2.6.18.ppc64.orig/arch/powerpc/kernel/cputable.c   2006-09-19 22:4
>> 
> 2:06.0 -0500
>   
>> +++ linux-2.6.18.ppc64/arch/powerpc/kernel/cputable.c2007-06-11 
>> 12:29:47.000
>> 
> 00 -0500
>   
>> @@ -236,6 +236,21 @@
>>  .oprofile_mmcra_sipr= MMCRA_SIPR,
>>  .platform   = "power5",
>>  },
>> +{   /* Power5++ */
>> +.pvr_mask   = 0xff00,
>> +.pvr_value  = 0x003b0300,
>> +.cpu_name   = "POWER5+ (gs)",
>> +.cpu_features   = CPU_FTRS_POWER5,
>> +.cpu_user_features  = COMMON_USER_POWER5_PLUS,
>> +.icache_bsize   = 128,
>> +.dcache_bsize   = 128,
>> +.num_pmcs   = 6,
>> +.oprofile_cpu_type  = "ppc64/power5++",
>> +.oprofile_type  = PPC_OPROFILE_POWER4,
>> +.oprofile_mmcra_sihv= MMCRA_SIHV,
>> +.oprofile_mmcra_sipr= MMCRA_SIPR,
>> +.platform   = "power5+",
>> +},
>>  {   /* Power5 GS */
>>  .pvr_mask   = 0x,
>>  .pvr_value  = 0x003b,
>>
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>> 

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[PATCH] powerpc: adjust oprofile_cpu_type

2009-04-17 Thread Mike Wolf

Oprofile is changing the naming it is using for the compatibility modes.
Instead of having compat-power, oprofile will go to family naming
convention and use compat-v.  Currently only compat-v1 will be
defined.

Signed off by: Mike Wolf 
---
--- mainline.orig/arch/powerpc/kernel/cputable.c2009-04-16
09:47:49.0 -0500
+++ mainline/arch/powerpc/kernel/cputable.c 2009-04-16
14:28:28.0 -0500
@@ -382,7 +382,8 @@
.icache_bsize   = 128,
.dcache_bsize   = 128,
.machine_check  = machine_check_generic,
-   .oprofile_cpu_type  = "ppc64/compat-power5+",
+   .oprofile_cpu_type  = "ppc64/compat-v1",
+   .oprofile_type  = PPC_OPROFILE_POWER4,
.platform   = "power5+",
},
{   /* Power6 */
@@ -416,7 +417,8 @@
.icache_bsize   = 128,
.dcache_bsize   = 128,
.machine_check  = machine_check_generic,
-   .oprofile_cpu_type  = "ppc64/compat-power6",
+   .oprofile_cpu_type  = "ppc64/compat-v1",
+   .oprofile_type  = PPC_OPROFILE_POWER4,
.platform   = "power6",
},
{   /* 2.06-compliant processor, i.e. Power7 "architected" mode */
@@ -429,7 +431,8 @@
.icache_bsize   = 128,
.dcache_bsize   = 128,
.machine_check  = machine_check_generic,
-   .oprofile_cpu_type  = "ppc64/compat-power7",
+   .oprofile_type  = PPC_OPROFILE_POWER4,
+   .oprofile_cpu_type  = "ppc64/compat-v1",
.platform   = "power7",
},
{   /* Power7 */
@@ -1833,8 +1836,10 @@
 * and, in that case, keep the current value for
 * oprofile_cpu_type.
 */
-   if (old.oprofile_cpu_type == NULL)
+   if (old.oprofile_cpu_type == NULL) {
t->oprofile_cpu_type = s->oprofile_cpu_type;
+   t->oprofile_type = s->oprofile_type;
+   }
}
 
*PTRRELOC(&cur_cpu_spec) = &the_cpu_spec;


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[PATCH] powerpc: adjust oprofile_cpu_type

2009-04-22 Thread Mike Wolf

Resending.  the patch was munged last time.


Oprofile is changing the naming it is using for the compatibility modes.
Instead of having compat-power, oprofile will go to family naming
convention and use compat-v.  Currently only compat-v1 will be
defined.

Signed-off-by: Mike Wolf 


--- mainline.orig/arch/powerpc/kernel/cputable.c2009-04-16 
09:47:49.0 -0500
+++ mainline/arch/powerpc/kernel/cputable.c 2009-04-16 14:28:28.0 
-0500
@@ -382,7 +382,8 @@
.icache_bsize   = 128,
.dcache_bsize   = 128,
.machine_check  = machine_check_generic,
-   .oprofile_cpu_type  = "ppc64/compat-power5+",
+   .oprofile_cpu_type  = "ppc64/compat-v1",
+   .oprofile_type  = PPC_OPROFILE_POWER4,
.platform   = "power5+",
},
{   /* Power6 */
@@ -416,7 +417,8 @@
.icache_bsize   = 128,
.dcache_bsize   = 128,
.machine_check  = machine_check_generic,
-   .oprofile_cpu_type  = "ppc64/compat-power6",
+   .oprofile_cpu_type  = "ppc64/compat-v1",
+   .oprofile_type  = PPC_OPROFILE_POWER4,
.platform   = "power6",
},
{   /* 2.06-compliant processor, i.e. Power7 "architected" mode */
@@ -429,7 +431,8 @@
.icache_bsize   = 128,
.dcache_bsize   = 128,
.machine_check  = machine_check_generic,
-   .oprofile_cpu_type  = "ppc64/compat-power7",
+   .oprofile_type  = PPC_OPROFILE_POWER4,
+   .oprofile_cpu_type  = "ppc64/compat-v1",
.platform   = "power7",
},
{   /* Power7 */
@@ -1833,8 +1836,10 @@
 * and, in that case, keep the current value for
 * oprofile_cpu_type.
 */
-   if (old.oprofile_cpu_type == NULL)
+   if (old.oprofile_cpu_type == NULL) {
t->oprofile_cpu_type = s->oprofile_cpu_type;
+   t->oprofile_type = s->oprofile_type;
+   }
}
 
*PTRRELOC(&cur_cpu_spec) = &the_cpu_spec;


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Re: [PATCH] powerpc: adjust oprofile_cpu_type

2009-04-23 Thread Mike Wolf

On Thu, 2009-04-23 at 12:52 -0500, Olof Johansson wrote:
> On Wed, Apr 22, 2009 at 06:40:12PM -0500, Mike Wolf wrote:
> > Resending.  the patch was munged last time.
> > 
> > 
> > Oprofile is changing the naming it is using for the compatibility modes.
> > Instead of having compat-power, oprofile will go to family naming
> > convention and use compat-v.  Currently only compat-v1 will be
> > defined.
> 
> Compat V1 of what? powerpc64? IBM powerpc64 PMC? 

IBM powerpc PMC

>  The performance
> monitors are not architected, to give them a version number without
> vendor information seems weird.
The current ones all fall into one family and they may be architected in
the future.
> 
> Also, doesn't this break compatibility with existing userspace tools?
AFAIK there is nothing else that uses these.  Oprofile patch was
rejected and this new naming was suggested from that community.

Mike

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[PATCH] powerpc adjust oprofile_cpu_type version 3

2009-04-27 Thread Mike Wolf

Oprofile is changing the naming it is using for the compatibility modes.
Instead of having compat-power, oprofile will go to family naming
convention and use ibm-compat-v.  Currently only ibm-compat-v1 will
be defined.
The notion of compatibility events just started with POWER6. So there is
no way that any other tool could exist that is using these
oprofile_cpu_type strings we want to change.

Signed-off-by: Mike Wolf 

---
--- mainline.orig/arch/powerpc/kernel/cputable.c2009-04-16 
09:47:49.0 -0500
+++ mainline/arch/powerpc/kernel/cputable.c 2009-04-27 10:28:03.0 
-0500
@@ -382,7 +382,8 @@
.icache_bsize   = 128,
.dcache_bsize   = 128,
.machine_check  = machine_check_generic,
-   .oprofile_cpu_type  = "ppc64/compat-power5+",
+   .oprofile_cpu_type  = "ppc64/ibm-compat-v1",
+   .oprofile_type  = PPC_OPROFILE_POWER4,
.platform   = "power5+",
},
{   /* Power6 */
@@ -416,7 +417,8 @@
.icache_bsize   = 128,
.dcache_bsize   = 128,
.machine_check  = machine_check_generic,
-   .oprofile_cpu_type  = "ppc64/compat-power6",
+   .oprofile_cpu_type  = "ppc64/ibm-compat-v1",
+   .oprofile_type  = PPC_OPROFILE_POWER4,
.platform   = "power6",
},
{   /* 2.06-compliant processor, i.e. Power7 "architected" mode */
@@ -429,7 +431,8 @@
.icache_bsize   = 128,
.dcache_bsize   = 128,
.machine_check  = machine_check_generic,
-   .oprofile_cpu_type  = "ppc64/compat-power7",
+   .oprofile_type  = PPC_OPROFILE_POWER4,
+   .oprofile_cpu_type  = "ppc64/ibm-compat-v1",
.platform   = "power7",
},
{   /* Power7 */
@@ -1833,8 +1836,10 @@
 * and, in that case, keep the current value for
 * oprofile_cpu_type.
 */
-   if (old.oprofile_cpu_type == NULL)
+   if (old.oprofile_cpu_type == NULL) {
t->oprofile_cpu_type = s->oprofile_cpu_type;
+   t->oprofile_type = s->oprofile_type;
+   }
}
 
*PTRRELOC(&cur_cpu_spec) = &the_cpu_spec;


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[PATCH] powerpc adjust oprofile_cpu_type version 3 resend

2009-04-29 Thread Mike Wolf

Oprofile is changing the naming it is using for the compatibility modes.
Instead of having compat-power, oprofile will go to family naming
convention and use ibm-compat-v.  Currently only ibm-compat-v1 will
be defined.
The notion of compatibility events just started with POWER6. So there is
no way that any other tool could exist that is using these
oprofile_cpu_type strings we want to change.

Signed-off-by: Mike Wolf 


--- mainline.orig/arch/powerpc/kernel/cputable.c2009-04-16 
09:47:49.0 -0500
+++ mainline/arch/powerpc/kernel/cputable.c 2009-04-27 10:28:03.0 
-0500
@@ -382,7 +382,8 @@
.icache_bsize   = 128,
.dcache_bsize   = 128,
.machine_check  = machine_check_generic,
-   .oprofile_cpu_type  = "ppc64/compat-power5+",
+   .oprofile_cpu_type  = "ppc64/ibm-compat-v1",
+   .oprofile_type  = PPC_OPROFILE_POWER4,
.platform   = "power5+",
},
{   /* Power6 */
@@ -416,7 +417,8 @@
.icache_bsize   = 128,
.dcache_bsize   = 128,
.machine_check  = machine_check_generic,
-   .oprofile_cpu_type  = "ppc64/compat-power6",
+   .oprofile_cpu_type  = "ppc64/ibm-compat-v1",
+   .oprofile_type  = PPC_OPROFILE_POWER4,
.platform   = "power6",
},
{   /* 2.06-compliant processor, i.e. Power7 "architected" mode */
@@ -429,7 +431,8 @@
.icache_bsize   = 128,
.dcache_bsize   = 128,
.machine_check  = machine_check_generic,
-   .oprofile_cpu_type  = "ppc64/compat-power7",
+   .oprofile_type  = PPC_OPROFILE_POWER4,
+   .oprofile_cpu_type  = "ppc64/ibm-compat-v1",
.platform   = "power7",
},
{   /* Power7 */
@@ -1833,8 +1836,10 @@
 * and, in that case, keep the current value for
 * oprofile_cpu_type.
 */
-   if (old.oprofile_cpu_type == NULL)
+   if (old.oprofile_cpu_type == NULL) {
t->oprofile_cpu_type = s->oprofile_cpu_type;
+   t->oprofile_type = s->oprofile_type;
+   }
}
 
*PTRRELOC(&cur_cpu_spec) = &the_cpu_spec;


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[PATCH] powerpc: Fix oprofile sampling of marked events on POWER7

2009-05-06 Thread Mike Wolf

>From Maynard Johnson 

Description
---
Change ppc64 oprofile kernel driver to use the SLOT bits (MMCRA[37:39]only on
older processors where those bits are defined.

Background
--
The performance monitor unit of the 64-bit POWER processor family has the
ability to collect accurate instruction-level samples when profiling on marked
events (i.e., "PM_MRK_").  In processors prior to POWER6, the MMCRA
register contained "slot information" that the oprofile kernel driver used to
adjust the value latched in the SIAR at the time of a PMU interrupt.  But as of
POWER6, these slot bits in MMCRA are no longer necessary for oprofile to use,
since the SIAR itself holds the accurate sampled instruction address.  With
POWER6, these MMCRA slot bits were zero'ed out by hardware so oprofile's use of
these slot bits was, in effect, a NOP.  But with POWER7, these bits are no
longer zero'ed out; however, they serve some other purpose rather than slot
information.  Thus, using these bits on POWER7 to adjust the SIAR value results
in samples being attributed to the wrong instructions.  The attached patch
changes the oprofile kernel driver to ignore these slot bits on all newer
processors starting with POWER6.

Signed-off-by: Michael Wolf 

---

diff -paur linux/arch/powerpc/oprofile/op_model_power4.c 
linux-p7-oprofile-patch//arch/powerpc/oprofile/op_model_power4.c
--- linux/arch/powerpc/oprofile/op_model_power4.c   2009-05-01 
08:20:21.0 -0500
+++ linux-p7-oprofile-patch//arch/powerpc/oprofile/op_model_power4.c
2009-05-01 08:20:05.0 -0500
@@ -26,6 +26,7 @@
 static unsigned long reset_value[OP_MAX_COUNTER];

 static int oprofile_running;
+static int use_slot_nums;

 /* mmcr values are set in power4_reg_setup, used in power4_cpu_setup */
 static u32 mmcr0_val;
@@ -61,6 +62,12 @@ static int power4_reg_setup(struct op_co
else
mmcr0_val |= MMCR0_PROBLEM_DISABLE;

+   if (__is_processor(PV_POWER4) || __is_processor(PV_POWER4p) ||
+   __is_processor(PV_970) || __is_processor(PV_970FX) ||
+   __is_processor(PV_970MP) || __is_processor(PV_970GX) ||
+   __is_processor(PV_POWER5) || __is_processor(PV_POWER5p))
+   use_slot_nums = 1;
+
return 0;
 }

@@ -206,7 +213,7 @@ static unsigned long get_pc(struct pt_re

mmcra = mfspr(SPRN_MMCRA);

-   if (mmcra & MMCRA_SAMPLE_ENABLE) {
+   if (use_slot_nums && (mmcra & MMCRA_SAMPLE_ENABLE)) {
slot = ((mmcra & MMCRA_SLOT) >> MMCRA_SLOT_SHIFT);
if (slot > 1)
pc += 4 * (slot - 1);




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[PATCH] powerpc: Fix oprofile sampling of marked events on POWER7

2009-05-07 Thread Mike Wolf

From: Maynard Johnson 

Description
---
Change ppc64 oprofile kernel driver to use the SLOT bits (MMCRA[37:39]only on
older processors where those bits are defined.

Background
--
The performance monitor unit of the 64-bit POWER processor family has the
ability to collect accurate instruction-level samples when profiling on marked
events (i.e., "PM_MRK_").  In processors prior to POWER6, the MMCRA
register contained "slot information" that the oprofile kernel driver used to
adjust the value latched in the SIAR at the time of a PMU interrupt.  But as of
POWER6, these slot bits in MMCRA are no longer necessary for oprofile to use,
since the SIAR itself holds the accurate sampled instruction address.  With
POWER6, these MMCRA slot bits were zero'ed out by hardware so oprofile's use of
these slot bits was, in effect, a NOP.  But with POWER7, these bits are no
longer zero'ed out; however, they serve some other purpose rather than slot
information.  Thus, using these bits on POWER7 to adjust the SIAR value results
in samples being attributed to the wrong instructions.  The attached patch
changes the oprofile kernel driver to ignore these slot bits on all newer
processors starting with POWER6.

Signed-off-by: Maynard Johnson 
Signed-off-by: Michael Wolf 

---
diff -paur linux/arch/powerpc/oprofile/op_model_power4.c 
linux-p7-oprofile-patch//arch/powerpc/oprofile/op_model_power4.c
--- linux/arch/powerpc/oprofile/op_model_power4.c   2009-05-01 
08:20:21.0 -0500
+++ linux-p7-oprofile-patch//arch/powerpc/oprofile/op_model_power4.c
2009-05-01 08:20:05.0 -0500
@@ -26,6 +26,7 @@
 static unsigned long reset_value[OP_MAX_COUNTER];

 static int oprofile_running;
+static int use_slot_nums;

 /* mmcr values are set in power4_reg_setup, used in power4_cpu_setup */
 static u32 mmcr0_val;
@@ -61,6 +62,12 @@ static int power4_reg_setup(struct op_co
else
mmcr0_val |= MMCR0_PROBLEM_DISABLE;

+   if (__is_processor(PV_POWER4) || __is_processor(PV_POWER4p) ||
+   __is_processor(PV_970) || __is_processor(PV_970FX) ||
+   __is_processor(PV_970MP) || __is_processor(PV_970GX) ||
+   __is_processor(PV_POWER5) || __is_processor(PV_POWER5p))
+   use_slot_nums = 1;
+
return 0;
 }

@@ -206,7 +213,7 @@ static unsigned long get_pc(struct pt_re

mmcra = mfspr(SPRN_MMCRA);

-   if (mmcra & MMCRA_SAMPLE_ENABLE) {
+   if (use_slot_nums && (mmcra & MMCRA_SAMPLE_ENABLE)) {
slot = ((mmcra & MMCRA_SLOT) >> MMCRA_SLOT_SHIFT);
if (slot > 1)
pc += 4 * (slot - 1);




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[PATCH] powerpc: Adjust base and index registers in Altivec macros

2009-08-20 Thread Mike Wolf

On POWER6 systems RA needs to be the base and RB the index.  
If they are reversed you take a misdirect hit.  

Signed-off-by: Mike Wolf 


--- altivec.orig/arch/powerpc/include/asm/ppc_asm.h 2009-08-17 
15:39:52.0 -0500
+++ altivec/arch/powerpc/include/asm/ppc_asm.h  2009-08-20 18:08:30.0 
-0500
@@ -98,13 +98,13 @@
 #define REST_16FPRS(n, base)   REST_8FPRS(n, base); REST_8FPRS(n+8, base)
 #define REST_32FPRS(n, base)   REST_16FPRS(n, base); REST_16FPRS(n+16, base)
 
-#define SAVE_VR(n,b,base)  li b,THREAD_VR0+(16*(n));  stvx n,b,base
+#define SAVE_VR(n,b,base)  li b,THREAD_VR0+(16*(n));  stvx n,base,b
 #define SAVE_2VRS(n,b,base)SAVE_VR(n,b,base); SAVE_VR(n+1,b,base)
 #define SAVE_4VRS(n,b,base)SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base)
 #define SAVE_8VRS(n,b,base)SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base)
 #define SAVE_16VRS(n,b,base)   SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base)
 #define SAVE_32VRS(n,b,base)   SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base)
-#define REST_VR(n,b,base)  li b,THREAD_VR0+(16*(n)); lvx n,b,base
+#define REST_VR(n,b,base)  li b,THREAD_VR0+(16*(n)); lvx n,base,b
 #define REST_2VRS(n,b,base)REST_VR(n,b,base); REST_VR(n+1,b,base)
 #define REST_4VRS(n,b,base)REST_2VRS(n,b,base); REST_2VRS(n+2,b,base)
 #define REST_8VRS(n,b,base)REST_4VRS(n,b,base); REST_4VRS(n+4,b,base)
@@ -112,26 +112,26 @@
 #define REST_32VRS(n,b,base)   REST_16VRS(n,b,base); REST_16VRS(n+16,b,base)
 
 /* Save the lower 32 VSRs in the thread VSR region */
-#define SAVE_VSR(n,b,base) li b,THREAD_VSR0+(16*(n));  STXVD2X(n,b,base)
+#define SAVE_VSR(n,b,base) li b,THREAD_VSR0+(16*(n));  STXVD2X(n,base,b)
 #define SAVE_2VSRS(n,b,base)   SAVE_VSR(n,b,base); SAVE_VSR(n+1,b,base)
 #define SAVE_4VSRS(n,b,base)   SAVE_2VSRS(n,b,base); SAVE_2VSRS(n+2,b,base)
 #define SAVE_8VSRS(n,b,base)   SAVE_4VSRS(n,b,base); SAVE_4VSRS(n+4,b,base)
 #define SAVE_16VSRS(n,b,base)  SAVE_8VSRS(n,b,base); SAVE_8VSRS(n+8,b,base)
 #define SAVE_32VSRS(n,b,base)  SAVE_16VSRS(n,b,base); SAVE_16VSRS(n+16,b,base)
-#define REST_VSR(n,b,base) li b,THREAD_VSR0+(16*(n)); LXVD2X(n,b,base)
+#define REST_VSR(n,b,base) li b,THREAD_VSR0+(16*(n)); LXVD2X(n,base,b)
 #define REST_2VSRS(n,b,base)   REST_VSR(n,b,base); REST_VSR(n+1,b,base)
 #define REST_4VSRS(n,b,base)   REST_2VSRS(n,b,base); REST_2VSRS(n+2,b,base)
 #define REST_8VSRS(n,b,base)   REST_4VSRS(n,b,base); REST_4VSRS(n+4,b,base)
 #define REST_16VSRS(n,b,base)  REST_8VSRS(n,b,base); REST_8VSRS(n+8,b,base)
 #define REST_32VSRS(n,b,base)  REST_16VSRS(n,b,base); REST_16VSRS(n+16,b,base)
 /* Save the upper 32 VSRs (32-63) in the thread VSX region (0-31) */
-#define SAVE_VSRU(n,b,base)li b,THREAD_VR0+(16*(n));  STXVD2X(n+32,b,base)
+#define SAVE_VSRU(n,b,base)li b,THREAD_VR0+(16*(n));  STXVD2X(n+32,base,b)
 #define SAVE_2VSRSU(n,b,base)  SAVE_VSRU(n,b,base); SAVE_VSRU(n+1,b,base)
 #define SAVE_4VSRSU(n,b,base)  SAVE_2VSRSU(n,b,base); SAVE_2VSRSU(n+2,b,base)
 #define SAVE_8VSRSU(n,b,base)  SAVE_4VSRSU(n,b,base); SAVE_4VSRSU(n+4,b,base)
 #define SAVE_16VSRSU(n,b,base) SAVE_8VSRSU(n,b,base); SAVE_8VSRSU(n+8,b,base)
 #define SAVE_32VSRSU(n,b,base) SAVE_16VSRSU(n,b,base); 
SAVE_16VSRSU(n+16,b,base)
-#define REST_VSRU(n,b,base)li b,THREAD_VR0+(16*(n)); LXVD2X(n+32,b,base)
+#define REST_VSRU(n,b,base)li b,THREAD_VR0+(16*(n)); LXVD2X(n+32,base,b)
 #define REST_2VSRSU(n,b,base)  REST_VSRU(n,b,base); REST_VSRU(n+1,b,base)
 #define REST_4VSRSU(n,b,base)  REST_2VSRSU(n,b,base); REST_2VSRSU(n+2,b,base)
 #define REST_8VSRSU(n,b,base)  REST_4VSRSU(n,b,base); REST_4VSRSU(n+4,b,base)


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[PATCH] change where the kernel loads

Resend: [PATCH] oprofile support for Power 5++

Re: Resend: [PATCH] oprofile support for Power 5++

[PATCH] powerpc: adjust oprofile_cpu_type

[PATCH] powerpc: adjust oprofile_cpu_type

Re: [PATCH] powerpc: adjust oprofile_cpu_type

[PATCH] powerpc adjust oprofile_cpu_type version 3

[PATCH] powerpc adjust oprofile_cpu_type version 3 resend

[PATCH] powerpc: Fix oprofile sampling of marked events on POWER7

[PATCH] powerpc: Fix oprofile sampling of marked events on POWER7

[PATCH] powerpc: Adjust base and index registers in Altivec macros

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