Re: [PATCH v8 2/2] mmc: host: sdhci: Disable 1.8V signaling for arasan 4.9a version of SDHCI controller.
On Tue, Jul 21, 2015 at 6:43 PM, Ulf Hansson ulf.hans...@linaro.org wrote:
On 19 June 2015 at 14:28, Suman Tripathi stripa...@apm.com wrote:
Hi ,
On Fri, Jun 19, 2015 at 5:30 PM, Suman Tripathi stripa...@apm.com wrote:
This patch disables the 1.8V signaling for arasan 4.9a version
of SDHCI controller with the help SDHCI_QUIRK2_NO_1_8_V quirk.
Signed-off-by: Suman Tripathi stripa...@apm.com
---
---
drivers/mmc/host/sdhci-of-arasan.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci-of-arasan.c
b/drivers/mmc/host/sdhci-of-arasan.c
index 21c0c08..4c99ea4 100644
--- a/drivers/mmc/host/sdhci-of-arasan.c
+++ b/drivers/mmc/host/sdhci-of-arasan.c
@@ -171,7 +171,8 @@ static int sdhci_arasan_probe(struct platform_device
*pdev)
if (of_device_is_compatible(pdev-dev.of_node,
arasan,sdhci-4.9a)) {
host-quirks |= SDHCI_QUIRK_NO_HISPD_BIT;
- host-quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23;
+ host-quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23 |
+SDHCI_QUIRK2_NO_1_8_V;
}
I think I am wrong here. No-1.8v is something related to board
regulator circuitry not related to IP version. So it should be dts
driven.
Agree!
So I guess that will change patch1 and this one can be completely dropped?
yes.
Kind regards
Uffe
--
Thanks,
with regards,
Suman Tripathi
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Re: [PATCH v8 1/2] arm64: dts: Add the arasan mmc nodes in apm-storm.dtsi
Any comments on this patch ??
On Fri, Jun 19, 2015 at 5:30 PM, Suman Tripathi stripa...@apm.com wrote:
This patch adds the arasan mmc nodes to reuse the of-arasan
driver for APM X-Gene SoC.
Signed-off-by: Suman Tripathi stripa...@apm.com
---
---
arch/arm64/boot/dts/apm/apm-mustang.dts | 4 +++
arch/arm64/boot/dts/apm/apm-storm.dtsi | 43
+
2 files changed, 47 insertions(+)
diff --git a/arch/arm64/boot/dts/apm/apm-mustang.dts
b/arch/arm64/boot/dts/apm/apm-mustang.dts
index 83578e7..7a3ea72 100644
--- a/arch/arm64/boot/dts/apm/apm-mustang.dts
+++ b/arch/arm64/boot/dts/apm/apm-mustang.dts
@@ -52,3 +52,7 @@
xgenet {
status = ok;
};
+
+mmc0 {
+ status = ok;
+};
diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi
b/arch/arm64/boot/dts/apm/apm-storm.dtsi
index c8d3e0e..8e03ecd 100644
--- a/arch/arm64/boot/dts/apm/apm-storm.dtsi
+++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi
@@ -145,6 +145,40 @@
clock-output-names = socplldiv2;
};
+ ahbclk: ahbclk@1f2ac000 {
+ compatible = apm,xgene-device-clock;
+ #clock-cells = 1;
+ clocks = socplldiv2 0;
+ reg = 0x0 0x1f2ac000 0x0 0x1000
+ 0x0 0x1700 0x0 0x2000;
+ reg-names = csr-reg, div-reg;
+ csr-offset = 0x0;
+ csr-mask = 0x1;
+ enable-offset = 0x8;
+ enable-mask = 0x1;
+ divider-offset = 0x164;
+ divider-width = 0x5;
+ divider-shift = 0x0;
+ clock-output-names = ahbclk;
+ };
+
+ sdioclk: sdioclk@1f2ac000 {
+ compatible = apm,xgene-device-clock;
+ #clock-cells = 1;
+ clocks = socplldiv2 0;
+ reg = 0x0 0x1f2ac000 0x0 0x1000
+ 0x0 0x1700 0x0 0x2000;
+ reg-names = csr-reg, div-reg;
+ csr-offset = 0x0;
+ csr-mask = 0x2;
+ enable-offset = 0x8;
+ enable-mask = 0x2;
+ divider-offset = 0x178;
+ divider-width = 0x8;
+ divider-shift = 0x0;
+ clock-output-names = sdioclk;
+ };
+
qmlclk: qmlclk {
compatible = apm,xgene-device-clock;
#clock-cells = 1;
@@ -533,6 +567,15 @@
interrupts = 0x0 0x4f 0x4;
};
+ mmc0: mmc@1c00 {
+ compatible = arasan,sdhci-4.9a;
+ reg = 0x0 0x1c00 0x0 0x100;
+ interrupts = 0x0 0x49 0x4;
+ dma-coherent;
+ clock-names = clk_xin, clk_ahb;
+ clocks = sdioclk 0, ahbclk 0;
+ };
+
phy1: phy@1f21a000 {
compatible = apm,xgene-phy;
reg = 0x0 0x1f21a000 0x0 0x100;
--
1.8.2.1
--
Thanks,
with regards,
Suman Tripathi
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[PATCH v8 2/2] mmc: host: sdhci: Disable 1.8V signaling for arasan 4.9a version of SDHCI controller.
This patch disables the 1.8V signaling for arasan 4.9a version
of SDHCI controller with the help SDHCI_QUIRK2_NO_1_8_V quirk.
Signed-off-by: Suman Tripathi stripa...@apm.com
---
---
drivers/mmc/host/sdhci-of-arasan.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci-of-arasan.c
b/drivers/mmc/host/sdhci-of-arasan.c
index 21c0c08..4c99ea4 100644
--- a/drivers/mmc/host/sdhci-of-arasan.c
+++ b/drivers/mmc/host/sdhci-of-arasan.c
@@ -171,7 +171,8 @@ static int sdhci_arasan_probe(struct platform_device *pdev)
if (of_device_is_compatible(pdev-dev.of_node, arasan,sdhci-4.9a)) {
host-quirks |= SDHCI_QUIRK_NO_HISPD_BIT;
- host-quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23;
+ host-quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23 |
+SDHCI_QUIRK2_NO_1_8_V;
}
sdhci_get_of_property(pdev);
--
1.8.2.1
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Re: [PATCH v8 2/2] mmc: host: sdhci: Disable 1.8V signaling for arasan 4.9a version of SDHCI controller.
Hi ,
On Fri, Jun 19, 2015 at 5:30 PM, Suman Tripathi stripa...@apm.com wrote:
This patch disables the 1.8V signaling for arasan 4.9a version
of SDHCI controller with the help SDHCI_QUIRK2_NO_1_8_V quirk.
Signed-off-by: Suman Tripathi stripa...@apm.com
---
---
drivers/mmc/host/sdhci-of-arasan.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci-of-arasan.c
b/drivers/mmc/host/sdhci-of-arasan.c
index 21c0c08..4c99ea4 100644
--- a/drivers/mmc/host/sdhci-of-arasan.c
+++ b/drivers/mmc/host/sdhci-of-arasan.c
@@ -171,7 +171,8 @@ static int sdhci_arasan_probe(struct platform_device
*pdev)
if (of_device_is_compatible(pdev-dev.of_node, arasan,sdhci-4.9a)) {
host-quirks |= SDHCI_QUIRK_NO_HISPD_BIT;
- host-quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23;
+ host-quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23 |
+SDHCI_QUIRK2_NO_1_8_V;
}
I think I am wrong here. No-1.8v is something related to board
regulator circuitry not related to IP version. So it should be dts
driven.
sdhci_get_of_property(pdev);
--
1.8.2.1
--
Thanks,
with regards,
Suman Tripathi
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[PATCH v8 1/2] arm64: dts: Add the arasan mmc nodes in apm-storm.dtsi
This patch adds the arasan mmc nodes to reuse the of-arasan
driver for APM X-Gene SoC.
Signed-off-by: Suman Tripathi stripa...@apm.com
---
---
arch/arm64/boot/dts/apm/apm-mustang.dts | 4 +++
arch/arm64/boot/dts/apm/apm-storm.dtsi | 43 +
2 files changed, 47 insertions(+)
diff --git a/arch/arm64/boot/dts/apm/apm-mustang.dts
b/arch/arm64/boot/dts/apm/apm-mustang.dts
index 83578e7..7a3ea72 100644
--- a/arch/arm64/boot/dts/apm/apm-mustang.dts
+++ b/arch/arm64/boot/dts/apm/apm-mustang.dts
@@ -52,3 +52,7 @@
xgenet {
status = ok;
};
+
+mmc0 {
+ status = ok;
+};
diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi
b/arch/arm64/boot/dts/apm/apm-storm.dtsi
index c8d3e0e..8e03ecd 100644
--- a/arch/arm64/boot/dts/apm/apm-storm.dtsi
+++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi
@@ -145,6 +145,40 @@
clock-output-names = socplldiv2;
};
+ ahbclk: ahbclk@1f2ac000 {
+ compatible = apm,xgene-device-clock;
+ #clock-cells = 1;
+ clocks = socplldiv2 0;
+ reg = 0x0 0x1f2ac000 0x0 0x1000
+ 0x0 0x1700 0x0 0x2000;
+ reg-names = csr-reg, div-reg;
+ csr-offset = 0x0;
+ csr-mask = 0x1;
+ enable-offset = 0x8;
+ enable-mask = 0x1;
+ divider-offset = 0x164;
+ divider-width = 0x5;
+ divider-shift = 0x0;
+ clock-output-names = ahbclk;
+ };
+
+ sdioclk: sdioclk@1f2ac000 {
+ compatible = apm,xgene-device-clock;
+ #clock-cells = 1;
+ clocks = socplldiv2 0;
+ reg = 0x0 0x1f2ac000 0x0 0x1000
+ 0x0 0x1700 0x0 0x2000;
+ reg-names = csr-reg, div-reg;
+ csr-offset = 0x0;
+ csr-mask = 0x2;
+ enable-offset = 0x8;
+ enable-mask = 0x2;
+ divider-offset = 0x178;
+ divider-width = 0x8;
+ divider-shift = 0x0;
+ clock-output-names = sdioclk;
+ };
+
qmlclk: qmlclk {
compatible = apm,xgene-device-clock;
#clock-cells = 1;
@@ -533,6 +567,15 @@
interrupts = 0x0 0x4f 0x4;
};
+ mmc0: mmc@1c00 {
+ compatible = arasan,sdhci-4.9a;
+ reg = 0x0 0x1c00 0x0 0x100;
+ interrupts = 0x0 0x49 0x4;
+ dma-coherent;
+ clock-names = clk_xin, clk_ahb;
+ clocks = sdioclk 0, ahbclk 0;
+ };
+
phy1: phy@1f21a000 {
compatible = apm,xgene-phy;
reg = 0x0 0x1f21a000 0x0 0x100;
--
1.8.2.1
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[PATCH v8 0/2] Add SDHCI support for APM X-Gene SoC using ARASAN SDHCI controller.
This patch adds the SDHCI support for APM X-Gene SoC using ARASAN SDHCI controller. v1 change: * Use the CONFIG_ARM64_DMA_HAS_IOMMU for dma-mapping. v2 change: * Drop the IOMMU support and switching to PIO mode for arasan. controller integrated inside APM X-Gene SoC. v3 change: * Change the sdhci-of-arasan.c to support arasan4.9a. * Add quirks for arasan4.9a. v4 change: * Cleanup the Documentation and dts. v5 change: * Rebase the dts files. * Drop patch 2 and 3 as it is applied. v6 change: * Clean the unrequired properties from dts. * Rename sdhc to sdhci. * support to disable timming using capability register read. v7 change: * Rename sdhci nodes to mmc. v8 change: * Drop the support to disable timming using capability register read. * Add SDHCI_QUIRK2_NO_1_8_V for 4.9a version of arasan. Suman Tripathi (2): arm64: dts: Add the arasan mmc nodes in apm-storm.dtsi mmc: host: sdhci: Disable 1.8V signaling for arasan 4.9a version of SDHCI controller. arch/arm64/boot/dts/apm/apm-mustang.dts | 4 +++ arch/arm64/boot/dts/apm/apm-storm.dtsi | 43 + drivers/mmc/host/sdhci-of-arasan.c | 3 ++- 3 files changed, 49 insertions(+), 1 deletion(-) -- 1.8.2.1 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH v7 1/2] arm64: dts: Add the arasan mmc nodes in apm-storm.dtsi
Hi Arnd and all
On Mon, May 18, 2015 at 12:34 PM, Suman Tripathi stripa...@apm.com wrote:
Hi Arnd,
On Wed, May 13, 2015 at 5:21 PM, Suman Tripathi stripa...@apm.com wrote:
This patch adds the arasan mmc nodes to reuse the of-arasan
driver for APM X-Gene SoC.
Signed-off-by: Suman Tripathi stripa...@apm.com
---
---
arch/arm64/boot/dts/apm/apm-mustang.dts | 4 +++
arch/arm64/boot/dts/apm/apm-storm.dtsi | 43
+
2 files changed, 47 insertions(+)
diff --git a/arch/arm64/boot/dts/apm/apm-mustang.dts
b/arch/arm64/boot/dts/apm/apm-mustang.dts
index 83578e7..7a3ea72 100644
--- a/arch/arm64/boot/dts/apm/apm-mustang.dts
+++ b/arch/arm64/boot/dts/apm/apm-mustang.dts
@@ -52,3 +52,7 @@
xgenet {
status = ok;
};
+
+mmc0 {
+ status = ok;
+};
diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi
b/arch/arm64/boot/dts/apm/apm-storm.dtsi
index c8d3e0e..8e03ecd 100644
--- a/arch/arm64/boot/dts/apm/apm-storm.dtsi
+++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi
@@ -145,6 +145,40 @@
clock-output-names = socplldiv2;
};
+ ahbclk: ahbclk@1f2ac000 {
+ compatible = apm,xgene-device-clock;
+ #clock-cells = 1;
+ clocks = socplldiv2 0;
+ reg = 0x0 0x1f2ac000 0x0 0x1000
+ 0x0 0x1700 0x0 0x2000;
+ reg-names = csr-reg, div-reg;
+ csr-offset = 0x0;
+ csr-mask = 0x1;
+ enable-offset = 0x8;
+ enable-mask = 0x1;
+ divider-offset = 0x164;
+ divider-width = 0x5;
+ divider-shift = 0x0;
+ clock-output-names = ahbclk;
+ };
+
+ sdioclk: sdioclk@1f2ac000 {
+ compatible = apm,xgene-device-clock;
+ #clock-cells = 1;
+ clocks = socplldiv2 0;
+ reg = 0x0 0x1f2ac000 0x0 0x1000
+ 0x0 0x1700 0x0 0x2000;
+ reg-names = csr-reg, div-reg;
+ csr-offset = 0x0;
+ csr-mask = 0x2;
+ enable-offset = 0x8;
+ enable-mask = 0x2;
+ divider-offset = 0x178;
+ divider-width = 0x8;
+ divider-shift = 0x0;
+ clock-output-names = sdioclk;
+ };
+
qmlclk: qmlclk {
compatible = apm,xgene-device-clock;
#clock-cells = 1;
@@ -533,6 +567,15 @@
interrupts = 0x0 0x4f 0x4;
};
+ mmc0: mmc@1c00 {
+ compatible = arasan,sdhci-4.9a;
+ reg = 0x0 0x1c00 0x0 0x100;
+ interrupts = 0x0 0x49 0x4;
+ dma-coherent;
+ clock-names = clk_xin, clk_ahb;
+ clocks = sdioclk 0, ahbclk 0;
+ };
+
phy1: phy@1f21a000 {
compatible = apm,xgene-phy;
reg = 0x0 0x1f21a000 0x0 0x100;
--
1.8.2.1
Can you review this ?
Sorry to bother on this again . Can you review it ?
--
Thanks,
with regards,
Suman Tripathi
--
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with regards,
Suman Tripathi
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Re: [PATCH RESEND v7 2/2] mmc: host: sdhci: Add support to disable SDR104/SDR50/DDR50 based on capability register 0.
Hi Ulf, Dong On Mon, Jun 8, 2015 at 2:08 PM, Ulf Hansson ulf.hans...@linaro.org wrote: On 8 June 2015 at 10:37, Ulf Hansson ulf.hans...@linaro.org wrote: [...] Can you test this patch on imx SoC ? (Your email have some format issue.) Yeah missed to sent in plain text mode. I have tested this patch and it does not break imx SoC. You can add my tag. Tested-by: Dong Aisheng aisheng.d...@freescale.com Thanks Dong !! However, it looks to me SDHCI_CAN_VDD_180 is only indicating the host VDD capabiliies, not IO voltage capability. I think Dong is correct. I don't think SDHCI_CAN_VDD_180 is not /s /is not /is related to UHS modes at all. At least the name of the field (SDHCI_CAN_VDD_180) indicates it's about VDD/VCC, the core power and not the IO voltage. Are you sure on this ?? If SDHCI host VDD is 1.8V then the cards are also capable to operate at 1.8V ? Didn't understand what you mean by IO voltage capability SD3.0 cards require 1.8v IO voltage support. So should this bit affect SD3.0 support? The preset value resgister says that SDR modes requires 1.8V and we disable the modes based on capability or quirk. It requires 1.8V *IO voltage*, not VDD/VCC. I agree on this now . I will post a version where this quirk will be added for arasan 4.9a that doesn't support 1.8v voltage signalling. [...] Kind regards Uffe -- Thanks, with regards, Suman Tripathi ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH RESEND v7 2/2] mmc: host: sdhci: Add support to disable SDR104/SDR50/DDR50 based on capability register 0.
On Fri, Jun 5, 2015 at 8:23 PM, Dong Aisheng b29...@freescale.com wrote: On Mon, Jun 01, 2015 at 01:38:47PM +0530, Suman Tripathi wrote: Hi Aisheng, On Wed, May 27, 2015 at 7:46 PM, Suman Tripathi [1]stripa...@apm.com wrote: On Tue, May 26, 2015 at 6:06 PM, Ulf Hansson [2]ulf.hans...@linaro.org wrote: On 21 May 2015 at 10:43, Suman Tripathi [3]stripa...@apm.com wrote: The sdhci framework disables SDR104/SDR50/DDR50 based on only quirk. This patch adds the support to disable SDR104/SDR50/DDR50 based on reading the capability register 0. Signed-off-by: Suman Tripathi [4]stripa...@apm.com --- --- drivers/mmc/host/sdhci.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 58c1770..a3d9b8a 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -3118,7 +3118,8 @@ int sdhci_add_host(struct sdhci_host *host) } } - if (host-quirks2 SDHCI_QUIRK2_NO_1_8_V) + if (host-quirks2 SDHCI_QUIRK2_NO_1_8_V || + !(caps[0] SDHCI_CAN_VDD_180)) caps[1] = ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50); -- 1.8.2.1 I have no problem with this patch, except that it would be nice to get a few tested by to make sure it doesn't break UHS support for some SoCs. Kind regards Uffe Can anyone test this in some other SoC ? Appreciate your help .. Can you test this patch on imx SoC ? (Your email have some format issue.) Yeah missed to sent in plain text mode. I have tested this patch and it does not break imx SoC. You can add my tag. Tested-by: Dong Aisheng aisheng.d...@freescale.com Thanks Dong !! However, it looks to me SDHCI_CAN_VDD_180 is only indicating the host VDD capabiliies, not IO voltage capability. Are you sure on this ?? If SDHCI host VDD is 1.8V then the cards are also capable to operate at 1.8V ? Didn't understand what you mean by IO voltage capability SD3.0 cards require 1.8v IO voltage support. So should this bit affect SD3.0 support? The preset value resgister says that SDR modes requires 1.8V and we disable the modes based on capability or quirk. e.g. some hosts can only work at VDD_330 (most VDD of SD slot on IMX boards is using external regulator and is fixed to 3.3v), but it can support 1.8v IO voltage, so it can support SD3.0 cards as well. Same for us but somehow 1.8v is broken in our version. Yeah so those host can still use 1.8V by not setting the quirk or not setting the capability register. Ulf, Can you help confirm it? Regards Dong Aisheng -- Thanks, with regards, Suman Tripathi -- Thanks, with regards, Suman Tripathi References Visible links 1. mailto:stripa...@apm.com 2. mailto:ulf.hans...@linaro.org 3. mailto:stripa...@apm.com 4. mailto:stripa...@apm.com perl: warning: Setting locale failed. perl: warning: Please check that your locale settings: LANGUAGE = (unset), LC_ALL = (unset), LC_TIME = zh_CN.UTF-8, LC_MONETARY = zh_CN.UTF-8, LC_ADDRESS = zh_CN.UTF-8, LC_TELEPHONE = zh_CN.UTF-8, LC_NAME = zh_CN.UTF-8, LC_MEASUREMENT = zh_CN.UTF-8, LC_IDENTIFICATION = zh_CN.UTF-8, LC_NUMERIC = zh_CN.UTF-8, LC_PAPER = zh_CN.UTF-8, LANG = en_US.UTF-8 are supported and installed on your system. perl: warning: Falling back to the standard locale (C). -- Thanks, with regards, Suman Tripathi ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH RESEND v7 2/2] mmc: host: sdhci: Add support to disable SDR104/SDR50/DDR50 based on capability register 0.
Hi Aisheng, On Wed, May 27, 2015 at 7:46 PM, Suman Tripathi stripa...@apm.com wrote: On Tue, May 26, 2015 at 6:06 PM, Ulf Hansson ulf.hans...@linaro.org wrote: On 21 May 2015 at 10:43, Suman Tripathi stripa...@apm.com wrote: The sdhci framework disables SDR104/SDR50/DDR50 based on only quirk. This patch adds the support to disable SDR104/SDR50/DDR50 based on reading the capability register 0. Signed-off-by: Suman Tripathi stripa...@apm.com --- --- drivers/mmc/host/sdhci.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 58c1770..a3d9b8a 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -3118,7 +3118,8 @@ int sdhci_add_host(struct sdhci_host *host) } } - if (host-quirks2 SDHCI_QUIRK2_NO_1_8_V) + if (host-quirks2 SDHCI_QUIRK2_NO_1_8_V || + !(caps[0] SDHCI_CAN_VDD_180)) caps[1] = ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50); -- 1.8.2.1 I have no problem with this patch, except that it would be nice to get a few tested by to make sure it doesn't break UHS support for some SoCs. Kind regards Uffe Can anyone test this in some other SoC ? Appreciate your help .. Can you test this patch on imx SoC ? -- Thanks, with regards, Suman Tripathi -- Thanks, with regards, Suman Tripathi ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH RESEND v7 2/2] mmc: host: sdhci: Add support to disable SDR104/SDR50/DDR50 based on capability register 0.
On Tue, May 26, 2015 at 6:06 PM, Ulf Hansson ulf.hans...@linaro.org wrote: On 21 May 2015 at 10:43, Suman Tripathi stripa...@apm.com wrote: The sdhci framework disables SDR104/SDR50/DDR50 based on only quirk. This patch adds the support to disable SDR104/SDR50/DDR50 based on reading the capability register 0. Signed-off-by: Suman Tripathi stripa...@apm.com --- --- drivers/mmc/host/sdhci.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 58c1770..a3d9b8a 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -3118,7 +3118,8 @@ int sdhci_add_host(struct sdhci_host *host) } } - if (host-quirks2 SDHCI_QUIRK2_NO_1_8_V) + if (host-quirks2 SDHCI_QUIRK2_NO_1_8_V || + !(caps[0] SDHCI_CAN_VDD_180)) caps[1] = ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50); -- 1.8.2.1 I have no problem with this patch, except that it would be nice to get a few tested by to make sure it doesn't break UHS support for some SoCs. Kind regards Uffe Can anyone test this in some other SoC ? Appreciate your help .. -- Thanks, with regards, Suman Tripathi ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH RESEND v7 2/2] mmc: host: sdhci: Add support to disable SDR104/SDR50/DDR50 based on capability register 0.
On Thu, May 21, 2015 at 2:13 PM, Suman Tripathi stripa...@apm.com wrote: The sdhci framework disables SDR104/SDR50/DDR50 based on only quirk. This patch adds the support to disable SDR104/SDR50/DDR50 based on reading the capability register 0. Signed-off-by: Suman Tripathi stripa...@apm.com --- --- drivers/mmc/host/sdhci.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 58c1770..a3d9b8a 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -3118,7 +3118,8 @@ int sdhci_add_host(struct sdhci_host *host) } } - if (host-quirks2 SDHCI_QUIRK2_NO_1_8_V) + if (host-quirks2 SDHCI_QUIRK2_NO_1_8_V || + !(caps[0] SDHCI_CAN_VDD_180)) caps[1] = ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50); -- 1.8.2.1 Any comments on this patch ? -- Thanks, with regards, Suman Tripathi ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH RESEND v7 1/2] arm64: dts: Add the arasan mmc nodes in apm-storm.dtsi
Hi ,
On Thu, May 21, 2015 at 2:13 PM, Suman Tripathi stripa...@apm.com wrote:
This patch adds the arasan mmc nodes to reuse the of-arasan
driver for APM X-Gene SoC.
Signed-off-by: Suman Tripathi stripa...@apm.com
---
---
arch/arm64/boot/dts/apm/apm-mustang.dts | 4 +++
arch/arm64/boot/dts/apm/apm-storm.dtsi | 43
+
2 files changed, 47 insertions(+)
diff --git a/arch/arm64/boot/dts/apm/apm-mustang.dts
b/arch/arm64/boot/dts/apm/apm-mustang.dts
index 83578e7..7a3ea72 100644
--- a/arch/arm64/boot/dts/apm/apm-mustang.dts
+++ b/arch/arm64/boot/dts/apm/apm-mustang.dts
@@ -52,3 +52,7 @@
xgenet {
status = ok;
};
+
+mmc0 {
+ status = ok;
+};
diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi
b/arch/arm64/boot/dts/apm/apm-storm.dtsi
index c8d3e0e..8e03ecd 100644
--- a/arch/arm64/boot/dts/apm/apm-storm.dtsi
+++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi
@@ -145,6 +145,40 @@
clock-output-names = socplldiv2;
};
+ ahbclk: ahbclk@1f2ac000 {
+ compatible = apm,xgene-device-clock;
+ #clock-cells = 1;
+ clocks = socplldiv2 0;
+ reg = 0x0 0x1f2ac000 0x0 0x1000
+ 0x0 0x1700 0x0 0x2000;
+ reg-names = csr-reg, div-reg;
+ csr-offset = 0x0;
+ csr-mask = 0x1;
+ enable-offset = 0x8;
+ enable-mask = 0x1;
+ divider-offset = 0x164;
+ divider-width = 0x5;
+ divider-shift = 0x0;
+ clock-output-names = ahbclk;
+ };
+
+ sdioclk: sdioclk@1f2ac000 {
+ compatible = apm,xgene-device-clock;
+ #clock-cells = 1;
+ clocks = socplldiv2 0;
+ reg = 0x0 0x1f2ac000 0x0 0x1000
+ 0x0 0x1700 0x0 0x2000;
+ reg-names = csr-reg, div-reg;
+ csr-offset = 0x0;
+ csr-mask = 0x2;
+ enable-offset = 0x8;
+ enable-mask = 0x2;
+ divider-offset = 0x178;
+ divider-width = 0x8;
+ divider-shift = 0x0;
+ clock-output-names = sdioclk;
+ };
+
qmlclk: qmlclk {
compatible = apm,xgene-device-clock;
#clock-cells = 1;
@@ -533,6 +567,15 @@
interrupts = 0x0 0x4f 0x4;
};
+ mmc0: mmc@1c00 {
+ compatible = arasan,sdhci-4.9a;
+ reg = 0x0 0x1c00 0x0 0x100;
+ interrupts = 0x0 0x49 0x4;
+ dma-coherent;
+ clock-names = clk_xin, clk_ahb;
+ clocks = sdioclk 0, ahbclk 0;
+ };
+
phy1: phy@1f21a000 {
compatible = apm,xgene-phy;
reg = 0x0 0x1f21a000 0x0 0x100;
--
1.8.2.1
Any comments on this patch ?? I changed the dts node name as per EPAR and
Arnd comments.
--
Thanks,
with regards,
Suman Tripathi
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[PATCH RESEND v7 2/2] mmc: host: sdhci: Add support to disable SDR104/SDR50/DDR50 based on capability register 0.
The sdhci framework disables SDR104/SDR50/DDR50 based on only quirk. This patch adds the support to disable SDR104/SDR50/DDR50 based on reading the capability register 0. Signed-off-by: Suman Tripathi stripa...@apm.com --- --- drivers/mmc/host/sdhci.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 58c1770..a3d9b8a 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -3118,7 +3118,8 @@ int sdhci_add_host(struct sdhci_host *host) } } - if (host-quirks2 SDHCI_QUIRK2_NO_1_8_V) + if (host-quirks2 SDHCI_QUIRK2_NO_1_8_V || + !(caps[0] SDHCI_CAN_VDD_180)) caps[1] = ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50); -- 1.8.2.1 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH RESEND v7 1/2] arm64: dts: Add the arasan mmc nodes in apm-storm.dtsi
This patch adds the arasan mmc nodes to reuse the of-arasan
driver for APM X-Gene SoC.
Signed-off-by: Suman Tripathi stripa...@apm.com
---
---
arch/arm64/boot/dts/apm/apm-mustang.dts | 4 +++
arch/arm64/boot/dts/apm/apm-storm.dtsi | 43 +
2 files changed, 47 insertions(+)
diff --git a/arch/arm64/boot/dts/apm/apm-mustang.dts
b/arch/arm64/boot/dts/apm/apm-mustang.dts
index 83578e7..7a3ea72 100644
--- a/arch/arm64/boot/dts/apm/apm-mustang.dts
+++ b/arch/arm64/boot/dts/apm/apm-mustang.dts
@@ -52,3 +52,7 @@
xgenet {
status = ok;
};
+
+mmc0 {
+ status = ok;
+};
diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi
b/arch/arm64/boot/dts/apm/apm-storm.dtsi
index c8d3e0e..8e03ecd 100644
--- a/arch/arm64/boot/dts/apm/apm-storm.dtsi
+++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi
@@ -145,6 +145,40 @@
clock-output-names = socplldiv2;
};
+ ahbclk: ahbclk@1f2ac000 {
+ compatible = apm,xgene-device-clock;
+ #clock-cells = 1;
+ clocks = socplldiv2 0;
+ reg = 0x0 0x1f2ac000 0x0 0x1000
+ 0x0 0x1700 0x0 0x2000;
+ reg-names = csr-reg, div-reg;
+ csr-offset = 0x0;
+ csr-mask = 0x1;
+ enable-offset = 0x8;
+ enable-mask = 0x1;
+ divider-offset = 0x164;
+ divider-width = 0x5;
+ divider-shift = 0x0;
+ clock-output-names = ahbclk;
+ };
+
+ sdioclk: sdioclk@1f2ac000 {
+ compatible = apm,xgene-device-clock;
+ #clock-cells = 1;
+ clocks = socplldiv2 0;
+ reg = 0x0 0x1f2ac000 0x0 0x1000
+ 0x0 0x1700 0x0 0x2000;
+ reg-names = csr-reg, div-reg;
+ csr-offset = 0x0;
+ csr-mask = 0x2;
+ enable-offset = 0x8;
+ enable-mask = 0x2;
+ divider-offset = 0x178;
+ divider-width = 0x8;
+ divider-shift = 0x0;
+ clock-output-names = sdioclk;
+ };
+
qmlclk: qmlclk {
compatible = apm,xgene-device-clock;
#clock-cells = 1;
@@ -533,6 +567,15 @@
interrupts = 0x0 0x4f 0x4;
};
+ mmc0: mmc@1c00 {
+ compatible = arasan,sdhci-4.9a;
+ reg = 0x0 0x1c00 0x0 0x100;
+ interrupts = 0x0 0x49 0x4;
+ dma-coherent;
+ clock-names = clk_xin, clk_ahb;
+ clocks = sdioclk 0, ahbclk 0;
+ };
+
phy1: phy@1f21a000 {
compatible = apm,xgene-phy;
reg = 0x0 0x1f21a000 0x0 0x100;
--
1.8.2.1
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[PATCH RESEND v7 0/2] Add SDHCI support for APM X-Gene SoC using ARASAN SDHCI controller.
This patch adds the SDHCI support for APM X-Gene SoC using ARASAN SDHCI controller. v1 change: * Use the CONFIG_ARM64_DMA_HAS_IOMMU for dma-mapping. v2 change: * Drop the IOMMU support and switching to PIO mode for arasan. controller integrated inside APM X-Gene SoC. v3 change: * Change the sdhci-of-arasan.c to support arasan4.9a. * Add quirks for arasan4.9a. v4 change: * Cleanup the Documentation and dts. v5 change: * Rebase the dts files. * Drop patch 2 and 3 as it is applied. v6 change: * Clean the unrequired properties from dts. * Rename sdhc to sdhci. * support to disable timming using capability register read. v7 change: * Rename sdhci nodes to mmc. Signed-off-by: Suman Tripathi stripa...@apm.com --- Suman Tripathi (2): arm64: dts: Add the arasan mmc nodes in apm-storm.dtsi mmc: host: sdhci: Add support to disable SDR104/SDR50/DDR50 based on capability register 0. arch/arm64/boot/dts/apm/apm-mustang.dts | 4 +++ arch/arm64/boot/dts/apm/apm-storm.dtsi | 43 + drivers/mmc/host/sdhci.c| 3 ++- 3 files changed, 49 insertions(+), 1 deletion(-) -- 1.8.2.1 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH v7 1/2] arm64: dts: Add the arasan mmc nodes in apm-storm.dtsi
Hi Arnd,
On Wed, May 13, 2015 at 5:21 PM, Suman Tripathi stripa...@apm.com wrote:
This patch adds the arasan mmc nodes to reuse the of-arasan
driver for APM X-Gene SoC.
Signed-off-by: Suman Tripathi stripa...@apm.com
---
---
arch/arm64/boot/dts/apm/apm-mustang.dts | 4 +++
arch/arm64/boot/dts/apm/apm-storm.dtsi | 43
+
2 files changed, 47 insertions(+)
diff --git a/arch/arm64/boot/dts/apm/apm-mustang.dts
b/arch/arm64/boot/dts/apm/apm-mustang.dts
index 83578e7..7a3ea72 100644
--- a/arch/arm64/boot/dts/apm/apm-mustang.dts
+++ b/arch/arm64/boot/dts/apm/apm-mustang.dts
@@ -52,3 +52,7 @@
xgenet {
status = ok;
};
+
+mmc0 {
+ status = ok;
+};
diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi
b/arch/arm64/boot/dts/apm/apm-storm.dtsi
index c8d3e0e..8e03ecd 100644
--- a/arch/arm64/boot/dts/apm/apm-storm.dtsi
+++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi
@@ -145,6 +145,40 @@
clock-output-names = socplldiv2;
};
+ ahbclk: ahbclk@1f2ac000 {
+ compatible = apm,xgene-device-clock;
+ #clock-cells = 1;
+ clocks = socplldiv2 0;
+ reg = 0x0 0x1f2ac000 0x0 0x1000
+ 0x0 0x1700 0x0 0x2000;
+ reg-names = csr-reg, div-reg;
+ csr-offset = 0x0;
+ csr-mask = 0x1;
+ enable-offset = 0x8;
+ enable-mask = 0x1;
+ divider-offset = 0x164;
+ divider-width = 0x5;
+ divider-shift = 0x0;
+ clock-output-names = ahbclk;
+ };
+
+ sdioclk: sdioclk@1f2ac000 {
+ compatible = apm,xgene-device-clock;
+ #clock-cells = 1;
+ clocks = socplldiv2 0;
+ reg = 0x0 0x1f2ac000 0x0 0x1000
+ 0x0 0x1700 0x0 0x2000;
+ reg-names = csr-reg, div-reg;
+ csr-offset = 0x0;
+ csr-mask = 0x2;
+ enable-offset = 0x8;
+ enable-mask = 0x2;
+ divider-offset = 0x178;
+ divider-width = 0x8;
+ divider-shift = 0x0;
+ clock-output-names = sdioclk;
+ };
+
qmlclk: qmlclk {
compatible = apm,xgene-device-clock;
#clock-cells = 1;
@@ -533,6 +567,15 @@
interrupts = 0x0 0x4f 0x4;
};
+ mmc0: mmc@1c00 {
+ compatible = arasan,sdhci-4.9a;
+ reg = 0x0 0x1c00 0x0 0x100;
+ interrupts = 0x0 0x49 0x4;
+ dma-coherent;
+ clock-names = clk_xin, clk_ahb;
+ clocks = sdioclk 0, ahbclk 0;
+ };
+
phy1: phy@1f21a000 {
compatible = apm,xgene-phy;
reg = 0x0 0x1f21a000 0x0 0x100;
--
1.8.2.1
Can you review this ?
--
Thanks,
with regards,
Suman Tripathi
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Re: [PATCH v7 2/2] mmc: host: sdhci: Add support to disable SDR104/SDR50/DDR50 based on capability register 0.
On Wed, May 13, 2015 at 5:21 PM, Suman Tripathi stripa...@apm.com wrote: The sdhci framework disables SDR104/SDR50/DDR50 based on only quirk. This patch adds the support to disable SDR104/SDR50/DDR50 based on reading the capability register 0. Signed-off-by: Suman Tripathi stripa...@apm.com --- --- drivers/mmc/host/sdhci.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 58c1770..a3d9b8a 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -3118,7 +3118,8 @@ int sdhci_add_host(struct sdhci_host *host) } } - if (host-quirks2 SDHCI_QUIRK2_NO_1_8_V) + if (host-quirks2 SDHCI_QUIRK2_NO_1_8_V || + !(caps[0] SDHCI_CAN_VDD_180)) caps[1] = ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50); -- 1.8.2.1 I didn't get any comments on this patch . Can anyone review it (Michal , Ulf , Arnd etc ...)? -- Thanks, with regards, Suman Tripathi ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v7 2/2] mmc: host: sdhci: Add support to disable SDR104/SDR50/DDR50 based on capability register 0.
The sdhci framework disables SDR104/SDR50/DDR50 based on only quirk. This patch adds the support to disable SDR104/SDR50/DDR50 based on reading the capability register 0. Signed-off-by: Suman Tripathi stripa...@apm.com --- --- drivers/mmc/host/sdhci.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 58c1770..a3d9b8a 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -3118,7 +3118,8 @@ int sdhci_add_host(struct sdhci_host *host) } } - if (host-quirks2 SDHCI_QUIRK2_NO_1_8_V) + if (host-quirks2 SDHCI_QUIRK2_NO_1_8_V || + !(caps[0] SDHCI_CAN_VDD_180)) caps[1] = ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50); -- 1.8.2.1 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v7 0/2] Add SDHCI support for APM X-Gene SoC using ARASAN SDHCI controller.
This patch adds the SDHCI support for APM X-Gene SoC using ARASAN SDHCI controller. v1 change: * Use the CONFIG_ARM64_DMA_HAS_IOMMU for dma-mapping. v2 change: * Drop the IOMMU support and switching to PIO mode for arasan. controller integrated inside APM X-Gene SoC. v3 change: * Change the sdhci-of-arasan.c to support arasan4.9a. * Add quirks for arasan4.9a. v4 change: * Cleanup the Documentation and dts. v5 change: * Rebase the dts files. * Drop patch 2 and 3 as it is applied. v6 change: * Clean the unrequired properties from dts. * Rename sdhc to sdhci. * support to disable timming using capability register read. v7 change: * Rename sdhci nodes to mmc. Signed-off-by: Suman Tripathi stripa...@apm.com --- Suman Tripathi (2): arm64: dts: Add the arasan mmc nodes in apm-storm.dtsi mmc: host: sdhci: Add support to disable SDR104/SDR50/DDR50 based on capability register 0. arch/arm64/boot/dts/apm/apm-mustang.dts | 4 +++ arch/arm64/boot/dts/apm/apm-storm.dtsi | 43 + drivers/mmc/host/sdhci.c| 3 ++- 3 files changed, 49 insertions(+), 1 deletion(-) -- 1.8.2.1 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v7 1/2] arm64: dts: Add the arasan mmc nodes in apm-storm.dtsi
This patch adds the arasan mmc nodes to reuse the of-arasan
driver for APM X-Gene SoC.
Signed-off-by: Suman Tripathi stripa...@apm.com
---
---
arch/arm64/boot/dts/apm/apm-mustang.dts | 4 +++
arch/arm64/boot/dts/apm/apm-storm.dtsi | 43 +
2 files changed, 47 insertions(+)
diff --git a/arch/arm64/boot/dts/apm/apm-mustang.dts
b/arch/arm64/boot/dts/apm/apm-mustang.dts
index 83578e7..7a3ea72 100644
--- a/arch/arm64/boot/dts/apm/apm-mustang.dts
+++ b/arch/arm64/boot/dts/apm/apm-mustang.dts
@@ -52,3 +52,7 @@
xgenet {
status = ok;
};
+
+mmc0 {
+ status = ok;
+};
diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi
b/arch/arm64/boot/dts/apm/apm-storm.dtsi
index c8d3e0e..8e03ecd 100644
--- a/arch/arm64/boot/dts/apm/apm-storm.dtsi
+++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi
@@ -145,6 +145,40 @@
clock-output-names = socplldiv2;
};
+ ahbclk: ahbclk@1f2ac000 {
+ compatible = apm,xgene-device-clock;
+ #clock-cells = 1;
+ clocks = socplldiv2 0;
+ reg = 0x0 0x1f2ac000 0x0 0x1000
+ 0x0 0x1700 0x0 0x2000;
+ reg-names = csr-reg, div-reg;
+ csr-offset = 0x0;
+ csr-mask = 0x1;
+ enable-offset = 0x8;
+ enable-mask = 0x1;
+ divider-offset = 0x164;
+ divider-width = 0x5;
+ divider-shift = 0x0;
+ clock-output-names = ahbclk;
+ };
+
+ sdioclk: sdioclk@1f2ac000 {
+ compatible = apm,xgene-device-clock;
+ #clock-cells = 1;
+ clocks = socplldiv2 0;
+ reg = 0x0 0x1f2ac000 0x0 0x1000
+ 0x0 0x1700 0x0 0x2000;
+ reg-names = csr-reg, div-reg;
+ csr-offset = 0x0;
+ csr-mask = 0x2;
+ enable-offset = 0x8;
+ enable-mask = 0x2;
+ divider-offset = 0x178;
+ divider-width = 0x8;
+ divider-shift = 0x0;
+ clock-output-names = sdioclk;
+ };
+
qmlclk: qmlclk {
compatible = apm,xgene-device-clock;
#clock-cells = 1;
@@ -533,6 +567,15 @@
interrupts = 0x0 0x4f 0x4;
};
+ mmc0: mmc@1c00 {
+ compatible = arasan,sdhci-4.9a;
+ reg = 0x0 0x1c00 0x0 0x100;
+ interrupts = 0x0 0x49 0x4;
+ dma-coherent;
+ clock-names = clk_xin, clk_ahb;
+ clocks = sdioclk 0, ahbclk 0;
+ };
+
phy1: phy@1f21a000 {
compatible = apm,xgene-phy;
reg = 0x0 0x1f21a000 0x0 0x100;
--
1.8.2.1
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[PATCH RESEND v6 2/2] mmc: sdhci: Add support to disable SDR104/SDR50/DDR50 based on capability register 0.
The sdhci framework disables SDR104/SDR50/DDR50 based on only quirk. This patch adds the support to disable SDR104/SDR50/DDR50 based on reading the capability register 0. Signed-off-by: Suman Tripathi stripa...@apm.com --- drivers/mmc/host/sdhci.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index c80287a..e024c64 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -3199,7 +3199,8 @@ int sdhci_add_host(struct sdhci_host *host) } } - if (host-quirks2 SDHCI_QUIRK2_NO_1_8_V) + if (host-quirks2 SDHCI_QUIRK2_NO_1_8_V || + !(caps[0] SDHCI_CAN_VDD_180)) caps[1] = ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50); -- 1.8.2.1 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH RESEND v6 0/2] Add SDHCI support for APM X-Gene SoC using ARASAN SDHCI controller.
This patch adds the SDHCI support for APM X-Gene SoC using ARASAN SDHCI controller. v1 change: * Use the CONFIG_ARM64_DMA_HAS_IOMMU for dma-mapping. v2 change: * Drop the IOMMU support and switching to PIO mode for arasan. controller integrated inside APM X-Gene SoC. v3 change: * Change the sdhci-of-arasan.c to support arasan4.9a. * Add quirks for arasan4.9a. v4 change: * Cleanup the Documentation and dts. v5 change: * Rebase the dts files. * Drop patch 2 and 3 as it is applied. v6 change: * Clean the unrequired properties from dts. * Rename sdhc to sdhci. * support to disable timming using capability register read. Signed-off-by: Suman Tripathi stripa...@apm.com --- Suman Tripathi (2): arm64: dts: Add the arasan sdhci nodes in apm-storm.dtsi. mmc: sdhci: Add support to disable SDR104/SDR50/DDR50 based on capability register 0. arch/arm64/boot/dts/apm/apm-mustang.dts | 4 +++ arch/arm64/boot/dts/apm/apm-storm.dtsi | 43 + drivers/mmc/host/sdhci.c| 3 ++- 3 files changed, 49 insertions(+), 1 deletion(-) -- 1.8.2.1 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH RESEND v6 1/2] arm64: dts: Add the arasan sdhci nodes in apm-storm.dtsi
This patch adds the arasan sdhci nodes to reuse the of-arasan
driver for APM X-Gene SoC.
Signed-off-by: Suman Tripathi stripa...@apm.com
---
arch/arm64/boot/dts/apm/apm-mustang.dts | 4 +++
arch/arm64/boot/dts/apm/apm-storm.dtsi | 43 +
2 files changed, 47 insertions(+)
diff --git a/arch/arm64/boot/dts/apm/apm-mustang.dts
b/arch/arm64/boot/dts/apm/apm-mustang.dts
index 83578e7..7ccd517 100644
--- a/arch/arm64/boot/dts/apm/apm-mustang.dts
+++ b/arch/arm64/boot/dts/apm/apm-mustang.dts
@@ -52,3 +52,7 @@
xgenet {
status = ok;
};
+
+sdhci0 {
+ status = ok;
+};
diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi
b/arch/arm64/boot/dts/apm/apm-storm.dtsi
index c8d3e0e..b5d2698 100644
--- a/arch/arm64/boot/dts/apm/apm-storm.dtsi
+++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi
@@ -145,6 +145,40 @@
clock-output-names = socplldiv2;
};
+ ahbclk: ahbclk@1f2ac000 {
+ compatible = apm,xgene-device-clock;
+ #clock-cells = 1;
+ clocks = socplldiv2 0;
+ reg = 0x0 0x1f2ac000 0x0 0x1000
+ 0x0 0x1700 0x0 0x2000;
+ reg-names = csr-reg, div-reg;
+ csr-offset = 0x0;
+ csr-mask = 0x1;
+ enable-offset = 0x8;
+ enable-mask = 0x1;
+ divider-offset = 0x164;
+ divider-width = 0x5;
+ divider-shift = 0x0;
+ clock-output-names = ahbclk;
+ };
+
+ sdioclk: sdioclk@1f2ac000 {
+ compatible = apm,xgene-device-clock;
+ #clock-cells = 1;
+ clocks = socplldiv2 0;
+ reg = 0x0 0x1f2ac000 0x0 0x1000
+ 0x0 0x1700 0x0 0x2000;
+ reg-names = csr-reg, div-reg;
+ csr-offset = 0x0;
+ csr-mask = 0x2;
+ enable-offset = 0x8;
+ enable-mask = 0x2;
+ divider-offset = 0x178;
+ divider-width = 0x8;
+ divider-shift = 0x0;
+ clock-output-names = sdioclk;
+ };
+
qmlclk: qmlclk {
compatible = apm,xgene-device-clock;
#clock-cells = 1;
@@ -533,6 +567,15 @@
interrupts = 0x0 0x4f 0x4;
};
+ sdhci0: sdhci@1c00 {
+ compatible = arasan,sdhci-4.9a;
+ reg = 0x0 0x1c00 0x0 0x100;
+ interrupts = 0x0 0x49 0x4;
+ dma-coherent;
+ clock-names = clk_xin, clk_ahb;
+ clocks = sdioclk 0, ahbclk 0;
+ };
+
phy1: phy@1f21a000 {
compatible = apm,xgene-phy;
reg = 0x0 0x1f21a000 0x0 0x100;
--
1.8.2.1
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Re: [PATCH RESEND v6 1/2] arm64: dts: Add the arasan sdhci nodes in apm-storm.dtsi
Hi ,
On Mon, May 11, 2015 at 2:08 PM, Suman Tripathi stripa...@apm.com wrote:
This patch adds the arasan sdhci nodes to reuse the of-arasan
driver for APM X-Gene SoC.
Signed-off-by: Suman Tripathi stripa...@apm.com
---
arch/arm64/boot/dts/apm/apm-mustang.dts | 4 +++
arch/arm64/boot/dts/apm/apm-storm.dtsi | 43
+
2 files changed, 47 insertions(+)
diff --git a/arch/arm64/boot/dts/apm/apm-mustang.dts
b/arch/arm64/boot/dts/apm/apm-mustang.dts
index 83578e7..7ccd517 100644
--- a/arch/arm64/boot/dts/apm/apm-mustang.dts
+++ b/arch/arm64/boot/dts/apm/apm-mustang.dts
@@ -52,3 +52,7 @@
xgenet {
status = ok;
};
+
+sdhci0 {
+ status = ok;
+};
diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi
b/arch/arm64/boot/dts/apm/apm-storm.dtsi
index c8d3e0e..b5d2698 100644
--- a/arch/arm64/boot/dts/apm/apm-storm.dtsi
+++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi
@@ -145,6 +145,40 @@
clock-output-names = socplldiv2;
};
+ ahbclk: ahbclk@1f2ac000 {
+ compatible = apm,xgene-device-clock;
+ #clock-cells = 1;
+ clocks = socplldiv2 0;
+ reg = 0x0 0x1f2ac000 0x0 0x1000
+ 0x0 0x1700 0x0 0x2000;
+ reg-names = csr-reg, div-reg;
+ csr-offset = 0x0;
+ csr-mask = 0x1;
+ enable-offset = 0x8;
+ enable-mask = 0x1;
+ divider-offset = 0x164;
+ divider-width = 0x5;
+ divider-shift = 0x0;
+ clock-output-names = ahbclk;
+ };
+
+ sdioclk: sdioclk@1f2ac000 {
+ compatible = apm,xgene-device-clock;
+ #clock-cells = 1;
+ clocks = socplldiv2 0;
+ reg = 0x0 0x1f2ac000 0x0 0x1000
+ 0x0 0x1700 0x0 0x2000;
+ reg-names = csr-reg, div-reg;
+ csr-offset = 0x0;
+ csr-mask = 0x2;
+ enable-offset = 0x8;
+ enable-mask = 0x2;
+ divider-offset = 0x178;
+ divider-width = 0x8;
+ divider-shift = 0x0;
+ clock-output-names = sdioclk;
+ };
+
qmlclk: qmlclk {
compatible = apm,xgene-device-clock;
#clock-cells = 1;
@@ -533,6 +567,15 @@
interrupts = 0x0 0x4f 0x4;
};
+ sdhci0: sdhci@1c00 {
+ compatible = arasan,sdhci-4.9a;
+ reg = 0x0 0x1c00 0x0 0x100;
+ interrupts = 0x0 0x49 0x4;
+ dma-coherent;
+ clock-names = clk_xin, clk_ahb;
+ clocks = sdioclk 0, ahbclk 0;
+ };
+
phy1: phy@1f21a000 {
compatible = apm,xgene-phy;
reg = 0x0 0x1f21a000 0x0 0x100;
--
1.8.2.1
Can anyone from dt community review this patch ? I have changed the dts node
names from sdhc to sdhci as per Arnd, Michael comments .
--
Thanks,
with regards,
Suman Tripathi
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Re: [PATCH v6 1/2] arm64: dts: Add the arasan sdhci nodes in apm-storm.dtsi.
On Wed, May 6, 2015 at 7:12 PM, Suman Tripathi stripa...@apm.com wrote:
This patch adds the arasan sdhci nodes to reuse the of-arasan
driver for APM X-Gene SoC.
Signed-off-by: Suman Tripathi stripa...@apm.com
---
arch/arm64/boot/dts/apm/apm-mustang.dts | 4 +++
arch/arm64/boot/dts/apm/apm-storm.dtsi | 43
+
2 files changed, 47 insertions(+)
diff --git a/arch/arm64/boot/dts/apm/apm-mustang.dts
b/arch/arm64/boot/dts/apm/apm-mustang.dts
index 83578e7..7ccd517 100644
--- a/arch/arm64/boot/dts/apm/apm-mustang.dts
+++ b/arch/arm64/boot/dts/apm/apm-mustang.dts
@@ -52,3 +52,7 @@
xgenet {
status = ok;
};
+
+sdhci0 {
+ status = ok;
+};
diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi
b/arch/arm64/boot/dts/apm/apm-storm.dtsi
index c8d3e0e..b5d2698 100644
--- a/arch/arm64/boot/dts/apm/apm-storm.dtsi
+++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi
@@ -145,6 +145,40 @@
clock-output-names = socplldiv2;
};
+ ahbclk: ahbclk@1f2ac000 {
+ compatible = apm,xgene-device-clock;
+ #clock-cells = 1;
+ clocks = socplldiv2 0;
+ reg = 0x0 0x1f2ac000 0x0 0x1000
+ 0x0 0x1700 0x0 0x2000;
+ reg-names = csr-reg, div-reg;
+ csr-offset = 0x0;
+ csr-mask = 0x1;
+ enable-offset = 0x8;
+ enable-mask = 0x1;
+ divider-offset = 0x164;
+ divider-width = 0x5;
+ divider-shift = 0x0;
+ clock-output-names = ahbclk;
+ };
+
+ sdioclk: sdioclk@1f2ac000 {
+ compatible = apm,xgene-device-clock;
+ #clock-cells = 1;
+ clocks = socplldiv2 0;
+ reg = 0x0 0x1f2ac000 0x0 0x1000
+ 0x0 0x1700 0x0 0x2000;
+ reg-names = csr-reg, div-reg;
+ csr-offset = 0x0;
+ csr-mask = 0x2;
+ enable-offset = 0x8;
+ enable-mask = 0x2;
+ divider-offset = 0x178;
+ divider-width = 0x8;
+ divider-shift = 0x0;
+ clock-output-names = sdioclk;
+ };
+
qmlclk: qmlclk {
compatible = apm,xgene-device-clock;
#clock-cells = 1;
@@ -533,6 +567,15 @@
interrupts = 0x0 0x4f 0x4;
};
+ sdhci0: sdhci@1c00 {
+ compatible = arasan,sdhci-4.9a;
+ reg = 0x0 0x1c00 0x0 0x100;
+ interrupts = 0x0 0x49 0x4;
+ dma-coherent;
+ clock-names = clk_xin, clk_ahb;
+ clocks = sdioclk 0, ahbclk 0;
+ };
+
phy1: phy@1f21a000 {
compatible = apm,xgene-phy;
reg = 0x0 0x1f21a000 0x0 0x100;
--
1.8.2.1
Any comments on this patch ??
--
Thanks,
with regards,
Suman Tripathi
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Re: [PATCH v6 2/2] mmc: sdhci: Add support to disable SDR104/SDR50/DDR50 based on capability register 0.
On Wed, May 6, 2015 at 7:12 PM, Suman Tripathi stripa...@apm.com wrote: The sdhci framework disables SDR104/SDR50/DDR50 based on only quirk. This patch adds the support to disable SDR104/SDR50/DDR50 based on reading the capability register 0. Signed-off-by: Suman Tripathi stripa...@apm.com --- drivers/mmc/host/sdhci.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index c80287a..e024c64 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -3199,7 +3199,8 @@ int sdhci_add_host(struct sdhci_host *host) } } - if (host-quirks2 SDHCI_QUIRK2_NO_1_8_V) + if (host-quirks2 SDHCI_QUIRK2_NO_1_8_V || + !(caps[0] SDHCI_CAN_VDD_180)) caps[1] = ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50); -- 1.8.2.1 Any comments on this patch ?? -- Thanks, with regards, Suman Tripathi ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH v5 1/1] arm64: dts: Add the arasan sdhc nodes in apm-storm.dtsi.
Hi Arnd,
On Wed, May 6, 2015 at 5:27 PM, Suman Tripathi stripa...@apm.com wrote:
On Wed, May 6, 2015 at 2:10 PM, Arnd Bergmann a...@arndb.de wrote:
On Wednesday 06 May 2015 09:45:15 Michal Simek wrote:
On 05/06/2015 09:31 AM, Arnd Bergmann wrote:
On Wednesday 06 May 2015 10:41:07 Suman Tripathi wrote:
@@ -533,6 +567,16 @@
interrupts = 0x0 0x4f 0x4;
};
+ sdhc0: sdhc@1c00 {
+ device_type = sdhc;
device_type generally should not be used (there are a few
exceptions).
Okay !!
While we're at it, please change sdhc@1c00 to mmc@1c00.
Even though Linux does not care, we try to use the standard device
names for consistency.
Do we have a list of these names somewhere?
Normally I do use ePARP - generic names recommendation but mmc or sdhci
are not listed there.
Both combination mmc@ or sdhci@ are used in the kernel.
On zynq and zynqmp we do use shdci@.
Ah, I thought ePAPR listed mmc already. Using sdhci is a little too
specific here, since a lot of mmc hosts are not sdhci compliant, and
sdhc is completely wrong, because that identifies a specific card
type, but a host that supports SDHC cards will generally also work
with SD (less than 4GB) or SDXC (more than 48GB) cards.
Agree on this . Will change it.
One more point as we are resuing the arasan driver, is it compulsory to
use the name used in binding info
for arasan ?? It is sdhci for arasan.
Arnd
--
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with regards,
Suman Tripathi
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with regards,
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Re: [PATCH v5 1/1] arm64: dts: Add the arasan sdhc nodes in apm-storm.dtsi.
On Wed, May 6, 2015 at 2:10 PM, Arnd Bergmann a...@arndb.de wrote:
On Wednesday 06 May 2015 09:45:15 Michal Simek wrote:
On 05/06/2015 09:31 AM, Arnd Bergmann wrote:
On Wednesday 06 May 2015 10:41:07 Suman Tripathi wrote:
@@ -533,6 +567,16 @@
interrupts = 0x0 0x4f 0x4;
};
+ sdhc0: sdhc@1c00 {
+ device_type = sdhc;
device_type generally should not be used (there are a few
exceptions).
Okay !!
While we're at it, please change sdhc@1c00 to mmc@1c00.
Even though Linux does not care, we try to use the standard device
names for consistency.
Do we have a list of these names somewhere?
Normally I do use ePARP - generic names recommendation but mmc or sdhci
are not listed there.
Both combination mmc@ or sdhci@ are used in the kernel.
On zynq and zynqmp we do use shdci@.
Ah, I thought ePAPR listed mmc already. Using sdhci is a little too
specific here, since a lot of mmc hosts are not sdhci compliant, and
sdhc is completely wrong, because that identifies a specific card
type, but a host that supports SDHC cards will generally also work
with SD (less than 4GB) or SDXC (more than 48GB) cards.
Agree on this . Will change it.
Arnd
--
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with regards,
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[PATCH v6 1/2] arm64: dts: Add the arasan sdhci nodes in apm-storm.dtsi.
This patch adds the arasan sdhci nodes to reuse the of-arasan
driver for APM X-Gene SoC.
Signed-off-by: Suman Tripathi stripa...@apm.com
---
arch/arm64/boot/dts/apm/apm-mustang.dts | 4 +++
arch/arm64/boot/dts/apm/apm-storm.dtsi | 43 +
2 files changed, 47 insertions(+)
diff --git a/arch/arm64/boot/dts/apm/apm-mustang.dts
b/arch/arm64/boot/dts/apm/apm-mustang.dts
index 83578e7..7ccd517 100644
--- a/arch/arm64/boot/dts/apm/apm-mustang.dts
+++ b/arch/arm64/boot/dts/apm/apm-mustang.dts
@@ -52,3 +52,7 @@
xgenet {
status = ok;
};
+
+sdhci0 {
+ status = ok;
+};
diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi
b/arch/arm64/boot/dts/apm/apm-storm.dtsi
index c8d3e0e..b5d2698 100644
--- a/arch/arm64/boot/dts/apm/apm-storm.dtsi
+++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi
@@ -145,6 +145,40 @@
clock-output-names = socplldiv2;
};
+ ahbclk: ahbclk@1f2ac000 {
+ compatible = apm,xgene-device-clock;
+ #clock-cells = 1;
+ clocks = socplldiv2 0;
+ reg = 0x0 0x1f2ac000 0x0 0x1000
+ 0x0 0x1700 0x0 0x2000;
+ reg-names = csr-reg, div-reg;
+ csr-offset = 0x0;
+ csr-mask = 0x1;
+ enable-offset = 0x8;
+ enable-mask = 0x1;
+ divider-offset = 0x164;
+ divider-width = 0x5;
+ divider-shift = 0x0;
+ clock-output-names = ahbclk;
+ };
+
+ sdioclk: sdioclk@1f2ac000 {
+ compatible = apm,xgene-device-clock;
+ #clock-cells = 1;
+ clocks = socplldiv2 0;
+ reg = 0x0 0x1f2ac000 0x0 0x1000
+ 0x0 0x1700 0x0 0x2000;
+ reg-names = csr-reg, div-reg;
+ csr-offset = 0x0;
+ csr-mask = 0x2;
+ enable-offset = 0x8;
+ enable-mask = 0x2;
+ divider-offset = 0x178;
+ divider-width = 0x8;
+ divider-shift = 0x0;
+ clock-output-names = sdioclk;
+ };
+
qmlclk: qmlclk {
compatible = apm,xgene-device-clock;
#clock-cells = 1;
@@ -533,6 +567,15 @@
interrupts = 0x0 0x4f 0x4;
};
+ sdhci0: sdhci@1c00 {
+ compatible = arasan,sdhci-4.9a;
+ reg = 0x0 0x1c00 0x0 0x100;
+ interrupts = 0x0 0x49 0x4;
+ dma-coherent;
+ clock-names = clk_xin, clk_ahb;
+ clocks = sdioclk 0, ahbclk 0;
+ };
+
phy1: phy@1f21a000 {
compatible = apm,xgene-phy;
reg = 0x0 0x1f21a000 0x0 0x100;
--
1.8.2.1
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[PATCH v6 2/2] mmc: sdhci: Add support to disable SDR104/SDR50/DDR50 based on capability register 0.
The sdhci framework disables SDR104/SDR50/DDR50 based on only quirk. This patch adds the support to disable SDR104/SDR50/DDR50 based on reading the capability register 0. Signed-off-by: Suman Tripathi stripa...@apm.com --- drivers/mmc/host/sdhci.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index c80287a..e024c64 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -3199,7 +3199,8 @@ int sdhci_add_host(struct sdhci_host *host) } } - if (host-quirks2 SDHCI_QUIRK2_NO_1_8_V) + if (host-quirks2 SDHCI_QUIRK2_NO_1_8_V || + !(caps[0] SDHCI_CAN_VDD_180)) caps[1] = ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50); -- 1.8.2.1 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v6 0/2] Add SDHCI support for APM X-Gene SoC using ARASAN SDHCI controller.
This patch adds the SDHCI support for APM X-Gene SoC using ARASAN SDHCI controller. v1 change: * Use the CONFIG_ARM64_DMA_HAS_IOMMU for dma-mapping. v2 change: * Drop the IOMMU support and switching to PIO mode for arasan. controller integrated inside APM X-Gene SoC. v3 change: * Change the sdhci-of-arasan.c to support arasan4.9a. * Add quirks for arasan4.9a. v4 change: * Cleanup the Documentation and dts. v5 change: * Rebase the dts files. * Drop patch 2 and 3 as it is applied. v6 change: * Clean the unrequired properties from dts. * Rename sdhc to sdhci. * support to disable timming using capability register read. Signed-off-by: Suman Tripathi stripa...@apm.com --- Suman Tripathi (2): arm64: dts: Add the arasan sdhci nodes in apm-storm.dtsi. mmc: sdhci: Add support to disable SDR104/SDR50/DDR50 based on capability register 0. arch/arm64/boot/dts/apm/apm-mustang.dts | 4 +++ arch/arm64/boot/dts/apm/apm-storm.dtsi | 43 + drivers/mmc/host/sdhci.c| 3 ++- 3 files changed, 49 insertions(+), 1 deletion(-) -- 1.8.2.1 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH v5 1/1] arm64: dts: Add the arasan sdhc nodes in apm-storm.dtsi.
On Wed, May 6, 2015 at 6:11 PM, Michal Simek michal.si...@xilinx.com
wrote:
On 05/06/2015 10:40 AM, Arnd Bergmann wrote:
On Wednesday 06 May 2015 09:45:15 Michal Simek wrote:
On 05/06/2015 09:31 AM, Arnd Bergmann wrote:
On Wednesday 06 May 2015 10:41:07 Suman Tripathi wrote:
@@ -533,6 +567,16 @@
interrupts = 0x0 0x4f 0x4;
};
+ sdhc0: sdhc@1c00 {
+ device_type = sdhc;
device_type generally should not be used (there are a few
exceptions).
Okay !!
While we're at it, please change sdhc@1c00 to mmc@1c00.
Even though Linux does not care, we try to use the standard device
names for consistency.
Do we have a list of these names somewhere?
Normally I do use ePARP - generic names recommendation but mmc or sdhci
are not listed there.
Both combination mmc@ or sdhci@ are used in the kernel.
On zynq and zynqmp we do use shdci@.
Ah, I thought ePAPR listed mmc already. Using sdhci is a little too
specific here, since a lot of mmc hosts are not sdhci compliant, and
sdhc is completely wrong, because that identifies a specific card
type, but a host that supports SDHC cards will generally also work
with SD (less than 4GB) or SDXC (more than 48GB) cards.
Yes sdhc is completely wrong.
But spec name in search engine's gives SDHC 3.0 as general.
Based on our datasheet(also version used on Zynq and ZynqMP) this IP is
compliant with SD HC 3.00, SDIO 3.0, SD MC 3.01 SD MCS 1.01, MMC 4.51.
Not sure about the version which they use.
Also not sure which spec the IP should have to be able to say that we
can use sdhci name. Do you have exact SPEC name?
I also think sdhci because the binding is sdhci written by Arasan. Anyway I
will change to sdhci.
Thanks,
Michal
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Re: [PATCH v5 1/1] arm64: dts: Add the arasan sdhc nodes in apm-storm.dtsi.
On Wed, May 6, 2015 at 1:11 AM, Rob Herring robherri...@gmail.com wrote:
On Tue, May 5, 2015 at 4:17 AM, Suman Tripathi stripa...@apm.com wrote:
This patch adds the arasan sdhc nodes to reuse the of-arasan
driver for APM X-Gene SoC.
Signed-off-by: Suman Tripathi stripa...@apm.com
---
arch/arm64/boot/dts/apm/apm-mustang.dts | 4 +++
arch/arm64/boot/dts/apm/apm-storm.dtsi | 44
+
2 files changed, 48 insertions(+)
[...]
@@ -533,6 +567,16 @@
interrupts = 0x0 0x4f 0x4;
};
+ sdhc0: sdhc@1c00 {
+ device_type = sdhc;
device_type generally should not be used (there are a few exceptions).
Okay !!
+ compatible = arasan,sdhci-4.9a;
If you ever have an integration or xgene specific problem, you need a
chip specific compatible.
No it;s a IP level problem. If it's a SoC level then probably we
cann't reuse the existing arasan version. If anything happens
in future we might need our own version.
Rob
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Re: [PATCH v4 0/3] Add SDHCI support for APM X-Gene SoC using ARASAN SDHCI controller.
On Tue, May 5, 2015 at 2:06 PM, Ulf Hansson ulf.hans...@linaro.org wrote: On 4 May 2015 at 15:39, Suman Tripathi stripa...@apm.com wrote: This patch adds the SDHCI support for APM X-Gene SoC using ARASAN SDHCI controller. v1 change: * Use the CONFIG_ARM64_DMA_HAS_IOMMU for dma-mapping. v2 change: * Drop the IOMMU support and switching to PIO mode for arasan. controller integrated inside APM X-Gene SoC. v3 change: * Change the sdhci-of-arasan.c to support arasan4.9a. * Add quirks for arasan4.9a. v4 change: * Cleanup the Documentation and dts. Signed-off-by: Suman Tripathi stripa...@apm.com --- Suman Tripathi (3): arm64: dts: Add the arasan sdhc nodes in apm-storm.dtsi. mmc: host: arasan: Add the support for sdhci-arasan4.9a in sdhci-of-arasan.c Documentation: mmc: Update Arasan SDHC documentation to support 4.9a version of Arasan SDHC controller. .../devicetree/bindings/mmc/arasan,sdhci.txt | 3 +- arch/arm64/boot/dts/apm-mustang.dts| 4 ++ arch/arm64/boot/dts/apm-storm.dtsi | 44 ++ drivers/mmc/host/sdhci-of-arasan.c | 7 4 files changed, 57 insertions(+), 1 deletion(-) Thanks! I have applied patch2 and patch3. Though, I decided to squash them into one patch and changed the commit message header a bit. I couldn't apply patch 1, so I guess that will be taken through arm soc? why it couldn't be applied?? I made it in top of git git://git.linaro.org/people/ulf.hansson/mmc.git Is this not correct ?? Kind regards Uffe -- Thanks, with regards, Suman Tripathi ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v5 0/1] Add SDHCI support for APM X-Gene SoC using ARASAN SDHCI controller.
This patch adds the SDHCI support for APM X-Gene SoC using ARASAN SDHCI controller. v1 change: * Use the CONFIG_ARM64_DMA_HAS_IOMMU for dma-mapping. v2 change: * Drop the IOMMU support and switching to PIO mode for arasan. controller integrated inside APM X-Gene SoC. v3 change: * Change the sdhci-of-arasan.c to support arasan4.9a. * Add quirks for arasan4.9a. v4 change: * Cleanup the Documentation and dts. v5 change: * Rebase the dts files. * Drop patch 2 and 3 as it is applied Signed-off-by: Suman Tripathi stripa...@apm.com --- Suman Tripathi (1): arm64: dts: Add the arasan sdhc nodes in apm-storm.dtsi. arch/arm64/boot/dts/apm/apm-mustang.dts | 4 +++ arch/arm64/boot/dts/apm/apm-storm.dtsi | 44 + 2 files changed, 48 insertions(+) -- 1.8.2.1 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v5 1/1] arm64: dts: Add the arasan sdhc nodes in apm-storm.dtsi.
This patch adds the arasan sdhc nodes to reuse the of-arasan
driver for APM X-Gene SoC.
Signed-off-by: Suman Tripathi stripa...@apm.com
---
arch/arm64/boot/dts/apm/apm-mustang.dts | 4 +++
arch/arm64/boot/dts/apm/apm-storm.dtsi | 44 +
2 files changed, 48 insertions(+)
diff --git a/arch/arm64/boot/dts/apm/apm-mustang.dts
b/arch/arm64/boot/dts/apm/apm-mustang.dts
index 83578e7..4cc5d07 100644
--- a/arch/arm64/boot/dts/apm/apm-mustang.dts
+++ b/arch/arm64/boot/dts/apm/apm-mustang.dts
@@ -52,3 +52,7 @@
xgenet {
status = ok;
};
+
+sdhc0 {
+ status = ok;
+};
diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi
b/arch/arm64/boot/dts/apm/apm-storm.dtsi
index c8d3e0e..240c793 100644
--- a/arch/arm64/boot/dts/apm/apm-storm.dtsi
+++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi
@@ -145,6 +145,40 @@
clock-output-names = socplldiv2;
};
+ ahbclk: ahbclk@1f2ac000 {
+ compatible = apm,xgene-device-clock;
+ #clock-cells = 1;
+ clocks = socplldiv2 0;
+ reg = 0x0 0x1f2ac000 0x0 0x1000
+ 0x0 0x1700 0x0 0x2000;
+ reg-names = csr-reg, div-reg;
+ csr-offset = 0x0;
+ csr-mask = 0x1;
+ enable-offset = 0x8;
+ enable-mask = 0x1;
+ divider-offset = 0x164;
+ divider-width = 0x5;
+ divider-shift = 0x0;
+ clock-output-names = ahbclk;
+ };
+
+ sdioclk: sdioclk@1f2ac000 {
+ compatible = apm,xgene-device-clock;
+ #clock-cells = 1;
+ clocks = socplldiv2 0;
+ reg = 0x0 0x1f2ac000 0x0 0x1000
+ 0x0 0x1700 0x0 0x2000;
+ reg-names = csr-reg, div-reg;
+ csr-offset = 0x0;
+ csr-mask = 0x2;
+ enable-offset = 0x8;
+ enable-mask = 0x2;
+ divider-offset = 0x178;
+ divider-width = 0x8;
+ divider-shift = 0x0;
+ clock-output-names = sdioclk;
+ };
+
qmlclk: qmlclk {
compatible = apm,xgene-device-clock;
#clock-cells = 1;
@@ -533,6 +567,16 @@
interrupts = 0x0 0x4f 0x4;
};
+ sdhc0: sdhc@1c00 {
+ device_type = sdhc;
+ compatible = arasan,sdhci-4.9a;
+ reg = 0x0 0x1c00 0x0 0x100;
+ interrupts = 0x0 0x49 0x4;
+ dma-coherent;
+ clock-names = clk_xin, clk_ahb;
+ clocks = sdioclk 0, ahbclk 0;
+ };
+
phy1: phy@1f21a000 {
compatible = apm,xgene-phy;
reg = 0x0 0x1f21a000 0x0 0x100;
--
1.8.2.1
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Re: [PATCH v3 3/3] Documentation: mmc: Update Arasan SDHC documentation to support 4.9a version of Arasan SDHC controller.
Hi,
On Mon, May 4, 2015 at 11:30 AM, Michal Simek michal.si...@xilinx.com wrote:
On 05/01/2015 06:54 AM, Suman Tripathi wrote:
This patch updates Arasan SDHC documentation to support
4.9a version of Arasan SDHC controller.
Signed-off-by: Suman Tripathi stripa...@apm.com
---
Documentation/devicetree/bindings/mmc/arasan,sdhci.txt | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
index 98ee2ab..f01d41a 100644
--- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
+++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
@@ -8,7 +8,8 @@ Device Tree Bindings for the Arasan SDHCI Controller
[3] Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
Required Properties:
- - compatible: Compatibility string. Must be 'arasan,sdhci-8.9a'
+ - compatible: Compatibility string. Must be 'arasan,sdhci-8.9a' or
+'arasan,sdhci-4.9a'
- reg: From mmc bindings: Register location and length.
- clocks: From clock bindings: Handles to clock inputs.
- clock-names: From clock bindings: Tuple including clk_xin and
clk_ahb
@@ -18,7 +19,7 @@ Required Properties:
Example:
sdhci@e010 {
- compatible = arasan,sdhci-8.9a;
+ compatible = arasan,sdhci-8.9a, arasan,sdhci-4.9a;
Is there any reason to change this example?
Thought that if dts is updated so why not update the binding too.
You probably want to have just one compatible string not both.
Okay will remove in next version.
Thanks,
Michal
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with regards,
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Re: [PATCH v3 1/3] arm64: dts: Add the arasan sdhc nodes in apm-storm.dtsi.
Hi,
On Mon, May 4, 2015 at 11:33 AM, Michal Simek michal.si...@xilinx.com wrote:
On 05/01/2015 06:54 AM, Suman Tripathi wrote:
This patch adds the arasan sdhc nodes to reuse the of-arasan
driver for APM X-Gene SoC.
Signed-off-by: Suman Tripathi stripa...@apm.com
---
arch/arm64/boot/dts/apm-mustang.dts | 4
arch/arm64/boot/dts/apm-storm.dtsi | 44
+
2 files changed, 48 insertions(+)
diff --git a/arch/arm64/boot/dts/apm-mustang.dts
b/arch/arm64/boot/dts/apm-mustang.dts
index 8eb6d94..d0e52a9 100644
--- a/arch/arm64/boot/dts/apm-mustang.dts
+++ b/arch/arm64/boot/dts/apm-mustang.dts
@@ -44,3 +44,7 @@
xgenet {
status = ok;
};
+
+sdhc0 {
+ status = ok;
+};
diff --git a/arch/arm64/boot/dts/apm-storm.dtsi
b/arch/arm64/boot/dts/apm-storm.dtsi
index 87d3205..d6c2216 100644
--- a/arch/arm64/boot/dts/apm-storm.dtsi
+++ b/arch/arm64/boot/dts/apm-storm.dtsi
@@ -144,6 +144,40 @@
clock-output-names = socplldiv2;
};
+ ahbclk: ahbclk@1f2ac000 {
+ compatible = apm,xgene-device-clock;
+ #clock-cells = 1;
+ clocks = socplldiv2 0;
+ reg = 0x0 0x1f2ac000 0x0 0x1000
+ 0x0 0x1700 0x0 0x2000;
+ reg-names = csr-reg, div-reg;
+ csr-offset = 0x0;
+ csr-mask = 0x1;
+ enable-offset = 0x8;
+ enable-mask = 0x1;
+ divider-offset = 0x164;
+ divider-width = 0x5;
+ divider-shift = 0x0;
+ clock-output-names = ahbclk;
+ };
+
+ sdioclk: sdioclk@1f2ac000 {
+ compatible = apm,xgene-device-clock;
+ #clock-cells = 1;
+ clocks = socplldiv2 0;
+ reg = 0x0 0x1f2ac000 0x0 0x1000
+ 0x0 0x1700 0x0 0x2000;
+ reg-names = csr-reg, div-reg;
+ csr-offset = 0x0;
+ csr-mask = 0x2;
+ enable-offset = 0x8;
+ enable-mask = 0x2;
+ divider-offset = 0x178;
+ divider-width = 0x8;
+ divider-shift = 0x0;
+ clock-output-names = sdioclk;
+ };
+
qmlclk: qmlclk {
compatible = apm,xgene-device-clock;
#clock-cells = 1;
@@ -503,6 +537,16 @@
interrupts = 0x0 0x4f 0x4;
};
+ sdhc0: sdhc@1c00 {
+ device_type = sdhc;
+ compatible = arasan,sdhci-8.9a, arasan,sdhci-4.9a;
I would just add 4.9a here because you want to use that quirks. We can
add some quirks to 8.9a version if any new problem arises.
Make sense too. Our's is 4.9a. Thanks for the catch.
Thanks,
Michal
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[PATCH v4 0/3] Add SDHCI support for APM X-Gene SoC using ARASAN SDHCI controller.
This patch adds the SDHCI support for APM X-Gene SoC using ARASAN SDHCI controller. v1 change: * Use the CONFIG_ARM64_DMA_HAS_IOMMU for dma-mapping. v2 change: * Drop the IOMMU support and switching to PIO mode for arasan. controller integrated inside APM X-Gene SoC. v3 change: * Change the sdhci-of-arasan.c to support arasan4.9a. * Add quirks for arasan4.9a. v4 change: * Cleanup the Documentation and dts. Signed-off-by: Suman Tripathi stripa...@apm.com --- Suman Tripathi (3): arm64: dts: Add the arasan sdhc nodes in apm-storm.dtsi. mmc: host: arasan: Add the support for sdhci-arasan4.9a in sdhci-of-arasan.c Documentation: mmc: Update Arasan SDHC documentation to support 4.9a version of Arasan SDHC controller. .../devicetree/bindings/mmc/arasan,sdhci.txt | 3 +- arch/arm64/boot/dts/apm-mustang.dts| 4 ++ arch/arm64/boot/dts/apm-storm.dtsi | 44 ++ drivers/mmc/host/sdhci-of-arasan.c | 7 4 files changed, 57 insertions(+), 1 deletion(-) -- 1.8.2.1 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v4 1/3] arm64: dts: Add the arasan sdhc nodes in apm-storm.dtsi.
This patch adds the arasan sdhc nodes to reuse the of-arasan
driver for APM X-Gene SoC.
Signed-off-by: Suman Tripathi stripa...@apm.com
---
arch/arm64/boot/dts/apm-mustang.dts | 4
arch/arm64/boot/dts/apm-storm.dtsi | 44 +
2 files changed, 48 insertions(+)
diff --git a/arch/arm64/boot/dts/apm-mustang.dts
b/arch/arm64/boot/dts/apm-mustang.dts
index 8eb6d94..d0e52a9 100644
--- a/arch/arm64/boot/dts/apm-mustang.dts
+++ b/arch/arm64/boot/dts/apm-mustang.dts
@@ -44,3 +44,7 @@
xgenet {
status = ok;
};
+
+sdhc0 {
+ status = ok;
+};
diff --git a/arch/arm64/boot/dts/apm-storm.dtsi
b/arch/arm64/boot/dts/apm-storm.dtsi
index 87d3205..a98ffc1 100644
--- a/arch/arm64/boot/dts/apm-storm.dtsi
+++ b/arch/arm64/boot/dts/apm-storm.dtsi
@@ -144,6 +144,40 @@
clock-output-names = socplldiv2;
};
+ ahbclk: ahbclk@1f2ac000 {
+ compatible = apm,xgene-device-clock;
+ #clock-cells = 1;
+ clocks = socplldiv2 0;
+ reg = 0x0 0x1f2ac000 0x0 0x1000
+ 0x0 0x1700 0x0 0x2000;
+ reg-names = csr-reg, div-reg;
+ csr-offset = 0x0;
+ csr-mask = 0x1;
+ enable-offset = 0x8;
+ enable-mask = 0x1;
+ divider-offset = 0x164;
+ divider-width = 0x5;
+ divider-shift = 0x0;
+ clock-output-names = ahbclk;
+ };
+
+ sdioclk: sdioclk@1f2ac000 {
+ compatible = apm,xgene-device-clock;
+ #clock-cells = 1;
+ clocks = socplldiv2 0;
+ reg = 0x0 0x1f2ac000 0x0 0x1000
+ 0x0 0x1700 0x0 0x2000;
+ reg-names = csr-reg, div-reg;
+ csr-offset = 0x0;
+ csr-mask = 0x2;
+ enable-offset = 0x8;
+ enable-mask = 0x2;
+ divider-offset = 0x178;
+ divider-width = 0x8;
+ divider-shift = 0x0;
+ clock-output-names = sdioclk;
+ };
+
qmlclk: qmlclk {
compatible = apm,xgene-device-clock;
#clock-cells = 1;
@@ -503,6 +537,16 @@
interrupts = 0x0 0x4f 0x4;
};
+ sdhc0: sdhc@1c00 {
+ device_type = sdhc;
+ compatible = arasan,sdhci-4.9a;
+ reg = 0x0 0x1c00 0x0 0x100;
+ interrupts = 0x0 0x49 0x4;
+ dma-coherent;
+ clock-names = clk_xin, clk_ahb;
+ clocks = sdioclk 0, ahbclk 0;
+ };
+
phy1: phy@1f21a000 {
compatible = apm,xgene-phy;
reg = 0x0 0x1f21a000 0x0 0x100;
--
1.8.2.1
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[PATCH v4 2/3] mmc: host: arasan: Add the support for sdhci-arasan4.9a in sdhci-of-arasan.c
This patch adds the quirks and compatible string in sdhci-of-arasan.c
to support sdhci-arasan4.9a version of controller.
Signed-off-by: Suman Tripathi stripa...@apm.com
---
drivers/mmc/host/sdhci-of-arasan.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/mmc/host/sdhci-of-arasan.c
b/drivers/mmc/host/sdhci-of-arasan.c
index 981d66e..92a4222 100644
--- a/drivers/mmc/host/sdhci-of-arasan.c
+++ b/drivers/mmc/host/sdhci-of-arasan.c
@@ -20,6 +20,7 @@
*/
#include linux/module.h
+#include linux/of_device.h
#include sdhci-pltfm.h
#define SDHCI_ARASAN_CLK_CTRL_OFFSET 0x2c
@@ -169,6 +170,11 @@ static int sdhci_arasan_probe(struct platform_device *pdev)
goto clk_disable_all;
}
+ if (of_device_is_compatible(pdev-dev.of_node, arasan,sdhci-4.9a)) {
+ host-quirks |= SDHCI_QUIRK_NO_HISPD_BIT;
+ host-quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23;
+ }
+
sdhci_get_of_property(pdev);
pltfm_host = sdhci_priv(host);
pltfm_host-priv = sdhci_arasan;
@@ -206,6 +212,7 @@ static int sdhci_arasan_remove(struct platform_device *pdev)
static const struct of_device_id sdhci_arasan_of_match[] = {
{ .compatible = arasan,sdhci-8.9a },
+ { .compatible = arasan,sdhci-4.9a },
{ }
};
MODULE_DEVICE_TABLE(of, sdhci_arasan_of_match);
--
1.8.2.1
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[PATCH v4 3/3] Documentation: mmc: Update Arasan SDHC documentation to support 4.9a version of Arasan SDHC controller.
This patch updates Arasan SDHC documentation to support 4.9a version of Arasan SDHC controller. Signed-off-by: Suman Tripathi stripa...@apm.com --- Documentation/devicetree/bindings/mmc/arasan,sdhci.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt index 98ee2ab..6dd3d60 100644 --- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt +++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt @@ -8,7 +8,8 @@ Device Tree Bindings for the Arasan SDHCI Controller [3] Documentation/devicetree/bindings/interrupt-controller/interrupts.txt Required Properties: - - compatible: Compatibility string. Must be 'arasan,sdhci-8.9a' + - compatible: Compatibility string. Must be 'arasan,sdhci-8.9a' or +'arasan,sdhci-4.9a' - reg: From mmc bindings: Register location and length. - clocks: From clock bindings: Handles to clock inputs. - clock-names: From clock bindings: Tuple including clk_xin and clk_ahb -- 1.8.2.1 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v3 3/3] Documentation: mmc: Update Arasan SDHC documentation to support 4.9a version of Arasan SDHC controller.
This patch updates Arasan SDHC documentation to support
4.9a version of Arasan SDHC controller.
Signed-off-by: Suman Tripathi stripa...@apm.com
---
Documentation/devicetree/bindings/mmc/arasan,sdhci.txt | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
index 98ee2ab..f01d41a 100644
--- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
+++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
@@ -8,7 +8,8 @@ Device Tree Bindings for the Arasan SDHCI Controller
[3] Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
Required Properties:
- - compatible: Compatibility string. Must be 'arasan,sdhci-8.9a'
+ - compatible: Compatibility string. Must be 'arasan,sdhci-8.9a' or
+'arasan,sdhci-4.9a'
- reg: From mmc bindings: Register location and length.
- clocks: From clock bindings: Handles to clock inputs.
- clock-names: From clock bindings: Tuple including clk_xin and clk_ahb
@@ -18,7 +19,7 @@ Required Properties:
Example:
sdhci@e010 {
- compatible = arasan,sdhci-8.9a;
+ compatible = arasan,sdhci-8.9a, arasan,sdhci-4.9a;
reg = 0xe010 0x1000;
clock-names = clk_xin, clk_ahb;
clocks = clkc 21, clkc 32;
--
1.8.2.1
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[PATCH v3 2/3] mmc: host: arasan: Add the support for sdhci-arasan4.9a in sdhci-of-arasan.c.
This patch adds the quirks and compatible string in sdhci-of-arasan.c
to support sdhci-arasan4.9a version of controller.
Signed-off-by: Suman Tripathi stripa...@apm.com
---
drivers/mmc/host/sdhci-of-arasan.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/mmc/host/sdhci-of-arasan.c
b/drivers/mmc/host/sdhci-of-arasan.c
index 981d66e..92a4222 100644
--- a/drivers/mmc/host/sdhci-of-arasan.c
+++ b/drivers/mmc/host/sdhci-of-arasan.c
@@ -20,6 +20,7 @@
*/
#include linux/module.h
+#include linux/of_device.h
#include sdhci-pltfm.h
#define SDHCI_ARASAN_CLK_CTRL_OFFSET 0x2c
@@ -169,6 +170,11 @@ static int sdhci_arasan_probe(struct platform_device *pdev)
goto clk_disable_all;
}
+ if (of_device_is_compatible(pdev-dev.of_node, arasan,sdhci-4.9a)) {
+ host-quirks |= SDHCI_QUIRK_NO_HISPD_BIT;
+ host-quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23;
+ }
+
sdhci_get_of_property(pdev);
pltfm_host = sdhci_priv(host);
pltfm_host-priv = sdhci_arasan;
@@ -206,6 +212,7 @@ static int sdhci_arasan_remove(struct platform_device *pdev)
static const struct of_device_id sdhci_arasan_of_match[] = {
{ .compatible = arasan,sdhci-8.9a },
+ { .compatible = arasan,sdhci-4.9a },
{ }
};
MODULE_DEVICE_TABLE(of, sdhci_arasan_of_match);
--
1.8.2.1
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[PATCH v3 1/3] arm64: dts: Add the arasan sdhc nodes in apm-storm.dtsi.
This patch adds the arasan sdhc nodes to reuse the of-arasan
driver for APM X-Gene SoC.
Signed-off-by: Suman Tripathi stripa...@apm.com
---
arch/arm64/boot/dts/apm-mustang.dts | 4
arch/arm64/boot/dts/apm-storm.dtsi | 44 +
2 files changed, 48 insertions(+)
diff --git a/arch/arm64/boot/dts/apm-mustang.dts
b/arch/arm64/boot/dts/apm-mustang.dts
index 8eb6d94..d0e52a9 100644
--- a/arch/arm64/boot/dts/apm-mustang.dts
+++ b/arch/arm64/boot/dts/apm-mustang.dts
@@ -44,3 +44,7 @@
xgenet {
status = ok;
};
+
+sdhc0 {
+ status = ok;
+};
diff --git a/arch/arm64/boot/dts/apm-storm.dtsi
b/arch/arm64/boot/dts/apm-storm.dtsi
index 87d3205..d6c2216 100644
--- a/arch/arm64/boot/dts/apm-storm.dtsi
+++ b/arch/arm64/boot/dts/apm-storm.dtsi
@@ -144,6 +144,40 @@
clock-output-names = socplldiv2;
};
+ ahbclk: ahbclk@1f2ac000 {
+ compatible = apm,xgene-device-clock;
+ #clock-cells = 1;
+ clocks = socplldiv2 0;
+ reg = 0x0 0x1f2ac000 0x0 0x1000
+ 0x0 0x1700 0x0 0x2000;
+ reg-names = csr-reg, div-reg;
+ csr-offset = 0x0;
+ csr-mask = 0x1;
+ enable-offset = 0x8;
+ enable-mask = 0x1;
+ divider-offset = 0x164;
+ divider-width = 0x5;
+ divider-shift = 0x0;
+ clock-output-names = ahbclk;
+ };
+
+ sdioclk: sdioclk@1f2ac000 {
+ compatible = apm,xgene-device-clock;
+ #clock-cells = 1;
+ clocks = socplldiv2 0;
+ reg = 0x0 0x1f2ac000 0x0 0x1000
+ 0x0 0x1700 0x0 0x2000;
+ reg-names = csr-reg, div-reg;
+ csr-offset = 0x0;
+ csr-mask = 0x2;
+ enable-offset = 0x8;
+ enable-mask = 0x2;
+ divider-offset = 0x178;
+ divider-width = 0x8;
+ divider-shift = 0x0;
+ clock-output-names = sdioclk;
+ };
+
qmlclk: qmlclk {
compatible = apm,xgene-device-clock;
#clock-cells = 1;
@@ -503,6 +537,16 @@
interrupts = 0x0 0x4f 0x4;
};
+ sdhc0: sdhc@1c00 {
+ device_type = sdhc;
+ compatible = arasan,sdhci-8.9a, arasan,sdhci-4.9a;
+ reg = 0x0 0x1c00 0x0 0x100;
+ interrupts = 0x0 0x49 0x4;
+ dma-coherent;
+ clock-names = clk_xin, clk_ahb;
+ clocks = sdioclk 0, ahbclk 0;
+ };
+
phy1: phy@1f21a000 {
compatible = apm,xgene-phy;
reg = 0x0 0x1f21a000 0x0 0x100;
--
1.8.2.1
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[PATCH v3 0/3] Add SDHCI support for APM X-Gene SoC using ARASAN SDHCI controller.
This patch adds the SDHCI support for APM X-Gene SoC using ARASAN SDHCI controller. v1 change: * Use the CONFIG_ARM64_DMA_HAS_IOMMU for dma-mapping. v2 change: * Drop the IOMMU support and switching to PIO mode for arasan. controller integrated inside APM X-Gene SoC. v3 change: * Change the sdhci-of-arasan.c to support arasan4.9a. * Add quirks for arasan4.9a. Signed-off-by: Suman Tripathi stripa...@apm.com --- Suman Tripathi (3): arm64: dts: Add the arasan sdhc nodes in apm-storm.dtsi. mmc: host: arasan: Add the support for sdhci-arasan4.9a in sdhci-of-arasan.c Documentation: mmc: Update Arasan SDHC documentation to support 4.9a version of Arasan SDHC controller. .../devicetree/bindings/mmc/arasan,sdhci.txt | 5 ++- arch/arm64/boot/dts/apm-mustang.dts| 4 ++ arch/arm64/boot/dts/apm-storm.dtsi | 44 ++ drivers/mmc/host/sdhci-of-arasan.c | 7 4 files changed, 58 insertions(+), 2 deletions(-) -- 1.8.2.1 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH v2 RESEND 2/2] mmc: host: Add some quirks to be read from fdt in sdhci-pltm.c
Hi Arnd, Please ignore the previous reply. On Tue, Apr 28, 2015 at 1:19 AM, Arnd Bergmann a...@arndb.de wrote: On Monday 27 April 2015 21:25:20 Suman Tripathi wrote: On Monday 27 April 2015 20:33:25 Suman Tripathi wrote: On Tuesday 21 April 2015 21:12:39 Suman Tripathi wrote: + host-quirks |= SDHCI_QUIRK_BROKEN_DMA; + + if (of_get_property(np, no-cmd23, NULL)) + host-quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23; if (of_get_property(np, no-1-8-v, NULL)) host-quirks2 |= SDHCI_QUIRK2_NO_1_8_V; Any property you add needs to be documented in the DT binding. If possible, add generic properties for each bug you have mmc.txt rather than the driver specific sdhci.txt, and implement the I will add the binding in mmc.txt. I thought this was present but not. parsing in a common function that is used for all mmc hosts. As per mine understanding the sdhci_get_of_porperty is a common parsing function . Am I wrong ?? A small side note: please fix your email client to use proper attribution of the citations. The way you reply, nobody knows what you are saying compare to what you quote. Also, reduce the quotation to the parts you are replying to. Okay. Sorry for that. I fixed it. No, this is only used for sdhci, not for the other controllers. But our's is a SHCI variant so I added it in this file. That's my point: a lot of the bugs are independent of the specific host controller and could happen with any one of them. We want to ensure that nobody tries to add another property with similar semantics and a different name just because they are using a different driver. Then I am not finding a reason why we have sdhci_get_of_property function ?? . I added a generic names like broken-adma that everyone can reuse it. I made mistake of not adding it in the binding. For eg : broken-cd is not added by me but I can use it. So I added something like broken-adma as it was not present. An alternative would be to set all these bits based on the compatible string of your host, if that is the only one that has all these bugs. The host driver (arasan) is reused but this quirks are needed due to board issues. so I have a control over dtb only to fix this. What is the nature of the bug on that board? Is there a different way to describe that without introducing six new properties? Sorry it is board and IP as well SoC errata's, 1. Delay after power is required due to some voltage issues that will be fixed in next board revision This is clearly not sdhci-specific, so make that a generic property for all mmc. Okay 2. We need to support PIO mode as of now because DMA or ADMA requires some kind of translation driver that I am working on. But this does not describe the hardware properties. Don't add properties that describe the lack of a kernel driver. If you can't do DMA yet, use a dma-ranges property that lists one empty range to prevent dma_set_mask() from working, so it will fall back to PIO mode. You may have to fix the driver if that doesn't already work. The generic sdhc framework doesn't have this capabiltiy. It uses the quirks to identify the broken DMA and ADMA modes even if the controller is capable of. What kind of driver do you need here? For DMA and adma we need some 32 bit to 64 bit translation driver. The existing arasan driver only support 32 bit. 3. The version of arasan variant we have in our SoC doesn't have the HISPD bit field in HI-SPEED SD card. So this makes HI-SPEED sdcard work. 4. NO_CMD23 is required for eMMC cards. These are not new properties. Only the fact is I am using it for our SoC from dtb. These quirks are already there in mmc common framework. Nothing is new. Are you sure that you have version 8.9a of the Arasan SDHCI? This sounds No We are using 4.9a ARASAN SDHCI like version specific quirks, so they are probably present in each SoC that uses the same version. Not sure Arnd -- Thanks, with regards, Suman Tripathi ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH v2 RESEND 2/2] mmc: host: Add some quirks to be read from fdt in sdhci-pltm.c
On Wed, Apr 29, 2015 at 2:45 PM, Arnd Bergmann a...@arndb.de wrote: On Wednesday 29 April 2015 12:34:41 Suman Tripathi wrote: On Tue, Apr 28, 2015 at 1:19 AM, Arnd Bergmann a...@arndb.de wrote: On Monday 27 April 2015 21:25:20 Suman Tripathi wrote: On Monday 27 April 2015 20:33:25 Suman Tripathi wrote: On Tuesday 21 April 2015 21:12:39 Suman Tripathi wrote: + host-quirks |= SDHCI_QUIRK_BROKEN_DMA; + + if (of_get_property(np, no-cmd23, NULL)) + host-quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23; if (of_get_property(np, no-1-8-v, NULL)) host-quirks2 |= SDHCI_QUIRK2_NO_1_8_V; Any property you add needs to be documented in the DT binding. If possible, add generic properties for each bug you have mmc.txt rather than the driver specific sdhci.txt, and implement the I will add the binding in mmc.txt. I thought this was present but not. parsing in a common function that is used for all mmc hosts. As per mine understanding the sdhci_get_of_porperty is a common parsing function . Am I wrong ?? A small side note: please fix your email client to use proper attribution of the citations. The way you reply, nobody knows what you are saying compare to what you quote. Also, reduce the quotation to the parts you are replying to. Okay. Sorry for that. I fixed it. Ok, much better. No, this is only used for sdhci, not for the other controllers. But our's is a SHCI variant so I added it in this file. That's my point: a lot of the bugs are independent of the specific host controller and could happen with any one of them. We want to ensure that nobody tries to add another property with similar semantics and a different name just because they are using a different driver. Then I am not finding a reason why we have sdhci_get_of_property function ?? . I added a generic names like broken-adma that everyone can reuse it. I made mistake of not adding it in the binding. For eg : broken-cd is not added by me but I can use it. So I added something like broken-adma as it was not present. The common mmc_of_parse() handles broken-cd, and the sdhci_get_of_property() does so too. This is really a mistake we made earlier when it was added to sdhi instead of the common code. We should remove the parsing for that property from the sdhci driver and have the core handle it always, but that require someone to do it and ensure that no subtle ABI changes are introduced on the way. I was not aware of the mmc_of_parse() . Agree now. For new properties, the right way is to add it to the common function only. 2. We need to support PIO mode as of now because DMA or ADMA requires some kind of translation driver that I am working on. But this does not describe the hardware properties. Don't add properties that describe the lack of a kernel driver. If you can't do DMA yet, use a dma-ranges property that lists one empty range to prevent dma_set_mask() from working, so it will fall back to PIO mode. You may have to fix the driver if that doesn't already work. The generic sdhc framework doesn't have this capabiltiy. It uses the quirks to identify the broken DMA and ADMA modes even if the controller is capable of. What kind of driver do you need here? For DMA and adma we need some 32 bit to 64 bit translation driver. The existing arasan driver only support 32 bit. Ok, that sounds like a very simple case: The width of the DMA is determined from DT by looking at the dma-ranges properties. If it doesn't work, one of these steps that are supposed to happen are broken and you should try to find out which one that is and fix it: - The parent node of the sdhci device in DT must not claim to support 64 bit if the bus is only 32-bit wide. A dma-ranges property containing 0 0 1 0 would describe a bus that has a 32-bit DMA address range that is 1:1 mapped to the root bus, which is the default. - The ARM64 code must check that property in a call to dma_set_mask() or dma_set_mask_and_coherent(), and not allow a mask to be set that exceeds the size of the dma-ranges property. - The sdhci driver must call dma_set_mask() or dma_set_mask_and_coherent() with the mask that is claimed by the device (usually 32 bit or 64 bit) and check the result. - If the call to dma_set_mask() for the 64-bit mask fails, the driver must fall back to using the 32-bit mask and not attempt to use the 64-bit DMA registers. This is the behavior we require anyway, and if this all works, you don't need the extra quirks. The above assumes that the limitation is enforced by the bus (e.g. an AHB bus can only do 32-bit DMA). It would be a little different if you have a 64-bit AXI bus and the Arasan device
Re: [PATCH v2 RESEND 2/2] mmc: host: Add some quirks to be read from fdt in sdhci-pltm.c
On Monday 27 April 2015 21:25:20 Suman Tripathi wrote: On Monday 27 April 2015 20:33:25 Suman Tripathi wrote: On Tuesday 21 April 2015 21:12:39 Suman Tripathi wrote: + host-quirks |= SDHCI_QUIRK_BROKEN_DMA; + + if (of_get_property(np, no-cmd23, NULL)) + host-quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23; if (of_get_property(np, no-1-8-v, NULL)) host-quirks2 |= SDHCI_QUIRK2_NO_1_8_V; Any property you add needs to be documented in the DT binding. If possible, add generic properties for each bug you have mmc.txt rather than the driver specific sdhci.txt, and implement the I will add the binding in mmc.txt. I thought this was present but not. parsing in a common function that is used for all mmc hosts. As per mine understanding the sdhci_get_of_porperty is a common parsing function . Am I wrong ?? A small side note: please fix your email client to use proper attribution of the citations. The way you reply, nobody knows what you are saying compare to what you quote. Also, reduce the quotation to the parts you are replying to. Ok . sorry for that .. No, this is only used for sdhci, not for the other controllers. But our's is a SHCI variant so I added it in this file. That's my point: a lot of the bugs are independent of the specific host controller and could happen with any one of them. We want to ensure that nobody tries to add another property with similar semantics and a different name just because they are using a different driver. Then I am not finding a reason why we have sdhci_get_of_property function ?? . I added a generic names like broken-adma that everyone can reuse it. I made mistake of not adding it in the binding. For eg : broken-cd is not added by me but I can use it. So I added something like broken-adma as it was not present. An alternative would be to set all these bits based on the compatible string of your host, if that is the only one that has all these bugs. The host driver (arasan) is reused but this quirks are needed due to board issues. so I have a control over dtb only to fix this. What is the nature of the bug on that board? Is there a different way to describe that without introducing six new properties? Sorry it is board and IP as well SoC errata's, 1. Delay after power is required due to some voltage issues that will be fixed in next board revision This is clearly not sdhci-specific, so make that a generic property for all mmc. okay. 2. We need to support PIO mode as of now because DMA or ADMA requires some kind of translation driver that I am working on. But this does not describe the hardware properties. Don't add properties that describe the lack of a kernel driver. If you can't do DMA yet, use a dma-ranges property that lists one empty range to prevent dma_set_mask() from working, so it will fall back to PIO mode. You may have to fix the driver if that doesn't already work. The generic sdhc framework doesn't have this capabiltiy. It uses the quirks to identify the broken DMA and ADMA modes even if the controller is capable of. What kind of driver do you need here? For DMA and adma we need some 32 bit to 64 bit translation driver. The existing arasan driver only support 32 bit. 3. The version of arasan variant we have in our SoC doesn't have the HISPD bit field in HI-SPEED SD card. So this makes HI-SPEED sdcard work. 4. NO_CMD23 is required for eMMC cards. These are not new properties. Only the fact is I am using it for our SoC from dtb. These quirks are already there in mmc common framework. Nothing is new. Are you sure that you have version 8.9a of the Arasan SDHCI? Yes This sounds like version specific quirks, so they are probably present in each SoC that uses the same version. Not sure. On Tue, Apr 28, 2015 at 1:19 AM, Arnd Bergmann a...@arndb.de wrote: On Monday 27 April 2015 21:25:20 Suman Tripathi wrote: On Monday 27 April 2015 20:33:25 Suman Tripathi wrote: On Tuesday 21 April 2015 21:12:39 Suman Tripathi wrote: + host-quirks |= SDHCI_QUIRK_BROKEN_DMA; + + if (of_get_property(np, no-cmd23, NULL)) + host-quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23; if (of_get_property(np, no-1-8-v, NULL)) host-quirks2 |= SDHCI_QUIRK2_NO_1_8_V; Any property you add needs to be documented in the DT binding. If possible, add generic properties for each bug you have mmc.txt rather than the driver specific sdhci.txt, and implement the I will add the binding in mmc.txt. I thought this was present but not. parsing in a common function that is used for all mmc hosts. As per mine understanding the sdhci_get_of_porperty is a common parsing function . Am I wrong
Re: [PATCH v2 RESEND 2/2] mmc: host: Add some quirks to be read from fdt in sdhci-pltm.c
On Tuesday 21 April 2015 21:12:39 Suman Tripathi wrote: index bef250e..9f6a4b9 100644 --- a/drivers/mmc/host/sdhci-pltfm.c +++ b/drivers/mmc/host/sdhci-pltfm.c @@ -85,6 +85,21 @@ void sdhci_get_of_property(struct platform_device *pdev) if (of_get_property(np, broken-cd, NULL)) host-quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION; + + if (of_get_property(np, delay-after-power, NULL)) + host-quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER; + + if (of_get_property(np, no-hispd, NULL)) + host-quirks |= SDHCI_QUIRK_NO_HISPD_BIT; + + if (of_get_property(np, broken-adma, NULL)) + host-quirks |= SDHCI_QUIRK_BROKEN_ADMA; + + if (of_get_property(np, broken-dma, NULL)) + host-quirks |= SDHCI_QUIRK_BROKEN_DMA; + + if (of_get_property(np, no-cmd23, NULL)) + host-quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23; if (of_get_property(np, no-1-8-v, NULL)) host-quirks2 |= SDHCI_QUIRK2_NO_1_8_V; Any property you add needs to be documented in the DT binding. If possible, add generic properties for each bug you have mmc.txt rather than the driver specific sdhci.txt, and implement the I will add the binding in mmc.txt. I thought this was present but not. parsing in a common function that is used for all mmc hosts. As per mine understanding the sdhci_get_of_porperty is a common parsing function . Am I wrong ?? An alternative would be to set all these bits based on the compatible string of your host, if that is the only one that has all these bugs. The host driver (arasan) is reused but this quirks are needed due to board issues. so I have a control over dtb only to fix this. On Tue, Apr 21, 2015 at 9:16 PM, Arnd Bergmann a...@arndb.de wrote: On Tuesday 21 April 2015 21:12:39 Suman Tripathi wrote: index bef250e..9f6a4b9 100644 --- a/drivers/mmc/host/sdhci-pltfm.c +++ b/drivers/mmc/host/sdhci-pltfm.c @@ -85,6 +85,21 @@ void sdhci_get_of_property(struct platform_device *pdev) if (of_get_property(np, broken-cd, NULL)) host-quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION; + + if (of_get_property(np, delay-after-power, NULL)) + host-quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER; + + if (of_get_property(np, no-hispd, NULL)) + host-quirks |= SDHCI_QUIRK_NO_HISPD_BIT; + + if (of_get_property(np, broken-adma, NULL)) + host-quirks |= SDHCI_QUIRK_BROKEN_ADMA; + + if (of_get_property(np, broken-dma, NULL)) + host-quirks |= SDHCI_QUIRK_BROKEN_DMA; + + if (of_get_property(np, no-cmd23, NULL)) + host-quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23; if (of_get_property(np, no-1-8-v, NULL)) host-quirks2 |= SDHCI_QUIRK2_NO_1_8_V; Any property you add needs to be documented in the DT binding. If possible, add generic properties for each bug you have mmc.txt rather than the driver specific sdhci.txt, and implement the parsing in a common function that is used for all mmc hosts. An alternative would be to set all these bits based on the compatible string of your host, if that is the only one that has all these bugs. Arnd -- Thanks, with regards, Suman Tripathi ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH v2 RESEND 2/2] mmc: host: Add some quirks to be read from fdt in sdhci-pltm.c
On Monday 27 April 2015 20:33:25 Suman Tripathi wrote: On Tuesday 21 April 2015 21:12:39 Suman Tripathi wrote: index bef250e..9f6a4b9 100644 --- a/drivers/mmc/host/sdhci-pltfm.c +++ b/drivers/mmc/host/sdhci-pltfm.c @@ -85,6 +85,21 @@ void sdhci_get_of_property(struct platform_device *pdev) if (of_get_property(np, broken-cd, NULL)) host-quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION; + + if (of_get_property(np, delay-after-power, NULL)) + host-quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER; + + if (of_get_property(np, no-hispd, NULL)) + host-quirks |= SDHCI_QUIRK_NO_HISPD_BIT; + + if (of_get_property(np, broken-adma, NULL)) + host-quirks |= SDHCI_QUIRK_BROKEN_ADMA; + + if (of_get_property(np, broken-dma, NULL)) + host-quirks |= SDHCI_QUIRK_BROKEN_DMA; + + if (of_get_property(np, no-cmd23, NULL)) + host-quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23; if (of_get_property(np, no-1-8-v, NULL)) host-quirks2 |= SDHCI_QUIRK2_NO_1_8_V; Any property you add needs to be documented in the DT binding. If possible, add generic properties for each bug you have mmc.txt rather than the driver specific sdhci.txt, and implement the I will add the binding in mmc.txt. I thought this was present but not. parsing in a common function that is used for all mmc hosts. As per mine understanding the sdhci_get_of_porperty is a common parsing function . Am I wrong ?? No, this is only used for sdhci, not for the other controllers. But our's is a SHCI variant so I added it in this file. An alternative would be to set all these bits based on the compatible string of your host, if that is the only one that has all these bugs. The host driver (arasan) is reused but this quirks are needed due to board issues. so I have a control over dtb only to fix this. What is the nature of the bug on that board? Is there a different way to describe that without introducing six new properties? Sorry it is board and IP as well SoC errata's, 1. Delay after power is required due to some voltage issues that will be fixed in next board revision 2. We need to support PIO mode as of now because DMA or ADMA requires some kind of translation driver that I am working on. 3. The version of arasan variant we have in our SoC doesn't have the HISPD bit field in HI-SPEED SD card. So this makes HI-SPEED sdcard work. 4. NO_CMD23 is required for eMMC cards. These are not new properties. Only the fact is I am using it for our SoC from dtb. These quirks are already there in mmc common framework. Nothing is new. On Mon, Apr 27, 2015 at 8:55 PM, Arnd Bergmann a...@arndb.de wrote: On Monday 27 April 2015 20:33:25 Suman Tripathi wrote: On Tuesday 21 April 2015 21:12:39 Suman Tripathi wrote: index bef250e..9f6a4b9 100644 --- a/drivers/mmc/host/sdhci-pltfm.c +++ b/drivers/mmc/host/sdhci-pltfm.c @@ -85,6 +85,21 @@ void sdhci_get_of_property(struct platform_device *pdev) if (of_get_property(np, broken-cd, NULL)) host-quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION; + + if (of_get_property(np, delay-after-power, NULL)) + host-quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER; + + if (of_get_property(np, no-hispd, NULL)) + host-quirks |= SDHCI_QUIRK_NO_HISPD_BIT; + + if (of_get_property(np, broken-adma, NULL)) + host-quirks |= SDHCI_QUIRK_BROKEN_ADMA; + + if (of_get_property(np, broken-dma, NULL)) + host-quirks |= SDHCI_QUIRK_BROKEN_DMA; + + if (of_get_property(np, no-cmd23, NULL)) + host-quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23; if (of_get_property(np, no-1-8-v, NULL)) host-quirks2 |= SDHCI_QUIRK2_NO_1_8_V; Any property you add needs to be documented in the DT binding. If possible, add generic properties for each bug you have mmc.txt rather than the driver specific sdhci.txt, and implement the I will add the binding in mmc.txt. I thought this was present but not. parsing in a common function that is used for all mmc hosts. As per mine understanding the sdhci_get_of_porperty is a common parsing function . Am I wrong ?? No, this is only used for sdhci, not for the other controllers. An alternative would be to set all these bits based on the compatible string of your host, if that is the only one that has all these bugs. The host driver (arasan) is reused but this quirks are needed due to board issues. so I have a control over dtb only to fix this. What is the nature
[PATCH v2 RESEND 1/2] arm64: dts: Add the arasan sdhc nodes in apm-storm.dtsi.
This patch adds the arasan sdhc nodes to reuse the of-arasan
driver for APM X-Gene SoC.
Signed-off-by: Suman Tripathi stripa...@apm.com
---
arch/arm64/boot/dts/apm-storm.dtsi | 44 ++
1 file changed, 44 insertions(+)
diff --git a/arch/arm64/boot/dts/apm-storm.dtsi
b/arch/arm64/boot/dts/apm-storm.dtsi
index c5f0a47..fd1c142 100644
--- a/arch/arm64/boot/dts/apm-storm.dtsi
+++ b/arch/arm64/boot/dts/apm-storm.dtsi
@@ -144,6 +144,40 @@
clock-output-names = socplldiv2;
};
+ ahbclk: ahbclk@1f2ac000 {
+ compatible = apm,xgene-device-clock;
+ #clock-cells = 1;
+ clocks = socplldiv2 0;
+ reg = 0x0 0x1f2ac000 0x0 0x1000
+ 0x0 0x1700 0x0 0x2000;
+ reg-names = csr-reg, div-reg;
+ csr-offset = 0x0;
+ csr-mask = 0x1;
+ enable-offset = 0x8;
+ enable-mask = 0x1;
+ divider-offset = 0x164;
+ divider-width = 0x5;
+ divider-shift = 0x0;
+ clock-output-names = ahbclk;
+ };
+
+ sdioclk: sdioclk@1f2ac000 {
+ compatible = apm,xgene-device-clock;
+ #clock-cells = 1;
+ clocks = socplldiv2 0;
+ reg = 0x0 0x1f2ac000 0x0 0x1000
+ 0x0 0x1700 0x0 0x2000;
+ reg-names = csr-reg, div-reg;
+ csr-offset = 0x0;
+ csr-mask = 0x2;
+ enable-offset = 0x8;
+ enable-mask = 0x2;
+ divider-offset = 0x178;
+ divider-width = 0x8;
+ divider-shift = 0x0;
+ clock-output-names = sdioclk;
+ };
+
qmlclk: qmlclk {
compatible = apm,xgene-device-clock;
#clock-cells = 1;
@@ -282,6 +316,16 @@
interrupts = 0x0 0x4c 0x4;
};
+ sdhc0: sdhc@1c00 {
+ device_type = sdhc;
+ compatible = arasan,sdhci-8.9a;
+ reg = 0x0 0x1c00 0x0 0x100;
+ interrupts = 0x0 0x49 0x4;
+ dma-coherent;
+ clock-names = clk_xin, clk_ahb;
+ clocks = sdioclk 0, ahbclk 0;
+ };
+
phy1: phy@1f21a000 {
compatible = apm,xgene-phy;
reg = 0x0 0x1f21a000 0x0 0x100;
--
1.8.2.1
___
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[PATCH v2 RESEND 2/2] mmc: host: Add some quirks to be read from fdt in sdhci-pltm.c
This patch adds some quirks support to be read from fdt. Signed-off-by: Suman Tripathi stripa...@apm.com --- drivers/mmc/host/sdhci-pltfm.c | 15 +++ 1 file changed, 15 insertions(+) diff --git a/drivers/mmc/host/sdhci-pltfm.c b/drivers/mmc/host/sdhci-pltfm.c index bef250e..9f6a4b9 100644 --- a/drivers/mmc/host/sdhci-pltfm.c +++ b/drivers/mmc/host/sdhci-pltfm.c @@ -85,6 +85,21 @@ void sdhci_get_of_property(struct platform_device *pdev) if (of_get_property(np, broken-cd, NULL)) host-quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION; + + if (of_get_property(np, delay-after-power, NULL)) + host-quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER; + + if (of_get_property(np, no-hispd, NULL)) + host-quirks |= SDHCI_QUIRK_NO_HISPD_BIT; + + if (of_get_property(np, broken-adma, NULL)) + host-quirks |= SDHCI_QUIRK_BROKEN_ADMA; + + if (of_get_property(np, broken-dma, NULL)) + host-quirks |= SDHCI_QUIRK_BROKEN_DMA; + + if (of_get_property(np, no-cmd23, NULL)) + host-quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23; if (of_get_property(np, no-1-8-v, NULL)) host-quirks2 |= SDHCI_QUIRK2_NO_1_8_V; -- 1.8.2.1 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v2 RESEND 0/2] Add SDHCI support for APM X-Gene SoC using ARASAN SDHCI controller.
This patch adds the SDHCI support for APM X-Gene SoC using ARASAN SDHCI controller. v1 change: * Use the CONFIG_ARM64_DMA_HAS_IOMMU for dma-mapping. v2 change: * Drop the IOMMU support and switching to PIO mode for arasan controller integrated inside APM X-Gene SoC. Signed-off-by: Suman Tripathi stripa...@apm.com Suman Tripathi (2): arm64: dts: Add the arasan sdhc nodes in apm-storm.dtsi. mmc: host: Add some quirks to be read from fdt in sdhci-pltm.c arch/arm64/boot/dts/apm-storm.dtsi | 44 ++ drivers/mmc/host/sdhci-pltfm.c | 15 + 2 files changed, 59 insertions(+) -- 1.8.2.1 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH v2 2/2] mmc: host: Add some quirks to be read from fdt in sdhci-pltm.c
On 30 March 2015 at 16:46, Suman Tripathi stripa...@apm.com wrote: This patch adds some quirks support to be read from fdt. Signed-off-by: Suman Tripathi stripa...@apm.com --- drivers/mmc/host/sdhci-pltfm.c | 15 +++ 1 file changed, 15 insertions(+) diff --git a/drivers/mmc/host/sdhci-pltfm.c b/drivers/mmc/host/sdhci-pltfm.c index bef250e..9f6a4b9 100644 --- a/drivers/mmc/host/sdhci-pltfm.c +++ b/drivers/mmc/host/sdhci-pltfm.c @@ -85,6 +85,21 @@ void sdhci_get_of_property(struct platform_device *pdev) if (of_get_property(np, broken-cd, NULL)) host-quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION; + + if (of_get_property(np, delay-after-power, NULL)) + host-quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER; + + if (of_get_property(np, no-hispd, NULL)) + host-quirks |= SDHCI_QUIRK_NO_HISPD_BIT; + + if (of_get_property(np, broken-adma, NULL)) + host-quirks |= SDHCI_QUIRK_BROKEN_ADMA; + + if (of_get_property(np, broken-dma, NULL)) + host-quirks |= SDHCI_QUIRK_BROKEN_DMA; + + if (of_get_property(np, no-cmd23, NULL)) + host-quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23; Can't at least some of these be distinguished from what sdhci variant that is being used? Instead of having them in DT... We are using arasan controller in our SOC. So reusing a the existing sdhci-of-arasan driver. Due to H/W issues we require this quirks. So for us only option left to pass the info is DTS or ACPI table. Kind regards Uffe On Thu, Apr 9, 2015 at 9:40 PM, Suman Tripathi stripa...@apm.com wrote: On 30 March 2015 at 16:46, Suman Tripathi stripa...@apm.com wrote: This patch adds some quirks support to be read from fdt. Signed-off-by: Suman Tripathi stripa...@apm.com --- drivers/mmc/host/sdhci-pltfm.c | 15 +++ 1 file changed, 15 insertions(+) diff --git a/drivers/mmc/host/sdhci-pltfm.c b/drivers/mmc/host/sdhci-pltfm.c index bef250e..9f6a4b9 100644 --- a/drivers/mmc/host/sdhci-pltfm.c +++ b/drivers/mmc/host/sdhci-pltfm.c @@ -85,6 +85,21 @@ void sdhci_get_of_property(struct platform_device *pdev) if (of_get_property(np, broken-cd, NULL)) host-quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION; + + if (of_get_property(np, delay-after-power, NULL)) + host-quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER; + + if (of_get_property(np, no-hispd, NULL)) + host-quirks |= SDHCI_QUIRK_NO_HISPD_BIT; + + if (of_get_property(np, broken-adma, NULL)) + host-quirks |= SDHCI_QUIRK_BROKEN_ADMA; + + if (of_get_property(np, broken-dma, NULL)) + host-quirks |= SDHCI_QUIRK_BROKEN_DMA; + + if (of_get_property(np, no-cmd23, NULL)) + host-quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23; Can't at least some of these be distinguished from what sdhci variant that is being used? Instead of having them in DT... We are using arasan controller in our SOC. So reusing a the existing sdhci-of-arasan driver. Due to H/W issues we require this quirks. So for us only option left to pass the info is DTS or ACPI table. Kind regards Uffe On Wed, Apr 8, 2015 at 3:10 PM, Ulf Hansson ulf.hans...@linaro.org wrote: On 30 March 2015 at 16:46, Suman Tripathi stripa...@apm.com wrote: This patch adds some quirks support to be read from fdt. Signed-off-by: Suman Tripathi stripa...@apm.com --- drivers/mmc/host/sdhci-pltfm.c | 15 +++ 1 file changed, 15 insertions(+) diff --git a/drivers/mmc/host/sdhci-pltfm.c b/drivers/mmc/host/sdhci-pltfm.c index bef250e..9f6a4b9 100644 --- a/drivers/mmc/host/sdhci-pltfm.c +++ b/drivers/mmc/host/sdhci-pltfm.c @@ -85,6 +85,21 @@ void sdhci_get_of_property(struct platform_device *pdev) if (of_get_property(np, broken-cd, NULL)) host-quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION; + + if (of_get_property(np, delay-after-power, NULL)) + host-quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER; + + if (of_get_property(np, no-hispd, NULL)) + host-quirks |= SDHCI_QUIRK_NO_HISPD_BIT; + + if (of_get_property(np, broken-adma, NULL)) + host-quirks |= SDHCI_QUIRK_BROKEN_ADMA; + + if (of_get_property(np, broken-dma, NULL)) + host-quirks |= SDHCI_QUIRK_BROKEN_DMA; + + if (of_get_property(np, no-cmd23, NULL)) + host-quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23; Can't at least some of these be distinguished from what sdhci variant that is being used? Instead of having them in DT... Kind regards Uffe
[PATCH v2 0/2] Add SDHCI support for APM X-Gene SoC using ARASAN SDHCI controller.
This patch adds the SDHCI support for APM X-Gene SoC using ARASAN SDHCI controller. v1 change: * Use the CONFIG_ARM64_DMA_HAS_IOMMU for dma-mapping. v2 change: * Drop the IOMMU support and switching to PIO mode for arasan controller integrated inside APM X-Gene SoC. Signed-off-by: Suman Tripathi stripa...@apm.com Suman Tripathi (2): arm64: dts: Add the arasan sdhc nodes in apm-storm.dtsi. mmc: host: Add some quirks to be read from fdt in sdhci-pltm.c arch/arm64/boot/dts/apm-storm.dtsi | 44 ++ drivers/mmc/host/sdhci-pltfm.c | 15 + 2 files changed, 59 insertions(+) -- 1.8.2.1 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v2 2/2] mmc: host: Add some quirks to be read from fdt in sdhci-pltm.c
This patch adds some quirks support to be read from fdt. Signed-off-by: Suman Tripathi stripa...@apm.com --- drivers/mmc/host/sdhci-pltfm.c | 15 +++ 1 file changed, 15 insertions(+) diff --git a/drivers/mmc/host/sdhci-pltfm.c b/drivers/mmc/host/sdhci-pltfm.c index bef250e..9f6a4b9 100644 --- a/drivers/mmc/host/sdhci-pltfm.c +++ b/drivers/mmc/host/sdhci-pltfm.c @@ -85,6 +85,21 @@ void sdhci_get_of_property(struct platform_device *pdev) if (of_get_property(np, broken-cd, NULL)) host-quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION; + + if (of_get_property(np, delay-after-power, NULL)) + host-quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER; + + if (of_get_property(np, no-hispd, NULL)) + host-quirks |= SDHCI_QUIRK_NO_HISPD_BIT; + + if (of_get_property(np, broken-adma, NULL)) + host-quirks |= SDHCI_QUIRK_BROKEN_ADMA; + + if (of_get_property(np, broken-dma, NULL)) + host-quirks |= SDHCI_QUIRK_BROKEN_DMA; + + if (of_get_property(np, no-cmd23, NULL)) + host-quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23; if (of_get_property(np, no-1-8-v, NULL)) host-quirks2 |= SDHCI_QUIRK2_NO_1_8_V; -- 1.8.2.1 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v2 1/2] arm64: dts: Add the arasan sdhc nodes in apm-storm.dtsi.
This patch adds the arasan sdhc nodes to reuse the of-arasan
driver for APM X-Gene SoC.
Signed-off-by: Suman Tripathi stripa...@apm.com
---
arch/arm64/boot/dts/apm-storm.dtsi | 44 ++
1 file changed, 44 insertions(+)
diff --git a/arch/arm64/boot/dts/apm-storm.dtsi
b/arch/arm64/boot/dts/apm-storm.dtsi
index c5f0a47..fd1c142 100644
--- a/arch/arm64/boot/dts/apm-storm.dtsi
+++ b/arch/arm64/boot/dts/apm-storm.dtsi
@@ -144,6 +144,40 @@
clock-output-names = socplldiv2;
};
+ ahbclk: ahbclk@1f2ac000 {
+ compatible = apm,xgene-device-clock;
+ #clock-cells = 1;
+ clocks = socplldiv2 0;
+ reg = 0x0 0x1f2ac000 0x0 0x1000
+ 0x0 0x1700 0x0 0x2000;
+ reg-names = csr-reg, div-reg;
+ csr-offset = 0x0;
+ csr-mask = 0x1;
+ enable-offset = 0x8;
+ enable-mask = 0x1;
+ divider-offset = 0x164;
+ divider-width = 0x5;
+ divider-shift = 0x0;
+ clock-output-names = ahbclk;
+ };
+
+ sdioclk: sdioclk@1f2ac000 {
+ compatible = apm,xgene-device-clock;
+ #clock-cells = 1;
+ clocks = socplldiv2 0;
+ reg = 0x0 0x1f2ac000 0x0 0x1000
+ 0x0 0x1700 0x0 0x2000;
+ reg-names = csr-reg, div-reg;
+ csr-offset = 0x0;
+ csr-mask = 0x2;
+ enable-offset = 0x8;
+ enable-mask = 0x2;
+ divider-offset = 0x178;
+ divider-width = 0x8;
+ divider-shift = 0x0;
+ clock-output-names = sdioclk;
+ };
+
qmlclk: qmlclk {
compatible = apm,xgene-device-clock;
#clock-cells = 1;
@@ -282,6 +316,16 @@
interrupts = 0x0 0x4c 0x4;
};
+ sdhc0: sdhc@1c00 {
+ device_type = sdhc;
+ compatible = arasan,sdhci-8.9a;
+ reg = 0x0 0x1c00 0x0 0x100;
+ interrupts = 0x0 0x49 0x4;
+ dma-coherent;
+ clock-names = clk_xin, clk_ahb;
+ clocks = sdioclk 0, ahbclk 0;
+ };
+
phy1: phy@1f21a000 {
compatible = apm,xgene-phy;
reg = 0x0 0x1f21a000 0x0 0x100;
--
1.8.2.1
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Re: [PATCH v1 2/2] arm64: dts: Add the arasan sdhc nodes in apm-storm.dtsi.
On Wednesday 28 January 2015 09:53:25 Suman Tripathi wrote: I added the iommus in the IOMMU AHBC patch. Anything wrong in that ? In the next version Also I will remove the IOMMU hacks from arasan driver Hmm, I guess you have a required ordering between the patches either way, which makes it hard to merge in a way that is bisectable. You are correct that you should not merge a patch with the iommu reference before adding the iommu device node, because it would otherwise break building the mmc tree. One more point is the binding for IOMMU needs to be in the same patch in which the IOMMU support is added. So to provide the binding info of the master node we require the sdhc nodes to be merged first. Usually, the right answer is to merged the dts changes through the arm-soc tree, and then you can just add the node for the sdhc device after the one for the iommu device. On Wed, Jan 28, 2015 at 6:16 PM, Arnd Bergmann a...@arndb.de wrote: On Wednesday 28 January 2015 09:53:25 Suman Tripathi wrote: I added the iommus in the IOMMU AHBC patch. Anything wrong in that ? In the next version Also I will remove the IOMMU hacks from arasan driver Hmm, I guess you have a required ordering between the patches either way, which makes it hard to merge in a way that is bisectable. You are correct that you should not merge a patch with the iommu reference before adding the iommu device node, because it would otherwise break building the mmc tree. Usually, the right answer is to merged the dts changes through the arm-soc tree, and then you can just add the node for the sdhc device after the one for the iommu device. Arnd -- Thanks, with regards, Suman Tripathi ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v1 1/2] mmc: host: arasan: Add addition of-arasan quirks and IOMMU support for arasan SDHCI driver.
Due to the fact that the existing of-arasan driver works with
32-bit platforms. This patch tweaks existing of-arasan driver
to work with 64-bit platform using IOMMU translation.
In addition it adds support for more quirks and quirks2 obtained
from device tree inside the generic sdhci-platform(sdhci-pltfm.c)
driver.
Signed-off-by: Suman Tripathi stripa...@apm.com
---
drivers/mmc/host/Makefile | 2 ++
drivers/mmc/host/sdhci-ahbc-xgene.c | 58 +
drivers/mmc/host/sdhci-ahbc-xgene.h | 49 +++
drivers/mmc/host/sdhci-of-arasan.c | 11 +++
drivers/mmc/host/sdhci-pltfm.c | 12
5 files changed, 132 insertions(+)
create mode 100644 drivers/mmc/host/sdhci-ahbc-xgene.c
create mode 100644 drivers/mmc/host/sdhci-ahbc-xgene.h
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index b09ecfb..82de8f0 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -75,3 +75,5 @@ obj-$(CONFIG_MMC_SDHCI_ST)+= sdhci-st.o
ifeq ($(CONFIG_CB710_DEBUG),y)
CFLAGS-cb710-mmc+= -DDEBUG
endif
+
+obj-$(CONFIG_XGENE_AHBC_IOMMU) += sdhci-ahbc-xgene.o
diff --git a/drivers/mmc/host/sdhci-ahbc-xgene.c
b/drivers/mmc/host/sdhci-ahbc-xgene.c
new file mode 100644
index 000..e23b69d98
--- /dev/null
+++ b/drivers/mmc/host/sdhci-ahbc-xgene.c
@@ -0,0 +1,58 @@
+/* sdhci-ahbc-xgene.c
+ *
+ * Copyright (c) 2014 Applied Micro Circuits Corporation.
+ * Author: Suman Tripathi stripa...@apm.com
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include linux/amba/bus.h
+#include linux/device.h
+
+#include asm/dma-iommu.h
+
+#include sdhci-ahbc-xgene.h
+
+int xgene_ahbc_iommu_attach_device(struct device *dev)
+{
+ struct dma_iommu_mapping *mapping;
+ int ret;
+
+ /*
+* AHBC iommu don't have specific
+* IOMMU area. Create a mapping for
+* dummy area 4GB.
+*/
+ mapping = arm64_iommu_create_mapping(amba_bustype,
+XGENE_AHBC_IOMMU_DMA_START,
+XGENE_AHBC_IOMMU_DMA_SIZE);
+
+ if (IS_ERR(mapping))
+ return PTR_ERR(mapping);
+
+ mapping-identical_map = true;
+
+ ret = arm64_iommu_attach_device(dev, mapping);
+ if (ret 0) {
+ dev_err(dev, failed iommu attach\n);
+ return ret;
+ }
+
+ return 0;
+}
+
+void xgene_ahbc_iommu_detach_device(struct device *dev)
+{
+ struct dma_iommu_mapping *mapping = dev-archdata.mapping;
+
+ if (!mapping || !mapping-domain)
+ return;
+
+ arm64_iommu_detach_device(dev);
+ arm64_iommu_release_mapping(mapping);
+
+}
+
diff --git a/drivers/mmc/host/sdhci-ahbc-xgene.h
b/drivers/mmc/host/sdhci-ahbc-xgene.h
new file mode 100644
index 000..97a2b6b
--- /dev/null
+++ b/drivers/mmc/host/sdhci-ahbc-xgene.h
@@ -0,0 +1,49 @@
+/* xgene_sdhci_ahbc.h
+ *
+ * Copyright (c) 2014 Applied Micro Circuits Corporation.
+ * Author: Suman Tripathi stripa...@apm.com
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef _XGENE_SDHCI_AHBC_H_
+#define _XGENE_SDHCI_AHBC_H_
+#include linux/err.h
+
+#ifdef CONFIG_XGENE_AHBC_IOMMU
+
+#define XGENE_AHBC_IOMMU_DMA_START 0x
+#define XGENE_AHBC_IOMMU_DMA_SIZE 0x1
+
+int xgene_ahbc_iommu_attach_device(struct device *dev);
+void xgene_ahbc_iommu_detach_device(struct device *dev);
+static inline bool is_xgene_ahbc_iommu_supported(struct device *dev)
+{
+#ifdef CONFIG_ARM64_DMA_USE_IOMMU
+ return dev-archdata.mapping ? true : false;
+#else
+ return false;
+#endif
+}
+
+#else
+
+static inline int xgene_ahbc_iommu_attach_device(struct device *dev)
+{
+ return -ENOSYS;
+}
+
+static inline void xgene_ahbc_iommu_detach_device(struct device *dev)
+{
+ return;
+}
+
+static inline bool is_xgene_ahbc_iommu_supported(struct device *dev)
+{
+ return false;
+}
+#endif
+#endif
diff --git a/drivers/mmc/host/sdhci-of-arasan.c
b/drivers/mmc/host/sdhci-of-arasan.c
index 981d66e..78de09c 100644
--- a/drivers/mmc/host/sdhci-of-arasan.c
+++ b/drivers/mmc/host/sdhci-of-arasan.c
@@ -22,6 +22,8 @@
#include linux/module.h
#include sdhci-pltfm.h
+#include sdhci-ahbc-xgene.h
+
#define SDHCI_ARASAN_CLK_CTRL_OFFSET 0x2c
#define CLK_CTRL_TIMEOUT_SHIFT 16
@@ -174,6 +176,13 @@ static int sdhci_arasan_probe(struct platform_device *pdev)
pltfm_host-priv = sdhci_arasan;
pltfm_host-clk = clk_xin
[PATCH v1 2/2] arm64: dts: Add the arasan sdhc nodes in apm-storm.dtsi.
This patch adds the arasan sdhc nodes to reuse the of-arasan
driver for APM X-Gene SoC.
Signed-off-by: Suman Tripathi stripa...@apm.com
---
arch/arm64/boot/dts/apm-storm.dtsi | 43 ++
1 file changed, 43 insertions(+)
diff --git a/arch/arm64/boot/dts/apm-storm.dtsi
b/arch/arm64/boot/dts/apm-storm.dtsi
index f1ad9c2..52de7d3 100644
--- a/arch/arm64/boot/dts/apm-storm.dtsi
+++ b/arch/arm64/boot/dts/apm-storm.dtsi
@@ -144,6 +144,40 @@
clock-output-names = socplldiv2;
};
+ ahbclk: ahbclk@1f2ac000 {
+ compatible = apm,xgene-device-clock;
+ #clock-cells = 1;
+ clocks = socplldiv2 0;
+ reg = 0x0 0x1f2ac000 0x0 0x1000
+ 0x0 0x1700 0x0 0x2000;
+ reg-names = csr-reg, div-reg;
+ csr-offset = 0x0;
+ csr-mask = 0x1;
+ enable-offset = 0x8;
+ enable-mask = 0x1;
+ divider-offset = 0x164;
+ divider-width = 0x5;
+ divider-shift = 0x0;
+ clock-output-names = ahbclk;
+ };
+
+ sdioclk: sdioclk@1f2ac000 {
+ compatible = apm,xgene-device-clock;
+ #clock-cells = 1;
+ clocks = socplldiv2 0;
+ reg = 0x0 0x1f2ac000 0x0 0x1000
+ 0x0 0x1700 0x0 0x2000;
+ reg-names = csr-reg, div-reg;
+ csr-offset = 0x0;
+ csr-mask = 0x2;
+ enable-offset = 0x8;
+ enable-mask = 0x2;
+ divider-offset = 0x178;
+ divider-width = 0x8;
+ divider-shift = 0x0;
+ clock-output-names = sdioclk;
+ };
+
qmlclk: qmlclk {
compatible = apm,xgene-device-clock;
#clock-cells = 1;
@@ -595,6 +629,15 @@
clocks = rtcclk 0;
};
+ sdhc0: sdhc@1c00 {
+ device_type = sdhc;
+ compatible = arasan,sdhci-8.9a;
+ reg = 0x0 0x1c00 0x0 0x100;
+ interrupts = 0x0 0x49 0x4;
+ clock-names = clk_xin, clk_ahb;
+ clocks = sdioclk 0, ahbclk 0;
+ };
+
menet: ethernet@1702 {
compatible = apm,xgene-enet;
status = disabled;
--
1.8.2.1
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[PATCH v1 0/2] Add SDHCI support for APM X-Gene SoC using ARASAN SDHCI controller.
Due to the fact that the existing of-arasan driver works with 32-bit platforms. This patch tweaks existing of-arasan driver to work with 64-bit X-Gene platform using IOMMU translation. v1 change: * Use the CONFIG_ARM64_DMA_HAS_IOMMU for dma-mapping. Signed-off-by: Suman Tripathi stripa...@apm.com --- Suman Tripathi (2): mmc: host: arasan: Add addition of-arasan quirks and IOMMU support for arasan SDHCI driver. arm64: dts: Add the arasan sdhc nodes in apm-storm.dtsi. arch/arm64/boot/dts/apm-storm.dtsi | 43 +++ drivers/mmc/host/Makefile | 2 ++ drivers/mmc/host/sdhci-ahbc-xgene.c | 58 + drivers/mmc/host/sdhci-ahbc-xgene.h | 49 +++ drivers/mmc/host/sdhci-of-arasan.c | 11 +++ drivers/mmc/host/sdhci-pltfm.c | 12 6 files changed, 175 insertions(+) create mode 100644 drivers/mmc/host/sdhci-ahbc-xgene.c create mode 100644 drivers/mmc/host/sdhci-ahbc-xgene.h -- 1.8.2.1 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH v1 2/2] arm64: dts: Add the arasan sdhc nodes in apm-storm.dtsi.
Hi Arnd,
On Tuesday 27 January 2015 22:51:00 Suman Tripathi wrote:
+ sdhc0: sdhc@1c00 {
+ device_type = sdhc;
+ compatible = arasan,sdhci-8.9a;
+ reg = 0x0 0x1c00 0x0 0x100;
+ interrupts = 0x0 0x49 0x4;
+ clock-names = clk_xin, clk_ahb;
+ clocks = sdioclk 0, ahbclk 0;
+ };
+
Here you don't provide an 'iommus' property, which means that the
device is unable to use the iommu.
I added the iommus in the IOMMU AHBC patch. Anything wrong in that ? In the
next version Also I will remove the IOMMU hacks from arasan driver
On Wed, Jan 28, 2015 at 1:43 AM, Arnd Bergmann a...@arndb.de wrote:
On Tuesday 27 January 2015 22:51:00 Suman Tripathi wrote:
+ sdhc0: sdhc@1c00 {
+ device_type = sdhc;
+ compatible = arasan,sdhci-8.9a;
+ reg = 0x0 0x1c00 0x0 0x100;
+ interrupts = 0x0 0x49 0x4;
+ clock-names = clk_xin, clk_ahb;
+ clocks = sdioclk 0, ahbclk 0;
+ };
+
Here you don't provide an 'iommus' property, which means that the
device is unable to use the iommu.
Arnd
--
Thanks,
with regards,
Suman Tripathi
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Re: [PATCH v1 2/2] arm64: dts: Add the arasan sdhc nodes in apm-storm.dtsi.
Hi Arnd,
I added the iommus in the IOMMU AHBC patch. Anything wrong in that ?
In the next version Also I will remove the IOMMU hacks from arasan
driver
On Wed, Jan 28, 2015 at 9:48 AM, Suman Tripathi stripa...@apm.com wrote:
Hi Arnd,
On Tuesday 27 January 2015 22:51:00 Suman Tripathi wrote:
+ sdhc0: sdhc@1c00 {
+ device_type = sdhc;
+ compatible = arasan,sdhci-8.9a;
+ reg = 0x0 0x1c00 0x0 0x100;
+ interrupts = 0x0 0x49 0x4;
+ clock-names = clk_xin, clk_ahb;
+ clocks = sdioclk 0, ahbclk 0;
+ };
+
Here you don't provide an 'iommus' property, which means that the
device is unable to use the iommu.
I added the iommus in the IOMMU AHBC patch. Anything wrong in that ? In the
next version Also I will remove the IOMMU hacks from arasan driver
On Wed, Jan 28, 2015 at 1:43 AM, Arnd Bergmann a...@arndb.de wrote:
On Tuesday 27 January 2015 22:51:00 Suman Tripathi wrote:
+ sdhc0: sdhc@1c00 {
+ device_type = sdhc;
+ compatible = arasan,sdhci-8.9a;
+ reg = 0x0 0x1c00 0x0 0x100;
+ interrupts = 0x0 0x49 0x4;
+ clock-names = clk_xin, clk_ahb;
+ clocks = sdioclk 0, ahbclk 0;
+ };
+
Here you don't provide an 'iommus' property, which means that the
device is unable to use the iommu.
Arnd
--
Thanks,
with regards,
Suman Tripathi
--
Thanks,
with regards,
Suman Tripathi
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Re: [PATCH 1/2] mmc: host: arasan: Add addition of-arasan quirks and add IOMMU support.
Hi Arnd,
On Monday 15 December 2014 22:31:06 Suman Tripathi wrote:
@@ -162,6 +206,16 @@ static int sdhci_arasan_probe(struct platform_device
*pdev)
goto clk_dis_ahb;
}
+#if defined(CONFIG_IOMMU_SUPPORT)
+ sdhci_arasan-domain = iommu_domain_alloc(amba_bustype);
+ if (!sdhci_arasan-domain) {
+ dev_err(pdev-dev, Unable to allocate iommu domain\n);
+ return PTR_ERR(sdhci_arasan-domain);
+ }
+
+ iommu_attach_device(sdhci_arasan-domain, pdev-dev);
+#endif
+
Device drivers should never care about the implementation details
of the iommu. Please change the code to use the regular dma_map_*
interfaces that will work both with and without IOMMU.
After refer to iommu binding , there is a service that allows Remap
address space to allow devices to access physical memory ranges that
they otherwise wouldn't be capable of accessing. eg : 32-bit to 64
bit DMA .
So do we have any existing driver that uses this service ? Just asking
for suggestions.
On Tue, Dec 16, 2014 at 2:57 AM, Arnd Bergmann a...@arndb.de wrote:
On Monday 15 December 2014 22:31:06 Suman Tripathi wrote:
@@ -162,6 +206,16 @@ static int sdhci_arasan_probe(struct platform_device
*pdev)
goto clk_dis_ahb;
}
+#if defined(CONFIG_IOMMU_SUPPORT)
+ sdhci_arasan-domain = iommu_domain_alloc(amba_bustype);
+ if (!sdhci_arasan-domain) {
+ dev_err(pdev-dev, Unable to allocate iommu domain\n);
+ return PTR_ERR(sdhci_arasan-domain);
+ }
+
+ iommu_attach_device(sdhci_arasan-domain, pdev-dev);
+#endif
+
Device drivers should never care about the implementation details
of the iommu. Please change the code to use the regular dma_map_*
interfaces that will work both with and without IOMMU.
Arnd
--
Thanks,
with regards,
Suman Tripathi
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[PATCH 0/2] Add SDHCI support for APM X-Gene SoC using ARASAN SDHCI controller.
Due to the fact that the existing of-arasan driver works with 32-bit platforms. This patch tweaks existing of-arasan driver to work with 64-bit X-Gene platform using IOMMU translation. Signed-off-by: Suman Tripathi stripa...@apm.com --- Suman Tripathi (2): mmc: host: arasan: Add addition of-arasan quirks and add IOMMU support. arm64: dts: Add APM X-Gene SDHCI DTS node. arch/arm64/boot/dts/apm-storm.dtsi | 43 ++ drivers/mmc/host/Kconfig | 1 + drivers/mmc/host/sdhci-of-arasan.c | 54 ++ drivers/mmc/host/sdhci-pltfm.c | 12 + 4 files changed, 110 insertions(+) -- 1.8.2.1 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 2/2] arm64: dts: Add APM X-Gene SDHCI DTS node.
This patch adds the ahbclk and sdhciclk clock nodes and
the sdhci device tree nodes of APM X-Gene SDHCI controller.
Signed-off-by: Suman Tripathi stripa...@apm.com
---
arch/arm64/boot/dts/apm-storm.dtsi | 43 ++
1 file changed, 43 insertions(+)
diff --git a/arch/arm64/boot/dts/apm-storm.dtsi
b/arch/arm64/boot/dts/apm-storm.dtsi
index c0aceef..18e291b 100644
--- a/arch/arm64/boot/dts/apm-storm.dtsi
+++ b/arch/arm64/boot/dts/apm-storm.dtsi
@@ -144,6 +144,40 @@
clock-output-names = socplldiv2;
};
+ ahbclk: ahbclk@1f2ac000 {
+ compatible = apm,xgene-device-clock;
+ #clock-cells = 1;
+ clocks = socplldiv2 0;
+ reg = 0x0 0x1f2ac000 0x0 0x1000
+ 0x0 0x1700 0x0 0x2000;
+ reg-names = csr-reg, div-reg;
+ csr-offset = 0x0;
+ csr-mask = 0x1;
+ enable-offset = 0x8;
+ enable-mask = 0x1;
+ divider-offset = 0x164;
+ divider-width = 0x5;
+ divider-shift = 0x0;
+ clock-output-names = ahbclk;
+ };
+
+ sdioclk: sdioclk@1f2ac000 {
+ compatible = apm,xgene-device-clock;
+ #clock-cells = 1;
+ clocks = socplldiv2 0;
+ reg = 0x0 0x1f2ac000 0x0 0x1000
+ 0x0 0x1700 0x0 0x2000;
+ reg-names = csr-reg, div-reg;
+ csr-offset = 0x0;
+ csr-mask = 0x2;
+ enable-offset = 0x8;
+ enable-mask = 0x2;
+ divider-offset = 0x178;
+ divider-width = 0x8;
+ divider-shift = 0x0;
+ clock-output-names = sdioclk;
+ };
+
qmlclk: qmlclk {
compatible = apm,xgene-device-clock;
#clock-cells = 1;
@@ -397,6 +431,15 @@
clocks = rtcclk 0;
};
+ sdhc0: sdhc@1c00 {
+ device_type = sdhc;
+ compatible = arasan,sdhci-8.9a;
+ reg = 0x0 0x1c00 0x0 0x100;
+ interrupts = 0x0 0x49 0x4;
+ clock-names = clk_xin, clk_ahb;
+ clocks = sdioclk 0, ahbclk 0;
+ };
+
menet: ethernet@1702 {
compatible = apm,xgene-enet;
status = disabled;
--
1.8.2.1
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[PATCH 1/2] mmc: host: arasan: Add addition of-arasan quirks and add IOMMU support.
Due to the fact that the existing of-arasan driver works with 32-bit platforms.
This patch tweaks existing of-arasan driver to work with 64-bit platform using
IOMMU translation.
In addition it adds support for more quirks and quirks2 obtained from device
tree
inside the generic sdhci-platform(sdhci-pltfm.c) driver.
Signed-off-by: Suman Tripathi stripa...@apm.com
---
drivers/mmc/host/Kconfig | 1 +
drivers/mmc/host/sdhci-of-arasan.c | 54 ++
drivers/mmc/host/sdhci-pltfm.c | 12 +
3 files changed, 67 insertions(+)
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 4511358..0c6dc47 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -108,6 +108,7 @@ config MMC_SDHCI_OF_ARASAN
tristate SDHCI OF support for the Arasan SDHCI controllers
depends on MMC_SDHCI_PLTFM
depends on OF
+ select MMC_SDHCI_IO_ACCESSORS
help
This selects the Arasan Secure Digital Host Controller Interface
(SDHCI). This hardware is found e.g. in Xilinx' Zynq SoC.
diff --git a/drivers/mmc/host/sdhci-of-arasan.c
b/drivers/mmc/host/sdhci-of-arasan.c
index 5bd1092..c0e0c9b 100644
--- a/drivers/mmc/host/sdhci-of-arasan.c
+++ b/drivers/mmc/host/sdhci-of-arasan.c
@@ -20,6 +20,10 @@
*/
#include linux/module.h
+#if defined(CONFIG_IOMMU_SUPPORT)
+#include linux/amba/bus.h
+#include linux/iommu.h
+#endif
#include sdhci-pltfm.h
#define SDHCI_ARASAN_CLK_CTRL_OFFSET 0x2c
@@ -34,8 +38,46 @@
*/
struct sdhci_arasan_data {
struct clk *clk_ahb;
+#if defined(CONFIG_IOMMU_SUPPORT)
+ struct iommu_domain *domain;
+#endif
};
+static void sdhci_arasan_write_l(struct sdhci_host *host, u32 val, int reg)
+{
+#if defined(CONFIG_IOMMU_SUPPORT)
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct sdhci_arasan_data *sdhci_arasan = pltfm_host-priv;
+ /*
+* This allows the arasan IP to integrate with 64-bit platform.
+* As the AHB dma masters generates 32-bit address so it needs
+* IO translation of 32-bit to 42-bit AXI address with help of IOMMU.
+*/
+ if (reg == SDHCI_DMA_ADDRESS) {
+ phys_addr_t dma_addr = sg_dma_address(host-data-sg);
+ sdhci_arasan-domain-ops-map(sdhci_arasan-domain, 0,
+ dma_addr, 0, 0);
+ }
+#endif
+ writel(val, host-ioaddr + reg);
+}
+
+static u32 xgene_sdhci_readl(struct sdhci_host *host, int reg)
+{
+#if defined(CONFIG_IOMMU_SUPPORT)
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct sdhci_arasan_data *sdhci_arasan = pltfm_host-priv;
+
+ if (reg == SDHCI_INT_STATUS ) {
+ if ((readl(host-ioaddr + reg) SDHCI_INT_DATA_MASK) ==
+SDHCI_INT_DMA_END)
+ sdhci_arasan-domain-ops-unmap(sdhci_arasan-domain,
+0, 0);
+ }
+#endif
+ return readl(host-ioaddr + reg);
+}
+
static unsigned int sdhci_arasan_get_timeout_clock(struct sdhci_host *host)
{
u32 div;
@@ -58,6 +100,8 @@ static struct sdhci_ops sdhci_arasan_ops = {
.set_bus_width = sdhci_set_bus_width,
.reset = sdhci_reset,
.set_uhs_signaling = sdhci_set_uhs_signaling,
+ .write_l = sdhci_arasan_write_l,
+ .read_l = xgene_sdhci_readl,
};
static struct sdhci_pltfm_data sdhci_arasan_pdata = {
@@ -162,6 +206,16 @@ static int sdhci_arasan_probe(struct platform_device *pdev)
goto clk_dis_ahb;
}
+#if defined(CONFIG_IOMMU_SUPPORT)
+ sdhci_arasan-domain = iommu_domain_alloc(amba_bustype);
+ if (!sdhci_arasan-domain) {
+ dev_err(pdev-dev, Unable to allocate iommu domain\n);
+ return PTR_ERR(sdhci_arasan-domain);
+ }
+
+ iommu_attach_device(sdhci_arasan-domain, pdev-dev);
+#endif
+
host = sdhci_pltfm_init(pdev, sdhci_arasan_pdata, 0);
if (IS_ERR(host)) {
ret = PTR_ERR(host);
diff --git a/drivers/mmc/host/sdhci-pltfm.c b/drivers/mmc/host/sdhci-pltfm.c
index 7e834fb..08a97dc 100644
--- a/drivers/mmc/host/sdhci-pltfm.c
+++ b/drivers/mmc/host/sdhci-pltfm.c
@@ -90,6 +90,18 @@ void sdhci_get_of_property(struct platform_device *pdev)
if (of_get_property(np, broken-cd, NULL))
host-quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
+ if (of_get_property(np, delay-after-power, NULL))
+ host-quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER;
+
+ if (of_get_property(np, no-hispd, NULL))
+ host-quirks |= SDHCI_QUIRK_NO_HISPD_BIT;
+
+ if (of_get_property(np, broken-adma, NULL))
+ host-quirks |= SDHCI_QUIRK_BROKEN_ADMA;
+
+ if (of_get_property(np, no-cmd23, NULL))
+ host-quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23
