RE: [EXT] [PATCH 2/2] clk: qoriq: add cpufreq platform device
> -Original Message-
> From: Mian Yousaf Kaukab
> Sent: 2020年4月4日 5:21
> To: linux...@vger.kernel.org; Andy Tang ;
> shawn...@kernel.org; Leo Li
> Cc: viresh.ku...@linaro.org; linux-ker...@vger.kernel.org;
> linux-arm-ker...@lists.infradead.org; linuxppc-dev@lists.ozlabs.org; Mian
> Yousaf Kaukab
> Subject: [EXT] [PATCH 2/2] clk: qoriq: add cpufreq platform device
>
> Caution: EXT Email
>
> Add a platform device for qoirq-cpufreq driver for the compatible clockgen
> blocks.
>
> Signed-off-by: Mian Yousaf Kaukab
> ---
> drivers/clk/clk-qoriq.c | 30 +++---
> 1 file changed, 27 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c index
> d5946f7486d6..374afcab89af 100644
> --- a/drivers/clk/clk-qoriq.c
> +++ b/drivers/clk/clk-qoriq.c
> @@ -95,6 +95,7 @@ struct clockgen {
> };
>
For both patches,
Reviewed-by: Yuantian Tang
BR,
Andy
RE: [PATCH 1/2 v3] powerpc/fsl: Use new clockgen binding
> -Original Message-
> From: Scott Wood
> Sent: 2018年11月26日 9:19
> To: Andy Tang
> Cc: mturque...@baylibre.com; sb...@kernel.org; robh...@kernel.org;
> mark.rutl...@arm.com; b...@kernel.crashing.org; pau...@samba.org;
> m...@ellerman.id.au; linux-...@vger.kernel.org;
> devicet...@vger.kernel.org; linux-ker...@vger.kernel.org;
> linuxppc-dev@lists.ozlabs.org
> Subject: Re: [PATCH 1/2 v3] powerpc/fsl: Use new clockgen binding
>
> On Wed, 2018-10-31 at 14:57 +0800, Yuantian Tang wrote:
> > From: Scott Wood
> >
> > The driver retains compatibility with old device trees, but we don't
> > want the old nodes lying around to be copied, or used as a reference
> > (some of the mux options are incorrect), or even just being clutter.
> >
> >
> > +sysclk: sysclk {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <1>;
> > + clock-output-names = "sysclk";
> > +};
> > +
> > clockgen: global-utilities@e1000 {
>
> The U-Boot fixup won't work with this. U-Boot patches the frequency
> directly into the clockgen node (BTW, this is another reason to preserve
> the generic
> 1.0/2.0 compatible string). The new binding does not require an input
> clock node when it is provided as clock-frequency directly in the clockgen
> node -- and the sysclk node was not in my original patch (nor did you note
> that you made changes from that original). Why did you add it?
>
> I would just remove it when applying, but I'm concerned that this indicates
> a lack of testing (and I don't have the hardware access to test it myself,
> except on t4240) -- unless the 100 MHz sysclk just happened to be correct
> on the machines you tested (which would also be a test coverage
> problem)?
[Andy] You are right. Sysclk may not be useful anymore.
Uboot will fixup the clockgen node correctly. Please apply this patch without
sysclk. We will
test it and catch the error if the clock is not fixed correctly.
BTW, which git tree are you going to apply it on? This one?
https://git.kernel.org/pub/scm/linux/kernel/git/scottwood/linux.git/log/?h=next
BR,
Andy
>
> -Scott
>
RE: [PATCH 1/2 v3] powerpc/fsl: Use new clockgen binding
Hi Scott,
Any comments on this patch set?
BR,
Andy
> -Original Message-
> From: Yuantian Tang
> Sent: 2018年10月31日 14:58
> To: o...@buserror.net
> Cc: mturque...@baylibre.com; sb...@kernel.org; robh...@kernel.org;
> mark.rutl...@arm.com; b...@kernel.crashing.org; pau...@samba.org;
> m...@ellerman.id.au; linux-...@vger.kernel.org;
> devicet...@vger.kernel.org; linux-ker...@vger.kernel.org;
> linuxppc-dev@lists.ozlabs.org; Andy Tang
> Subject: [PATCH 1/2 v3] powerpc/fsl: Use new clockgen binding
>
> From: Scott Wood
>
> The driver retains compatibility with old device trees, but we don't want
> the old nodes lying around to be copied, or used as a reference (some of
> the mux options are incorrect), or even just being clutter.
>
> Signed-off-by: Scott Wood
> Signed-off-by: Tang Yuantian
> ---
> v3:
> - update the commit message
> - split the dts and driver to different patchset
>
> arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi |4 +-
> arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi |8 ++--
> arch/powerpc/boot/dts/fsl/b4si-post.dtsi | 15 -
> arch/powerpc/boot/dts/fsl/p2041si-post.dtsi| 18 --
> arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi |8 ++--
> arch/powerpc/boot/dts/fsl/p3041si-post.dtsi| 18 --
> arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi |8 ++--
> arch/powerpc/boot/dts/fsl/p4080si-post.dtsi| 70
>
> arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi | 16 +++---
> arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi |4 +-
> arch/powerpc/boot/dts/fsl/p5040si-post.dtsi| 18 --
> arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi |8 ++--
> arch/powerpc/boot/dts/fsl/qoriq-clockgen1.dtsi | 55 +++
> arch/powerpc/boot/dts/fsl/qoriq-clockgen2.dtsi | 38 +++--
> arch/powerpc/boot/dts/fsl/t1023si-post.dtsi| 16 --
> arch/powerpc/boot/dts/fsl/t102xsi-pre.dtsi |4 +-
> arch/powerpc/boot/dts/fsl/t1040si-post.dtsi| 44 ---
> arch/powerpc/boot/dts/fsl/t104xsi-pre.dtsi |8 ++--
> arch/powerpc/boot/dts/fsl/t2081si-post.dtsi| 22
> arch/powerpc/boot/dts/fsl/t208xsi-pre.dtsi |8 ++--
> arch/powerpc/boot/dts/fsl/t4240si-post.dtsi| 61 -
> arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi | 24
> 22 files changed, 66 insertions(+), 409 deletions(-)
>
> diff --git a/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
> b/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
> index 88d8423..bb7b9b9 100644
> --- a/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
> +++ b/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
> @@ -70,14 +70,14 @@
> cpu0: PowerPC,e6500@0 {
> device_type = "cpu";
> reg = <0 1>;
> - clocks = <&mux0>;
> + clocks = <&clockgen 1 0>;
> next-level-cache = <&L2_1>;
> fsl,portid-mapping = <0x8000>;
> };
> cpu1: PowerPC,e6500@2 {
> device_type = "cpu";
> reg = <2 3>;
> - clocks = <&mux0>;
> + clocks = <&clockgen 1 0>;
> next-level-cache = <&L2_1>;
> fsl,portid-mapping = <0x8000>;
> };
> diff --git a/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
> b/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
> index f3f968c..388ba1b 100644
> --- a/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
> +++ b/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
> @@ -75,28 +75,28 @@
> cpu0: PowerPC,e6500@0 {
> device_type = "cpu";
> reg = <0 1>;
> - clocks = <&mux0>;
> + clocks = <&clockgen 1 0>;
> next-level-cache = <&L2_1>;
> fsl,portid-mapping = <0x8000>;
> };
> cpu1: PowerPC,e6500@2 {
> device_type = "cpu";
> reg = <2 3>;
> - clocks = <&mux0>;
> + clocks = <&clockgen 1 0>;
> next-level-cache = <&L2_1>;
> fsl,portid-mapping = <0x8000>;
> };
> cpu2: PowerPC,e6500@4 {
> device_type = "cpu";
> reg = <4 5>;
> -
RE: [PATCH 2/3 v2] clk: qoriq: remove legacy bindings and add more compatibles
> -Original Message- > From: Rob Herring > Sent: 2018年10月25日 6:11 > To: Andy Tang > Cc: sb...@kernel.org; mturque...@baylibre.com; o...@buserror.net; > mark.rutl...@arm.com; b...@kernel.crashing.org; pau...@samba.org; > m...@ellerman.id.au; linux-...@vger.kernel.org; > devicet...@vger.kernel.org; linux-ker...@vger.kernel.org; > linuxppc-dev@lists.ozlabs.org > Subject: Re: [PATCH 2/3 v2] clk: qoriq: remove legacy bindings and add > more compatibles > > On Wed, Oct 24, 2018 at 10:11:21AM +0800, andy.t...@nxp.com wrote: > > From: Yuantian Tang > > > > The new bindings will be used, so delete the old bindings. > > Add more SOC compatibles as needed as well. > > I'm a bit confused by this series. Normally you want to update the dts files > first and wait some period of time before removing driver support (and > bindings). Thanks, got your points. BR, Andy > > Rob > > > > > Signed-off-by: Tang Yuantian > > --- > > v2: > > - involve more chips > > > > .../devicetree/bindings/clock/qoriq-clock.txt | 112 > +-- > > 1 files changed, 6 insertions(+), 106 deletions(-)
RE: [PATCH 3/3 v2] clk: qoriq: update clock driver
> -Original Message- > From: Scott Wood > Sent: 2018年10月25日 2:37 > To: Andy Tang ; sb...@kernel.org; > mturque...@baylibre.com > Cc: robh...@kernel.org; mark.rutl...@arm.com; > b...@kernel.crashing.org; pau...@samba.org; m...@ellerman.id.au; > linux-...@vger.kernel.org; devicet...@vger.kernel.org; > linux-ker...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org > Subject: Re: [PATCH 3/3 v2] clk: qoriq: update clock driver > > On Wed, 2018-10-24 at 10:11 +0800, andy.t...@nxp.com wrote: > > From: Yuantian Tang > > > > Legacy bindings are deleted. So the legacy support in driver can be > > deleted safely. > > NACK (both this and 2/3). The legacy support is intended to preserve > compatibility, regardless of what the dts files in the current kernel tree do. > If years later we find it's been broken for a while and nobody complained, > then maybe it'll be time to remove it, but why deliberately throw away > compatibility the instant the users have been removed from reference > DTs that might be copied by board vendors, etc? > > Note that even if we didn't care about long-term compatibility at all, > removing the support in the same patchset as the change to the dts files > means that the patches can't go in via separate trees (though if that's still > the intent, you should make it clear who you're asking to take what by > putting them in separate patchsets). Points are taken. Will update this patch set. Thanks a lot. BR, Andy > > -Scott
[PATCH 1/3 v2] powerpc/fsl: Use new clockgen binding
From: Scott Wood
The driver retains compatibility with old device trees, but we don't
want the old nodes lying around to be copied, or used as a reference
(some of the mux options are incorrect), or even just being clutter.
We will also need the #clock-cells in the clockgen node in order to
add fman nodes.
Signed-off-by: Scott Wood
Signed-off-by: Tang Yuantian
---
v2:
- involve more soc
arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi |4 +-
arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi |8 ++--
arch/powerpc/boot/dts/fsl/b4si-post.dtsi | 15 -
arch/powerpc/boot/dts/fsl/p2041si-post.dtsi| 18 --
arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi |8 ++--
arch/powerpc/boot/dts/fsl/p3041si-post.dtsi| 18 --
arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi |8 ++--
arch/powerpc/boot/dts/fsl/p4080si-post.dtsi| 70
arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi | 16 +++---
arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi |4 +-
arch/powerpc/boot/dts/fsl/p5040si-post.dtsi| 18 --
arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi |8 ++--
arch/powerpc/boot/dts/fsl/qoriq-clockgen1.dtsi | 55 +++
arch/powerpc/boot/dts/fsl/qoriq-clockgen2.dtsi | 38 +++--
arch/powerpc/boot/dts/fsl/t1023si-post.dtsi| 16 --
arch/powerpc/boot/dts/fsl/t102xsi-pre.dtsi |4 +-
arch/powerpc/boot/dts/fsl/t1040si-post.dtsi| 44 ---
arch/powerpc/boot/dts/fsl/t104xsi-pre.dtsi |8 ++--
arch/powerpc/boot/dts/fsl/t2081si-post.dtsi| 22
arch/powerpc/boot/dts/fsl/t208xsi-pre.dtsi |8 ++--
arch/powerpc/boot/dts/fsl/t4240si-post.dtsi| 61 -
arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi | 24
22 files changed, 66 insertions(+), 409 deletions(-)
diff --git a/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
b/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
index 88d8423..bb7b9b9 100644
--- a/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
@@ -70,14 +70,14 @@
cpu0: PowerPC,e6500@0 {
device_type = "cpu";
reg = <0 1>;
- clocks = <&mux0>;
+ clocks = <&clockgen 1 0>;
next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x8000>;
};
cpu1: PowerPC,e6500@2 {
device_type = "cpu";
reg = <2 3>;
- clocks = <&mux0>;
+ clocks = <&clockgen 1 0>;
next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x8000>;
};
diff --git a/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
b/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
index f3f968c..388ba1b 100644
--- a/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
@@ -75,28 +75,28 @@
cpu0: PowerPC,e6500@0 {
device_type = "cpu";
reg = <0 1>;
- clocks = <&mux0>;
+ clocks = <&clockgen 1 0>;
next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x8000>;
};
cpu1: PowerPC,e6500@2 {
device_type = "cpu";
reg = <2 3>;
- clocks = <&mux0>;
+ clocks = <&clockgen 1 0>;
next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x8000>;
};
cpu2: PowerPC,e6500@4 {
device_type = "cpu";
reg = <4 5>;
- clocks = <&mux0>;
+ clocks = <&clockgen 1 0>;
next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x8000>;
};
cpu3: PowerPC,e6500@6 {
device_type = "cpu";
reg = <6 7>;
- clocks = <&mux0>;
+ clocks = <&clockgen 1 0>;
next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x8000>;
};
diff --git a/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
b/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
index 1b33f51..4f044b4 100644
--- a/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
@@ -398,21 +398,6 @@
};
/include/ "qoriq-clockgen2.dtsi"
- clockgen: global-utilities@e1000 {
- compatible = "fsl,b4-clockgen", "fsl,qoriq-clockgen-2.0";
- reg = <0xe1000 0x1000>;
-
- mux0: mux0@0 {
- #clock-cells = <0>;
- reg = <0x0 0x4>;
-
[PATCH 2/3 v2] clk: qoriq: remove legacy bindings and add more compatibles
From: Yuantian Tang
The new bindings will be used, so delete the old bindings.
Add more SOC compatibles as needed as well.
Signed-off-by: Tang Yuantian
---
v2:
- involve more chips
.../devicetree/bindings/clock/qoriq-clock.txt | 112 +--
1 files changed, 6 insertions(+), 106 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
index 97f46ad..8484d90 100644
--- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
+++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
@@ -28,6 +28,12 @@ Required properties:
* "fsl,p4080-clockgen"
* "fsl,p5020-clockgen"
* "fsl,p5040-clockgen"
+ * "fsl,t1023-clockgen"
+ * "fsl,t1024-clockgen"
+ * "fsl,t1040-clockgen"
+ * "fsl,t1042-clockgen"
+ * "fsl,t2080-clockgen"
+ * "fsl,t2081-clockgen"
* "fsl,t4240-clockgen"
* "fsl,b4420-clockgen"
* "fsl,b4860-clockgen"
@@ -96,109 +102,3 @@ second cell is the clock index for the specified type.
...
};
}
-4. Legacy Child Nodes
-
-NOTE: These nodes are deprecated. Kernels should continue to support
-device trees with these nodes, but new device trees should not use them.
-
-Most of the bindings are from the common clock binding[1].
- [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
-
-Required properties:
-- compatible : Should include one of the following:
- * "fsl,qoriq-core-pll-1.0" for core PLL clocks (v1.0)
- * "fsl,qoriq-core-pll-2.0" for core PLL clocks (v2.0)
- * "fsl,qoriq-core-mux-1.0" for core mux clocks (v1.0)
- * "fsl,qoriq-core-mux-2.0" for core mux clocks (v2.0)
- * "fsl,qoriq-sysclk-1.0": for input system clock (v1.0).
- It takes parent's clock-frequency as its clock.
- * "fsl,qoriq-sysclk-2.0": for input system clock (v2.0).
- It takes parent's clock-frequency as its clock.
- * "fsl,qoriq-platform-pll-1.0" for the platform PLL clock (v1.0)
- * "fsl,qoriq-platform-pll-2.0" for the platform PLL clock (v2.0)
-- #clock-cells: From common clock binding. The number of cells in a
- clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0"
- clocks, or <1> for "fsl,qoriq-core-pll-[1,2].0" clocks.
- For "fsl,qoriq-core-pll-[1,2].0" clocks, the single
- clock-specifier cell may take the following values:
- * 0 - equal to the PLL frequency
- * 1 - equal to the PLL frequency divided by 2
- * 2 - equal to the PLL frequency divided by 4
-
-Recommended properties:
-- clocks: Should be the phandle of input parent clock
-- clock-names: From common clock binding, indicates the clock name
-- clock-output-names: From common clock binding, indicates the names of
- output clocks
-- reg: Should be the offset and length of clock block base address.
- The length should be 4.
-
-Legacy Example:
-/ {
- clockgen: global-utilities@e1000 {
- compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
- ranges = <0x0 0xe1000 0x1000>;
- clock-frequency = <1>;
- reg = <0xe1000 0x1000>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- sysclk: sysclk {
- #clock-cells = <0>;
- compatible = "fsl,qoriq-sysclk-1.0";
- clock-output-names = "sysclk";
- };
-
- pll0: pll0@800 {
- #clock-cells = <1>;
- reg = <0x800 0x4>;
- compatible = "fsl,qoriq-core-pll-1.0";
- clocks = <&sysclk>;
- clock-output-names = "pll0", "pll0-div2";
- };
-
- pll1: pll1@820 {
- #clock-cells = <1>;
- reg = <0x820 0x4>;
- compatible = "fsl,qoriq-core-pll-1.0";
- clocks = <&sysclk>;
- clock-output-names = "pll1", "pll1-div2";
- };
-
- mux0: mux0@0 {
- #clock-cells = <0>;
- reg = <0x0 0x4>;
- compatible = "fsl,qoriq-core-mux-1.0";
- clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
- clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
- clock-output-names = "cmux0";
- };
-
- mux1: mux1@20 {
- #clock-cells = <0>;
- reg = <0x20 0x4>;
- compatible = "fsl,qoriq-core-mux-1.0";
- clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
- clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
- clock-output-names = "cmux1";
- };
-
-
[PATCH 3/3 v2] clk: qoriq: update clock driver
From: Yuantian Tang
Legacy bindings are deleted. So the legacy support in driver
can be deleted safely.
Add more chip-specific compatible as well to support more Socs.
Signed-off-by: Tang Yuantian
---
v2:
- remove all legacy code
drivers/clk/clk-qoriq.c | 159 +++---
1 files changed, 11 insertions(+), 148 deletions(-)
diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
index 3a1812f..405a9ab 100644
--- a/drivers/clk/clk-qoriq.c
+++ b/drivers/clk/clk-qoriq.c
@@ -914,43 +914,6 @@ static void __init create_muxes(struct clockgen *cg)
}
}
-static void __init clockgen_init(struct device_node *np);
-
-/*
- * Legacy nodes may get probed before the parent clockgen node.
- * It is assumed that device trees with legacy nodes will not
- * contain a "clocks" property -- otherwise the input clocks may
- * not be initialized at this point.
- */
-static void __init legacy_init_clockgen(struct device_node *np)
-{
- if (!clockgen.node)
- clockgen_init(of_get_parent(np));
-}
-
-/* Legacy node */
-static void __init core_mux_init(struct device_node *np)
-{
- struct clk *clk;
- struct resource res;
- int idx, rc;
-
- legacy_init_clockgen(np);
-
- if (of_address_to_resource(np, 0, &res))
- return;
-
- idx = (res.start & 0xf0) >> 5;
- clk = clockgen.cmux[idx];
-
- rc = of_clk_add_provider(np, of_clk_src_simple_get, clk);
- if (rc) {
- pr_err("%s: Couldn't register clk provider for node %s: %d\n",
- __func__, np->name, rc);
- return;
- }
-}
-
static struct clk __init
*sysclk_from_fixed(struct device_node *node, const char *name)
{
@@ -1036,30 +999,9 @@ static void __init core_mux_init(struct device_node *np)
if (!IS_ERR(clk))
return clk;
- /*
-* This indicates a mix of legacy nodes with the new coreclk
-* mechanism, which should never happen. If this error occurs,
-* don't use the wrong input clock just because coreclk isn't
-* ready yet.
-*/
- if (WARN_ON(PTR_ERR(clk) == -EPROBE_DEFER))
- return clk;
-
return NULL;
}
-/* Legacy node */
-static void __init sysclk_init(struct device_node *node)
-{
- struct clk *clk;
-
- legacy_init_clockgen(node);
-
- clk = clockgen.sysclk;
- if (clk)
- of_clk_add_provider(node, of_clk_src_simple_get, clk);
-}
-
#define PLL_KILL BIT(31)
static void __init create_one_pll(struct clockgen *cg, int idx)
@@ -1162,82 +1104,6 @@ static void __init create_plls(struct clockgen *cg)
create_one_pll(cg, i);
}
-static void __init legacy_pll_init(struct device_node *np, int idx)
-{
- struct clockgen_pll *pll;
- struct clk_onecell_data *onecell_data;
- struct clk **subclks;
- int count, rc;
-
- legacy_init_clockgen(np);
-
- pll = &clockgen.pll[idx];
- count = of_property_count_strings(np, "clock-output-names");
-
- BUILD_BUG_ON(ARRAY_SIZE(pll->div) < 4);
- subclks = kcalloc(4, sizeof(struct clk *), GFP_KERNEL);
- if (!subclks)
- return;
-
- onecell_data = kmalloc(sizeof(*onecell_data), GFP_KERNEL);
- if (!onecell_data)
- goto err_clks;
-
- if (count <= 3) {
- subclks[0] = pll->div[0].clk;
- subclks[1] = pll->div[1].clk;
- subclks[2] = pll->div[3].clk;
- } else {
- subclks[0] = pll->div[0].clk;
- subclks[1] = pll->div[1].clk;
- subclks[2] = pll->div[2].clk;
- subclks[3] = pll->div[3].clk;
- }
-
- onecell_data->clks = subclks;
- onecell_data->clk_num = count;
-
- rc = of_clk_add_provider(np, of_clk_src_onecell_get, onecell_data);
- if (rc) {
- pr_err("%s: Couldn't register clk provider for node %s: %d\n",
- __func__, np->name, rc);
- goto err_cell;
- }
-
- return;
-err_cell:
- kfree(onecell_data);
-err_clks:
- kfree(subclks);
-}
-
-/* Legacy node */
-static void __init pltfrm_pll_init(struct device_node *np)
-{
- legacy_pll_init(np, PLATFORM_PLL);
-}
-
-/* Legacy node */
-static void __init core_pll_init(struct device_node *np)
-{
- struct resource res;
- int idx;
-
- if (of_address_to_resource(np, 0, &res))
- return;
-
- if ((res.start & 0xfff) == 0xc00) {
- /*
-* ls1021a devtree labels the platform PLL
-* with the core PLL compatible
-*/
- pltfrm_pll_init(np);
- } else {
- idx = (res.start & 0xf0) >> 5;
- legacy_pll_init(np, CGA_PLL1 + idx);
- }
-}
-
static struct clk *clockgen_clk_get(struct of_phandle_args *clkspec, void
*data)
{
struct clockgen *cg = data;
@@
RE: [PATCH] powerpc/mpc85xx: fix issues in clock node
Hi Scott,
What you said makes sense well. I will resend the patch.
Thanks,
Andy
> -Original Message-
> From: Scott Wood
> Sent: 2018年9月19日 6:24
> To: Andy Tang
> Cc: robh...@kernel.org; mark.rutl...@arm.com;
> b...@kernel.crashing.org; devicet...@vger.kernel.org;
> linuxppc-dev@lists.ozlabs.org
> Subject: Re: [PATCH] powerpc/mpc85xx: fix issues in clock node
>
> On Tue, 2018-09-11 at 10:12 +0800, andy.t...@nxp.com wrote:
> > From: Yuantian Tang
> >
> > The compatible string is not correct in the clock node.
> > The clocks property refers to the wrong node too.
> > This patch is to fix them.
> >
> > Signed-off-by: Tang Yuantian
> > ---
> > arch/powerpc/boot/dts/fsl/t1023si-post.dtsi |8
> > 1 files changed, 4 insertions(+), 4 deletions(-)
> >
> > diff --git a/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
> > b/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
> > index 4908af5..763caf4 100644
> > --- a/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
> > +++ b/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
> > @@ -348,7 +348,7 @@
> > mux0: mux0@0 {
> > #clock-cells = <0>;
> > reg = <0x0 4>;
> > - compatible = "fsl,core-mux-clock";
> > + compatible = "fsl,qoriq-core-mux-2.0";
> > clocks = <&pll0 0>, <&pll0 1>;
> > clock-names = "pll0_0", "pll0_1";
> > clock-output-names = "cmux0";
> > @@ -356,9 +356,9 @@
> > mux1: mux1@20 {
> > #clock-cells = <0>;
> > reg = <0x20 4>;
> > - compatible = "fsl,core-mux-clock";
> > - clocks = <&pll0 0>, <&pll0 1>;
> > - clock-names = "pll0_0", "pll0_1";
> > + compatible = "fsl,qoriq-core-mux-2.0";
> > + clocks = <&pll1 0>, <&pll1 1>;
> > + clock-names = "pll1_0", "pll1_1";
> > clock-output-names = "cmux1";
> > };
> > };
>
> These are the legacy nodes. Why not just remove them instead of fixing
> them?
> Now that the cpufreq driver is fixed we could get rid of the legacy nodes
> for all the chips.
>
> -Scott
RE: [PATCH] powerpc/mpc85xx: fix issues in clock node
Hi Scott,
Could you please take a look at this patch?
Thanks,
Andy
> -Original Message-
> From: andy.t...@nxp.com
> Sent: 2018年9月11日 10:12
> To: o...@buserror.net
> Cc: robh...@kernel.org; mark.rutl...@arm.com;
> b...@kernel.crashing.org; devicet...@vger.kernel.org;
> linuxppc-dev@lists.ozlabs.org; Andy Tang
> Subject: [PATCH] powerpc/mpc85xx: fix issues in clock node
>
> From: Yuantian Tang
>
> The compatible string is not correct in the clock node.
> The clocks property refers to the wrong node too.
> This patch is to fix them.
>
> Signed-off-by: Tang Yuantian
> ---
> arch/powerpc/boot/dts/fsl/t1023si-post.dtsi |8
> 1 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
> b/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
> index 4908af5..763caf4 100644
> --- a/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
> +++ b/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
> @@ -348,7 +348,7 @@
> mux0: mux0@0 {
> #clock-cells = <0>;
> reg = <0x0 4>;
> - compatible = "fsl,core-mux-clock";
> + compatible = "fsl,qoriq-core-mux-2.0";
> clocks = <&pll0 0>, <&pll0 1>;
> clock-names = "pll0_0", "pll0_1";
> clock-output-names = "cmux0";
> @@ -356,9 +356,9 @@
> mux1: mux1@20 {
> #clock-cells = <0>;
> reg = <0x20 4>;
> - compatible = "fsl,core-mux-clock";
> - clocks = <&pll0 0>, <&pll0 1>;
> - clock-names = "pll0_0", "pll0_1";
> + compatible = "fsl,qoriq-core-mux-2.0";
> + clocks = <&pll1 0>, <&pll1 1>;
> + clock-names = "pll1_0", "pll1_1";
> clock-output-names = "cmux1";
> };
> };
> --
> 1.7.1
[PATCH] powerpc/mpc85xx: fix issues in clock node
From: Yuantian Tang
The compatible string is not correct in the clock node.
The clocks property refers to the wrong node too.
This patch is to fix them.
Signed-off-by: Tang Yuantian
---
arch/powerpc/boot/dts/fsl/t1023si-post.dtsi |8
1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
b/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
index 4908af5..763caf4 100644
--- a/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
@@ -348,7 +348,7 @@
mux0: mux0@0 {
#clock-cells = <0>;
reg = <0x0 4>;
- compatible = "fsl,core-mux-clock";
+ compatible = "fsl,qoriq-core-mux-2.0";
clocks = <&pll0 0>, <&pll0 1>;
clock-names = "pll0_0", "pll0_1";
clock-output-names = "cmux0";
@@ -356,9 +356,9 @@
mux1: mux1@20 {
#clock-cells = <0>;
reg = <0x20 4>;
- compatible = "fsl,core-mux-clock";
- clocks = <&pll0 0>, <&pll0 1>;
- clock-names = "pll0_0", "pll0_1";
+ compatible = "fsl,qoriq-core-mux-2.0";
+ clocks = <&pll1 0>, <&pll1 1>;
+ clock-names = "pll1_0", "pll1_1";
clock-output-names = "cmux1";
};
};
--
1.7.1
RE: [PATCH 3/5] drivers: clk-qoriq: Add clockgen support for lx2160a
Hi Scott, Please see my replay inline. > -Original Message- > From: linux-arm-kernel > On Behalf Of Scott Wood > Sent: 2018年9月4日 4:34 > To: Andy Tang ; Vabhav Sharma > ; linux-ker...@vger.kernel.org; > devicet...@vger.kernel.org; robh...@kernel.org; > mark.rutl...@arm.com; linuxppc-dev@lists.ozlabs.org; > linux-arm-ker...@lists.infradead.org; mturque...@baylibre.com; > sb...@kernel.org; r...@rjwysocki.net; viresh.ku...@linaro.org; > linux-...@vger.kernel.org; linux...@vger.kernel.org; > linux-kernel-ow...@vger.kernel.org; catalin.mari...@arm.com; > will.dea...@arm.com; gre...@linuxfoundation.org; a...@arndb.de; > kstew...@linuxfoundation.org; yamada.masah...@socionext.com > Cc: Yogesh Narayan Gaur ; > li...@armlinux.org.uk; Varun Sethi ; Udit Kumar > > Subject: Re: [PATCH 3/5] drivers: clk-qoriq: Add clockgen support for > lx2160a > > On Mon, 2018-09-03 at 01:17 +, Andy Tang wrote: > > Hi Scott, > > > > Please see my replay in line. > > > > > -Original Message- > > > From: Linuxppc-dev > > > On > > > Behalf Of Scott Wood > > > Sent: 2018年9月1日 4:29 > > > To: Andy Tang ; Vabhav Sharma > > > ; linux-ker...@vger.kernel.org; > > > devicet...@vger.kernel.org; robh...@kernel.org; > > > mark.rutl...@arm.com; linuxppc-dev@lists.ozlabs.org; > > > linux-arm-ker...@lists.infradead.org; mturque...@baylibre.com; > > > sb...@kernel.org; r...@rjwysocki.net; viresh.ku...@linaro.org; > > > linux-...@vger.kernel.org; linux...@vger.kernel.org; > > > linux-kernel-ow...@vger.kernel.org; catalin.mari...@arm.com; > > > will.dea...@arm.com; gre...@linuxfoundation.org; a...@arndb.de; > > > kstew...@linuxfoundation.org; yamada.masah...@socionext.com > > > Cc: Yogesh Narayan Gaur ; > > > li...@armlinux.org.uk; Udit Kumar ; Varun > Sethi > > > > > > Subject: Re: [PATCH 3/5] drivers: clk-qoriq: Add clockgen support > > > for lx2160a > > > > > > On Fri, 2018-08-31 at 06:12 +, Andy Tang wrote: > > > > We don't want to increase NUM_CMUX each time new soc with > more > > > > > > cmuxes added. > > > > > > You don't want to have to make a trivial change each time you exceed > > > a limit that has yet to be exceeded once since NUM_CMUX was added? > > > This isn't ABI or in any other way hard to change. It's right in > > > the same file as the chip description you'd be adding. > > > > > > And even if a chip did come along with 16 cmuxes, you'd then need to > > > increase the array to 17 to hold the -1 if you don't want to leave a > > > situation like the > > > p4080 is in now, where a chip's cmux array could be broken by > > > increasing NUM_CMUX further. > > > > > > > [Andy] Adding buffer to a limitation number is always a good habit > > when coding. We often forget to increase this value when a new chip > > with more cmuxes added. > > "often"? There has never been a new chip added with more cmuxes > than p4080's 8, and if one does come along and you forget, the compiler > should complain about exceeding the array length with a static initializer. > This isn't like an array that is filled with a runtime-determined length. > > > Like this patch, we didn't increase this value at first. We spent a > > lot of time finding out that NUM_CMUX needs to be increased too. > > Are you talking about some other chip that you haven't sent a patch for > yet? > Or is the cmux array for this chip wrong? What specifically did you see > happen "at first"? > [Andy] Sorry, "Often" is not a right word. I meant we tend to add new soc without updating NUM_CMUX. > > It is a personal preference how to set this value. I think it is > > better to increase it to 16, not NUM_CMUX+1 as long as we fix the > > P4080 issue even though it is a trivial change. And I agree the > > description needs to be updated. > > I'm not the clock maintainer, so it's not up to me, but I don't see the point > in setting it to an arbitrary number, and I do not agree that increasing > NUM_CMUX is a suitable replacement for NUM_CMUX+1 in > cmux_to_group[], as that array should be one larger than cmux[] in order > to allow every chip to have a > -1 terminator. In any case, any change to NUM_CMUX should be a > separate patch because it's not required for lx2160a support (assuming > lx2160a was correctly described by this patch). [Andy] I don't see any impropriate about your suggestion. so we are going to do in your way. Thanks, Andy > > -Scott > > > > ___ > linux-arm-kernel mailing list > linux-arm-ker...@lists.infradead.org > https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Flist > s.infradead.org%2Fmailman%2Flistinfo%2Flinux-arm-kernel&data=02 > %7C01%7Candy.tang%40nxp.com%7Cdbc824fc39674711316208d611dcf > 61b%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C63671603 > 8060797113&sdata=iCLKGMEzRX2dpH5%2Bf4NWIiPDc5L5NpTcpZ7X > usehdIw%3D&reserved=0
RE: [PATCH 3/5] drivers: clk-qoriq: Add clockgen support for lx2160a
Hi Scott, Please see my replay in line. > -Original Message- > From: Linuxppc-dev > On > Behalf Of Scott Wood > Sent: 2018年9月1日 4:29 > To: Andy Tang ; Vabhav Sharma > ; linux-ker...@vger.kernel.org; > devicet...@vger.kernel.org; robh...@kernel.org; > mark.rutl...@arm.com; linuxppc-dev@lists.ozlabs.org; > linux-arm-ker...@lists.infradead.org; mturque...@baylibre.com; > sb...@kernel.org; r...@rjwysocki.net; viresh.ku...@linaro.org; > linux-...@vger.kernel.org; linux...@vger.kernel.org; > linux-kernel-ow...@vger.kernel.org; catalin.mari...@arm.com; > will.dea...@arm.com; gre...@linuxfoundation.org; a...@arndb.de; > kstew...@linuxfoundation.org; yamada.masah...@socionext.com > Cc: Yogesh Narayan Gaur ; > li...@armlinux.org.uk; Udit Kumar ; Varun Sethi > > Subject: Re: [PATCH 3/5] drivers: clk-qoriq: Add clockgen support for > lx2160a > > On Fri, 2018-08-31 at 06:12 +, Andy Tang wrote: > > Hi Scott, > > > > Please see my replay inline. > > > > > -Original Message- > > > From: linux-arm-kernel > > > > > > On Behalf Of Scott Wood > > > Sent: 2018年8月31日 1:43 > > > To: Vabhav Sharma ; > > > linux-ker...@vger.kernel.org; devicet...@vger.kernel.org; > > > robh...@kernel.org; mark.rutl...@arm.com; > > > linuxppc-dev@lists.ozlabs.org; linux-arm-ker...@lists.infradead.org; > > > mturque...@baylibre.com; sb...@kernel.org; r...@rjwysocki.net; > > > viresh.ku...@linaro.org; linux-...@vger.kernel.org; > > > linux...@vger.kernel.org; linux-kernel-ow...@vger.kernel.org; > > > catalin.mari...@arm.com; will.dea...@arm.com; > > > gre...@linuxfoundation.org; a...@arndb.de; > > > kstew...@linuxfoundation.org; yamada.masah...@socionext.com > > > Cc: Yogesh Narayan Gaur ; Andy Tang > > > ; li...@armlinux.org.uk; Varun Sethi > > > ; Udit Kumar > > > Subject: Re: [PATCH 3/5] drivers: clk-qoriq: Add clockgen support > > > for lx2160a > > > > > > On Thu, 2018-08-30 at 12:39 -0500, Scott Wood wrote: > > > > On Thu, 2018-08-30 at 07:36 +, Vabhav Sharma wrote: > > > > > > > > > > > > Why are you increasing NUM_CMUX beyond 8 for a chip that > only > > > > > > has > > > > > > 8 entries in cmux_to_group? > > > > > > > > > > Configuration is 16 cores,8 cluster with 2 cores in each cluster > > > > > > > > So? This is about cmuxes, not cores. You're increasing the array > > > > without ever using the new size. > > > > > > Oh, and you also broke p4080 which has 8 cmuxes but no -1 > > > terminator, because the array was of length 8. Probably the array > > > should be changed to NUM_CMUX+1 so every array can be -1 > terminated. > > > > > > > [Andy] How about we add -1 terminator to p4080 and increase > NUM_CMUX to 16? > > Why 16? What does such a change have to do with this chip, which > according to the rest of the patch has 8 cmuxes? [Andy] NUM_CMUX is a limitation number. We better give it an extra buffer, not exactly equal to the limitation. 16 is the limitation number with extra buffer. > > > We don't want to increase NUM_CMUX each time new soc with more > cmuxes added. > > You don't want to have to make a trivial change each time you exceed a > limit that has yet to be exceeded once since NUM_CMUX was added? > This isn't ABI or in any other way hard to change. It's right in the same > file > as the chip description you'd be adding. > > And even if a chip did come along with 16 cmuxes, you'd then need to > increase the array to 17 to hold the -1 if you don't want to leave a situation > like the > p4080 is in now, where a chip's cmux array could be broken by increasing > NUM_CMUX further. > [Andy] Adding buffer to a limitation number is always a good habit when coding. We often forget to increase this value when a new chip with more cmuxes added. Like this patch, we didn't increase this value at first. We spent a lot of time finding out that NUM_CMUX needs to be increased too. It is a personal preference how to set this value. I think it is better to increase it to 16, not NUM_CMUX+1 as long as we fix the P4080 issue even though it is a trivial change. And I agree the description needs to be updated. BR, Andy > -Scott
RE: [PATCH 3/5] drivers: clk-qoriq: Add clockgen support for lx2160a
Hi Scott,
Please see my replay inline.
> -Original Message-
> From: linux-arm-kernel
> On Behalf Of Scott Wood
> Sent: 2018年8月31日 1:43
> To: Vabhav Sharma ;
> linux-ker...@vger.kernel.org; devicet...@vger.kernel.org;
> robh...@kernel.org; mark.rutl...@arm.com;
> linuxppc-dev@lists.ozlabs.org; linux-arm-ker...@lists.infradead.org;
> mturque...@baylibre.com; sb...@kernel.org; r...@rjwysocki.net;
> viresh.ku...@linaro.org; linux-...@vger.kernel.org;
> linux...@vger.kernel.org; linux-kernel-ow...@vger.kernel.org;
> catalin.mari...@arm.com; will.dea...@arm.com;
> gre...@linuxfoundation.org; a...@arndb.de;
> kstew...@linuxfoundation.org; yamada.masah...@socionext.com
> Cc: Yogesh Narayan Gaur ; Andy Tang
> ; li...@armlinux.org.uk; Varun Sethi
> ; Udit Kumar
> Subject: Re: [PATCH 3/5] drivers: clk-qoriq: Add clockgen support for
> lx2160a
>
> On Thu, 2018-08-30 at 12:39 -0500, Scott Wood wrote:
> > On Thu, 2018-08-30 at 07:36 +, Vabhav Sharma wrote:
> > > > -Original Message-
> > > > From: linux-kernel-ow...@vger.kernel.org > > > ow...@vger.kernel.org> On Behalf Of Scott Wood
> > > > Sent: Wednesday, August 29, 2018 5:49 AM
> > > > To: Vabhav Sharma ; linux-
> > > > ker...@vger.kernel.org; devicet...@vger.kernel.org;
> > > > robh...@kernel.org; mark.rutl...@arm.com;
> > > > linuxppc-dev@lists.ozlabs.org; linux-arm-
> > > > ker...@lists.infradead.org; mturque...@baylibre.com;
> > > > sb...@kernel.org; r...@rjwysocki.net; viresh.ku...@linaro.org;
> > > > linux-...@vger.kernel.org; linux...@vger.kernel.org;
> > > > linux-kernel-ow...@vger.kernel.org;
> > > > catalin.mari...@arm.com; will.dea...@arm.com;
> > > > gre...@linuxfoundation.org; a...@arndb.de;
> > > > kstew...@linuxfoundation.org; yamada.masah...@socionext.com
> > > > Cc: Yogesh Narayan Gaur ; Andy
> Tang
> > > > ; Udit Kumar ;
> > > > li...@armlinux.org.uk; Varun Sethi
> > > > Subject: Re: [PATCH 3/5] drivers: clk-qoriq: Add clockgen support
> > > > for lx2160a
> > > >
> > > > On Mon, 2018-08-20 at 12:17 +0530, Vabhav Sharma wrote:
> > > > > From: Yogesh Gaur
> > > > >
> > > > > Add clockgen support for lx2160a.
> > > > > Added entry for compat 'fsl,lx2160a-clockgen'.
> > > > > As LX2160A is 16 core, so modified value for NUM_CMUX
> > > > >
> > > > > Signed-off-by: Tang Yuantian
> > > > > Signed-off-by: Yogesh Gaur
> > > > > Signed-off-by: Vabhav Sharma
> > > > > ---
> > > > > drivers/clk/clk-qoriq.c | 14 +-
> > > > > drivers/cpufreq/qoriq-cpufreq.c | 1 +
> > > > > 2 files changed, 14 insertions(+), 1 deletion(-)
> > > > >
> > > > > diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
> > > > > index
> > > > > 3a1812f..fc6e308 100644
> > > > > --- a/drivers/clk/clk-qoriq.c
> > > > > +++ b/drivers/clk/clk-qoriq.c
> > > > > @@ -60,7 +60,7 @@ struct clockgen_muxinfo { };
> > > > >
> > > > > #define NUM_HWACCEL 5
> > > > > -#define NUM_CMUX 8
> > > > > +#define NUM_CMUX 16
> > > > >
> > > > > struct clockgen;
> > > > >
> > > > > @@ -570,6 +570,17 @@ static const struct clockgen_chipinfo
> > > > > chipinfo[] = {
> > > > > .flags = CG_VER3 | CG_LITTLE_ENDIAN,
> > > > > },
> > > > > {
> > > > > + .compat = "fsl,lx2160a-clockgen",
> > > > > + .cmux_groups = {
> > > > > + &clockgen2_cmux_cga12, &clockgen2_cmux_cgb
> > > > > + },
> > > > > + .cmux_to_group = {
> > > > > + 0, 0, 0, 0, 1, 1, 1, 1, -1
> > > > > + },
> > > > > + .pll_mask = 0x37,
> > > > > + .flags = CG_VER3 | CG_LITTLE_ENDIAN,
> > > > > + },
> > > >
> > > > Why are you increasing NUM_CMUX beyond 8 for a chip that only
> has
> > > > 8 entries in cmux_to_group?
> > >
> > > Configuration is 16 cores,8 cluster with 2 cores in each cluster
> >
> > So? This is about cmuxes, not cores. You're increasing the array
> > without ever using the new size.
>
> Oh, and you also broke p4080 which has 8 cmuxes but no -1 terminator,
> because the array was of length 8. Probably the array should be changed
> to NUM_CMUX+1 so every array can be -1 terminated.
>
[Andy] How about we add -1 terminator to p4080 and increase NUM_CMUX to 16?
We don't want to increase NUM_CMUX each time new soc with more cmuxes added.
BR,
Andy Tang
> -Scott
>
>
> ___
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