[PATCH][v2][powerpc/85xx] P2020RDB Platform Support Added
Adds P2020RDB basic support in linux. Overview of P2020RDB platform - DDR DDR2 1G - NOR Flash 16MByte - NAND Flash 32MByte - 3 Ethernet interfaces 1) etSEC1 - RGMII - connected to a 5 port Vitesse Switch(VSC7385) - Switch is memory mapped through eLBC interface(CS#2) - IRQ1 2) etSEC2 - SGMII - connected to VSC8221 - IRQ2 3) etSEC3 - RGMII - connected to VSC8641 - IRQ3 - 2 1X PCIe interfaces - SD/MMC ,USB - SPI EEPROM - Serial I2C EEPROM Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com --- based on http://www.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git incorporated Felix feedback regarding the partition names. fixed the vitesse switch ranges entry in device tree. arch/powerpc/boot/dts/p2020rdb.dts| 586 + arch/powerpc/configs/mpc85xx_defconfig|1 + arch/powerpc/platforms/85xx/Kconfig |9 + arch/powerpc/platforms/85xx/Makefile |3 +- arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 141 +++ 5 files changed, 739 insertions(+), 1 deletions(-) create mode 100644 arch/powerpc/boot/dts/p2020rdb.dts create mode 100644 arch/powerpc/platforms/85xx/mpc85xx_rdb.c diff --git a/arch/powerpc/boot/dts/p2020rdb.dts b/arch/powerpc/boot/dts/p2020rdb.dts new file mode 100644 index 000..617029f --- /dev/null +++ b/arch/powerpc/boot/dts/p2020rdb.dts @@ -0,0 +1,586 @@ +/* + * P2020 RDB Device Tree Source + * + * Copyright 2009 Freescale Semiconductor Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +/dts-v1/; +/ { + model = fsl,P2020; + compatible = fsl,P2020RDB; + #address-cells = 2; + #size-cells = 2; + + aliases { + ethernet0 = enet0; + ethernet1 = enet1; + ethernet2 = enet2; + serial0 = serial0; + serial1 = serial1; + pci0 = pci0; + pci1 = pci1; + }; + + cpus { + #address-cells = 1; + #size-cells = 0; + + PowerPC,p2...@0 { + device_type = cpu; + reg = 0x0; + next-level-cache = L2; + }; + + PowerPC,p2...@1 { + device_type = cpu; + reg = 0x1; + next-level-cache = L2; + }; + }; + + memory { + device_type = memory; + }; + + local...@ffe05000 { + #address-cells = 2; + #size-cells = 1; + compatible = fsl,p2020-elbc, fsl,elbc, simple-bus; + reg = 0 0xffe05000 0 0x1000; + interrupts = 19 2; + interrupt-parent = mpic; + + /* NOR and NAND Flashes */ + ranges = 0x0 0x0 0x0 0xef00 0x0100 + 0x1 0x0 0x0 0xffa0 0x0004 + 0x2 0x0 0x0 0xffb0 0x0002; + + n...@0,0 { + #address-cells = 1; + #size-cells = 1; + compatible = cfi-flash; + reg = 0x0 0x0 0x100; + bank-width = 2; + device-width = 1; + + partit...@0 { + /* This location must not be altered */ + /* 256KB for Vitesse 7385 Switch firmware */ + reg = 0x0 0x0004; + label = NOR (RO) Vitesse-7385 Firmware; + read-only; + }; + + partit...@4 { + /* 256KB for DTB Image */ + reg = 0x0004 0x0004; + label = NOR (RO) DTB Image; + read-only; + }; + + partit...@8 { + /* 3.5 MB for Linux Kernel Image */ + reg = 0x0008 0x0038; + label = NOR (RO) Linux Kernel Image; + read-only; + }; + + partit...@40 { + /* 11MB for JFFS2 based Root file System */ + reg = 0x0040 0x00b0; + label = NOR (RW) JFFS2 Root File System; +
Re: [PATCH][v2][powerpc/85xx] P2020RDB Platform Support Added
Hi, Poonam See some more comments below. Poonam Aggrwal wrote: Adds P2020RDB basic support in linux. Overview of P2020RDB platform - DDR DDR2 1G - NOR Flash 16MByte - NAND Flash 32MByte - 3 Ethernet interfaces 1) etSEC1 - RGMII - connected to a 5 port Vitesse Switch(VSC7385) - Switch is memory mapped through eLBC interface(CS#2) - IRQ1 2) etSEC2 - SGMII - connected to VSC8221 - IRQ2 3) etSEC3 - RGMII - connected to VSC8641 - IRQ3 - 2 1X PCIe interfaces - SD/MMC ,USB - SPI EEPROM - Serial I2C EEPROM Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com --- based on http://www.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git incorporated Felix feedback regarding the partition names. fixed the vitesse switch ranges entry in device tree. arch/powerpc/boot/dts/p2020rdb.dts| 586 + arch/powerpc/configs/mpc85xx_defconfig|1 + arch/powerpc/platforms/85xx/Kconfig |9 + arch/powerpc/platforms/85xx/Makefile |3 +- arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 141 +++ 5 files changed, 739 insertions(+), 1 deletions(-) create mode 100644 arch/powerpc/boot/dts/p2020rdb.dts create mode 100644 arch/powerpc/platforms/85xx/mpc85xx_rdb.c diff --git a/arch/powerpc/boot/dts/p2020rdb.dts b/arch/powerpc/boot/dts/p2020rdb.dts new file mode 100644 index 000..617029f --- /dev/null +++ b/arch/powerpc/boot/dts/p2020rdb.dts @@ -0,0 +1,586 @@ +/* + * P2020 RDB Device Tree Source + * + * Copyright 2009 Freescale Semiconductor Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +/dts-v1/; +/ { + model = fsl,P2020; + compatible = fsl,P2020RDB; + #address-cells = 2; + #size-cells = 2; + + aliases { + ethernet0 = enet0; + ethernet1 = enet1; + ethernet2 = enet2; + serial0 = serial0; + serial1 = serial1; + pci0 = pci0; + pci1 = pci1; + }; + + cpus { + #address-cells = 1; + #size-cells = 0; + + PowerPC,p2...@0 { + device_type = cpu; + reg = 0x0; + next-level-cache = L2; + }; + + PowerPC,p2...@1 { + device_type = cpu; + reg = 0x1; + next-level-cache = L2; + }; + }; + + memory { + device_type = memory; + }; + + local...@ffe05000 { + #address-cells = 2; + #size-cells = 1; + compatible = fsl,p2020-elbc, fsl,elbc, simple-bus; + reg = 0 0xffe05000 0 0x1000; + interrupts = 19 2; + interrupt-parent = mpic; + + /* NOR and NAND Flashes */ + ranges = 0x0 0x0 0x0 0xef00 0x0100 + 0x1 0x0 0x0 0xffa0 0x0004 + 0x2 0x0 0x0 0xffb0 0x0002; + + n...@0,0 { + #address-cells = 1; + #size-cells = 1; + compatible = cfi-flash; + reg = 0x0 0x0 0x100; + bank-width = 2; + device-width = 1; + + partit...@0 { + /* This location must not be altered */ + /* 256KB for Vitesse 7385 Switch firmware */ + reg = 0x0 0x0004; + label = NOR (RO) Vitesse-7385 Firmware; + read-only; + }; + + partit...@4 { + /* 256KB for DTB Image */ + reg = 0x0004 0x0004; + label = NOR (RO) DTB Image; + read-only; + }; + + partit...@8 { + /* 3.5 MB for Linux Kernel Image */ + reg = 0x0008 0x0038; + label = NOR (RO) Linux Kernel Image; + read-only; + }; + + partit...@40 { + /* 11MB for JFFS2 based Root file System */ + reg = 0x0040 0x00b0; +
RE: [PATCH][v2][powerpc/85xx] P2020RDB Platform Support Added
-Original Message- From: Felix Radensky [mailto:fe...@embedded-sol.com] Sent: Friday, August 07, 2009 4:42 PM To: Aggrwal Poonam-B10812 Cc: linuxppc-...@ozlabs.org Subject: Re: [PATCH][v2][powerpc/85xx] P2020RDB Platform Support Added Hi, Poonam See some more comments below. Poonam Aggrwal wrote: Adds P2020RDB basic support in linux. Overview of P2020RDB platform - DDR DDR2 1G - NOR Flash 16MByte - NAND Flash 32MByte - 3 Ethernet interfaces 1) etSEC1 - RGMII - connected to a 5 port Vitesse Switch(VSC7385) - Switch is memory mapped through eLBC interface(CS#2) - IRQ1 2) etSEC2 - SGMII - connected to VSC8221 - IRQ2 3) etSEC3 - RGMII - connected to VSC8641 - IRQ3 - 2 1X PCIe interfaces - SD/MMC ,USB - SPI EEPROM - Serial I2C EEPROM Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com --- based on http://www.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git incorporated Felix feedback regarding the partition names. fixed the vitesse switch ranges entry in device tree. arch/powerpc/boot/dts/p2020rdb.dts| 586 + arch/powerpc/configs/mpc85xx_defconfig|1 + arch/powerpc/platforms/85xx/Kconfig |9 + arch/powerpc/platforms/85xx/Makefile |3 +- arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 141 +++ 5 files changed, 739 insertions(+), 1 deletions(-) create mode 100644 arch/powerpc/boot/dts/p2020rdb.dts create mode 100644 arch/powerpc/platforms/85xx/mpc85xx_rdb.c diff --git a/arch/powerpc/boot/dts/p2020rdb.dts b/arch/powerpc/boot/dts/p2020rdb.dts new file mode 100644 index 000..617029f --- /dev/null +++ b/arch/powerpc/boot/dts/p2020rdb.dts @@ -0,0 +1,586 @@ +/* + * P2020 RDB Device Tree Source + * + * Copyright 2009 Freescale Semiconductor Inc. + * + * This program is free software; you can redistribute it and/or +modify it + * under the terms of the GNU General Public License as published +by the + * Free Software Foundation; either version 2 of the License, or +(at your + * option) any later version. + */ + +/dts-v1/; +/ { + model = fsl,P2020; + compatible = fsl,P2020RDB; + #address-cells = 2; + #size-cells = 2; + + aliases { + ethernet0 = enet0; + ethernet1 = enet1; + ethernet2 = enet2; + serial0 = serial0; + serial1 = serial1; + pci0 = pci0; + pci1 = pci1; + }; + + cpus { + #address-cells = 1; + #size-cells = 0; + + PowerPC,p2...@0 { + device_type = cpu; + reg = 0x0; + next-level-cache = L2; + }; + + PowerPC,p2...@1 { + device_type = cpu; + reg = 0x1; + next-level-cache = L2; + }; + }; + + memory { + device_type = memory; + }; + + local...@ffe05000 { + #address-cells = 2; + #size-cells = 1; + compatible = fsl,p2020-elbc, fsl,elbc, simple-bus; + reg = 0 0xffe05000 0 0x1000; + interrupts = 19 2; + interrupt-parent = mpic; + + /* NOR and NAND Flashes */ + ranges = 0x0 0x0 0x0 0xef00 0x0100 + 0x1 0x0 0x0 0xffa0 0x0004 + 0x2 0x0 0x0 0xffb0 0x0002; + + n...@0,0 { + #address-cells = 1; + #size-cells = 1; + compatible = cfi-flash; + reg = 0x0 0x0 0x100; + bank-width = 2; + device-width = 1; + + partit...@0 { + /* This location must not be altered */ + /* 256KB for Vitesse 7385 Switch firmware */ + reg = 0x0 0x0004; + label = NOR (RO) Vitesse-7385 Firmware; + read-only; + }; + + partit...@4 { + /* 256KB for DTB Image */ + reg = 0x0004 0x0004; + label = NOR (RO) DTB Image; + read-only; + }; + + partit...@8 { + /* 3.5 MB for Linux Kernel Image */ + reg = 0x0008 0x0038; + label = NOR (RO) Linux Kernel Image; + read-only