RE: [PATCH][v3] powerpc/85xx: P1020RDB Support Added
Hello Kumar
Could you please accept this patch if it is okay.
Regards
POonam
-Original Message-
From: Aggrwal Poonam-B10812
Sent: Monday, August 31, 2009 5:22 PM
To: linuxppc-...@ozlabs.org
Cc: Aggrwal Poonam-B10812
Subject: [PATCH][v3] powerpc/85xx: P1020RDB Support Added
P1020 is another member of Freescale QorIQ series of processors.
It is an e500 based dual core SOC.
Being a scaled down version of P2020 it has following
differences from P2020:
- 533MHz - 800MHz core frequency.
- 256Kbyte L2 cache
- Ethernet controllers with classification capabilities(new
controller).
From board perspective P1020RDB is same as P2020RDB.
* This code adds the basic basic platform support for P1020RDB.
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
---
- based on
http://www.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git
- branch-next
- The patch does not contain ethernet support because P1020
contains new eTSEC
controller. The support will be added in the later patches.
arch/powerpc/boot/dts/p1020rdb.dts| 477
+
arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 24 ++
2 files changed, 501 insertions(+), 0 deletions(-) create
mode 100644 arch/powerpc/boot/dts/p1020rdb.dts
diff --git a/arch/powerpc/boot/dts/p1020rdb.dts
b/arch/powerpc/boot/dts/p1020rdb.dts
new file mode 100644
index 000..de5672c
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1020rdb.dts
@@ -0,0 +1,477 @@
+/*
+ * P1020 RDB Device Tree Source
+ *
+ * Copyright 2009 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+modify it
+ * under the terms of the GNU General Public License as
published by
+the
+ * Free Software Foundation; either version 2 of the
License, or (at
+your
+ * option) any later version.
+ */
+
+/dts-v1/;
+/ {
+ model = fsl,P1020;
+ compatible = fsl,P1020RDB;
+ #address-cells = 2;
+ #size-cells = 2;
+
+ aliases {
+ serial0 = serial0;
+ serial1 = serial1;
+ pci0 = pci0;
+ pci1 = pci1;
+ };
+
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ PowerPC,p1...@0 {
+ device_type = cpu;
+ reg = 0x0;
+ next-level-cache = L2;
+ };
+
+ PowerPC,p1...@1 {
+ device_type = cpu;
+ reg = 0x1;
+ next-level-cache = L2;
+ };
+ };
+
+ memory {
+ device_type = memory;
+ };
+
+ local...@ffe05000 {
+ #address-cells = 2;
+ #size-cells = 1;
+ compatible = fsl,p1020-elbc, fsl,elbc, simple-bus;
+ reg = 0 0xffe05000 0 0x1000;
+ interrupts = 19 2;
+ interrupt-parent = mpic;
+
+ /* NOR and NAND Flashes */
+ ranges = 0x0 0x0 0x0 0xef00 0x0100
+ 0x1 0x0 0x0 0xffa0 0x0004
+ 0x2 0x0 0x0 0xffb0 0x0002;
+
+ n...@0,0 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = cfi-flash;
+ reg = 0x0 0x0 0x100;
+ bank-width = 2;
+ device-width = 1;
+
+ partit...@0 {
+ /* This location must not be altered */
+ /* 256KB for Vitesse 7385
Switch firmware */
+ reg = 0x0 0x0004;
+ label = NOR (RO) Vitesse-7385
Firmware;
+ read-only;
+ };
+
+ partit...@4 {
+ /* 256KB for DTB Image */
+ reg = 0x0004 0x0004;
+ label = NOR (RO) DTB Image;
+ read-only;
+ };
+
+ partit...@8 {
+ /* 3.5 MB for Linux Kernel Image */
+ reg = 0x0008 0x0038;
+ label = NOR (RO) Linux Kernel Image;
+ read-only;
+ };
+
+ partit...@40 {
+ /* 11MB for JFFS2 based Root
file System */
+ reg = 0x0040 0x00b0;
+ label = NOR (RW) JFFS2 Root
File System;
+ };
+
+ partit...@f0 {
+ /* This location must not be altered */
+ /* 512KB for u-boot Bootloader Image */
+ /* 512KB for u-boot Environment
Variables
[PATCH][v3] powerpc/85xx: P1020RDB Support Added
P1020 is another member of Freescale QorIQ series of processors.
It is an e500 based dual core SOC.
Being a scaled down version of P2020 it has following differences from P2020:
- 533MHz - 800MHz core frequency.
- 256Kbyte L2 cache
- Ethernet controllers with classification capabilities(new controller).
From board perspective P1020RDB is same as P2020RDB.
* This code adds the basic basic platform support for P1020RDB.
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
---
- based on http://www.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git
- branch-next
- The patch does not contain ethernet support because P1020 contains new eTSEC
controller. The support will be added in the later patches.
arch/powerpc/boot/dts/p1020rdb.dts| 477 +
arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 24 ++
2 files changed, 501 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/boot/dts/p1020rdb.dts
diff --git a/arch/powerpc/boot/dts/p1020rdb.dts
b/arch/powerpc/boot/dts/p1020rdb.dts
new file mode 100644
index 000..de5672c
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1020rdb.dts
@@ -0,0 +1,477 @@
+/*
+ * P1020 RDB Device Tree Source
+ *
+ * Copyright 2009 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+/ {
+ model = fsl,P1020;
+ compatible = fsl,P1020RDB;
+ #address-cells = 2;
+ #size-cells = 2;
+
+ aliases {
+ serial0 = serial0;
+ serial1 = serial1;
+ pci0 = pci0;
+ pci1 = pci1;
+ };
+
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ PowerPC,p1...@0 {
+ device_type = cpu;
+ reg = 0x0;
+ next-level-cache = L2;
+ };
+
+ PowerPC,p1...@1 {
+ device_type = cpu;
+ reg = 0x1;
+ next-level-cache = L2;
+ };
+ };
+
+ memory {
+ device_type = memory;
+ };
+
+ local...@ffe05000 {
+ #address-cells = 2;
+ #size-cells = 1;
+ compatible = fsl,p1020-elbc, fsl,elbc, simple-bus;
+ reg = 0 0xffe05000 0 0x1000;
+ interrupts = 19 2;
+ interrupt-parent = mpic;
+
+ /* NOR and NAND Flashes */
+ ranges = 0x0 0x0 0x0 0xef00 0x0100
+ 0x1 0x0 0x0 0xffa0 0x0004
+ 0x2 0x0 0x0 0xffb0 0x0002;
+
+ n...@0,0 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = cfi-flash;
+ reg = 0x0 0x0 0x100;
+ bank-width = 2;
+ device-width = 1;
+
+ partit...@0 {
+ /* This location must not be altered */
+ /* 256KB for Vitesse 7385 Switch firmware */
+ reg = 0x0 0x0004;
+ label = NOR (RO) Vitesse-7385 Firmware;
+ read-only;
+ };
+
+ partit...@4 {
+ /* 256KB for DTB Image */
+ reg = 0x0004 0x0004;
+ label = NOR (RO) DTB Image;
+ read-only;
+ };
+
+ partit...@8 {
+ /* 3.5 MB for Linux Kernel Image */
+ reg = 0x0008 0x0038;
+ label = NOR (RO) Linux Kernel Image;
+ read-only;
+ };
+
+ partit...@40 {
+ /* 11MB for JFFS2 based Root file System */
+ reg = 0x0040 0x00b0;
+ label = NOR (RW) JFFS2 Root File System;
+ };
+
+ partit...@f0 {
+ /* This location must not be altered */
+ /* 512KB for u-boot Bootloader Image */
+ /* 512KB for u-boot Environment Variables */
+ reg = 0x00f0 0x0010;
+ label = NOR (RO) U-Boot Image;
+ read-only;
+ };
+ };
+
+ n...@1,0 {
+ #address-cells = 1;
+
