Re: [PATCH] SBC8548: Add flash support and HW Rev reporting
On May 5, 2008, at 5:17 PM, Jeremy McNicoll wrote: The following adds local bus, flash and MTD partition nodes for sbc8548. As well, a compatible field for the soc node, so that of_platform_bus_probe() will pick it up. Something that is provided through this newly added epld node is the Hardware Revision which is now being utilized. Signed-off-by: Jeremy McNicoll [EMAIL PROTECTED] --- arch/powerpc/boot/dts/sbc8548.dts | 94 + arch/powerpc/platforms/85xx/sbc8548.c | 30 ++- 2 files changed, 123 insertions(+), 1 deletions(-) applied (also fixed a few white spaces this introduced). - k ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH] SBC8548: Add flash support and HW Rev reporting
Jeremy McNicoll wrote: The following adds local bus, flash and MTD partition nodes for sbc8548. As well, a compatible field for the soc node, so that of_platform_bus_probe() will pick it up. Something that is provided through this newly added epld node is the Hardware Revision is now being reported at bootup. Signed-off-by: Jeremy McNicoll [EMAIL PROTECTED] --- arch/powerpc/boot/dts/sbc8548.dts | 94 + arch/powerpc/platforms/85xx/sbc8548.c | 25 + 2 files changed, 119 insertions(+), 0 deletions(-) This patch may not be as efficient as it could be, an updated version to follow. -jeremy ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
[PATCH] SBC8548: Add flash support and HW Rev reporting
The following adds local bus, flash and MTD partition nodes for
sbc8548. As well, a compatible field for the soc node, so that
of_platform_bus_probe() will pick it up.
Something that is provided through this newly added epld node
is the Hardware Revision which is now being utilized.
Signed-off-by: Jeremy McNicoll [EMAIL PROTECTED]
---
arch/powerpc/boot/dts/sbc8548.dts | 94 +
arch/powerpc/platforms/85xx/sbc8548.c | 30 ++-
2 files changed, 123 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/boot/dts/sbc8548.dts
b/arch/powerpc/boot/dts/sbc8548.dts
index b86e65d..dd9a061 100644
--- a/arch/powerpc/boot/dts/sbc8548.dts
+++ b/arch/powerpc/boot/dts/sbc8548.dts
@@ -52,6 +52,99 @@
reg = 0x 0x1000;
};
+ [EMAIL PROTECTED] {
+ #address-cells = 2;
+ #size-cells = 1;
+ compatible = simple-bus;
+ reg = 0xe000 0x5000;
+ interrupt-parent = mpic;
+
+ ranges = 0x0 0x0 0xff80 0x0080 /*8MB Flash*/
+ 0x3 0x0 0xf000 0x0400 /*64MB SDRAM*/
+ 0x4 0x0 0xf400 0x0400 /*64MB SDRAM*/
+ 0x5 0x0 0xf800 0x00b1 /* EPLD */
+ 0x6 0x0 0xfb80 0x0400; /*64MB Flash*/
+
+
+ [EMAIL PROTECTED],0 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = cfi-flash;
+ reg = 0x0 0x0 0x80;
+ bank-width = 1;
+ device-width = 1;
+ [EMAIL PROTECTED] {
+ label = space;
+ reg = 0x 0x0010;
+ };
+ [EMAIL PROTECTED] {
+ label = bootloader;
+ reg = 0x0010 0x0070;
+ read-only;
+ };
+ };
+
+ [EMAIL PROTECTED],0 {
+ compatible = wrs,epld-localbus;
+ #address-cells = 2;
+ #size-cells = 1;
+ reg = 0x5 0x0 0x00b1;
+ ranges =
+ 0x0 0x0 0x5 0x00 0x1fff /* LED */
+ 0x1 0x0 0x5 0x10 0x1fff /* Switches */
+ 0x3 0x0 0x5 0x30 0x1fff /* HW Rev. */
+ 0xb 0x0 0x5 0xb0 0x1fff /* EEPROM */
+ ;
+
+ [EMAIL PROTECTED],0 {
+ compatible = led;
+ reg = 0x0 0x0 0x1fff;
+ };
+
+ [EMAIL PROTECTED],0 {
+ compatible = switches;
+ reg = 0x1 0x0 0x1fff;
+ };
+
+ [EMAIL PROTECTED],0 {
+ compatible = hw-rev;
+ reg = 0x3 0x0 0x1fff;
+ };
+
+ [EMAIL PROTECTED],0 {
+ compatible = eeprom;
+ reg = 0xb 0 0x1fff;
+ };
+
+ };
+
+ [EMAIL PROTECTED],0 {
+ #address-cells = 1;
+ #size-cells = 1;
+ reg = 0x6 0x0 0x0400;
+ compatible = cfi-flash;
+ bank-width = 4;
+ device-width = 1;
+ [EMAIL PROTECTED] {
+ label = bootloader;
+ reg = 0x 0x0010;
+ read-only;
+ };
+ [EMAIL PROTECTED] {
+ label = file-system;
+ reg = 0x0010 0x01f0;
+ };
+ [EMAIL PROTECTED] {
+ label = boot-config;
+ reg = 0x0200 0x0010;
+ };
+ [EMAIL PROTECTED] {
+ label = space;
+ reg = 0x0210 0x01f0;
+ };
+};
+};
+
[EMAIL PROTECTED] {
#address-cells = 1;
#size-cells = 1;
@@ -59,6 +152,7 @@
ranges = 0x 0xe000 0x0010;
reg = 0xe000 0x1000; // CCSRBAR
bus-frequency = 0;
+ compatible = simple-bus;
[EMAIL PROTECTED] {
Re: [PATCH] SBC8548: Add flash support and HW Rev reporting
On May 5, 2008, at 5:17 PM, Jeremy McNicoll wrote: The following adds local bus, flash and MTD partition nodes for sbc8548. As well, a compatible field for the soc node, so that of_platform_bus_probe() will pick it up. Something that is provided through this newly added epld node is the Hardware Revision which is now being utilized. Signed-off-by: Jeremy McNicoll [EMAIL PROTECTED] What was changed in this version? - k ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH] SBC8548: Add flash support and HW Rev reporting
Kumar Gala wrote: On May 5, 2008, at 5:17 PM, Jeremy McNicoll wrote: The following adds local bus, flash and MTD partition nodes for sbc8548. As well, a compatible field for the soc node, so that of_platform_bus_probe() will pick it up. Something that is provided through this newly added epld node is the Hardware Revision which is now being utilized. Signed-off-by: Jeremy McNicoll [EMAIL PROTECTED] What was changed in this version? The dts is the same. I decided to remove the arch_initcall and the associated printk in sbc8548_hw_rev(). -jeremy ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
[PATCH] SBC8548: Add flash support and HW Rev reporting
The following adds local bus, flash and MTD partition nodes for
sbc8548. As well, a compatible field for the soc node, so that
of_platform_bus_probe() will pick it up.
Something that is provided through this newly added epld node
is the Hardware Revision is now being reported at bootup.
Signed-off-by: Jeremy McNicoll [EMAIL PROTECTED]
---
arch/powerpc/boot/dts/sbc8548.dts | 94 +
arch/powerpc/platforms/85xx/sbc8548.c | 25 +
2 files changed, 119 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/boot/dts/sbc8548.dts
b/arch/powerpc/boot/dts/sbc8548.dts
index b86e65d..dd9a061 100644
--- a/arch/powerpc/boot/dts/sbc8548.dts
+++ b/arch/powerpc/boot/dts/sbc8548.dts
@@ -52,6 +52,99 @@
reg = 0x 0x1000;
};
+ [EMAIL PROTECTED] {
+ #address-cells = 2;
+ #size-cells = 1;
+ compatible = simple-bus;
+ reg = 0xe000 0x5000;
+ interrupt-parent = mpic;
+
+ ranges = 0x0 0x0 0xff80 0x0080 /*8MB Flash*/
+ 0x3 0x0 0xf000 0x0400 /*64MB SDRAM*/
+ 0x4 0x0 0xf400 0x0400 /*64MB SDRAM*/
+ 0x5 0x0 0xf800 0x00b1 /* EPLD */
+ 0x6 0x0 0xfb80 0x0400; /*64MB Flash*/
+
+
+ [EMAIL PROTECTED],0 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = cfi-flash;
+ reg = 0x0 0x0 0x80;
+ bank-width = 1;
+ device-width = 1;
+ [EMAIL PROTECTED] {
+ label = space;
+ reg = 0x 0x0010;
+ };
+ [EMAIL PROTECTED] {
+ label = bootloader;
+ reg = 0x0010 0x0070;
+ read-only;
+ };
+ };
+
+ [EMAIL PROTECTED],0 {
+ compatible = wrs,epld-localbus;
+ #address-cells = 2;
+ #size-cells = 1;
+ reg = 0x5 0x0 0x00b1;
+ ranges =
+ 0x0 0x0 0x5 0x00 0x1fff /* LED */
+ 0x1 0x0 0x5 0x10 0x1fff /* Switches */
+ 0x3 0x0 0x5 0x30 0x1fff /* HW Rev. */
+ 0xb 0x0 0x5 0xb0 0x1fff /* EEPROM */
+ ;
+
+ [EMAIL PROTECTED],0 {
+ compatible = led;
+ reg = 0x0 0x0 0x1fff;
+ };
+
+ [EMAIL PROTECTED],0 {
+ compatible = switches;
+ reg = 0x1 0x0 0x1fff;
+ };
+
+ [EMAIL PROTECTED],0 {
+ compatible = hw-rev;
+ reg = 0x3 0x0 0x1fff;
+ };
+
+ [EMAIL PROTECTED],0 {
+ compatible = eeprom;
+ reg = 0xb 0 0x1fff;
+ };
+
+ };
+
+ [EMAIL PROTECTED],0 {
+ #address-cells = 1;
+ #size-cells = 1;
+ reg = 0x6 0x0 0x0400;
+ compatible = cfi-flash;
+ bank-width = 4;
+ device-width = 1;
+ [EMAIL PROTECTED] {
+ label = bootloader;
+ reg = 0x 0x0010;
+ read-only;
+ };
+ [EMAIL PROTECTED] {
+ label = file-system;
+ reg = 0x0010 0x01f0;
+ };
+ [EMAIL PROTECTED] {
+ label = boot-config;
+ reg = 0x0200 0x0010;
+ };
+ [EMAIL PROTECTED] {
+ label = space;
+ reg = 0x0210 0x01f0;
+ };
+};
+};
+
[EMAIL PROTECTED] {
#address-cells = 1;
#size-cells = 1;
@@ -59,6 +152,7 @@
ranges = 0x 0xe000 0x0010;
reg = 0xe000 0x1000; // CCSRBAR
bus-frequency = 0;
+ compatible = simple-bus;
[EMAIL PROTECTED] {
