Re: [PATCH] powerpc/pseries: Define PCI bus speed for Gen4 and Gen5

[Michael Ellerman]

On Mon, 30 Nov 2020 16:29:49 +0100, Frederic Barrat wrote:
> Update bus speed definition for PCI Gen4 and 5.

Applied to powerpc/next.

[1/1] powerpc/pseries: Define PCI bus speed for Gen4 and Gen5
  https://git.kernel.org/powerpc/c/c8754c517e37270a01b0561ad46ee647a721a09b

cheers

[PATCH] powerpc/pseries: Define PCI bus speed for Gen4 and Gen5

[Frederic Barrat]

Update bus speed definition for PCI Gen4 and 5.

Signed-off-by: Frederic Barrat 
---
 arch/powerpc/platforms/pseries/pci.c | 51 
 1 file changed, 21 insertions(+), 30 deletions(-)

diff --git a/arch/powerpc/platforms/pseries/pci.c 
b/arch/powerpc/platforms/pseries/pci.c
index 911534b89c85..72a4d4167849 100644
--- a/arch/powerpc/platforms/pseries/pci.c
+++ b/arch/powerpc/platforms/pseries/pci.c
@@ -290,6 +290,25 @@ static void fixup_winbond_82c105(struct pci_dev* dev)
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_82C105,
 fixup_winbond_82c105);
 
+static enum pci_bus_speed prop_to_pci_speed(u32 prop)
+{
+   switch (prop) {
+   case 0x01:
+   return PCIE_SPEED_2_5GT;
+   case 0x02:
+   return PCIE_SPEED_5_0GT;
+   case 0x04:
+   return PCIE_SPEED_8_0GT;
+   case 0x08:
+   return PCIE_SPEED_16_0GT;
+   case 0x10:
+   return PCIE_SPEED_32_0GT;
+   default:
+   pr_debug("Unexpected PCI link speed property value\n");
+   return PCI_SPEED_UNKNOWN;
+   }
+}
+
 int pseries_root_bridge_prepare(struct pci_host_bridge *bridge)
 {
struct device_node *dn, *pdn;
@@ -322,35 +341,7 @@ int pseries_root_bridge_prepare(struct pci_host_bridge 
*bridge)
return 0;
}
 
-   switch (pcie_link_speed_stats[0]) {
-   case 0x01:
-   bus->max_bus_speed = PCIE_SPEED_2_5GT;
-   break;
-   case 0x02:
-   bus->max_bus_speed = PCIE_SPEED_5_0GT;
-   break;
-   case 0x04:
-   bus->max_bus_speed = PCIE_SPEED_8_0GT;
-   break;
-   default:
-   bus->max_bus_speed = PCI_SPEED_UNKNOWN;
-   break;
-   }
-
-   switch (pcie_link_speed_stats[1]) {
-   case 0x01:
-   bus->cur_bus_speed = PCIE_SPEED_2_5GT;
-   break;
-   case 0x02:
-   bus->cur_bus_speed = PCIE_SPEED_5_0GT;
-   break;
-   case 0x04:
-   bus->cur_bus_speed = PCIE_SPEED_8_0GT;
-   break;
-   default:
-   bus->cur_bus_speed = PCI_SPEED_UNKNOWN;
-   break;
-   }
-
+   bus->max_bus_speed = prop_to_pci_speed(pcie_link_speed_stats[0]);
+   bus->cur_bus_speed = prop_to_pci_speed(pcie_link_speed_stats[1]);
return 0;
 }
-- 
2.26.2