Re: [PATCH]460EX on-chip SATA driver Kernel 2.6.33 resubmission
On Wed, 19 May 2010 10:49:59 +0900 Jassi Brar jassisinghb...@gmail.com wrote: On Thu, May 6, 2010 at 2:57 AM, Rupjyoti Sarmah rsar...@amcc.com wrote: This patch enables the on-chip DWC SATA controller of the AppliedMicro processor 460EX. The controller seems to be a thrid party IP (from Synopsys) in your SoC and there are many chances the IP will appear in some other SOCs too. This implementation doesn't seem to take care of that scenario. I'd question if that is worth it seriously. At the point there are multiple users of the device you know what it will look like. Until then you neither know if the work is needed nor what will require abstracting. Lazy evaluation is good for code too ;) Alan ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH]460EX on-chip SATA driver Kernel 2.6.33 resubmission
On Wed, May 19, 2010 at 6:53 PM, Alan Cox a...@lxorguk.ukuu.org.uk wrote: On Wed, 19 May 2010 10:49:59 +0900 Jassi Brar jassisinghb...@gmail.com wrote: On Thu, May 6, 2010 at 2:57 AM, Rupjyoti Sarmah rsar...@amcc.com wrote: This patch enables the on-chip DWC SATA controller of the AppliedMicro processor 460EX. The controller seems to be a thrid party IP (from Synopsys) in your SoC and there are many chances the IP will appear in some other SOCs too. This implementation doesn't seem to take care of that scenario. I'd question if that is worth it seriously. At the point there are multiple users of the device you know what it will look like. Until then you neither know if the work is needed nor what will require abstracting. Well, am to start writing driver for some dwc sata core in near future, not sure of the exact version because I've not yet had my hands on the specs. Even if my version happens to be different, we don't wanna count on such odds. So I believe it's worthwhile. Btw, I presented two options and the author can always choose the first one - rename the driver as SoC specific. And in a way, I'd prefer that :) Lazy evaluation is good for code too ;) Apart from increasing re-usability, that POV brings out neat code too. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH]460EX on-chip SATA driver Kernel 2.6.33 resubmission
On Thu, May 6, 2010 at 2:57 AM, Rupjyoti Sarmah rsar...@amcc.com wrote: This patch enables the on-chip DWC SATA controller of the AppliedMicro processor 460EX. The controller seems to be a thrid party IP (from Synopsys) in your SoC and there are many chances the IP will appear in some other SOCs too. This implementation doesn't seem to take care of that scenario. So, please either call the driver something like sata_460ex.c or, better still, segregate the driver in two parts - SoC specific stuff and DWC IP core driver that can be reused by other SoCs having the same IP in future. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH]460EX on-chip SATA driver Kernel 2.6.33 resubmission
Hi Ben,
On Sunday 16 May 2010 01:40:28 Benjamin Herrenschmidt wrote:
+ SATA0: s...@bffd1000 {
+compatible = amcc,sata-460ex;
+ reg = 4 0xbffd1000 0x800 4 0xbffd0800 0x400;
+interrupt-parent = UIC3;
+interrupts = 0x0 0x4 /* SATA */
+ 0x5 0x4; /* AHBDMA */
+};
+
POB0: opb {
compatible = ibm,opb-460ex, ibm,opb;
#address-cells = 1;
Please put the device tree update in a separate patch to go thru the
PowerPC tree.
Additionally, the boot wrapper should probably either remove the node or
at least use a status property ok / disabled to represent whether
the board is configured for SATA or PCIe x1...
U-Boot already sets the status property of the PCIe or SATA node
accordingly. Just let me know if this doesn't work for you.
Cheers,
Stefan
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Re: [PATCH]460EX on-chip SATA driver Kernel 2.6.33 resubmission
Additionally, the boot wrapper should probably either remove the node or at least use a status property ok / disabled to represent whether the board is configured for SATA or PCIe x1... U-Boot already sets the status property of the PCIe or SATA node accordingly. Just let me know if this doesn't work for you. That's probably enough. Cheers, Ben. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH]460EX on-chip SATA driver Kernel 2.6.33 resubmission
On Fri, 2010-05-14 at 21:44 +0400, Sergei Shtylyov wrote:
Hello.
Rupjyoti Sarmah wrote:
This patch enables the on-chip DWC SATA controller of the AppliedMicro
processor 460EX.
Signed-off-by: Rupjyoti Sarmah rsar...@appliedmicro.com
Signed-off-by: Mark Miesfeld mmiesf...@appliedmicro.com
Signed-off-by: Prodyut Hazarika phazar...@appliedmicro.com
---
arch/powerpc/boot/dts/canyonlands.dts |8 +
drivers/ata/Kconfig |9 +
drivers/ata/Makefile |1 +
drivers/ata/sata_dwc.c| 1827
+
4 files changed, 1845 insertions(+), 0 deletions(-)
create mode 100644 drivers/ata/sata_dwc.c
diff --git a/arch/powerpc/boot/dts/canyonlands.dts
b/arch/powerpc/boot/dts/canyonlands.dts
index cd56bb5..d3b2c99 100644
--- a/arch/powerpc/boot/dts/canyonlands.dts
+++ b/arch/powerpc/boot/dts/canyonlands.dts
@@ -163,6 +163,14 @@
interrupts = 0x1e 4;
};
+ SATA0: s...@bffd1000 {
+compatible = amcc,sata-460ex;
+ reg = 4 0xbffd1000 0x800 4 0xbffd0800 0x400;
+interrupt-parent = UIC3;
+interrupts = 0x0 0x4 /* SATA */
+ 0x5 0x4; /* AHBDMA */
+};
+
POB0: opb {
compatible = ibm,opb-460ex, ibm,opb;
#address-cells = 1;
Please put the device tree update in a separate patch to go thru the
PowerPC tree.
Additionally, the boot wrapper should probably either remove the node or
at least use a status property ok / disabled to represent whether
the board is configured for SATA or PCIe x1...
Cheers,
Ben.
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Re: [PATCH]460EX on-chip SATA driver Kernel 2.6.33 resubmission
Hello.
Rupjyoti Sarmah wrote:
This patch enables the on-chip DWC SATA controller of the AppliedMicro
processor 460EX.
Signed-off-by: Rupjyoti Sarmah rsar...@appliedmicro.com
Signed-off-by: Mark Miesfeld mmiesf...@appliedmicro.com
Signed-off-by: Prodyut Hazarika phazar...@appliedmicro.com
---
arch/powerpc/boot/dts/canyonlands.dts |8 +
drivers/ata/Kconfig |9 +
drivers/ata/Makefile |1 +
drivers/ata/sata_dwc.c| 1827 +
4 files changed, 1845 insertions(+), 0 deletions(-)
create mode 100644 drivers/ata/sata_dwc.c
diff --git a/arch/powerpc/boot/dts/canyonlands.dts
b/arch/powerpc/boot/dts/canyonlands.dts
index cd56bb5..d3b2c99 100644
--- a/arch/powerpc/boot/dts/canyonlands.dts
+++ b/arch/powerpc/boot/dts/canyonlands.dts
@@ -163,6 +163,14 @@
interrupts = 0x1e 4;
};
+ SATA0: s...@bffd1000 {
+compatible = amcc,sata-460ex;
+ reg = 4 0xbffd1000 0x800 4 0xbffd0800 0x400;
+interrupt-parent = UIC3;
+interrupts = 0x0 0x4 /* SATA */
+ 0x5 0x4; /* AHBDMA */
+};
+
POB0: opb {
compatible = ibm,opb-460ex, ibm,opb;
#address-cells = 1;
Please put the device tree update in a separate patch to go thru the
PowerPC tree.
MBR, Sergei
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Re: [PATCH]460EX on-chip SATA driver Kernel 2.6.33 resubmission
On 05/05/2010 01:57 PM, Rupjyoti Sarmah wrote:
+static void clear_interrupt_bit(struct sata_dwc_device *hsdev, u32 bit)
+{
+ out_le32(hsdev-sata_dwc_regs-intpr,
+in_le32(hsdev-sata_dwc_regs-intpr));
+}
+
+static u32 qcmd_tag_to_mask(u8 tag)
+{
+ return 0x0001 (tag 0x1f);
+}
+
+/* See ahci.c */
+static void sata_dwc_error_intr(struct ata_port *ap,
+ struct sata_dwc_device *hsdev, uint intpr)
+{
+ struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
+ struct ata_eh_info *ehi =ap-link.eh_info;
+ unsigned int err_mask = 0, action = 0;
+ struct ata_queued_cmd *qc;
+ u32 serror;
+ u8 status, tag;
+ u32 err_reg;
+
+ ata_ehi_clear_desc(ehi);
+
+ serror = core_scr_read(SCR_ERROR);
+ status = ap-ops-sff_check_status(ap);
+
+ err_reg = in_le32((host_pvt.sata_dma_regs-interrupt_status.error.\
+ low));
+ tag = ap-link.active_tag;
+
+ dev_err(ap-dev, %s SCR_ERROR=0x%08x intpr=0x%08x status=0x%08x
+ dma_intp=%d pending=%d issued=%d dma_err_status=0x%08x\n,
+ __func__, serror, intpr, status, host_pvt.dma_interrupt_count,
+ hsdevp-dma_pending[tag], hsdevp-cmd_issued[tag], err_reg);
+
+ /* Clear error register and interrupt bit */
+ clear_serror();
+ clear_interrupt_bit(hsdev, SATA_DWC_INTPR_ERR);
+
+ /* This is the only error happening now. TODO check for exact error */
+ err_mask |= AC_ERR_HOST_BUS;
+ action |= ATA_EH_RESET;
this is a rather poor error mapping.
+/**
+ * Function : sata_dwc_isr
+ * arguments : irq, void *dev_instance, struct pt_regs *regs
+ * Return value : irqreturn_t - status of IRQ
+ * This Interrupt handler called via port ops registered function.
+ * .irq_handler = sata_dwc_isr
+ */
+static irqreturn_t sata_dwc_isr(int irq, void *dev_instance)
+{
+ struct ata_host *host = (struct ata_host *)dev_instance;
+ struct sata_dwc_device *hsdev = HSDEV_FROM_HOST(host);
+ struct ata_port *ap;
+ struct ata_queued_cmd *qc;
+ unsigned long flags;
+ u8 status, tag;
+ int handled, num_processed, port = 0;
+ uint intpr, sactive, sactive2, tag_mask;
+ struct sata_dwc_device_port *hsdevp;
+ host_pvt.sata_dwc_sactive_issued = 0;
+
+ spin_lock_irqsave(host-lock, flags);
+
+ /* Read the interrupt register */
+ intpr = in_le32(hsdev-sata_dwc_regs-intpr);
+
+ ap = host-ports[port];
+ hsdevp = HSDEVP_FROM_AP(ap);
+
+ dev_dbg(ap-dev, %s intpr=0x%08x active_tag=%d\n, __func__, intpr,
+ ap-link.active_tag);
+
+ /* Check for error interrupt */
+ if (intpr SATA_DWC_INTPR_ERR) {
+ sata_dwc_error_intr(ap, hsdev, intpr);
+ handled = 1;
+ goto DONE;
+ }
+
+ /* Check for DMA SETUP FIS (FP DMA) interrupt */
+ if (intpr SATA_DWC_INTPR_NEWFP) {
+ clear_interrupt_bit(hsdev, SATA_DWC_INTPR_NEWFP);
+
+ tag = (u8)(in_le32(hsdev-sata_dwc_regs-fptagr));
+ dev_dbg(ap-dev, %s: NEWFP tag=%d\n, __func__, tag);
+ if (hsdevp-cmd_issued[tag] != SATA_DWC_CMD_ISSUED_PEND)
+ dev_warn(ap-dev, CMD tag=%d not pending?\n, tag);
+
+ host_pvt.sata_dwc_sactive_issued |= qcmd_tag_to_mask(tag);
+
+ qc = ata_qc_from_tag(ap, tag);
+ /* Start FP DMA for NCQ command. At this point the tag is the
+* active tag. It is the tag that matches the command about to
+* be completed.
+*/
+ qc-ap-link.active_tag = tag;
+ sata_dwc_bmdma_start_by_tag(qc, tag);
+
+ handled = 1;
+ goto DONE;
+ }
+
+ sactive = core_scr_read(SCR_ACTIVE);
+ tag_mask = (host_pvt.sata_dwc_sactive_issued | sactive) ^ sactive;
+
+ /* If no sactive issued and tag_mask is zero then this is not NCQ */
+ if (host_pvt.sata_dwc_sactive_issued == 0 tag_mask == 0) {
+ if (ap-link.active_tag == ATA_TAG_POISON)
+ tag = 0;
+ else
+ tag = ap-link.active_tag;
+ qc = ata_qc_from_tag(ap, tag);
+
+ /* DEV interrupt w/ no active qc? */
+ if (unlikely(!qc || (qc-tf.flags ATA_TFLAG_POLLING))) {
+ dev_err(ap-dev, %s interrupt with no active qc
+ qc=%p\n, __func__, qc);
+ ap-ops-sff_check_status(ap);
+ handled = 1;
+ goto DONE;
+ }
+
+ status = ap-ops-sff_check_status(ap);
+
+ qc-ap-link.active_tag = tag;
+
[PATCH]460EX on-chip SATA driver Kernel 2.6.33 resubmission
This patch enables the on-chip DWC SATA controller of the AppliedMicro
processor 460EX.
Signed-off-by: Rupjyoti Sarmah rsar...@appliedmicro.com
Signed-off-by: Mark Miesfeld mmiesf...@appliedmicro.com
Signed-off-by: Prodyut Hazarika phazar...@appliedmicro.com
---
arch/powerpc/boot/dts/canyonlands.dts |8 +
drivers/ata/Kconfig |9 +
drivers/ata/Makefile |1 +
drivers/ata/sata_dwc.c| 1827 +
4 files changed, 1845 insertions(+), 0 deletions(-)
create mode 100644 drivers/ata/sata_dwc.c
diff --git a/arch/powerpc/boot/dts/canyonlands.dts
b/arch/powerpc/boot/dts/canyonlands.dts
index cd56bb5..d3b2c99 100644
--- a/arch/powerpc/boot/dts/canyonlands.dts
+++ b/arch/powerpc/boot/dts/canyonlands.dts
@@ -163,6 +163,14 @@
interrupts = 0x1e 4;
};
+ SATA0: s...@bffd1000 {
+compatible = amcc,sata-460ex;
+ reg = 4 0xbffd1000 0x800 4 0xbffd0800 0x400;
+interrupt-parent = UIC3;
+interrupts = 0x0 0x4 /* SATA */
+ 0x5 0x4; /* AHBDMA */
+};
+
POB0: opb {
compatible = ibm,opb-460ex, ibm,opb;
#address-cells = 1;
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index 56c6374..bba7b8a 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -82,6 +82,15 @@ config SATA_FSL
If unsure, say N.
+config SATA_DWC
+ tristate DesignWare Cores SATA support
+ depends on 460EX
+ help
+ This option enables support for the on-chip SATA controller of the
+ AppliedMicro processor 460EX.
+
+ If unsure, say N.
+
config ATA_SFF
bool ATA SFF support
default y
diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
index fc936d4..0de7a33 100644
--- a/drivers/ata/Makefile
+++ b/drivers/ata/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_SATA_INIC162X) += sata_inic162x.o
obj-$(CONFIG_PDC_ADMA) += pdc_adma.o
obj-$(CONFIG_SATA_FSL) += sata_fsl.o
obj-$(CONFIG_PATA_MACIO) += pata_macio.o
+obj-$(CONFIG_SATA_DWC) += sata_dwc.o
obj-$(CONFIG_PATA_ALI) += pata_ali.o
obj-$(CONFIG_PATA_AMD) += pata_amd.o
diff --git a/drivers/ata/sata_dwc.c b/drivers/ata/sata_dwc.c
new file mode 100644
index 000..e499ac6
--- /dev/null
+++ b/drivers/ata/sata_dwc.c
@@ -0,0 +1,1827 @@
+/*
+ * drivers/ata/sata_dwc.c
+ *
+ * Synopsys DesignWare Cores (DWC) SATA host driver
+ *
+ * Author: Mark Miesfeld mmiesf...@amcc.com
+ *
+ * Ported from 2.6.19.2 to 2.6.25/26 by Stefan Roese s...@denx.de
+ * Copyright 2008 DENX Software Engineering
+ *
+ * Based on versions provided by AMCC and Synopsys which are:
+ * Copyright 2006 Applied Micro Circuits Corporation
+ * COPYRIGHT (C) 2005 SYNOPSYS, INC. ALL RIGHTS RESERVED
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
+#ifdef CONFIG_SATA_DWC_DEBUG
+#define DEBUG
+#endif
+
+#ifdef CONFIG_SATA_DWC_VDEBUG
+#define VERBOSE_DEBUG
+#define DEBUG_NCQ
+#endif
+
+#include linux/kernel.h
+#include linux/module.h
+#include linux/init.h
+#include linux/device.h
+#include linux/of_platform.h
+#include linux/libata.h
+#include libata.h
+
+#include scsi/scsi_host.h
+#include scsi/scsi_cmnd.h
+
+#define DRV_NAMEsata-dwc
+#define DRV_VERSION 1.0
+
+/* SATA DMA driver Globals */
+#define DMA_NUM_CHANS 1
+#define DMA_NUM_CHAN_REGS 8
+
+/* SATA DMA Register definitions */
+#define AHB_DMA_BRST_DFLT 64 /* 16 data items burst length*/
+
+struct dmareg {
+ u32 low;/* Low bits 0-31 */
+ u32 high; /* High bits 32-63 */
+};
+
+/* DMA Per Channel registers */
+
+struct dma_chan_regs {
+ struct dmareg sar; /* Source Address */
+ struct dmareg dar; /* Destination address */
+ struct dmareg llp; /* Linked List Pointer */
+ struct dmareg ctl; /* Control */
+ struct dmareg sstat;/* Source Status not implemented in core */
+ struct dmareg dstat;/* Destination Status not implemented in core*/
+ struct dmareg sstatar; /* Source Status Address not impl in core */
+ struct dmareg dstatar; /* Destination Status Address not implemente */
+ struct dmareg cfg; /* Config */
+ struct dmareg sgr; /* Source Gather */
+ struct dmareg dsr; /* Destination Scatter */
+};
+
+/* Generic Interrupt Registers */
+struct dma_interrupt_regs {
+ struct dmareg tfr; /* Transfer Interrupt */
+ struct dmareg block;/* Block Interrupt */
+ struct
