Re: [PATCH 0/9] powerpc: Preliminary work to enable SMP BookE
On Tue, 2008-12-09 at 07:17 -0600, Kumar Gala wrote: > > There are some semingly unrelated patches in the pile as they > > are dependencies of the main ones so I'm including them in. > > You'll be happy to know these patches at least boot on real 85xx SMP HW. Ah excellent ! Now time for you to torture test them :-) BTW. Don't you guys support larger than 8-bit PIDs on some E500 cores ? The latest patch I posted yesterday should allow to slip than in easily too. Cheers, Ben. ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH 0/9] powerpc: Preliminary work to enable SMP BookE
On Dec 7, 2008, at 11:39 PM, Benjamin Herrenschmidt wrote: This series of patches is aimed at supporting SMP on non-hash based processors. It consists of a rework of the MMU context management and TLB management, clearly splitting hash32, hash64 and nohash in both cases, adding SMP safe context handling and some basic SMP TLB management. There is room for improvements, such as implementing lazy TLB flushing on processors without invalidate-by-PID support HW, some better IPI mechanism, support for variable sizes PID, lock less fast path in the MMU context switch, etc... but it should basically work. There are some semingly unrelated patches in the pile as they are dependencies of the main ones so I'm including them in. You'll be happy to know these patches at least boot on real 85xx SMP HW. - k ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
[PATCH 0/9] powerpc: Preliminary work to enable SMP BookE
This series of patches is aimed at supporting SMP on non-hash based processors. It consists of a rework of the MMU context management and TLB management, clearly splitting hash32, hash64 and nohash in both cases, adding SMP safe context handling and some basic SMP TLB management. There is room for improvements, such as implementing lazy TLB flushing on processors without invalidate-by-PID support HW, some better IPI mechanism, support for variable sizes PID, lock less fast path in the MMU context switch, etc... but it should basically work. There are some semingly unrelated patches in the pile as they are dependencies of the main ones so I'm including them in. ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
