Support for the PPC9A VME Single Board Computer from GE Fanuc (PowerPC
MPC8641D).
This is the basic board support for GE Fanuc's PPC9A, a 6U single board
computer, based on Freescale's MPC8641D.
Signed-off-by: Martyn Welch martyn.we...@gefanuc.com
---
arch/powerpc/boot/dts/gef_ppc9a.dts | 363 +++
arch/powerpc/platforms/86xx/Kconfig | 10 +
arch/powerpc/platforms/86xx/Makefile|1
arch/powerpc/platforms/86xx/gef_ppc9a.c | 223 +++
drivers/watchdog/Kconfig|2
5 files changed, 597 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/boot/dts/gef_ppc9a.dts
b/arch/powerpc/boot/dts/gef_ppc9a.dts
new file mode 100644
index 000..3be1c43
--- /dev/null
+++ b/arch/powerpc/boot/dts/gef_ppc9a.dts
@@ -0,0 +1,363 @@
+/*
+ * GE Fanuc PPC9A Device Tree Source
+ *
+ * Copyright 2008 GE Fanuc Intelligent Platforms Embedded Systems, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * Based on: SBS CM6 Device Tree Source
+ * Copyright 2007 SBS Technologies GmbH Co. KG
+ * And: mpc8641_hpcn.dts (MPC8641 HPCN Device Tree Source)
+ * Copyright 2006 Freescale Semiconductor Inc.
+ */
+
+/*
+ * Compiled with dtc -I dts -O dtb -o gef_ppc9a.dtb gef_ppc9a.dts
+ */
+
+/dts-v1/;
+
+/ {
+ model = GEF_PPC9A;
+ compatible = gef,ppc9a;
+ #address-cells = 1;
+ #size-cells = 1;
+
+ aliases {
+ ethernet0 = enet0;
+ ethernet1 = enet1;
+ serial0 = serial0;
+ serial1 = serial1;
+ pci0 = pci0;
+ };
+
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ PowerPC,8...@0 {
+ device_type = cpu;
+ reg = 0;
+ d-cache-line-size = 32; // 32 bytes
+ i-cache-line-size = 32; // 32 bytes
+ d-cache-size = 32768; // L1, 32K
+ i-cache-size = 32768; // L1, 32K
+ timebase-frequency = 0; // From uboot
+ bus-frequency = 0;// From uboot
+ clock-frequency = 0; // From uboot
+ };
+ PowerPC,8...@1 {
+ device_type = cpu;
+ reg = 1;
+ d-cache-line-size = 32; // 32 bytes
+ i-cache-line-size = 32; // 32 bytes
+ d-cache-size = 32768; // L1, 32K
+ i-cache-size = 32768; // L1, 32K
+ timebase-frequency = 0; // From uboot
+ bus-frequency = 0;// From uboot
+ clock-frequency = 0; // From uboot
+ };
+ };
+
+ memory {
+ device_type = memory;
+ reg = 0x0 0x4000; // set by uboot
+ };
+
+ local...@fef05000 {
+ #address-cells = 2;
+ #size-cells = 1;
+ compatible = fsl,mpc8641-localbus, simple-bus;
+ reg = 0xfef05000 0x1000;
+ interrupts = 19 2;
+ interrupt-parent = mpic;
+
+ ranges = 0 0 0xff00 0x0100 // 16MB Boot flash
+ 1 0 0xe800 0x0800 // Paged Flash 0
+ 2 0 0xe000 0x0800 // Paged Flash 1
+ 3 0 0xfc10 0x0002 // NVRAM
+ 4 0 0xfc00 0x8000 // FPGA
+ 5 0 0xfc008000 0x8000 // AFIX FPGA
+ 6 0 0xfd00 0x0080 // IO FPGA (8-bit)
+ 7 0 0xfd80 0x0080; // IO FPGA (32-bit)
+
+ /* fl...@0,0 is a mirror of part of the memory in fl...@1,0
+ fl...@0,0 {
+ compatible = cfi-flash;
+ reg = 0x0 0x0 0x100;
+ bank-width = 4;
+ device-width = 2;
+ #address-cells = 1;
+ #size-cells = 1;
+ partit...@0 {
+ label = firmware;
+ reg = 0x0 0x100;
+ read-only;
+ };
+ };
+ */
+
+ fl...@1,0 {
+ compatible = cfi-flash;
+ reg = 0x1 0x0 0x800;
+ bank-width = 4;
+ device-width = 2;
+ #address-cells = 1;
+ #size-cells = 1;
+
