[PATCH 1/4] 8xx: Optimze TLB Miss handlers
This removes a couple of insn's from the TLB Miss handlers whithout changing functionality. Signed-off-by: Joakim Tjernlund --- arch/powerpc/kernel/head_8xx.S | 11 +++ 1 files changed, 3 insertions(+), 8 deletions(-) diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S index 3ef743f..ecc4a02 100644 --- a/arch/powerpc/kernel/head_8xx.S +++ b/arch/powerpc/kernel/head_8xx.S @@ -343,17 +343,14 @@ InstructionTLBMiss: cmpwi cr0, r11, _PAGE_ACCESSED | _PAGE_PRESENT bne-cr0, 2f - /* Clear PP lsb, 0x400 */ - rlwinm r10, r10, 0, 22, 20 - /* The Linux PTE won't go exactly into the MMU TLB. -* Software indicator bits 22 and 28 must be clear. +* Software indicator bits 21 and 28 must be clear. * Software indicator bits 24, 25, 26, and 27 must be * set. All other Linux PTE bits control the behavior * of the MMU. */ li r11, 0x00f0 - rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */ + rlwimi r10, r11, 0, 0x07f8 /* Set 24-27, clear 21-23,28 */ DO_8xx_CPU6(0x2d80, r3) mtspr SPRN_MI_RPN, r10/* Update TLB entry */ @@ -444,9 +441,7 @@ DataStoreTLBMiss: /* Honour kernel RO, User NA */ /* 0x200 == Extended encoding, bit 22 */ - /* r11 = (r10 & _PAGE_USER) >> 2 */ - rlwinm r11, r10, 32-2, 0x200 - or r10, r11, r10 + rlwimi r10, r10, 32-2, 0x200 /* Copy USER to bit 22, 0x200 */ /* r11 = (r10 & _PAGE_RW) >> 1 */ rlwinm r11, r10, 32-1, 0x200 or r10, r11, r10 -- 1.6.4.4 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 1/4] 8xx: Optimze TLB Miss handlers
Kumar Gala wrote on 2010/02/26 21:10:31: > > > On Feb 26, 2010, at 2:29 AM, Joakim Tjernlund wrote: > > >li r11, 0x00f0 > > - rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */ > > + rlwimi r10, r11, 0, 0x07f8 /* Set 24-27, clear 21-23,28 */ > >DO_8xx_CPU6(0x2d80, r3) > >mtspr SPRN_MI_RPN, r10 /* Update TLB entry */ > > Cool, didn't know 'as' supported this notation. Yeah, it was Scott who gave me the clue and from what I can tell it is an official syntax form. I find much easier to understand. Jocke ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 1/4] 8xx: Optimze TLB Miss handlers
Scott Wood wrote on 2010/02/26 20:50:18: > > On Fri, Feb 26, 2010 at 09:29:40AM +0100, Joakim Tjernlund wrote: > > This removes a couple of insn's from the TLB Miss > > handlers whithout changing functionality. > > --- > > Did a quick test of the patchset, seems to work OK (without CONFIG_SWAP or > CONFIG_MODULES). Didn't try with CONFIG_8xx_CPU6. Cool, thanks a lot! Not sure anyone is using 2.6 with CPU6 errata. Seems it was fixed years ago. Should I resend the whole series with SOB line or just include it here? Signed-off-by: Joakim Tjernlund ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 1/4] 8xx: Optimze TLB Miss handlers
On Feb 26, 2010, at 2:29 AM, Joakim Tjernlund wrote: > li r11, 0x00f0 > - rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */ > + rlwimi r10, r11, 0, 0x07f8 /* Set 24-27, clear 21-23,28 */ > DO_8xx_CPU6(0x2d80, r3) > mtspr SPRN_MI_RPN, r10/* Update TLB entry */ Cool, didn't know 'as' supported this notation. - k ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 1/4] 8xx: Optimze TLB Miss handlers
On Fri, Feb 26, 2010 at 09:29:40AM +0100, Joakim Tjernlund wrote: > This removes a couple of insn's from the TLB Miss > handlers whithout changing functionality. > --- Did a quick test of the patchset, seems to work OK (without CONFIG_SWAP or CONFIG_MODULES). Didn't try with CONFIG_8xx_CPU6. -Scott ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 1/4] 8xx: Optimze TLB Miss handlers
This removes a couple of insn's from the TLB Miss handlers whithout changing functionality. --- arch/powerpc/kernel/head_8xx.S | 11 +++ 1 files changed, 3 insertions(+), 8 deletions(-) diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S index 3ef743f..ecc4a02 100644 --- a/arch/powerpc/kernel/head_8xx.S +++ b/arch/powerpc/kernel/head_8xx.S @@ -343,17 +343,14 @@ InstructionTLBMiss: cmpwi cr0, r11, _PAGE_ACCESSED | _PAGE_PRESENT bne-cr0, 2f - /* Clear PP lsb, 0x400 */ - rlwinm r10, r10, 0, 22, 20 - /* The Linux PTE won't go exactly into the MMU TLB. -* Software indicator bits 22 and 28 must be clear. +* Software indicator bits 21 and 28 must be clear. * Software indicator bits 24, 25, 26, and 27 must be * set. All other Linux PTE bits control the behavior * of the MMU. */ li r11, 0x00f0 - rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */ + rlwimi r10, r11, 0, 0x07f8 /* Set 24-27, clear 21-23,28 */ DO_8xx_CPU6(0x2d80, r3) mtspr SPRN_MI_RPN, r10/* Update TLB entry */ @@ -444,9 +441,7 @@ DataStoreTLBMiss: /* Honour kernel RO, User NA */ /* 0x200 == Extended encoding, bit 22 */ - /* r11 = (r10 & _PAGE_USER) >> 2 */ - rlwinm r11, r10, 32-2, 0x200 - or r10, r11, r10 + rlwimi r10, r10, 32-2, 0x200 /* Copy USER to bit 22, 0x200 */ /* r11 = (r10 & _PAGE_RW) >> 1 */ rlwinm r11, r10, 32-1, 0x200 or r10, r11, r10 -- 1.6.4.4 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
