[PATCH 10/11] celleb: add support for PCI Express
This patch adds support for PCI Express port on Celleb. I/O space
of this PCI Express port is not mapped in memory space. So we use
the io-workaround mechanism to make accesses indirect.
Signed-off-by: Kou Ishizaki <[EMAIL PROTECTED]>
Acked-by: Arnd Bergmann <[EMAIL PROTECTED]>
---
arch/powerpc/platforms/cell/Makefile |1
arch/powerpc/platforms/cell/celleb_pci.c |9
arch/powerpc/platforms/cell/celleb_pci.h |4
arch/powerpc/platforms/cell/celleb_scc.h | 87
arch/powerpc/platforms/cell/celleb_scc_pciex.c | 541 +
5 files changed, 642 insertions(+)
Index: b/arch/powerpc/platforms/cell/celleb_pci.c
===
--- a/arch/powerpc/platforms/cell/celleb_pci.c 2008-03-13 17:57:55.0
+0900
+++ b/arch/powerpc/platforms/cell/celleb_pci.c 2008-03-13 18:01:16.0
+0900
@@ -464,6 +464,9 @@
.name = "epci",
.data = celleb_setup_epci,
}, {
+ .name = "pcie",
+ .data = celleb_setup_pciex,
+ }, {
},
};
@@ -504,6 +507,12 @@
.data = (void *)0,
},
}, {
+ .name = "pcie",
+ .data = &(struct celleb_iowa_bus_param){
+ .ops = &scc_pciex_ops,
+ .init = &scc_pciex_iowa_init,
+ }
+ }, {
},
};
Index: b/arch/powerpc/platforms/cell/celleb_pci.h
===
--- a/arch/powerpc/platforms/cell/celleb_pci.h 2008-03-13 17:57:55.0
+0900
+++ b/arch/powerpc/platforms/cell/celleb_pci.h 2008-03-13 18:01:16.0
+0900
@@ -33,7 +33,11 @@
extern int celleb_pci_probe_mode(struct pci_bus *);
extern int celleb_setup_epci(struct device_node *, struct pci_controller *);
+extern int celleb_setup_pciex(struct device_node *, struct pci_controller *);
+
extern int __init celleb_io_workaround_init(void);
+extern struct ppc_pci_io scc_pciex_ops;
+int __init scc_pciex_iowa_init(struct iowa_bus *, void *);
#endif /* _CELLEB_PCI_H */
Index: b/arch/powerpc/platforms/cell/celleb_scc.h
===
--- a/arch/powerpc/platforms/cell/celleb_scc.h 2008-03-13 17:58:52.0
+0900
+++ b/arch/powerpc/platforms/cell/celleb_scc.h 2008-03-13 18:01:16.0
+0900
@@ -125,6 +125,93 @@
/* bits for SCC_EPCI_CNTOPT */
#define SCC_EPCI_CNTOPT_O2PMB 0x0002
+/* SCC PCIEXC SMMIO registers */
+#define PEXCADRS 0x000
+#define PEXCWDATA 0x004
+#define PEXCRDATA 0x008
+#define PEXDADRS 0x010
+#define PEXDCMND 0x014
+#define PEXDWDATA 0x018
+#define PEXDRDATA 0x01c
+#define PEXREQID 0x020
+#define PEXTIDMAP 0x024
+#define PEXINTMASK 0x028
+#define PEXINTSTS 0x02c
+#define PEXAERRMASK0x030
+#define PEXAERRSTS 0x034
+#define PEXPRERRMASK 0x040
+#define PEXPRERRSTS0x044
+#define PEXPRERRID01 0x048
+#define PEXPRERRID23 0x04c
+#define PEXVDMASK 0x050
+#define PEXVDSTS 0x054
+#define PEXRCVCPLIDA 0x060
+#define PEXLENERRIDA 0x068
+#define PEXPHYPLLST0x070
+#define PEXDMRDEN0 0x100
+#define PEXDMRDADR00x104
+#define PEXDMRDENX 0x110
+#define PEXDMRDADRX0x114
+#define PEXECMODE 0xf00
+#define PEXMAEA(n) (0xf50 + (8 * n))
+#define PEXMAEC(n) (0xf54 + (8 * n))
+#define PEXCCRCTRL 0xff0
+
+/* SCC PCIEXC bits and shifts for PEXCADRS */
+#define PEXCADRS_BYTE_EN_SHIFT 20
+#define PEXCADRS_CMD_SHIFT 16
+#define PEXCADRS_CMD_READ (0xa << PEXCADRS_CMD_SHIFT)
+#define PEXCADRS_CMD_WRITE (0xb << PEXCADRS_CMD_SHIFT)
+
+/* SCC PCIEXC shifts for PEXDADRS */
+#define PEXDADRS_BUSNO_SHIFT 20
+#define PEXDADRS_DEVNO_SHIFT 15
+#define PEXDADRS_FUNCNO_SHIFT 12
+
+/* SCC PCIEXC bits and shifts for PEXDCMND */
+#define PEXDCMND_BYTE_EN_SHIFT 4
+#define PEXDCMND_IO_READ 0x2
+#define PEXDCMND_IO_WRITE 0x3
+#define PEXDCMND_CONFIG_READ 0xa
+#define PEXDCMND_CONFIG_WRITE 0xb
+
+/* SCC PCIEXC bits for PEXPHYPLLST */
+#define PEXPHYPLLST_PEXPHYAPLLST 0x0001
+
+/* SCC PCIEXC bits for PEXECMODE */
+#define PEXECMODE_ALL_THROUGH 0x
+#define PEXECMODE_ALL_8BIT 0x00550155
+#define PEXECMODE_ALL_16BIT0x00aa02aa
+
+/* SCC PCIEXC bits for PEXCCRCTRL */
+#define PEXCCRCTRL_PEXIPCOREEN 0x0004
+#define PEXCCRCTRL_PEXIPCONTEN 0x0002
+#define PEXCCRCTRL_PEXPHYPLLEN 0x0001
+#define PEXCCRCTRL_PCIEXCAOCKEN0x0100
Re: [PATCH 10/11] celleb: add support for PCI Express
Arnd Bergmann <[EMAIL PROTECTED]> wrote:
> On Wednesday 05 March 2008, Ishizaki Kou wrote:
> > This patch adds support for PCI Express port on Celleb. I/O space
> > of this PCI Express port is not mapped in memory space. So we use
> > the io-workaround mechanism to make accesses indirect.
> >
> > Signed-off-by: Kou Ishizaki <[EMAIL PROTECTED]>
>
> Acked-by: Arnd Bergmann <[EMAIL PROTECTED]>
>
> This one looks good, but I wonder if we should make it possible to
> also use it on QS20, which the current code doesn't allow.
>
> It's a rather hypothetical question, because QS20 has been replaced
> by QS21 as a product and it never supported PCIe cards with I/O space
> mappings, but it would be the "right" thing to do.
>
> Since you don't have the QS20 hardware to test that, and I currently
> doubt anyone at IBM has the energy to do the work, it will probably
> never get done. If you send another version of the patch, maybe you
> can add comments to hint that this is actually possible, just hasn't
> been implemented.
Sorry, I don't know about QS20 and its chipset. However, if anyone
changes the code to work also on QS20, I'll welcome the change and
test it on Celleb.
Though I don't know it helps you, I explain a little about Celleb.
The way to access SCC PCIe I/O port is the same as the way to access
its config space.
- Write an address to the address register.
- Write an 'I/O port write' or 'I/O port read' command with byte
enable bits to the command register.
- Write or Read the data register.
That's all, and you can find this in my code.
By the way, I found a minor bug in my patch. I'll send fixed one.
> + dummy_page_da = dma_map_single(bus->phb->parent, dummy_page_va,
> + PAGE_SIZE, DMA_FROM_DEVICE);
> + if (dummy_page_da == DMA_FROM_DEVICE) {
Comparing with DMA_FROM_DEVICE is wrong. We should compare with
DMA_ERROR_CODE. And using dma_mapping_error() is the right way.
Best regards,
Kou Ishizaki
___
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Re: [PATCH 10/11] celleb: add support for PCI Express
On Wednesday 05 March 2008, Ishizaki Kou wrote: > This patch adds support for PCI Express port on Celleb. I/O space > of this PCI Express port is not mapped in memory space. So we use > the io-workaround mechanism to make accesses indirect. > > Signed-off-by: Kou Ishizaki <[EMAIL PROTECTED]> Acked-by: Arnd Bergmann <[EMAIL PROTECTED]> This one looks good, but I wonder if we should make it possible to also use it on QS20, which the current code doesn't allow. It's a rather hypothetical question, because QS20 has been replaced by QS21 as a product and it never supported PCIe cards with I/O space mappings, but it would be the "right" thing to do. Since you don't have the QS20 hardware to test that, and I currently doubt anyone at IBM has the energy to do the work, it will probably never get done. If you send another version of the patch, maybe you can add comments to hint that this is actually possible, just hasn't been implemented. ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
[PATCH 10/11] celleb: add support for PCI Express
This patch adds support for PCI Express port on Celleb. I/O space
of this PCI Express port is not mapped in memory space. So we use
the io-workaround mechanism to make accesses indirect.
Signed-off-by: Kou Ishizaki <[EMAIL PROTECTED]>
---
arch/powerpc/platforms/cell/celleb_pci.c |9
arch/powerpc/platforms/cell/celleb_pci.h |4
arch/powerpc/platforms/cell/celleb_scc.h | 87
arch/powerpc/platforms/cell/celleb_scc_pciex.c | 541 +
4 files changed, 641 insertions(+)
Index: b/arch/powerpc/platforms/cell/celleb_pci.c
===
--- a/arch/powerpc/platforms/cell/celleb_pci.c 2008-03-04 14:01:10.0
+0900
+++ b/arch/powerpc/platforms/cell/celleb_pci.c 2008-03-04 14:01:27.0
+0900
@@ -464,6 +464,9 @@
.name = "epci",
.data = celleb_setup_epci,
}, {
+ .name = "pcie",
+ .data = celleb_setup_pciex,
+ }, {
},
};
@@ -504,6 +507,12 @@
.data = (void *)0,
},
}, {
+ .name = "pcie",
+ .data = &(struct celleb_iowa_bus_param){
+ .ops = &scc_pciex_ops,
+ .init = &scc_pciex_iowa_init,
+ }
+ }, {
},
};
Index: b/arch/powerpc/platforms/cell/celleb_pci.h
===
--- a/arch/powerpc/platforms/cell/celleb_pci.h 2008-03-04 14:01:10.0
+0900
+++ b/arch/powerpc/platforms/cell/celleb_pci.h 2008-03-04 14:01:27.0
+0900
@@ -33,7 +33,11 @@
extern int celleb_pci_probe_mode(struct pci_bus *);
extern int celleb_setup_epci(struct device_node *, struct pci_controller *);
+extern int celleb_setup_pciex(struct device_node *, struct pci_controller *);
+
extern int __init celleb_io_workaround_init(void);
+extern struct ppc_pci_io scc_pciex_ops;
+int __init scc_pciex_iowa_init(struct iowa_bus *, void *);
#endif /* _CELLEB_PCI_H */
Index: b/arch/powerpc/platforms/cell/celleb_scc.h
===
--- a/arch/powerpc/platforms/cell/celleb_scc.h 2008-03-04 14:00:42.0
+0900
+++ b/arch/powerpc/platforms/cell/celleb_scc.h 2008-03-04 14:01:27.0
+0900
@@ -125,6 +125,93 @@
/* bits for SCC_EPCI_CNTOPT */
#define SCC_EPCI_CNTOPT_O2PMB 0x0002
+/* SCC PCIEXC SMMIO registers */
+#define PEXCADRS 0x000
+#define PEXCWDATA 0x004
+#define PEXCRDATA 0x008
+#define PEXDADRS 0x010
+#define PEXDCMND 0x014
+#define PEXDWDATA 0x018
+#define PEXDRDATA 0x01c
+#define PEXREQID 0x020
+#define PEXTIDMAP 0x024
+#define PEXINTMASK 0x028
+#define PEXINTSTS 0x02c
+#define PEXAERRMASK0x030
+#define PEXAERRSTS 0x034
+#define PEXPRERRMASK 0x040
+#define PEXPRERRSTS0x044
+#define PEXPRERRID01 0x048
+#define PEXPRERRID23 0x04c
+#define PEXVDMASK 0x050
+#define PEXVDSTS 0x054
+#define PEXRCVCPLIDA 0x060
+#define PEXLENERRIDA 0x068
+#define PEXPHYPLLST0x070
+#define PEXDMRDEN0 0x100
+#define PEXDMRDADR00x104
+#define PEXDMRDENX 0x110
+#define PEXDMRDADRX0x114
+#define PEXECMODE 0xf00
+#define PEXMAEA(n) (0xf50 + (8 * n))
+#define PEXMAEC(n) (0xf54 + (8 * n))
+#define PEXCCRCTRL 0xff0
+
+/* SCC PCIEXC bits and shifts for PEXCADRS */
+#define PEXCADRS_BYTE_EN_SHIFT 20
+#define PEXCADRS_CMD_SHIFT 16
+#define PEXCADRS_CMD_READ (0xa << PEXCADRS_CMD_SHIFT)
+#define PEXCADRS_CMD_WRITE (0xb << PEXCADRS_CMD_SHIFT)
+
+/* SCC PCIEXC shifts for PEXDADRS */
+#define PEXDADRS_BUSNO_SHIFT 20
+#define PEXDADRS_DEVNO_SHIFT 15
+#define PEXDADRS_FUNCNO_SHIFT 12
+
+/* SCC PCIEXC bits and shifts for PEXDCMND */
+#define PEXDCMND_BYTE_EN_SHIFT 4
+#define PEXDCMND_IO_READ 0x2
+#define PEXDCMND_IO_WRITE 0x3
+#define PEXDCMND_CONFIG_READ 0xa
+#define PEXDCMND_CONFIG_WRITE 0xb
+
+/* SCC PCIEXC bits for PEXPHYPLLST */
+#define PEXPHYPLLST_PEXPHYAPLLST 0x0001
+
+/* SCC PCIEXC bits for PEXECMODE */
+#define PEXECMODE_ALL_THROUGH 0x
+#define PEXECMODE_ALL_8BIT 0x00550155
+#define PEXECMODE_ALL_16BIT0x00aa02aa
+
+/* SCC PCIEXC bits for PEXCCRCTRL */
+#define PEXCCRCTRL_PEXIPCOREEN 0x0004
+#define PEXCCRCTRL_PEXIPCONTEN 0x0002
+#define PEXCCRCTRL_PEXPHYPLLEN 0x0001
+#define PEXCCRCTRL_PCIEXCAOCKEN0x0100
+
+/* SCC PCIEXC port configuration registers */
+#define PEXTCERRCHK0x21c
+#define PEX
