[PATCH 2/2] PPC4xx: Merge xor.h and dma.h into onefile ppc440spe-dma.h
From: Tirumala Marri
This patch combines drivers/dma/ppc4xx/xor.h and driver/dma/dma/ppc4xx/dma.h
into drivers/dma/ppc4xx/ppx440spe-dma.h .
Signed-off-by: Tirumala R Marri
---
drivers/dma/ppc4xx/dma.h | 223 -
drivers/dma/ppc4xx/ppc440spe-dma.h | 318
drivers/dma/ppc4xx/xor.h | 110 -
3 files changed, 318 insertions(+), 333 deletions(-)
delete mode 100644 drivers/dma/ppc4xx/dma.h
create mode 100644 drivers/dma/ppc4xx/ppc440spe-dma.h
delete mode 100644 drivers/dma/ppc4xx/xor.h
diff --git a/drivers/dma/ppc4xx/dma.h b/drivers/dma/ppc4xx/dma.h
deleted file mode 100644
index bcde2df..000
--- a/drivers/dma/ppc4xx/dma.h
+++ /dev/null
@@ -1,223 +0,0 @@
-/*
- * 440SPe's DMA engines support header file
- *
- * 2006-2009 (C) DENX Software Engineering.
- *
- * Author: Yuri Tikhonov
- *
- * This file is licensed under the term of the GNU General Public License
- * version 2. The program licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-
-#ifndef_PPC440SPE_DMA_H
-#define _PPC440SPE_DMA_H
-
-#include
-
-/* Number of elements in the array with statical CDBs */
-#defineMAX_STAT_DMA_CDBS 16
-/* Number of DMA engines available on the contoller */
-#define DMA_ENGINES_NUM2
-
-/* Maximum h/w supported number of destinations */
-#define DMA_DEST_MAX_NUM 2
-
-/* FIFO's params */
-#define DMA0_FIFO_SIZE 0x1000
-#define DMA1_FIFO_SIZE 0x1000
-#define DMA_FIFO_ENABLE(1<<12)
-
-/* DMA Configuration Register. Data Transfer Engine PLB Priority: */
-#define DMA_CFG_DXEPR_LP (0<<26)
-#define DMA_CFG_DXEPR_HP (3<<26)
-#define DMA_CFG_DXEPR_HHP (2<<26)
-#define DMA_CFG_DXEPR_HHHP (1<<26)
-
-/* DMA Configuration Register. DMA FIFO Manager PLB Priority: */
-#define DMA_CFG_DFMPP_LP (0<<23)
-#define DMA_CFG_DFMPP_HP (3<<23)
-#define DMA_CFG_DFMPP_HHP (2<<23)
-#define DMA_CFG_DFMPP_HHHP (1<<23)
-
-/* DMA Configuration Register. Force 64-byte Alignment */
-#define DMA_CFG_FALGN (1 << 19)
-
-/*UIC0:*/
-#define D0CPF_INT (1<<12)
-#define D0CSF_INT (1<<11)
-#define D1CPF_INT (1<<10)
-#define D1CSF_INT (1<<9)
-/*UIC1:*/
-#define DMAE_INT (1<<9)
-
-/* I2O IOP Interrupt Mask Register */
-#define I2O_IOPIM_P0SNE(1<<3)
-#define I2O_IOPIM_P0EM (1<<5)
-#define I2O_IOPIM_P1SNE(1<<6)
-#define I2O_IOPIM_P1EM (1<<8)
-
-/* DMA CDB fields */
-#define DMA_CDB_MSK(0xF)
-#define DMA_CDB_64B_ADDR (1<<2)
-#define DMA_CDB_NO_INT (1<<3)
-#define DMA_CDB_STATUS_MSK (0x3)
-#define DMA_CDB_ADDR_MSK (0xFFF0)
-
-/* DMA CDB OpCodes */
-#define DMA_CDB_OPC_NO_OP (0x00)
-#define DMA_CDB_OPC_MV_SG1_SG2 (0x01)
-#define DMA_CDB_OPC_MULTICAST (0x05)
-#define DMA_CDB_OPC_DFILL128 (0x24)
-#define DMA_CDB_OPC_DCHECK128 (0x23)
-
-#define DMA_CUED_XOR_BASE (0x1000)
-#define DMA_CUED_XOR_HB(0x0008)
-
-#ifdef CONFIG_440SP
-#define DMA_CUED_MULT1_OFF 0
-#define DMA_CUED_MULT2_OFF 8
-#define DMA_CUED_MULT3_OFF 16
-#define DMA_CUED_REGION_OFF24
-#define DMA_CUED_XOR_WIN_MSK (0xFC00)
-#else
-#define DMA_CUED_MULT1_OFF 2
-#define DMA_CUED_MULT2_OFF 10
-#define DMA_CUED_MULT3_OFF 18
-#define DMA_CUED_REGION_OFF26
-#define DMA_CUED_XOR_WIN_MSK (0xF000)
-#endif
-
-#define DMA_CUED_REGION_MSK0x3
-#define DMA_RXOR1230x0
-#define DMA_RXOR1240x1
-#define DMA_RXOR1250x2
-#define DMA_RXOR12 0x3
-
-/* S/G addresses */
-#define DMA_CDB_SG_SRC 1
-#define DMA_CDB_SG_DST12
-#define DMA_CDB_SG_DST23
-
-/*
- * DMAx engines Command Descriptor Block Type
- */
-struct dma_cdb {
- /*
-* Basic CDB structure (Table 20-17, p.499, 440spe_um_1_22.pdf)
-*/
- u8 pad0[2];/* reserved */
- u8 attr; /* attributes */
- u8 opc;/* opcode */
- u32 sg1u; /* upper SG1 address */
- u32 sg1l; /* lower SG1 address */
- u32 cnt;/* SG count, 3B used */
- u32 sg2u; /* upper SG2 address */
- u32 sg2l; /* lower SG2 address */
- u32 sg3u; /* upper SG3 address */
- u32 sg3l; /* lower SG3 address */
-};
-
-/*
- * DMAx hardware registers (p.515 in 440SPe UM 1.22)
- */
-struct dma_regs {
- u32 cpfpl;
- u32 cpfph;
- u32 csfpl;
- u32 csfph;
- u32 dsts;
- u32 cfg;
- u8 pad0[0x8];
- u16 cpfhp;
- u16 cpftp;
- u16 csfhp;
- u16 csftp;
- u8 pad1[0x8];
- u32 acpl;
- u32 acph;
- u32
Re: [PATCH 2/2] PPC4xx: Merge xor.h and dma.h into onefile ppc440spe-dma.h
Dear tma...@apm.com, In message <1284774162-14652-1-git-send-email-tma...@apm.com> you wrote: > From: Tirumala Marri > > This patch combines drivers/dma/ppc4xx/xor.h and driver/dma/dma/ppc4xx/dma.h > into drivers/dma/ppc4xx/ppx440spe-dma.h . > > Signed-off-by: Tirumala R Marri > --- > drivers/dma/ppc4xx/dma.h | 223 - > drivers/dma/ppc4xx/ppc440spe-dma.h | 318 > > drivers/dma/ppc4xx/xor.h | 110 - > 3 files changed, 318 insertions(+), 333 deletions(-) Please use -M with "git format-patch" so it detects renames (here we should probably see a rename from dma.h into ppc440spe-dma.h [plus some changes]) instead of a remove plus add file. That would make it much easier to review your changes. Thanks. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de It's a small world, but I wouldn't want to paint it. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 2/2] PPC4xx: Merge xor.h and dma.h into onefile ppc440spe-dma.h
On Fri, Sep 17, 2010 at 6:42 PM, wrote: > From: Tirumala Marri > This patch combines drivers/dma/ppc4xx/xor.h and driver/dma/dma/ppc4xx/dma.h > into drivers/dma/ppc4xx/ppx440spe-dma.h . > Is this just code churn, or do we gain anything by combining these header files? Don't add "ppc440spe-" back to the prefix, we're already in the ppc4xx directory, unless the file will only contain definitions that are relevant to ppc440spe. -- Dan ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
