[PATCH 2/2] powerpc: add support for MPIC message register API
Some MPIC implementations contain one or more blocks of message registers
that are used to send messages between cores via IPIs. A simple API has
been added to access (get/put, read, write, etc ...) these message registers.
The available message registers are initially discovered via nodes in the
device tree. A separate commit contains a binding for the message register
nodes.
Signed-off-by: Meador Inge
Signed-off-by: Jia Hongtao
Signed-off-by: Li Yang
---
This patch is an update for : http://patchwork.ozlabs.org/patch/98075/
Meador Inge addressed the following points from Ben's feedback:
* Drop the 'mpic_msgr.msr' field.
* Drop the 'mpic_msgr.mer' field in favor of address arithmetic off of
'mpic_msgr.addr'.
* Document the API.
* Disable MPIC register in 'mpic_msgr_put'.
* Put locking in 'mpic_msgr_disable'.
* s/EXPORT_SYMBOL/EXPORT_SYMBOL_GPL/g.
* Make 'mpic_msgr_write' and 'mpic_msgr_read' 'static inline'.
I just fixed the checkpatch errors and addressed the following item:
* In 'mpic_msgr_set_destination' have a wrapper that goes from Linux
CPU number to HW CPU number.
arch/powerpc/include/asm/mpic_msgr.h | 132
arch/powerpc/platforms/Kconfig |8 +
arch/powerpc/sysdev/Makefile |2 +
arch/powerpc/sysdev/mpic_msgr.c | 282 ++
4 files changed, 424 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/include/asm/mpic_msgr.h
create mode 100644 arch/powerpc/sysdev/mpic_msgr.c
diff --git a/arch/powerpc/include/asm/mpic_msgr.h
b/arch/powerpc/include/asm/mpic_msgr.h
new file mode 100644
index 000..3ec37dc
--- /dev/null
+++ b/arch/powerpc/include/asm/mpic_msgr.h
@@ -0,0 +1,132 @@
+/*
+ * Copyright 2011-2012, Meador Inge, Mentor Graphics Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; version 2 of the
+ * License.
+ *
+ */
+
+#ifndef _ASM_MPIC_MSGR_H
+#define _ASM_MPIC_MSGR_H
+
+#include
+#include
+
+struct mpic_msgr {
+ u32 __iomem *base;
+ u32 __iomem *mer;
+ int irq;
+ unsigned char in_use;
+ raw_spinlock_t lock;
+ int num;
+};
+
+/* Get a message register
+ *
+ * @reg_num: the MPIC message register to get
+ *
+ * A pointer to the message register is returned. If
+ * the message register asked for is already in use, then
+ * EBUSY is returned. If the number given is not associated
+ * with an actual message register, then ENODEV is returned.
+ * Successfully getting the register marks it as in use.
+ */
+extern struct mpic_msgr *mpic_msgr_get(unsigned int reg_num);
+
+/* Relinquish a message register
+ *
+ * @msgr: the message register to return
+ *
+ * Disables the given message register and marks it as free.
+ * After this call has completed successully the message
+ * register is available to be acquired by a call to
+ * mpic_msgr_get.
+ */
+extern void mpic_msgr_put(struct mpic_msgr *msgr);
+
+/* Enable a message register
+ *
+ * @msgr: the message register to enable
+ *
+ * The given message register is enabled for sending
+ * messages.
+ */
+extern void mpic_msgr_enable(struct mpic_msgr *msgr);
+
+/* Disable a message register
+ *
+ * @msgr: the message register to disable
+ *
+ * The given message register is disabled for sending
+ * messages.
+ */
+extern void mpic_msgr_disable(struct mpic_msgr *msgr);
+
+/* Write a message to a message register
+ *
+ * @msgr: the message register to write to
+ * @message: the message to write
+ *
+ * The given 32-bit message is written to the given message
+ * register. Writing to an enabled message registers fires
+ * an interrupt.
+ */
+static inline void mpic_msgr_write(struct mpic_msgr *msgr, u32 message)
+{
+ out_be32(msgr->base, message);
+}
+
+/* Read a message from a message register
+ *
+ * @msgr: the message register to read from
+ *
+ * Returns the 32-bit value currently in the given message register.
+ * Upon reading the register any interrupts for that register are
+ * cleared.
+ */
+static inline u32 mpic_msgr_read(struct mpic_msgr *msgr)
+{
+ return in_be32(msgr->base);
+}
+
+/* Clear a message register
+ *
+ * @msgr: the message register to clear
+ *
+ * Clears any interrupts associated with the given message register.
+ */
+static inline void mpic_msgr_clear(struct mpic_msgr *msgr)
+{
+ (void) mpic_msgr_read(msgr);
+}
+
+/* Set the destination CPU for the message register
+ *
+ * @msgr: the message register whose destination is to be set
+ * @cpu_num: the Linux CPU number to bind the message register to
+ *
+ * Note that the CPU number given is the CPU number used by the kernel
+ * and *not* the actual hardware CPU number.
+ */
+static inline void mpic_msgr_set_destination(struct mpic_msgr *msgr,
+u32 cpu_num)
+{
+ out_be32(msgr->base, 1 << get_hard_s
[PATCH 2/2] powerpc: add support for MPIC message register API
Some MPIC implementations contain one or more blocks of message registers
that are used to send messages between cores via IPIs. A simple API has
been added to access (get/put, read, write, etc ...) these message registers.
The available message registers are initially discovered via nodes in the
device tree. A separate commit contains a binding for the message register
nodes.
Signed-off-by: Meador Inge
Cc: Benjamin Herrenschmidt
Cc: Hollis Blanchard
---
arch/powerpc/include/asm/mpic_msgr.h | 35 +
arch/powerpc/platforms/Kconfig |8 +
arch/powerpc/sysdev/Makefile |3 +-
arch/powerpc/sysdev/mpic_msgr.c | 279 ++
4 files changed, 324 insertions(+), 1 deletions(-)
create mode 100644 arch/powerpc/include/asm/mpic_msgr.h
create mode 100644 arch/powerpc/sysdev/mpic_msgr.c
diff --git a/arch/powerpc/include/asm/mpic_msgr.h
b/arch/powerpc/include/asm/mpic_msgr.h
new file mode 100644
index 000..370dcb4
--- /dev/null
+++ b/arch/powerpc/include/asm/mpic_msgr.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright 2011-2012, Meador Inge, Mentor Graphics Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; version 2 of the
+ * License.
+ *
+ */
+
+#ifndef _ASM_MPIC_MSGR_H
+#define _ASM_MPIC_MSGR_H
+
+#include
+
+struct mpic_msgr {
+ u32 __iomem *addr;
+ u32 __iomem *mer;
+ u32 __iomem *msr;
+ int irq;
+ atomic_t in_use;
+ int num;
+};
+
+extern struct mpic_msgr* mpic_msgr_get(unsigned int reg_num);
+extern void mpic_msgr_put(struct mpic_msgr* msgr);
+extern void mpic_msgr_enable(struct mpic_msgr *msgr);
+extern void mpic_msgr_disable(struct mpic_msgr *msgr);
+extern void mpic_msgr_write(struct mpic_msgr *msgr, u32 message);
+extern u32 mpic_msgr_read(struct mpic_msgr *msgr);
+extern void mpic_msgr_clear(struct mpic_msgr *msgr);
+extern void mpic_msgr_set_destination(struct mpic_msgr *msgr, u32 cpu_num);
+extern int mpic_msgr_get_irq(struct mpic_msgr *msgr);
+
+#endif
diff --git a/arch/powerpc/platforms/Kconfig b/arch/powerpc/platforms/Kconfig
index f7b0772..4d65593 100644
--- a/arch/powerpc/platforms/Kconfig
+++ b/arch/powerpc/platforms/Kconfig
@@ -78,6 +78,14 @@ config MPIC_WEIRD
bool
default n
+config MPIC_MSGR
+ bool "MPIC message register support"
+ depends on MPIC
+ default n
+ help
+ Enables support for the MPIC message registers. These
+ registers are used for inter-processor communication.
+
config PPC_I8259
bool
default n
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index 1e0c933..6d40185 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -3,7 +3,8 @@ subdir-ccflags-$(CONFIG_PPC_WERROR) := -Werror
ccflags-$(CONFIG_PPC64):= -mno-minimal-toc
mpic-msi-obj-$(CONFIG_PCI_MSI) += mpic_msi.o mpic_u3msi.o mpic_pasemi_msi.o
-obj-$(CONFIG_MPIC) += mpic.o $(mpic-msi-obj-y)
+mpic-msgr-obj-$(CONFIG_MPIC_MSGR) += mpic_msgr.o
+obj-$(CONFIG_MPIC) += mpic.o $(mpic-msi-obj-y) $(mpic-msgr-obj-y)
fsl-msi-obj-$(CONFIG_PCI_MSI) += fsl_msi.o
obj-$(CONFIG_PPC_MSI_BITMAP) += msi_bitmap.o
diff --git a/arch/powerpc/sysdev/mpic_msgr.c b/arch/powerpc/sysdev/mpic_msgr.c
new file mode 100644
index 000..352bfa6
--- /dev/null
+++ b/arch/powerpc/sysdev/mpic_msgr.c
@@ -0,0 +1,279 @@
+/*
+ * Copyright 2011-2012, Meador Inge, Mentor Graphics Corporation.
+ *
+ * Some ideas based on un-pushed work done by Vivek Mahajan, Jason Jin, and
+ * Mingkai Hu from Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; version 2 of the
+ * License.
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define MPIC_MSGR_REGISTERS_PER_BLOCK 4
+#define MSGR_INUSE 0
+#define MSGR_FREE 1
+
+/* Internal structure used *only* for IO mapping register blocks. */
+struct mpic_msgr_block {
+ struct msgr {
+ u32 msgr;
+ u8 res[12];
+ } msgrs[MPIC_MSGR_REGISTERS_PER_BLOCK];
+ u8 res0[192];
+ u32 mer;
+ u8 res1[12];
+ u32 msr;
+};
+
+static struct mpic_msgr **mpic_msgrs = 0;
+static unsigned int mpic_msgr_count = 0;
+
+struct mpic_msgr* mpic_msgr_get(unsigned int reg_num)
+{
+ struct mpic_msgr* msgr;
+
+ if (reg_num >= mpic_msgr_count)
+ return ERR_PTR(-ENODEV);
+
+ msgr = mpic_msgrs[reg_num];
+
+ if (atomic_cmpxchg(&msgr->in_use, MSGR_FREE, MSGR_INUSE) == MSGR_FREE)
+ return msgr;
+
+ return ERR_PTR(-EBUSY);
+}
+EXPORT_SYMBOL(mpic_msgr_get);
+
+void mpic_msgr_put(struct mpic_msgr* msgr)
+{
+ atomic_set(&msgr->in_use, MSGR_F
Re: [PATCH 2/2] powerpc: add support for MPIC message register API
On Feb 16, 2012, at 8:49 PM, Jia Hongtao wrote: > Some MPIC implementations contain one or more blocks of message registers > that are used to send messages between cores via IPIs. A simple API has > been added to access (get/put, read, write, etc ...) these message registers. > The available message registers are initially discovered via nodes in the > device tree. A separate commit contains a binding for the message register > nodes. > > Signed-off-by: Meador Inge > Signed-off-by: Jia Hongtao > Signed-off-by: Li Yang > --- > This patch is an update for : http://patchwork.ozlabs.org/patch/98075/ > > Meador Inge addressed the following points from Ben's feedback: > * Drop the 'mpic_msgr.msr' field. > * Drop the 'mpic_msgr.mer' field in favor of address arithmetic off of > 'mpic_msgr.addr'. > * Document the API. > * Disable MPIC register in 'mpic_msgr_put'. > * Put locking in 'mpic_msgr_disable'. > * s/EXPORT_SYMBOL/EXPORT_SYMBOL_GPL/g. > * Make 'mpic_msgr_write' and 'mpic_msgr_read' 'static inline'. > > I just fixed the checkpatch errors and addressed the following item: > * In 'mpic_msgr_set_destination' have a wrapper that goes from Linux > CPU number to HW CPU number. > > arch/powerpc/include/asm/mpic_msgr.h | 132 > arch/powerpc/platforms/Kconfig |8 + > arch/powerpc/sysdev/Makefile |2 + > arch/powerpc/sysdev/mpic_msgr.c | 282 ++ > 4 files changed, 424 insertions(+), 0 deletions(-) > create mode 100644 arch/powerpc/include/asm/mpic_msgr.h > create mode 100644 arch/powerpc/sysdev/mpic_msgr.c applied - k ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
RE: [PATCH 2/2] powerpc: add support for MPIC message register API
Hi,
I have no comments about coding and architecture. It looks fine.
Only have a query about its use case..
"Any application intended to use message interrupt requires to know reg_num
because of struct mpic_msgr* mpic_msgr_get(unsigned int reg_num) API"
It will be good to search available unit internally and provide its pointer. It
will make application more flexible.
Regards,
Prabhakar
> -Original Message-
> From: devicetree-discuss-bounces+b32579=freescale@lists.ozlabs.org
> [mailto:devicetree-discuss-bounces+b32579=freescale@lists.ozlabs.org]
> On Behalf Of Meador Inge
> Sent: Tuesday, April 19, 2011 10:30 PM
> To: linuxppc-dev@lists.ozlabs.org
> Cc: openmcapi-...@googlegroups.com; devicetree-disc...@lists.ozlabs.org;
> Hollis Blanchard
> Subject: [PATCH 2/2] powerpc: add support for MPIC message register API
>
> Some MPIC implementations contain one or more blocks of message registers
> that are used to send messages between cores via IPIs. A simple API has
> been added to access (get/put, read, write, etc ...) these message
> registers.
> The available message registers are initially discovered via nodes in the
> device tree. A separate commit contains a binding for the message
> register nodes.
>
> Signed-off-by: Meador Inge
> Cc: Benjamin Herrenschmidt
> Cc: Hollis Blanchard
> ---
> arch/powerpc/include/asm/mpic_msgr.h | 35 +
> arch/powerpc/platforms/Kconfig |8 +
> arch/powerpc/sysdev/Makefile |3 +-
> arch/powerpc/sysdev/mpic_msgr.c | 279
> ++
> 4 files changed, 324 insertions(+), 1 deletions(-) create mode 100644
> arch/powerpc/include/asm/mpic_msgr.h
> create mode 100644 arch/powerpc/sysdev/mpic_msgr.c
>
> diff --git a/arch/powerpc/include/asm/mpic_msgr.h
> b/arch/powerpc/include/asm/mpic_msgr.h
> new file mode 100644
> index 000..370dcb4
> --- /dev/null
> +++ b/arch/powerpc/include/asm/mpic_msgr.h
> @@ -0,0 +1,35 @@
> +/*
> + * Copyright 2011-2012, Meador Inge, Mentor Graphics Corporation.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License
> + * as published by the Free Software Foundation; version 2 of the
> + * License.
> + *
> + */
> +
> +#ifndef _ASM_MPIC_MSGR_H
> +#define _ASM_MPIC_MSGR_H
> +
> +#include
> +
> +struct mpic_msgr {
> + u32 __iomem *addr;
> + u32 __iomem *mer;
> + u32 __iomem *msr;
> + int irq;
> + atomic_t in_use;
> + int num;
> +};
> +
> +extern struct mpic_msgr* mpic_msgr_get(unsigned int reg_num); extern
> +void mpic_msgr_put(struct mpic_msgr* msgr); extern void
> +mpic_msgr_enable(struct mpic_msgr *msgr); extern void
> +mpic_msgr_disable(struct mpic_msgr *msgr); extern void
> +mpic_msgr_write(struct mpic_msgr *msgr, u32 message); extern u32
> +mpic_msgr_read(struct mpic_msgr *msgr); extern void
> +mpic_msgr_clear(struct mpic_msgr *msgr); extern void
> +mpic_msgr_set_destination(struct mpic_msgr *msgr, u32 cpu_num); extern
> +int mpic_msgr_get_irq(struct mpic_msgr *msgr);
> +
> +#endif
> diff --git a/arch/powerpc/platforms/Kconfig
> b/arch/powerpc/platforms/Kconfig index f7b0772..4d65593 100644
> --- a/arch/powerpc/platforms/Kconfig
> +++ b/arch/powerpc/platforms/Kconfig
> @@ -78,6 +78,14 @@ config MPIC_WEIRD
> bool
> default n
>
> +config MPIC_MSGR
> + bool "MPIC message register support"
> + depends on MPIC
> + default n
> + help
> + Enables support for the MPIC message registers. These
> + registers are used for inter-processor communication.
> +
> config PPC_I8259
> bool
> default n
> diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
> index 1e0c933..6d40185 100644
> --- a/arch/powerpc/sysdev/Makefile
> +++ b/arch/powerpc/sysdev/Makefile
> @@ -3,7 +3,8 @@ subdir-ccflags-$(CONFIG_PPC_WERROR) := -Werror
> ccflags-$(CONFIG_PPC64) := -mno-minimal-toc
>
> mpic-msi-obj-$(CONFIG_PCI_MSI) += mpic_msi.o mpic_u3msi.o
> mpic_pasemi_msi.o
> -obj-$(CONFIG_MPIC) += mpic.o $(mpic-msi-obj-y)
> +mpic-msgr-obj-$(CONFIG_MPIC_MSGR)+= mpic_msgr.o
> +obj-$(CONFIG_MPIC) += mpic.o $(mpic-msi-obj-y) $(mpic-msgr-
> obj-y)
> fsl-msi-obj-$(CONFIG_PCI_MSI)+= fsl_msi.o
> obj-$(CONFIG_PPC_MSI_BITMAP) += msi_bitmap.o
>
> diff --git a/arch/powerpc/sysdev/mpic_msgr.c
> b/arch/powerpc/sysdev/mpic_msgr.c new file mode 100644 index
> 000..352bfa6
> --- /dev/null
> +++ b/arch/powerpc/sysdev/mpic_msgr.c
> @@ -0,0 +1,279 @@
> +/*
> + * Copyright 2011-2012, Meador Inge, Mentor Gr
Re: [PATCH 2/2] powerpc: add support for MPIC message register API
On 04/28/2011 10:00 PM, Kushwaha Prabhakar-B32579 wrote: Hi, I have no comments about coding and architecture. It looks fine. Only have a query about its use case.. "Any application intended to use message interrupt requires to know reg_num because of struct mpic_msgr* mpic_msgr_get(unsigned int reg_num) API" It will be good to search available unit internally and provide its pointer. It will make application more flexible. The problem is that you fundamentally cannot implement an allocator for MSG registers if you're going to communicate with another kernel (how would both kernels' allocators be synchronized?). So the message register allocation must be decided at design time, not run time. Hollis Blanchard Mentor Graphics, Embedded Systems Division ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
RE: [PATCH 2/2] powerpc: add support for MPIC message register API
> > Hi, > > > > I have no comments about coding and architecture. It looks fine. > > > > Only have a query about its use case.. > >"Any application intended to use message interrupt requires to know > reg_num because of struct mpic_msgr* mpic_msgr_get(unsigned int reg_num) > API" > > > > It will be good to search available unit internally and provide its > pointer. It will make application more flexible. > > > > The problem is that you fundamentally cannot implement an allocator for > MSG registers if you're going to communicate with another kernel (how > would both kernels' allocators be synchronized?). So the message register > allocation must be decided at design time, not run time. > I agree with you.. It is true while communicating with another kernel. But message interrupts can be used by different independent drivers within same kernel. For eg. PCIe and Ethernet driver. As per current design both drivers needs to be in sync before requesting any message unit for avoiding any conflict. As these drivers are completely independent. It is very difficult. Can it be possible to provide new API to take care it. --Prabhakar ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 2/2] powerpc: add support for MPIC message register API
On Fri, 29 Apr 2011 17:27:06 + Kushwaha Prabhakar-B32579 wrote: > > > > > Hi, > > > > > > I have no comments about coding and architecture. It looks fine. > > > > > > Only have a query about its use case.. > > >"Any application intended to use message interrupt requires to know > > reg_num because of struct mpic_msgr* mpic_msgr_get(unsigned int reg_num) > > API" > > > > > > It will be good to search available unit internally and provide its > > pointer. It will make application more flexible. > > > > > > > The problem is that you fundamentally cannot implement an allocator for > > MSG registers if you're going to communicate with another kernel (how > > would both kernels' allocators be synchronized?). So the message register > > allocation must be decided at design time, not run time. > > > > I agree with you.. It is true while communicating with another kernel. > But message interrupts can be used by different independent drivers within > same kernel. For eg. PCIe and Ethernet driver. > As per current design both drivers needs to be in sync before requesting any > message unit for avoiding any conflict. As these drivers are completely > independent. It is very difficult. > > Can it be possible to provide new API to take care it. Do you have a real use case in mind where these message registers (not MSIs) are used internally in this manner? Perhaps an allocator could be added in the same patchset that adds such a user. -Scott ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
RE: [PATCH 2/2] powerpc: add support for MPIC message register API
> > > > > > > > > Hi, > > > > > > > > I have no comments about coding and architecture. It looks fine. > > > > > > > > Only have a query about its use case.. > > > >"Any application intended to use message interrupt requires to > > > > know > > > reg_num because of struct mpic_msgr* mpic_msgr_get(unsigned int > > > reg_num) API" > > > > > > > > It will be good to search available unit internally and provide > > > > its > > > pointer. It will make application more flexible. > > > > > > > > > > The problem is that you fundamentally cannot implement an allocator > > > for MSG registers if you're going to communicate with another kernel > > > (how would both kernels' allocators be synchronized?). So the > > > message register allocation must be decided at design time, not run > time. > > > > > > > I agree with you.. It is true while communicating with another kernel. > > But message interrupts can be used by different independent drivers > within same kernel. For eg. PCIe and Ethernet driver. > > As per current design both drivers needs to be in sync before > requesting any message unit for avoiding any conflict. As these drivers > are completely independent. It is very difficult. > > > > Can it be possible to provide new API to take care it. > > Do you have a real use case in mind where these message registers (not > MSIs) are used internally in this manner? Yes, we use for PCIe host/agent test case scenario. Host usage message register to interrupt Agent... Agent uses message register to generate irq_out (automatically generate MSI) to interrupt master. Please see RM for more details about irq_out Note: PCIe host/agent test scenario is used internally and we are working on pushing it out.. > Perhaps an allocator could be added in the same patchset that adds such a > user. > Yaa. It can be done. Otherwise module has to query each message unit for its availability. --Prabhakar ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 2/2] powerpc: add support for MPIC message register API
On 05/01/2011 08:41 PM, Kushwaha Prabhakar-B32579 wrote: Hi, I have no comments about coding and architecture. It looks fine. Only have a query about its use case.. "Any application intended to use message interrupt requires to know reg_num because of struct mpic_msgr* mpic_msgr_get(unsigned int reg_num) API" It will be good to search available unit internally and provide its pointer. It will make application more flexible. The problem is that you fundamentally cannot implement an allocator for MSG registers if you're going to communicate with another kernel (how would both kernels' allocators be synchronized?). So the message register allocation must be decided at design time, not run time. I agree with you.. It is true while communicating with another kernel. But message interrupts can be used by different independent drivers within same kernel. For eg. PCIe and Ethernet driver. As per current design both drivers needs to be in sync before requesting any message unit for avoiding any conflict. As these drivers are completely independent. It is very difficult. Can it be possible to provide new API to take care it. Do you have a real use case in mind where these message registers (not MSIs) are used internally in this manner? Yes, we use for PCIe host/agent test case scenario. Host usage message register to interrupt Agent... Agent uses message register to generate irq_out (automatically generate MSI) to interrupt master. Please see RM for more details about irq_out Note: PCIe host/agent test scenario is used internally and we are working on pushing it out.. I believe this has been true for several years. Perhaps an allocator could be added in the same patchset that adds such a user. Yaa. It can be done. Otherwise module has to query each message unit for its availability. No, instead the system designer should pick one. If it doesn't matter which one, then the designer is free to pick any. An allocator can't work if you're going to mix drivers. For example, driver A needs MSRG0, and driver B doesn't care. Driver B loads first, the allocator selects MSGR0; driver A loads and fails. Having an allocator at all will create this conflict. To prevent this scenario, either don't use a MSGR (can you configure anything else for irq_out?), or have the system designer choose all MSGRs. Hollis Blanchard Mentor Graphics, Embedded Systems Division ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 2/2] powerpc: add support for MPIC message register API
On Mon, 2 May 2011 09:03:53 -0700 Hollis Blanchard wrote: > On 05/01/2011 08:41 PM, Kushwaha Prabhakar-B32579 wrote: > >> Perhaps an allocator could be added in the same patchset that adds such a > >> user. > > Yaa. It can be done. Otherwise module has to query each message unit for > > its availability. > > No, instead the system designer should pick one. If it doesn't matter > which one, then the designer is free to pick any. We should avoid resorting to the notion of a "system designer" if possible -- it's hard to avoid it when dealing with partitioning, but it shouldn't be needed for unpartitioned basic driver operation. > An allocator can't work if you're going to mix drivers. For example, > driver A needs MSRG0, and driver B doesn't care. Driver B loads first, > the allocator selects MSGR0; driver A loads and fails. Having an > allocator at all will create this conflict. In the absence of partitioning, no driver should need a specific one. With partitioning, let the system designer mark those resources as reserved so they don't get allocated. :-) -Scott ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 2/2] powerpc: add support for MPIC message register API
On 05/03/2011 10:19 AM, Scott Wood wrote:
> In the absence of partitioning, no driver should need a specific one. With
> partitioning, let the system designer mark those resources as reserved so
> they don't get allocated. :-)
That seem reasonable. Back to the device tree then. One option is to bring
back the sister-send property 'mpic-msgr-send-mask', which was discussed some
months back. For example, consider:
/* OS 1 */
mpic_msgr_block0: mpic-msgr-block@41400 {
compatible = "fsl,mpic-v3.1-msgr";
reg = <0x41400 0x200>;
interrupts = <0xb0 2 0xb2 2>;
mpic-msgr-receive-mask = <0x5>;
mpic-msgr-send-mask = <0xa>;
};
mpic_msgr_block1: mpic-msgr-block@42400 {
compatible = "fsl,mpic-v3.1-msgr";
reg = <0x42400 0x200>;
interrupts = <0xb4 2 0xb6 2>;
mpic-msgr-receive-mask = <0x5>;
};
/* OS 2 */
mpic_msgr_block0: mpic-msgr-block@41400 {
compatible = "fsl,mpic-v3.1-msgr";
reg = <0x41400 0x200>;
interrupts = <0xb0 2 0xb2 2>;
mpic-msgr-receive-mask = <0xa>;
mpic-msgr-send-mask = <0x5>;
};
mpic_msgr_block1: mpic-msgr-block@42400 {
compatible = "fsl,mpic-v3.1-msgr";
reg = <0x42400 0x200>;
interrupts = <0xb4 2 0xb6 2>;
mpic-msgr-send-mask = <0x5>;
};
In block0 for both OSes, all registers are partitioned and are thus not
available for allocation. In block1 for both OSes, registers 0 and 2 are
reserved and registers 1 and 3 are available for general allocation.
So any register mentioned in one of 'mpic-msgr-receive-mask' or
'mpic-msgr-send-mask' is out of the running for general allocation.
If neither of the properties appear, then all registers are available
for general allocation.
You could get into trouble with this method with cases like:
/* OS 1 */
mpic_msgr_block0: mpic-msgr-block@41400 {
compatible = "fsl,mpic-v3.1-msgr";
reg = <0x41400 0x200>;
interrupts = <0xb0 2 0xb2 2>;
mpic-msgr-send-mask = <0xa>;
};
/* OS 2 */
mpic_msgr_block0: mpic-msgr-block@41400 {
compatible = "fsl,mpic-v3.1-msgr";
reg = <0x41400 0x200>;
interrupts = <0xb0 2 0xb2 2>;
mpic-msgr-receive-mask = <0x5>;
};
Now OS 1 has registers 0 and 2 available for general allocation, which
OS 2 is receiving on. However, we already have that problem if someone
botches the masks. So I am not very worried about that.
Clearly this is just one method, but I think tagging what is available from the
device tree is a must.
Thoughts?
--
Meador Inge | meador_inge AT mentor.com
Mentor Embedded | http://www.mentor.com/embedded-software
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Re: [PATCH 2/2] powerpc: add support for MPIC message register API
On Thu, 5 May 2011 16:41:29 -0500
Meador Inge wrote:
> /* OS 1 */
> mpic_msgr_block0: mpic-msgr-block@41400 {
> compatible = "fsl,mpic-v3.1-msgr";
> reg = <0x41400 0x200>;
> interrupts = <0xb0 2 0xb2 2>;
> mpic-msgr-receive-mask = <0x5>;
> mpic-msgr-send-mask = <0xa>;
> };
>
> mpic_msgr_block1: mpic-msgr-block@42400 {
> compatible = "fsl,mpic-v3.1-msgr";
> reg = <0x42400 0x200>;
> interrupts = <0xb4 2 0xb6 2>;
> mpic-msgr-receive-mask = <0x5>;
> };
>
> /* OS 2 */
> mpic_msgr_block0: mpic-msgr-block@41400 {
> compatible = "fsl,mpic-v3.1-msgr";
> reg = <0x41400 0x200>;
> interrupts = <0xb0 2 0xb2 2>;
> mpic-msgr-receive-mask = <0xa>;
> mpic-msgr-send-mask = <0x5>;
> };
>
> mpic_msgr_block1: mpic-msgr-block@42400 {
> compatible = "fsl,mpic-v3.1-msgr";
> reg = <0x42400 0x200>;
> interrupts = <0xb4 2 0xb6 2>;
> mpic-msgr-send-mask = <0x5>;
> };
>
> In block0 for both OSes, all registers are partitioned and are thus not
> available for allocation. In block1 for both OSes, registers 0 and 2 are
> reserved and registers 1 and 3 are available for general allocation.
How can both OSes independently own registers 1 and 3 for alloction? And
where are the interrupt specifiers for these registers?
> So any register mentioned in one of 'mpic-msgr-receive-mask' or
> 'mpic-msgr-send-mask' is out of the running for general allocation.
mpic-msgr-receive-mask has to match interrupts -- it's not intended to be
an indication of usage, just that this partition is granted those
interrupts.
Plus, a dynamically allocated message register must be owned for both
sending and receiving, so it doesn't make sense to separate it. I'd have
an "mpic-msgr-free-mask" property, which must be a subset of
"mpic-msgr-receive-mask". If the register is not in free-mask, it is
reserved for a fixed purpose. If free-mask is absent, all registers in the
receive-mask can be allocated.
So the above example would be:
/* OS 1 */
mpic_msgr_block0: mpic-msgr-block@41400 {
compatible = "fsl,mpic-v3.1-msgr";
reg = <0x41400 0x200>;
interrupts = <0xb0 2 0xb2 2>;
mpic-msgr-receive-mask = <0x5>;
mpic-msgr-free-mask = <0>;
};
mpic_msgr_block1: mpic-msgr-block@42400 {
compatible = "fsl,mpic-v3.1-msgr";
reg = <0x42400 0x200>;
interrupts = <0xb4 2 0xb5 2>;
mpic-msgr-receive-mask = <0x3>;
mpic-msgr-free-mask = <0x2>;
};
/* OS 2 */
mpic_msgr_block0: mpic-msgr-block@41400 {
compatible = "fsl,mpic-v3.1-msgr";
reg = <0x41400 0x200>;
interrupts = <0xb1 2 0xb3 2>;
mpic-msgr-receive-mask = <0xa>;
mpic-msgr-free-mask = <0>;
};
mpic_msgr_block1: mpic-msgr-block@42400 {
compatible = "fsl,mpic-v3.1-msgr";
reg = <0x42400 0x200>;
interrupts = <0xb6 2 0xb7 2>;
mpic-msgr-receive-mask = <0xc>;
mpic-msgr-free-mask = <0x8>;
};
mpic-msgr-send-mask could be added as well, as a permissions mechanism to
serve as extra protection against an improperly specified non-free message
register -- especially if the interface is exposed to a less-trusted realm
such as userspace, or if a hypervisor is reading the device tree to
determine what to allow guests to do. In this case, just like
mpic-msgr-receive-mask, it would list both free and non-free message
registers that the partition can send to, and mpic-msgr-free-mask would be
a subset of both the send and receive masks.
> You could get into trouble with this method with cases like:
>
> /* OS 1 */
> mpic_msgr_block0: mpic-msgr-block@41400 {
> compatible = "fsl,mpic-v3.1-msgr";
> reg = <0x41400 0x200>;
> interrupts = <0xb0 2 0xb2 2>;
> mpic-msgr-send-mask = <0xa>;
> };
>
> /* OS 2 */
> mpic_msgr_block0: mpic-msgr-block@41400 {
> compatible = "fsl,mpic-v3.1-msgr";
> reg = <0x41400 0x200>;
> interrupts = <0xb0 2 0xb2 2>;
> mpic-msgr-receive-mask = <0x5>;
> };
>
> Now OS 1 has registers 0 and 2 available for general allocation, which
> OS 2 is receiving on. However, we already have that problem if someone
> botches the masks. So I am not very worried about that.
There's a big difference between "botching the masks" and having no way to
express the situation properly.
BTW, the above fragment has the two OSes inappropriately sharing
interrupts, and OS1 has only two interrupts but n
Re: [PATCH 2/2] powerpc: add support for MPIC message register API
On 05/06/2011 02:29 PM, Scott Wood wrote:
> On Thu, 5 May 2011 16:41:29 -0500
>
> How can both OSes independently own registers 1 and 3 for alloction?
They can't. I just choose a horrible example. It does point to a serious
flaw (which you allude to later) in inferring free registers from send/receive:
in some cases one will have to arbitrarily add registers to send/receive masks
just to keep registers out of the free allocation pool. Your free-mask
proposal is better.
>> So any register mentioned in one of 'mpic-msgr-receive-mask' or
>> 'mpic-msgr-send-mask' is out of the running for general allocation.
>
> mpic-msgr-receive-mask has to match interrupts -- it's not intended to be
> an indication of usage, just that this partition is granted those
> interrupts.
>
> Plus, a dynamically allocated message register must be owned for both
> sending and receiving, so it doesn't make sense to separate it. I'd have
> an "mpic-msgr-free-mask" property, which must be a subset of
> "mpic-msgr-receive-mask". If the register is not in free-mask, it is
> reserved for a fixed purpose. If free-mask is absent, all registers in the
> receive-mask can be allocated.
>
> So the above example would be:
>
> /* OS 1 */
> mpic_msgr_block0: mpic-msgr-block@41400 {
> compatible = "fsl,mpic-v3.1-msgr";
> reg = <0x41400 0x200>;
> interrupts = <0xb0 2 0xb2 2>;
> mpic-msgr-receive-mask = <0x5>;
> mpic-msgr-free-mask = <0>;
> };
>
> mpic_msgr_block1: mpic-msgr-block@42400 {
> compatible = "fsl,mpic-v3.1-msgr";
> reg = <0x42400 0x200>;
> interrupts = <0xb4 2 0xb5 2>;
> mpic-msgr-receive-mask = <0x3>;
> mpic-msgr-free-mask = <0x2>;
> };
>
> /* OS 2 */
> mpic_msgr_block0: mpic-msgr-block@41400 {
> compatible = "fsl,mpic-v3.1-msgr";
> reg = <0x41400 0x200>;
> interrupts = <0xb1 2 0xb3 2>;
> mpic-msgr-receive-mask = <0xa>;
> mpic-msgr-free-mask = <0>;
> };
>
> mpic_msgr_block1: mpic-msgr-block@42400 {
> compatible = "fsl,mpic-v3.1-msgr";
> reg = <0x42400 0x200>;
> interrupts = <0xb6 2 0xb7 2>;
> mpic-msgr-receive-mask = <0xc>;
> mpic-msgr-free-mask = <0x8>;
> };
>
> mpic-msgr-send-mask could be added as well, as a permissions mechanism to
> serve as extra protection against an improperly specified non-free message
> register -- especially if the interface is exposed to a less-trusted realm
> such as userspace, or if a hypervisor is reading the device tree to
> determine what to allow guests to do. In this case, just like
> mpic-msgr-receive-mask, it would list both free and non-free message
> registers that the partition can send to, and mpic-msgr-free-mask would be
> a subset of both the send and receive masks.
free-mask seems reasonable. Although, all of these masks are starting to get
rather complicated :-)
Anyway, I am going to cut a v2 patch without the dynamic allocation. All
of this is getting complicated without a public use case. I agree with your
previous suggestion that the dynamic allocation can be added as a part of the
patch set that actually uses it.
Thanks Scott.
--
Meador Inge | meador_inge AT mentor.com
Mentor Embedded | http://www.mentor.com/embedded-software
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