Re: [PATCH 3/4] Device tree bindings for Xilinx devices
On Mon, 22 Oct 2007 22:27:41 -0600
Grant Likely <[EMAIL PROTECTED]> wrote:
> From: Grant Likely <[EMAIL PROTECTED]>
>
> Signed-off-by: Grant Likely <[EMAIL PROTECTED]>
> Acked-by: Stephen Neuendorffer <[EMAIL PROTECTED]>
This looks pretty good to me.
Acked-by: Josh Boyer <[EMAIL PROTECTED]>
josh
> ---
>
> Documentation/powerpc/booting-without-of.txt | 261
> ++
> 1 files changed, 261 insertions(+), 0 deletions(-)
>
> diff --git a/Documentation/powerpc/booting-without-of.txt
> b/Documentation/powerpc/booting-without-of.txt
> index a96e853..59df69d 100644
> --- a/Documentation/powerpc/booting-without-of.txt
> +++ b/Documentation/powerpc/booting-without-of.txt
> @@ -52,6 +52,7 @@ Table of Contents
>i) Freescale QUICC Engine module (QE)
>j) CFI or JEDEC memory-mapped NOR flash
>k) Global Utilities Block
> + l) Xilinx IP cores
>
>VII - Specifying interrupt information for devices
> 1) interrupts property
> @@ -2242,6 +2243,266 @@ platforms are moved over to use the
> flattened-device-tree model.
> available.
> For Axon: 0x012a
>
> + l) Xilinx IP cores
> +
> + The Xilinx EDK toolchain ships with a set of IP cores (devices) for use
> + in Xilinx Spartan and Virtex FPGAs. The devices cover the whole range
> + of standard device types (network, serial, etc.) and miscellanious
> + devices (gpio, LCD, spi, etc). Also, since these devices are
> + implemented within the fpga fabric every instance of the device can be
> + synthesised with different options that change the behaviour.
> +
> + Each IP-core has a set of parameters which the FPGA designer can use to
> + control how the core is synthesized. Historically, the EDK tool would
> + extract the device parameters relevant to device drivers and copy them
> + into an 'xparameters.h' in the form of #define symbols. This tells the
> + device drivers how the IP cores are configured, but it requres the kernel
> + to be recompiled every time the FPGA bitstream is resynthesized.
> +
> + The new approach is to export the parameters into the device tree and
> + generate a new device tree each time the FPGA bitstream changes. The
> + parameters which used to be exported as #defines will now become
> + properties of the device node. In general, device nodes for IP-cores
> + will take the following form:
> +
> + (name)@(base-address) {
> + compatible = "xlnx,(ip-core-name)-(HW_VER)"
> + [, (list of compatible devices), ...];
> + reg = <(baseaddr) (size)>;
> + interrupt-parent = <&interrupt-controller-phandle>;
> + interrupts = < ... >;
> + xlnx,(parameter1) = "(string-value)";
> + xlnx,(parameter2) = <(int-value)>;
> + };
> +
> + (ip-core-name): the name of the ip block (given after the BEGIN
> + directive in system.mhs). Should be in lowercase
> + and all underscores '_' converted to dashes '-'.
> + (name): is derived from the "PARAMETER INSTANCE" value.
> + (parameter#): C_* parameters from system.mhs. The C_ prefix is
> + dropped from the parameter name, the name is converted
> + to lowercase and all underscore '_' characters are
> + converted to dashes '-'.
> + (baseaddr): the C_BASEADDR parameter.
> + (HW_VER): from the HW_VER parameter.
> + (size): equals C_HIGHADDR - C_BASEADDR + 1
> +
> + Typically, the compatible list will include the exact IP core version
> + followed by an older IP core version which implements the same
> + interface or any other device with the same interface.
> +
> + 'reg', 'interrupt-parent' and 'interrupts' are all optional properties.
> +
> + For example, the following block from system.mhs:
> +
> + BEGIN opb_uartlite
> + PARAMETER INSTANCE = opb_uartlite_0
> + PARAMETER HW_VER = 1.00.b
> + PARAMETER C_BAUDRATE = 115200
> + PARAMETER C_DATA_BITS = 8
> + PARAMETER C_ODD_PARITY = 0
> + PARAMETER C_USE_PARITY = 0
> + PARAMETER C_CLK_FREQ = 5000
> + PARAMETER C_BASEADDR = 0xEC10
> + PARAMETER C_HIGHADDR = 0xEC10
> + BUS_INTERFACE SOPB = opb_7
> + PORT OPB_Clk = CLK_50MHz
> + PORT Interrupt = opb_uartlite_0_Interrupt
> + PORT RX = opb_uartlite_0_RX
> + PORT TX = opb_uartlite_0_TX
> + PORT OPB_Rst = sys_bus_reset_0
> + END
> +
> + becomes the following device tree node:
> +
> + [EMAIL PROTECTED] {
> + device_type = "serial";
> + compatible = "xlnx,opb-uartlite-1.00.b";
> + reg = ;
> + interrupt-parent = <&opb-intc>;
> + interrupts = <1 0>; // got this from t
[PATCH 3/4] Device tree bindings for Xilinx devices
From: Grant Likely <[EMAIL PROTECTED]>
Signed-off-by: Grant Likely <[EMAIL PROTECTED]>
Acked-by: Stephen Neuendorffer <[EMAIL PROTECTED]>
---
Documentation/powerpc/booting-without-of.txt | 261 ++
1 files changed, 261 insertions(+), 0 deletions(-)
diff --git a/Documentation/powerpc/booting-without-of.txt
b/Documentation/powerpc/booting-without-of.txt
index a96e853..59df69d 100644
--- a/Documentation/powerpc/booting-without-of.txt
+++ b/Documentation/powerpc/booting-without-of.txt
@@ -52,6 +52,7 @@ Table of Contents
i) Freescale QUICC Engine module (QE)
j) CFI or JEDEC memory-mapped NOR flash
k) Global Utilities Block
+ l) Xilinx IP cores
VII - Specifying interrupt information for devices
1) interrupts property
@@ -2242,6 +2243,266 @@ platforms are moved over to use the
flattened-device-tree model.
available.
For Axon: 0x012a
+ l) Xilinx IP cores
+
+ The Xilinx EDK toolchain ships with a set of IP cores (devices) for use
+ in Xilinx Spartan and Virtex FPGAs. The devices cover the whole range
+ of standard device types (network, serial, etc.) and miscellanious
+ devices (gpio, LCD, spi, etc). Also, since these devices are
+ implemented within the fpga fabric every instance of the device can be
+ synthesised with different options that change the behaviour.
+
+ Each IP-core has a set of parameters which the FPGA designer can use to
+ control how the core is synthesized. Historically, the EDK tool would
+ extract the device parameters relevant to device drivers and copy them
+ into an 'xparameters.h' in the form of #define symbols. This tells the
+ device drivers how the IP cores are configured, but it requres the kernel
+ to be recompiled every time the FPGA bitstream is resynthesized.
+
+ The new approach is to export the parameters into the device tree and
+ generate a new device tree each time the FPGA bitstream changes. The
+ parameters which used to be exported as #defines will now become
+ properties of the device node. In general, device nodes for IP-cores
+ will take the following form:
+
+ (name)@(base-address) {
+ compatible = "xlnx,(ip-core-name)-(HW_VER)"
+[, (list of compatible devices), ...];
+ reg = <(baseaddr) (size)>;
+ interrupt-parent = <&interrupt-controller-phandle>;
+ interrupts = < ... >;
+ xlnx,(parameter1) = "(string-value)";
+ xlnx,(parameter2) = <(int-value)>;
+ };
+
+ (ip-core-name): the name of the ip block (given after the BEGIN
+ directive in system.mhs). Should be in lowercase
+ and all underscores '_' converted to dashes '-'.
+ (name): is derived from the "PARAMETER INSTANCE" value.
+ (parameter#): C_* parameters from system.mhs. The C_ prefix is
+ dropped from the parameter name, the name is converted
+ to lowercase and all underscore '_' characters are
+ converted to dashes '-'.
+ (baseaddr): the C_BASEADDR parameter.
+ (HW_VER): from the HW_VER parameter.
+ (size): equals C_HIGHADDR - C_BASEADDR + 1
+
+ Typically, the compatible list will include the exact IP core version
+ followed by an older IP core version which implements the same
+ interface or any other device with the same interface.
+
+ 'reg', 'interrupt-parent' and 'interrupts' are all optional properties.
+
+ For example, the following block from system.mhs:
+
+ BEGIN opb_uartlite
+ PARAMETER INSTANCE = opb_uartlite_0
+ PARAMETER HW_VER = 1.00.b
+ PARAMETER C_BAUDRATE = 115200
+ PARAMETER C_DATA_BITS = 8
+ PARAMETER C_ODD_PARITY = 0
+ PARAMETER C_USE_PARITY = 0
+ PARAMETER C_CLK_FREQ = 5000
+ PARAMETER C_BASEADDR = 0xEC10
+ PARAMETER C_HIGHADDR = 0xEC10
+ BUS_INTERFACE SOPB = opb_7
+ PORT OPB_Clk = CLK_50MHz
+ PORT Interrupt = opb_uartlite_0_Interrupt
+ PORT RX = opb_uartlite_0_RX
+ PORT TX = opb_uartlite_0_TX
+ PORT OPB_Rst = sys_bus_reset_0
+ END
+
+ becomes the following device tree node:
+
+ [EMAIL PROTECTED] {
+ device_type = "serial";
+ compatible = "xlnx,opb-uartlite-1.00.b";
+ reg = ;
+ interrupt-parent = <&opb-intc>;
+ interrupts = <1 0>; // got this from the opb_intc parameters
+ current-speed = ; // standard serial device prop
+ clock-frequency = ; // standard serial device prop
+ xlnx,data-bits = <8>;
+ xlnx,odd-parity = <0>;
+ xlnx,use-parity = <0>;
+
