Re: [PATCH V4 1/2] powerpc/perf: Add support for outputting extended regs in perf intr_regs
"Linuxppc-dev" wrote on 27/05/2020 03:20:17
PM:
> From: "Athira Rajeev"
> To: linuxppc-dev@lists.ozlabs.org
> Cc: ravi.bango...@linux.ibm.com, atraj...@linux.vnet.ibm.com,
> ma...@linux.vnet.ibm.com, linux-ker...@vger.kernel.org,
> a...@kernel.org, a...@linux.vnet.ibm.com, jo...@kernel.org
> Date: 28/05/2020 02:46 PM
> Subject: [PATCH V4 1/2] powerpc/perf: Add support for outputting
> extended regs in perf intr_regs
> Sent by: "Linuxppc-dev" +maddy=linux.vnet.ibm@lists.ozlabs.org>
>
> From: Anju T Sudhakar
>
> Add support for perf extended register capability in powerpc.
> The capability flag PERF_PMU_CAP_EXTENDED_REGS, is used to indicate the
> PMU which support extended registers. The generic code define the mask
> of extended registers as 0 for non supported architectures.
>
> Patch adds extended regs support for power9 platform by
> exposing MMCR0, MMCR1 and MMCR2 registers.
>
> REG_RESERVED mask needs update to include extended regs.
> `PERF_REG_EXTENDED_MASK`, contains mask value of the supported registers,
> is defined at runtime in the kernel based on platform since the supported
> registers may differ from one processor version to another and hence the
> MASK value.
>
> with patch
> --
>
> available registers: r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11
> r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26
> r27 r28 r29 r30 r31 nip msr orig_r3 ctr link xer ccr softe
> trap dar dsisr sier mmcra mmcr0 mmcr1 mmcr2
>
> PERF_RECORD_SAMPLE(IP, 0x1): 4784/4784: 0 period: 1 addr: 0
> ... intr regs: mask 0x ABI 64-bit
> r00xc012b77c
> r10xc03fe5e03930
> r20xc1b0e000
> r30xc03fdcddf800
> r40xc03fc788
> r50x9c422724be
> r60xc03fe5e03908
> r70xff63bddc8706
> r80x9e4
> r90x0
> r10 0x1
> r11 0x0
> r12 0xc01299c0
> r13 0xc03c4800
> r14 0x0
> r15 0x7fffdd8b8b00
> r16 0x0
> r17 0x7fffdd8be6b8
> r18 0x7e7076607730
> r19 0x2f
> r20 0xc0001fc26c68
> r21 0xc0002041e4227e00
> r22 0xc0002018fb60
> r23 0x1
> r24 0xc03ffec4d900
> r25 0x8000
> r26 0x0
> r27 0x1
> r28 0x1
> r29 0xc1be1260
> r30 0x6008010
> r31 0xc03ffebb7218
> nip 0xc012b910
> msr 0x90009033
> orig_r3 0xc012b86c
> ctr 0xc01299c0
> link 0xc012b77c
> xer 0x0
> ccr 0x2800
> softe 0x1
> trap 0xf00
> dar 0x0
> dsisr 0x800
> sier 0x0
> mmcra 0x800
> mmcr0 0x82008090
> mmcr1 0x1e00
> mmcr2 0x0
> ... thread: perf:4784
>
> Signed-off-by: Anju T Sudhakar
> [Defined PERF_REG_EXTENDED_MASK at run time to add support for
> different platforms ]
> Signed-off-by: Athira Rajeev
> Reviewed-by: Madhavan Srinivasan
Tested with 5.7.0-rc2
Tested-by: Nageswara R Sastry
> ---
> arch/powerpc/include/asm/perf_event_server.h | 8 +++
> arch/powerpc/include/uapi/asm/perf_regs.h| 14 +++-
> arch/powerpc/perf/core-book3s.c | 1 +
> arch/powerpc/perf/perf_regs.c| 34 +
> ---
> arch/powerpc/perf/power9-pmu.c | 6 +
> 5 files changed, 59 insertions(+), 4 deletions(-)
>
> diff --git a/arch/powerpc/include/asm/perf_event_server.h b/arch/
> powerpc/include/asm/perf_event_server.h
> index 3e9703f..1458e1a 100644
> --- a/arch/powerpc/include/asm/perf_event_server.h
> +++ b/arch/powerpc/include/asm/perf_event_server.h
> @@ -15,6 +15,9 @@
> #define MAX_EVENT_ALTERNATIVES 8
> #define MAX_LIMITED_HWCOUNTERS 2
>
> +extern u64 mask_var;
> +#define PERF_REG_EXTENDED_MASK mask_var
> +
> struct perf_event;
>
> /*
> @@ -55,6 +58,11 @@ struct power_pmu {
> int *blacklist_ev;
> /* BHRB entries in the PMU */
> int bhrb_nr;
> + /*
> +* set this flag with `PERF_PMU_CAP_EXTENDED_REGS` if
> +* the pmu supports extended perf regs capability
> +*/
> + int capabilities;
> };
>
> /*
> diff --git a/arch/powerpc/include/uapi/asm/perf_regs.h b/arch/
> powerpc/include/uapi/asm/perf_regs.h
> index f599064..485b1d5 100644
> --- a/arch/powerpc/include/uapi/asm/perf_regs.h
> +++ b/arch/powerpc/include/uapi/asm/perf_regs.h
> @@ -48,6 +48,18 @@ enum perf_event_powerpc_regs {
> PERF_REG_POWERPC_DSISR,
> PERF_
[PATCH V4 1/2] powerpc/perf: Add support for outputting extended regs in perf intr_regs
From: Anju T Sudhakar
Add support for perf extended register capability in powerpc.
The capability flag PERF_PMU_CAP_EXTENDED_REGS, is used to indicate the
PMU which support extended registers. The generic code define the mask
of extended registers as 0 for non supported architectures.
Patch adds extended regs support for power9 platform by
exposing MMCR0, MMCR1 and MMCR2 registers.
REG_RESERVED mask needs update to include extended regs.
`PERF_REG_EXTENDED_MASK`, contains mask value of the supported registers,
is defined at runtime in the kernel based on platform since the supported
registers may differ from one processor version to another and hence the
MASK value.
with patch
--
available registers: r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11
r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26
r27 r28 r29 r30 r31 nip msr orig_r3 ctr link xer ccr softe
trap dar dsisr sier mmcra mmcr0 mmcr1 mmcr2
PERF_RECORD_SAMPLE(IP, 0x1): 4784/4784: 0 period: 1 addr: 0
... intr regs: mask 0x ABI 64-bit
r00xc012b77c
r10xc03fe5e03930
r20xc1b0e000
r30xc03fdcddf800
r40xc03fc788
r50x9c422724be
r60xc03fe5e03908
r70xff63bddc8706
r80x9e4
r90x0
r10 0x1
r11 0x0
r12 0xc01299c0
r13 0xc03c4800
r14 0x0
r15 0x7fffdd8b8b00
r16 0x0
r17 0x7fffdd8be6b8
r18 0x7e7076607730
r19 0x2f
r20 0xc0001fc26c68
r21 0xc0002041e4227e00
r22 0xc0002018fb60
r23 0x1
r24 0xc03ffec4d900
r25 0x8000
r26 0x0
r27 0x1
r28 0x1
r29 0xc1be1260
r30 0x6008010
r31 0xc03ffebb7218
nip 0xc012b910
msr 0x90009033
orig_r3 0xc012b86c
ctr 0xc01299c0
link 0xc012b77c
xer 0x0
ccr 0x2800
softe 0x1
trap 0xf00
dar 0x0
dsisr 0x800
sier 0x0
mmcra 0x800
mmcr0 0x82008090
mmcr1 0x1e00
mmcr2 0x0
... thread: perf:4784
Signed-off-by: Anju T Sudhakar
[Defined PERF_REG_EXTENDED_MASK at run time to add support for different
platforms ]
Signed-off-by: Athira Rajeev
Reviewed-by: Madhavan Srinivasan
---
arch/powerpc/include/asm/perf_event_server.h | 8 +++
arch/powerpc/include/uapi/asm/perf_regs.h| 14 +++-
arch/powerpc/perf/core-book3s.c | 1 +
arch/powerpc/perf/perf_regs.c| 34 +---
arch/powerpc/perf/power9-pmu.c | 6 +
5 files changed, 59 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/include/asm/perf_event_server.h
b/arch/powerpc/include/asm/perf_event_server.h
index 3e9703f..1458e1a 100644
--- a/arch/powerpc/include/asm/perf_event_server.h
+++ b/arch/powerpc/include/asm/perf_event_server.h
@@ -15,6 +15,9 @@
#define MAX_EVENT_ALTERNATIVES 8
#define MAX_LIMITED_HWCOUNTERS 2
+extern u64 mask_var;
+#define PERF_REG_EXTENDED_MASK mask_var
+
struct perf_event;
/*
@@ -55,6 +58,11 @@ struct power_pmu {
int *blacklist_ev;
/* BHRB entries in the PMU */
int bhrb_nr;
+ /*
+* set this flag with `PERF_PMU_CAP_EXTENDED_REGS` if
+* the pmu supports extended perf regs capability
+*/
+ int capabilities;
};
/*
diff --git a/arch/powerpc/include/uapi/asm/perf_regs.h
b/arch/powerpc/include/uapi/asm/perf_regs.h
index f599064..485b1d5 100644
--- a/arch/powerpc/include/uapi/asm/perf_regs.h
+++ b/arch/powerpc/include/uapi/asm/perf_regs.h
@@ -48,6 +48,18 @@ enum perf_event_powerpc_regs {
PERF_REG_POWERPC_DSISR,
PERF_REG_POWERPC_SIER,
PERF_REG_POWERPC_MMCRA,
- PERF_REG_POWERPC_MAX,
+ /* Extended registers */
+ PERF_REG_POWERPC_MMCR0,
+ PERF_REG_POWERPC_MMCR1,
+ PERF_REG_POWERPC_MMCR2,
+ /* Max regs without the extended regs */
+ PERF_REG_POWERPC_MAX = PERF_REG_POWERPC_MMCRA + 1,
};
+
+#define PERF_REG_PMU_MASK ((1ULL << PERF_REG_POWERPC_MAX) - 1)
+
+/* PERF_REG_EXTENDED_MASK value for CPU_FTR_ARCH_300 */
+#define PERF_REG_PMU_MASK_300 (((1ULL << (PERF_REG_POWERPC_MMCR2 + 1)) - 1) \
+ - PERF_REG_PMU_MASK)
+
#endif /* _UAPI_ASM_POWERPC_PERF_REGS_H */
diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c
index 3dcfecf..7f63edf 100644
--- a/arch/powerpc/perf/core-book3s.c
+++ b/arch/powerpc/perf/core-book3s.c
@@ -2275,6 +2275,7 @@ int register_power_pmu(struct power_pmu *pmu)
pmu->name);
power_pmu.attr_groups = ppmu->attr_groups;
+ power_pmu.capabilities |= (ppmu->capabilities &
PERF_PMU_CAP_EXTENDED_REGS);
#ifdef MSR_HV
/*
diff --git a/arch/powerpc/perf/perf_regs.c b/arch/powerpc/perf/perf_regs.c
index a213a0a..c8a7e8c
