Signed-off-by: Heiko Schocher h...@denx.de
cc: Wolfram Sang w.s...@pengutronix.de
---
- based against 2.6.37-rc4
./scripts/checkpatch.pl 0001-powerpc-5200-add-support-for-charon-board.patch
total: 0 errors, 0 warnings, 233 lines checked
0001-powerpc-5200-add-support-for-charon-board.patch has no obvious style
problems and is ready for submission.
- changes since v1:
add comments from Wolfram Sang
- no defconfig file
- comment corrected in DTS
- boardlist sorted alphabetically
- commit log without boardinfo
arch/powerpc/boot/dts/charon.dts | 226 ++
arch/powerpc/platforms/52xx/mpc5200_simple.c |1 +
2 files changed, 227 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/boot/dts/charon.dts
diff --git a/arch/powerpc/boot/dts/charon.dts b/arch/powerpc/boot/dts/charon.dts
new file mode 100644
index 000..9776889
--- /dev/null
+++ b/arch/powerpc/boot/dts/charon.dts
@@ -0,0 +1,226 @@
+/*
+ * charon board Device Tree Source
+ *
+ * Copyright (C) 2007 Semihalf
+ * Marian Balakowicz m...@semihalf.com
+ *
+ * Copyright (C) 2010 DENX Software Engineering GmbH
+ * Heiko Schocher h...@denx.de
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+
+/ {
+ model = anon,charon;
+ compatible = anon,charon;
+ #address-cells = 1;
+ #size-cells = 1;
+ interrupt-parent = mpc5200_pic;
+
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ PowerPC,5...@0 {
+ device_type = cpu;
+ reg = 0;
+ d-cache-line-size = 32;
+ i-cache-line-size = 32;
+ d-cache-size = 0x4000;// L1, 16K
+ i-cache-size = 0x4000;// L1, 16K
+ timebase-frequency = 0; // from bootloader
+ bus-frequency = 0;// from bootloader
+ clock-frequency = 0; // from bootloader
+ };
+ };
+
+ memory {
+ device_type = memory;
+ reg = 0x 0x0800; // 128MB
+ };
+
+ soc5...@f000 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = fsl,mpc5200-immr;
+ ranges = 0 0xf000 0xc000;
+ reg = 0xf000 0x0100;
+ bus-frequency = 0;// from bootloader
+ system-frequency = 0; // from bootloader
+
+ c...@200 {
+ compatible = fsl,mpc5200-cdm;
+ reg = 0x200 0x38;
+ };
+
+ mpc5200_pic: interrupt-control...@500 {
+ // 5200 interrupts are encoded into two levels;
+ interrupt-controller;
+ #interrupt-cells = 3;
+ compatible = fsl,mpc5200-pic;
+ reg = 0x500 0x80;
+ };
+
+ ti...@600 { // General Purpose Timer
+ compatible = fsl,mpc5200-gpt;
+ reg = 0x600 0x10;
+ interrupts = 1 9 0;
+ fsl,has-wdt;
+ };
+
+ c...@900 {
+ compatible = fsl,mpc5200-mscan;
+ interrupts = 2 17 0;
+ reg = 0x900 0x80;
+ };
+
+ c...@980 {
+ compatible = fsl,mpc5200-mscan;
+ interrupts = 2 18 0;
+ reg = 0x980 0x80;
+ };
+
+ gpio_simple: g...@b00 {
+ compatible = fsl,mpc5200-gpio;
+ reg = 0xb00 0x40;
+ interrupts = 1 7 0;
+ gpio-controller;
+ #gpio-cells = 2;
+ };
+
+ u...@1000 {
+ compatible = fsl,mpc5200-ohci,ohci-be;
+ reg = 0x1000 0xff;
+ interrupts = 2 6 0;
+ };
+
+ dma-control...@1200 {
+ device_type = dma-controller;
+ compatible = fsl,mpc5200-bestcomm;
+ reg = 0x1200 0x80;
+ interrupts = 3 0 0 3 1 0 3 2 0 3 3 0
+ 3 4 0 3 5 0 3 6 0 3 7 0
+ 3 8 0 3 9 0 3 10 0 3 11 0
+ 3 12 0 3 13 0 3 14 0 3 15 0;
+ };
+
+ x...@1f00 {
+ compatible = fsl,mpc5200-xlb;
+ reg = 0x1f00 0x100;
+
