Update GE Fanuc DTS to match the alterations suggested during the merge of
the ppc9a DTS in commit 740d36ae6344f38c4da64c2ede765d7d2dd1f132
Signed-off-by: Martyn Welch martyn.we...@gefanuc.com
---
v2: Fixed run on message.
Kumar: I think the problem may be that this patch depends on a previous patch:
http://patchwork.ozlabs.org/patch/29335/
Martyn
arch/powerpc/boot/dts/gef_sbc310.dts | 29 +
1 files changed, 13 insertions(+), 16 deletions(-)
diff --git a/arch/powerpc/boot/dts/gef_sbc310.dts
b/arch/powerpc/boot/dts/gef_sbc310.dts
index 7810ea9..2107d3c 100644
--- a/arch/powerpc/boot/dts/gef_sbc310.dts
+++ b/arch/powerpc/boot/dts/gef_sbc310.dts
@@ -83,34 +83,34 @@
/* fl...@0,0 is a mirror of part of the memory in fl...@1,0
fl...@0,0 {
- compatible = cfi-flash;
- reg = 0 0 0x0100;
+ compatible = gef,sbc310-firmware-mirror, cfi-flash;
+ reg = 0x0 0x0 0x0100;
bank-width = 2;
device-width = 2;
#address-cells = 1;
#size-cells = 1;
partit...@0 {
label = firmware;
- reg = 0x 0x0100;
+ reg = 0x0 0x0100;
read-only;
};
};
*/
fl...@1,0 {
- compatible = cfi-flash;
- reg = 1 0 0x800;
+ compatible = gef,sbc310-paged-flash, cfi-flash;
+ reg = 0x1 0x0 0x800;
bank-width = 2;
device-width = 2;
#address-cells = 1;
#size-cells = 1;
partit...@0 {
label = user;
- reg = 0x 0x0780;
+ reg = 0x0 0x780;
};
partit...@780 {
label = firmware;
- reg = 0x0780 0x0080;
+ reg = 0x780 0x80;
read-only;
};
};
@@ -121,18 +121,16 @@
};
w...@4,2000 {
- #interrupt-cells = 2;
- device_type = watchdog;
- compatible = gef,fpga-wdt;
+ compatible = gef,sbc310-fpga-wdt, gef,fpga-wdt-1.00,
+ gef,fpga-wdt;
reg = 0x4 0x2000 0x8;
interrupts = 0x1a 0x4;
interrupt-parent = gef_pic;
};
/*
w...@4,2010 {
- #interrupt-cells = 2;
- device_type = watchdog;
- compatible = gef,fpga-wdt;
+ compatible = gef,sbc310-fpga-wdt, gef,fpga-wdt-1.00,
+ gef,fpga-wdt;
reg = 0x4 0x2010 0x8;
interrupts = 0x1b 0x4;
interrupt-parent = gef_pic;
@@ -141,7 +139,7 @@
gef_pic: p...@4,4000 {
#interrupt-cells = 1;
interrupt-controller;
- compatible = gef,fpga-pic;
+ compatible = gef,sbc310-fpga-pic, gef,fpga-pic;
reg = 0x4 0x4000 0x20;
interrupts = 0x8
0x9;
@@ -161,7 +159,7 @@
#size-cells = 1;
#interrupt-cells = 2;
device_type = soc;
- compatible = simple-bus;
+ compatible = fsl,mpc8641-soc, simple-bus;
ranges = 0x0 0xfef0 0x0010;
bus-frequency = ;
@@ -412,5 +410,4 @@
0x0 0x0040;
};
};
-
};
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