Re: [PATCH v2 1/2] powerpc: Board support for GE Fanuc SBC610
On Fri, 22 Aug 2008 12:11:35 -0500 Scott Wood [EMAIL PROTECTED] wrote: On Fri, Aug 22, 2008 at 12:26:01PM +0100, Martyn Welch wrote: drop device_type. Ah - _all_ device_type! Um, not all - just the ones where the name of the block matches the device type(?) All except cpu and memory. -Scott And, it would appear, soc as well. Martyn -- Martyn Welch MEng MPhil MIET (Principal Software Engineer) T:+44(0)1327322748 GE Fanuc Intelligent Platforms Ltd,|Registered in England and Wales Tove Valley Business Park, Towcester, |(3828642) at 100 Barbirolli Square, Northants, NN12 6PF, UK T:+44(0)1327359444 |Manchester,M2 3AB VAT:GB 729849476 ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH v2 1/2] powerpc: Board support for GE Fanuc SBC610
On Aug 22, 2008, at 12:11 PM, Scott Wood wrote: On Fri, Aug 22, 2008 at 12:26:01PM +0100, Martyn Welch wrote: drop device_type. Ah - _all_ device_type! Um, not all - just the ones where the name of the block matches the device type(?) All except cpu and memory. I think network is ok. - k ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH v2 1/2] powerpc: Board support for GE Fanuc SBC610
On Aug 22, 2008, at 6:11 AM, Martyn Welch wrote:
+static void __init
+gef_sbc610_init_irq(void)
+{
+ struct mpic *mpic1;
+ struct device_node *np;
+ struct resource res;
+
+ /* Determine PIC address. */
+ np = of_find_node_by_type(NULL, open-pic);
+ if (np == NULL)
+ return;
+ of_address_to_resource(np, 0, res);
+
+ mpic1 = mpic_alloc(np, res.start,
+ MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
+ 0, 256, mpic);
+ of_node_put(np);
+ BUG_ON(mpic1 == NULL);
+
+ mpic_init(mpic1);
+}
any reason not to use mpc86xx_init_irq() in pic.c?
Yes, the afore-mentioned chained interrupt controller that is rather
specific to our boards that I will/have added to this function in a
patch that I shall post soon.
Hmm, does that chained interrupt-controller really effect this bit of
code any? I'd expect you'd be able to still call mpc86xx_init_irq()
and than in your board file hook up the cascade (like how we hookup
the i8259 in pic.c).
If not here are a few comments:
* Use *mpic instead mpic1
* Add MPIC_BROKEN_FRR_NIRQS to the flags
- k
___
Linuxppc-dev mailing list
Linuxppc-dev@ozlabs.org
https://ozlabs.org/mailman/listinfo/linuxppc-dev
[PATCH v2 1/2] powerpc: Board support for GE Fanuc SBC610
Support for the SBC610 VPX Single Board Computer from GE Fanuc (PowerPC
MPC8641D).
This is the basic board support for GE Fanuc's SBC610, a 6U single board
computer, based on Freescale's MPC8641D.
Signed-off-by: Martyn Welch [EMAIL PROTECTED]
---
arch/powerpc/boot/dts/gef_sbc610.dts | 268 ++
arch/powerpc/platforms/86xx/Kconfig |9 +
arch/powerpc/platforms/86xx/Makefile |1
arch/powerpc/platforms/86xx/gef_sbc610.c | 177
4 files changed, 454 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/boot/dts/gef_sbc610.dts
b/arch/powerpc/boot/dts/gef_sbc610.dts
new file mode 100644
index 000..598deda
--- /dev/null
+++ b/arch/powerpc/boot/dts/gef_sbc610.dts
@@ -0,0 +1,268 @@
+/*
+ * GE Fanuc SBC610 Device Tree Source
+ *
+ * Copyright 2008 GE Fanuc Intelligent Platforms Embedded Systems, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * Based on: SBS CM6 Device Tree Source
+ * Copyright 2007 SBS Technologies GmbH Co. KG
+ * And: mpc8641_hpcn.dts (MPC8641 HPCN Device Tree Source)
+ * Copyright 2006 Freescale Semiconductor Inc.
+ */
+
+/*
+ * Compiled with dtc -I dts -O dtb -o gef_sbc610.dtb gef_sbc610.dts
+ */
+
+/dts-v1/;
+
+/ {
+ model = GEF_SBC610;
+ compatible = gef,sbc610;
+ #address-cells = 1;
+ #size-cells = 1;
+
+ aliases {
+ ethernet0 = enet0;
+ ethernet1 = enet1;
+ serial0 = serial0;
+ serial1 = serial1;
+ pci0 = pci0;
+ };
+
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ PowerPC,[EMAIL PROTECTED] {
+ device_type = cpu;
+ reg = 0x;
+ d-cache-line-size = 32; // 32 bytes
+ i-cache-line-size = 32; // 32 bytes
+ d-cache-size = 32768; // L1, 32K
+ i-cache-size = 32768; // L1, 32K
+ timebase-frequency = 0; // From uboot
+ bus-frequency = 0;// From uboot
+ clock-frequency = 0; // From uboot
+ l2cr = 0x8000;// Enable L2
+ };
+ PowerPC,[EMAIL PROTECTED] {
+ device_type = cpu;
+ reg = 0x0001;
+ d-cache-line-size = 32; // 32 bytes
+ i-cache-line-size = 32; // 32 bytes
+ d-cache-size = 32768; // L1, 32K
+ i-cache-size = 32768; // L1, 32K
+ timebase-frequency = 0; // From uboot
+ bus-frequency = 0;// From uboot
+ clock-frequency = 0; // From uboot
+ l2cr = 0x8000;// Enable L2
+ };
+ };
+
+ memory {
+ device_type = memory;
+ reg = 0x 0x4000; // set by u-boot
+ };
+
+ [EMAIL PROTECTED] {
+ #address-cells = 1;
+ #size-cells = 1;
+ #interrupt-cells = 2;
+ device_type = soc;
+ ranges = 0x 0xfef0 0x0010;
+ reg = 0xfef0 0x0010; // CCSRBAR 1M
+ bus-frequency = 0;
+
+ i2c1: [EMAIL PROTECTED] {
+ #address-cells = 1;
+ #size-cells = 0;
+ device_type = i2c;
+ compatible = fsl-i2c;
+ reg = 0x3000 0x0100;
+ interrupts = 0x2b 0x2;
+ interrupt-parent = mpic;
+ dfsrr;
+
+ [EMAIL PROTECTED] {
+ compatible = dallas,ds1682;
+ reg = 0x006b;
+ };
+ };
+
+ i2c2: [EMAIL PROTECTED] {
+ device_type = i2c;
+ compatible = fsl-i2c;
+ reg = 0x3100 0x0100;
+ interrupts = 0x2b 0x2;
+ interrupt-parent = mpic;
+ dfsrr;
+ };
+
+ [EMAIL PROTECTED] {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = fsl,mpc8641-dma, fsl,eloplus-dma;
+ reg = 0x21300 0x4;
+ ranges = 0x0 0x21100 0x200;
+ cell-index = 0;
+ [EMAIL PROTECTED] {
+
Re: [PATCH v2 1/2] powerpc: Board support for GE Fanuc SBC610
+ PowerPC,[EMAIL PROTECTED] {
+ device_type = cpu;
+ reg = 0x;
+ d-cache-line-size = 32; // 32 bytes
+ i-cache-line-size = 32; // 32 bytes
+ d-cache-size = 32768; // L1, 32K
+ i-cache-size = 32768; // L1, 32K
+ timebase-frequency = 0; // From uboot
+ bus-frequency = 0; // From uboot
+ clock-frequency = 0;// From uboot
+ l2cr = 0x8000; // Enable L2
do you expect the 'l2cr' prop to do anything? Not sure if this is
something apple invented or you did?
+ i2c1: [EMAIL PROTECTED] {
+ #address-cells = 1;
+ #size-cells = 0;
+ device_type = i2c;
drop device_type.
+ compatible = fsl-i2c;
+ reg = 0x3000 0x0100;
+ interrupts = 0x2b 0x2;
+ interrupt-parent = mpic;
+ dfsrr;
+
+ [EMAIL PROTECTED] {
+ compatible = dallas,ds1682;
+ reg = 0x006b;
+ };
+ };
+
+ i2c2: [EMAIL PROTECTED] {
I recommend having #addr/#size cells here.
+ device_type = i2c;
ditto
+ compatible = fsl-i2c;
+ reg = 0x3100 0x0100;
+ interrupts = 0x2b 0x2;
+ interrupt-parent = mpic;
+ dfsrr;
+ };
+
+ [EMAIL PROTECTED] {
+ #address-cells = 1;
+ #size-cells = 0;
+ device_type = mdio;
drop device_type, (see a theme here ;)
+ compatible = fsl,gianfar-mdio;
+ reg = 0x00024520 0x0020;
+
+ phy0: [EMAIL PROTECTED] {
+ interrupt-parent = mpic;
+ interrupts = 0x0 0x1;
+ reg = 0x0001;
+ device_type = ethernet-phy;
drop device_type.
+ };
+ phy2: [EMAIL PROTECTED] {
+ interrupt-parent = mpic;
+ interrupts = 0x0 0x1;
+ reg = 0x0003;
+ device_type = ethernet-phy;
ditto
+ };
+ };
+
+ enet0: [EMAIL PROTECTED] {
+ #address-cells = 1;
+ #size-cells = 0;
there is no need for #add/size cells here.
+ device_type = network;
+ model = eTSEC;
+ compatible = gianfar;
+ reg = 0x00024000 0x1000;
+ mac-address = [ 00 00 00 00 00 00 ]; // set by u-boot
+ interrupts = 0x1d 0x2 0x1e 0x2 0x22 0x2;
+ interrupt-parent = mpic;
+ phy-handle = phy0;
+ phy-connection-type = gmii;
+ };
+
+ enet1: [EMAIL PROTECTED] {
+ #address-cells = 1;
+ #size-cells = 0;
there is no need for #add/size cells here.
+ device_type = network;
+ model = eTSEC;
+ compatible = gianfar;
+ reg = 0x00026000 0x1000;
+ mac-address = [ 00 00 00 00 00 00 ]; // set by u-boot
+ interrupts = 0x1f 0x2 0x20 0x2 0x21 0x2;
+ interrupt-parent = mpic;
+ phy-handle = phy2;
+ phy-connection-type = gmii;
+ };
+
You may want to add in msi interrupts for PCIe support (see
mpc8572ds.dtb)
+
+ mpic: [EMAIL PROTECTED] {
+ clock-frequency = 0;
+ interrupt-controller;
+ #address-cells = 0;
+ #interrupt-cells = 2;
+ reg = 0x0004 0x0004;
+ compatible = chrp,open-pic;
+ device_type = open-pic;
+ };
+
+ [EMAIL PROTECTED] {
+ compatible = fsl,mpc8641-guts;
+ reg = 0x000e 0x1000;
+ fsl,has-rstcr;
+ };
+ };
+
+ pci0: [EMAIL PROTECTED] {
+ compatible = fsl,mpc8641-pcie;
+ device_type = pci;
+ #interrupt-cells = 1;
+ #size-cells = 2;
+
Re: [PATCH v2 1/2] powerpc: Board support for GE Fanuc SBC610
On Fri, 22 Aug 2008 05:56:53 -0500
Kumar Gala [EMAIL PROTECTED] wrote:
+ PowerPC,[EMAIL PROTECTED] {
+ device_type = cpu;
+ reg = 0x;
+ d-cache-line-size = 32; // 32 bytes
+ i-cache-line-size = 32; // 32 bytes
+ d-cache-size = 32768; // L1, 32K
+ i-cache-size = 32768; // L1, 32K
+ timebase-frequency = 0; // From uboot
+ bus-frequency = 0;// From uboot
+ clock-frequency = 0; // From uboot
+ l2cr = 0x8000;// Enable L2
do you expect the 'l2cr' prop to do anything? Not sure if this is
something apple invented or you did?
TBH, it was in the dts file that I based this on - I thought it was in the
others as well - my mistake, I shall remove it.
+ i2c1: [EMAIL PROTECTED] {
+ #address-cells = 1;
+ #size-cells = 0;
+ device_type = i2c;
drop device_type.
Ah - _all_ device_type!
snip
+ };
+ };
+
+ enet0: [EMAIL PROTECTED] {
+ #address-cells = 1;
+ #size-cells = 0;
there is no need for #add/size cells here.
Will remove.
+ device_type = network;
+ model = eTSEC;
+ compatible = gianfar;
+ reg = 0x00024000 0x1000;
+ mac-address = [ 00 00 00 00 00 00 ]; // set by u-boot
+ interrupts = 0x1d 0x2 0x1e 0x2 0x22 0x2;
+ interrupt-parent = mpic;
+ phy-handle = phy0;
+ phy-connection-type = gmii;
+ };
+
+ enet1: [EMAIL PROTECTED] {
+ #address-cells = 1;
+ #size-cells = 0;
there is no need for #add/size cells here.
ditto.
+ device_type = network;
+ model = eTSEC;
+ compatible = gianfar;
+ reg = 0x00026000 0x1000;
+ mac-address = [ 00 00 00 00 00 00 ]; // set by u-boot
+ interrupts = 0x1f 0x2 0x20 0x2 0x21 0x2;
+ interrupt-parent = mpic;
+ phy-handle = phy2;
+ phy-connection-type = gmii;
+ };
+
You may want to add in msi interrupts for PCIe support (see
mpc8572ds.dtb)
Interrupts are routed on this board - just via a custom interrupt controller.
I have a patch to add this, but I was getting the basics right first...
+
+ mpic: [EMAIL PROTECTED] {
+ clock-frequency = 0;
+ interrupt-controller;
+ #address-cells = 0;
+ #interrupt-cells = 2;
+ reg = 0x0004 0x0004;
+ compatible = chrp,open-pic;
+ device_type = open-pic;
+ };
+
+ [EMAIL PROTECTED] {
+ compatible = fsl,mpc8641-guts;
+ reg = 0x000e 0x1000;
+ fsl,has-rstcr;
+ };
+ };
+
+ pci0: [EMAIL PROTECTED] {
+ compatible = fsl,mpc8641-pcie;
+ device_type = pci;
+ #interrupt-cells = 1;
+ #size-cells = 2;
+ #address-cells = 3;
+ reg = 0xfef08000 0x1000;
+ bus-range = 0x0 0xff;
+ ranges = 0x0200 0x0 0x8000 0x8000 0x0 0x4000
+ 0x0100 0x0 0x 0xfe00 0x0 0x0040;
+ clock-frequency = ;
+ interrupt-parent = mpic;
+ interrupts = 0x18 0x2;
+ interrupt-map-mask = 0xf800 0x0 0x0 0x7;
+ interrupt-map =
+ 0x 0x0 0x0 0x1 mpic 0x0 0x1
+ 0x 0x0 0x0 0x2 mpic 0x1 0x1
+ 0x 0x0 0x0 0x3 mpic 0x2 0x1
+ 0x 0x0 0x0 0x4 mpic 0x3 0x1
+ ;
+
+ [EMAIL PROTECTED] {
+ reg = 0 0 0 0 0;
+ #size-cells = 2;
+ #address-cells = 3;
+ device_type = pci;
+ ranges = 0x0200 0x0 0x8000
+ 0x0200 0x0 0x8000
+ 0x0 0x4000
+
+ 0x0100 0x0 0x
+ 0x0100 0x0 0x
+ 0x0 0x0040;
+ };
+ };
+};
diff --git a/arch/powerpc/platforms/86xx/Makefile b/arch/powerpc/
platforms/86xx/Makefile
index 8fee37d..cb9fc8f 100644
--- a/arch/powerpc/platforms/86xx/Makefile
+++
Re: [PATCH v2 1/2] powerpc: Board support for GE Fanuc SBC610
On Fri, 22 Aug 2008 12:11:52 +0100
Martyn Welch [EMAIL PROTECTED] wrote:
On Fri, 22 Aug 2008 05:56:53 -0500
Kumar Gala [EMAIL PROTECTED] wrote:
+ PowerPC,[EMAIL PROTECTED] {
+ device_type = cpu;
+ reg = 0x;
+ d-cache-line-size = 32; // 32 bytes
+ i-cache-line-size = 32; // 32 bytes
+ d-cache-size = 32768; // L1, 32K
+ i-cache-size = 32768; // L1, 32K
+ timebase-frequency = 0; // From uboot
+ bus-frequency = 0;// From uboot
+ clock-frequency = 0; // From uboot
+ l2cr = 0x8000;// Enable L2
do you expect the 'l2cr' prop to do anything? Not sure if this is
something apple invented or you did?
TBH, it was in the dts file that I based this on - I thought it was in the
others as well - my mistake, I shall remove it.
+ i2c1: [EMAIL PROTECTED] {
+ #address-cells = 1;
+ #size-cells = 0;
+ device_type = i2c;
drop device_type.
Ah - _all_ device_type!
Um, not all - just the ones where the name of the block matches the device
type(?)
Martyn
--
Martyn Welch MEng MPhil MIET (Principal Software Engineer) T:+44(0)1327322748
GE Fanuc Intelligent Platforms Ltd,|Registered in England and Wales
Tove Valley Business Park, Towcester, |(3828642) at 100 Barbirolli Square,
Northants, NN12 6PF, UK T:+44(0)1327359444 |Manchester,M2 3AB VAT:GB 729849476
___
Linuxppc-dev mailing list
Linuxppc-dev@ozlabs.org
https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH v2 1/2] powerpc: Board support for GE Fanuc SBC610
On Fri, Aug 22, 2008 at 06:46:20AM -0400, Martyn Welch wrote:
+ enet0: [EMAIL PROTECTED] {
+ #address-cells = 1;
+ #size-cells = 0;
+ device_type = network;
+ model = eTSEC;
+ compatible = gianfar;
+ reg = 0x00024000 0x1000;
+ mac-address = [ 00 00 00 00 00 00 ]; // set by u-boot
local-mac-address
-Scott
___
Linuxppc-dev mailing list
Linuxppc-dev@ozlabs.org
https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH v2 1/2] powerpc: Board support for GE Fanuc SBC610
On Fri, Aug 22, 2008 at 12:26:01PM +0100, Martyn Welch wrote: drop device_type. Ah - _all_ device_type! Um, not all - just the ones where the name of the block matches the device type(?) All except cpu and memory. -Scott ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
