subject:"\[PATCH v3\] dmaengine\: driver support for FSL RaidEngine device."

Re: [PATCH v3] dmaengine: driver support for FSL RaidEngine device.

2014-10-17 Thread Vinod Koul

On Fri, Oct 17, 2014 at 02:13:20AM +, Xuelin Shi wrote:
> Hi Dan & Vinod,
> 
> I have sent out the v4 of this patch and not received any further feedback 
> yet.
> 
> This patch looks ruled out from the patchwork. 
> https://patchwork.kernel.org/project/linux-dmaengine/list/?page=2
> 
> So do you know what happened to this patch?

First pls do not top post on mailing list

Yes I did clean patchworks this week for older patches, can you please
resubmit and we can review them

Thanks
-- 
~Vinod

> 
> Thanks,
> Xuelin Shi
> 
> 
> -Original Message-
> From: Shi Xuelin-B29237 
> Sent: 2014年4月15日 11:08
> To: 'Dan Williams'
> Cc: Koul, Vinod; andriy.shevche...@intel.com; dmaeng...@vger.kernel.org; 
> linuxppc-dev; Rai Harninder-B01044; Burmi Naveen-B16502
> Subject: RE: [PATCH v3] dmaengine: driver support for FSL RaidEngine device.
> 
> Yes, "depend on !ASYNC_TX_CHANNEL_SWITCH" is better since fsldma selects this 
> condition.
> 
> Thanks,
> Xuelin Shi
> 
> -Original Message-
> From: Dan Williams [mailto:dan.j.willi...@intel.com]
> Sent: 2014年4月15日 8:30
> To: Shi Xuelin-B29237
> Cc: Koul, Vinod; andriy.shevche...@intel.com; dmaeng...@vger.kernel.org; 
> linuxppc-dev; Rai Harninder-B01044; Burmi Naveen-B16502
> Subject: Re: [PATCH v3] dmaengine: driver support for FSL RaidEngine device.
> 
> On Sun, Apr 13, 2014 at 7:48 PM, Xuelin Shi  wrote:
> > Hi Dan,
> >
> > fsl dma device and fsl raid device are two differenct devices that 
> > both provide async_memcpy capability, so I use !FSL_DMA to disable the fsl 
> > dma device.
> >
> > That's to say, either select fsldma device, either fsl raid device.
> >
> 
> Right, but that's not what your proposed Kconfig dependency line does.
> 
> You want something like "depends on FSL_SOC && !(FSL_DMA || FSL_DMA=m)"
> 
> However, the more problematic option is ASYNC_TX_CHANNEL_SWITCH.  That option 
> is problematic for RAID, so I propose "depend on !ASYNC_TX_CHANNEL_SWITCH" 
> since that addresses both problems.
> 
> 

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RE: [PATCH v3] dmaengine: driver support for FSL RaidEngine device.

2014-10-16 Thread Xuelin Shi

Hi Dan & Vinod,

I have sent out the v4 of this patch and not received any further feedback yet.

This patch looks ruled out from the patchwork. 
https://patchwork.kernel.org/project/linux-dmaengine/list/?page=2

So do you know what happened to this patch?

Thanks,
Xuelin Shi

-Original Message-
From: Shi Xuelin-B29237 
Sent: 2014年4月15日 11:08
To: 'Dan Williams'
Cc: Koul, Vinod; andriy.shevche...@intel.com; dmaeng...@vger.kernel.org; 
linuxppc-dev; Rai Harninder-B01044; Burmi Naveen-B16502
Subject: RE: [PATCH v3] dmaengine: driver support for FSL RaidEngine device.

Yes, "depend on !ASYNC_TX_CHANNEL_SWITCH" is better since fsldma selects this 
condition.

Thanks,
Xuelin Shi

-Original Message-
From: Dan Williams [mailto:dan.j.willi...@intel.com]
Sent: 2014年4月15日 8:30
To: Shi Xuelin-B29237
Cc: Koul, Vinod; andriy.shevche...@intel.com; dmaeng...@vger.kernel.org; 
linuxppc-dev; Rai Harninder-B01044; Burmi Naveen-B16502
Subject: Re: [PATCH v3] dmaengine: driver support for FSL RaidEngine device.

On Sun, Apr 13, 2014 at 7:48 PM, Xuelin Shi  wrote:
> Hi Dan,
>
> fsl dma device and fsl raid device are two differenct devices that 
> both provide async_memcpy capability, so I use !FSL_DMA to disable the fsl 
> dma device.
>
> That's to say, either select fsldma device, either fsl raid device.
>

Right, but that's not what your proposed Kconfig dependency line does.

You want something like "depends on FSL_SOC && !(FSL_DMA || FSL_DMA=m)"

However, the more problematic option is ASYNC_TX_CHANNEL_SWITCH.  That option 
is problematic for RAID, so I propose "depend on !ASYNC_TX_CHANNEL_SWITCH" 
since that addresses both problems.

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RE: [PATCH v3] dmaengine: driver support for FSL RaidEngine device.

2014-04-14 Thread Xuelin Shi

Yes, "depend on !ASYNC_TX_CHANNEL_SWITCH" is better since fsldma selects this 
condition.

Thanks,
Xuelin Shi

-Original Message-
From: Dan Williams [mailto:dan.j.willi...@intel.com] 
Sent: 2014年4月15日 8:30
To: Shi Xuelin-B29237
Cc: Koul, Vinod; andriy.shevche...@intel.com; dmaeng...@vger.kernel.org; 
linuxppc-dev; Rai Harninder-B01044; Burmi Naveen-B16502
Subject: Re: [PATCH v3] dmaengine: driver support for FSL RaidEngine device.

On Sun, Apr 13, 2014 at 7:48 PM, Xuelin Shi  wrote:
> Hi Dan,
>
> fsl dma device and fsl raid device are two differenct devices that 
> both provide async_memcpy capability, so I use !FSL_DMA to disable the fsl 
> dma device.
>
> That's to say, either select fsldma device, either fsl raid device.
>

Right, but that's not what your proposed Kconfig dependency line does.

You want something like "depends on FSL_SOC && !(FSL_DMA || FSL_DMA=m)"

However, the more problematic option is ASYNC_TX_CHANNEL_SWITCH.  That option 
is problematic for RAID, so I propose "depend on !ASYNC_TX_CHANNEL_SWITCH" 
since that addresses both problems.


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Re: [PATCH v3] dmaengine: driver support for FSL RaidEngine device.

2014-04-14 Thread Dan Williams

On Sun, Apr 13, 2014 at 7:48 PM, Xuelin Shi  wrote:
> Hi Dan,
>
> fsl dma device and fsl raid device are two differenct devices that both 
> provide async_memcpy
> capability, so I use !FSL_DMA to disable the fsl dma device.
>
> That's to say, either select fsldma device, either fsl raid device.
>

Right, but that's not what your proposed Kconfig dependency line does.

You want something like "depends on FSL_SOC && !(FSL_DMA || FSL_DMA=m)"

However, the more problematic option is ASYNC_TX_CHANNEL_SWITCH.  That
option is problematic for RAID, so I propose "depend on
!ASYNC_TX_CHANNEL_SWITCH" since that addresses both problems.
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RE: [PATCH v3] dmaengine: driver support for FSL RaidEngine device.

2014-04-13 Thread Xuelin Shi

Hi Dan,

fsl dma device and fsl raid device are two differenct devices that both provide 
async_memcpy
capability, so I use !FSL_DMA to disable the fsl dma device. 

That's to say, either select fsldma device, either fsl raid device.

Thanks,
Xuelin Shi

-Original Message-
From: dan.j.willi...@gmail.com [mailto:dan.j.willi...@gmail.com] On Behalf Of 
Dan Williams
Sent: 2014年4月12日 1:43
To: Shi Xuelin-B29237
Cc: Koul, Vinod; andriy.shevche...@intel.com; dmaeng...@vger.kernel.org; 
linuxppc-dev; Rai Harninder-B01044; Burmi Naveen-B16502
Subject: Re: [PATCH v3] dmaengine: driver support for FSL RaidEngine device.

A few more comments:

On Fri, Apr 11, 2014 at 12:41 AM,   wrote:
> From: Xuelin Shi 
>
> The RaidEngine is a new FSL hardware used for Raid5/6 acceration.
>
> This patch enables the RaidEngine functionality and provides hardware 
> offloading capability for memcpy, xor and pq computation.
> It works with async_tx.
>
> Signed-off-by: Harninder Rai 
> Signed-off-by: Naveen Burmi 
> Signed-off-by: Xuelin Shi 
> ---
>  changes for v3:
>   - fix memory allocation flag GFP_xxx usage.
>   - add re_jr_issue_pending call in cleanup.
>   - remove unnecessary dma_run_dependencies(...).
>   - use dma_cookie_complete(...) instead of direct updating cookie.
>
>  drivers/dma/Kconfig|  11 +
>  drivers/dma/Makefile   |   1 +
>  drivers/dma/fsl_raid.c | 878 
> +
>  drivers/dma/fsl_raid.h | 308 +
>  4 files changed, 1198 insertions(+)
>  create mode 100644 drivers/dma/fsl_raid.c  create mode 100644 
> drivers/dma/fsl_raid.h
>
> diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index 
> 605b016..829f41c 100644
> --- a/drivers/dma/Kconfig
> +++ b/drivers/dma/Kconfig
> @@ -100,6 +100,17 @@ config FSL_DMA
>   EloPlus is on mpc85xx and mpc86xx and Pxxx parts, and the Elo3 is on
>   some Txxx and Bxxx parts.
>
> +config FSL_RAID
> +tristate "Freescale RAID engine Support"
> +depends on FSL_SOC && !FSL_DMA

This won't work in the case where FSL_DMA=m.

Instead, I think you want to use "depends on !ASYNC_TX_ENABLE_CHANNEL_SWITCH" 
which is the actual dependency.

> +select DMA_ENGINE
> +select DMA_ENGINE_RAID
> +---help---
> +  Enable support for Freescale RAID Engine. RAID Engine is
> +  available on some QorIQ SoCs (like P5020). It has
> +  the capability to offload memcpy, xor and pq computation
> + for raid5/6.
> +
[..]
> diff --git a/drivers/dma/fsl_raid.c b/drivers/dma/fsl_raid.c new file 
> mode 100644 index 000..4b389b1
> --- /dev/null
> +++ b/drivers/dma/fsl_raid.c
> @@ -0,0 +1,878 @@
[..]
> +void fill_cfd_frame(struct cmpnd_frame *cf, u8 index,
> +   size_t length, dma_addr_t addr, bool final) {
> +   u32 efrl = length & CF_LENGTH_MASK;
> +   efrl |= final << CF_FINAL_SHIFT;
> +   cf[index].efrl32 = efrl;
> +   cf[index].addr_high = (addr >> 32) & HWDESC_ADDR_HIGH_MASK;

Use "upper_32_bits()" here otherwise:

  drivers/dma/fsl_raid.c: In function 'fill_cfd_frame':
  drivers/dma/fsl_raid.c:258:2: warning: right shift count >= width of type

> +   cf[index].addr_low = (u32)addr;

Use lower_32_bits() here to be symmetrical.

> +}
> +
> +static struct fsl_re_dma_async_tx_desc *re_jr_init_desc(struct re_jr *jr,
> +   struct fsl_re_dma_async_tx_desc *desc, void *cf, dma_addr_t 
> +paddr) {
> +   desc->jr = jr;
> +   desc->async_tx.tx_submit = re_jr_tx_submit;
> +   dma_async_tx_descriptor_init(&desc->async_tx, &jr->chan);
> +   INIT_LIST_HEAD(&desc->node);
> +
> +   desc->hwdesc.fmt32 = FRAME_FORMAT << HWDESC_FMT_SHIFT;
> +   desc->hwdesc.lbea32 = (paddr >> 32) & HWDESC_ADDR_HIGH_MASK;

Same comment/warning as above...

> +   desc->hwdesc.addr_low = (u32)paddr;

ditto.


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Re: [PATCH v3] dmaengine: driver support for FSL RaidEngine device.

2014-04-11 Thread Dan Williams

On Fri, Apr 11, 2014 at 10:42 AM, Dan Williams  wrote:
> A few more comments:
>
> On Fri, Apr 11, 2014 at 12:41 AM,   wrote:
>> From: Xuelin Shi 
>>
>> The RaidEngine is a new FSL hardware used for Raid5/6 acceration.
>>
>> This patch enables the RaidEngine functionality and provides
>> hardware offloading capability for memcpy, xor and pq computation.
>> It works with async_tx.
>>
>> Signed-off-by: Harninder Rai 
>> Signed-off-by: Naveen Burmi 
>> Signed-off-by: Xuelin Shi 
>> ---
>>  changes for v3:
>>   - fix memory allocation flag GFP_xxx usage.
>>   - add re_jr_issue_pending call in cleanup.
>>   - remove unnecessary dma_run_dependencies(...).
>>   - use dma_cookie_complete(...) instead of direct updating cookie.
>>
>>  drivers/dma/Kconfig|  11 +
>>  drivers/dma/Makefile   |   1 +
>>  drivers/dma/fsl_raid.c | 878 
>> +
>>  drivers/dma/fsl_raid.h | 308 +
>>  4 files changed, 1198 insertions(+)
>>  create mode 100644 drivers/dma/fsl_raid.c
>>  create mode 100644 drivers/dma/fsl_raid.h
>>
>> diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
>> index 605b016..829f41c 100644
>> --- a/drivers/dma/Kconfig
>> +++ b/drivers/dma/Kconfig
>> @@ -100,6 +100,17 @@ config FSL_DMA
>>   EloPlus is on mpc85xx and mpc86xx and Pxxx parts, and the Elo3 is 
>> on
>>   some Txxx and Bxxx parts.
>>
>> +config FSL_RAID
>> +tristate "Freescale RAID engine Support"
>> +depends on FSL_SOC && !FSL_DMA
>
> This won't work in the case where FSL_DMA=m.
>
> Instead, I think you want to use "depends on
> !ASYNC_TX_ENABLE_CHANNEL_SWITCH" which is the actual dependency.
>
>> +select DMA_ENGINE
>> +select DMA_ENGINE_RAID
>> +---help---
>> +  Enable support for Freescale RAID Engine. RAID Engine is
>> +  available on some QorIQ SoCs (like P5020). It has
>> +  the capability to offload memcpy, xor and pq computation
>> + for raid5/6.
>> +
> [..]
>> diff --git a/drivers/dma/fsl_raid.c b/drivers/dma/fsl_raid.c
>> new file mode 100644
>> index 000..4b389b1
>> --- /dev/null
>> +++ b/drivers/dma/fsl_raid.c
>> @@ -0,0 +1,878 @@
> [..]
>> +void fill_cfd_frame(struct cmpnd_frame *cf, u8 index,
>> +   size_t length, dma_addr_t addr, bool final)
>> +{
>> +   u32 efrl = length & CF_LENGTH_MASK;
>> +   efrl |= final << CF_FINAL_SHIFT;
>> +   cf[index].efrl32 = efrl;
>> +   cf[index].addr_high = (addr >> 32) & HWDESC_ADDR_HIGH_MASK;
>
> Use "upper_32_bits()" here otherwise:
>
>   drivers/dma/fsl_raid.c: In function 'fill_cfd_frame':
>   drivers/dma/fsl_raid.c:258:2: warning: right shift count >= width of type
>
>> +   cf[index].addr_low = (u32)addr;
>
> Use lower_32_bits() here to be symmetrical.
>
>> +}
>> +
>> +static struct fsl_re_dma_async_tx_desc *re_jr_init_desc(struct re_jr *jr,
>> +   struct fsl_re_dma_async_tx_desc *desc, void *cf, dma_addr_t paddr)
>> +{
>> +   desc->jr = jr;
>> +   desc->async_tx.tx_submit = re_jr_tx_submit;
>> +   dma_async_tx_descriptor_init(&desc->async_tx, &jr->chan);
>> +   INIT_LIST_HEAD(&desc->node);
>> +
>> +   desc->hwdesc.fmt32 = FRAME_FORMAT << HWDESC_FMT_SHIFT;
>> +   desc->hwdesc.lbea32 = (paddr >> 32) & HWDESC_ADDR_HIGH_MASK;
>
> Same comment/warning as above...
>
>> +   desc->hwdesc.addr_low = (u32)paddr;
>
> ditto.

Oh, and be mindful of checkpatch output:

ERROR: trailing whitespace
#35: FILE: drivers/dma/Kconfig:106:
+select DMA_ENGINE $

ERROR: trailing whitespace
#42: FILE: drivers/dma/Kconfig:113:
+ $

total: 2 errors, 0 warnings, 1207 lines checked
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Re: [PATCH v3] dmaengine: driver support for FSL RaidEngine device.

2014-04-11 Thread Dan Williams

A few more comments:

On Fri, Apr 11, 2014 at 12:41 AM,   wrote:
> From: Xuelin Shi 
>
> The RaidEngine is a new FSL hardware used for Raid5/6 acceration.
>
> This patch enables the RaidEngine functionality and provides
> hardware offloading capability for memcpy, xor and pq computation.
> It works with async_tx.
>
> Signed-off-by: Harninder Rai 
> Signed-off-by: Naveen Burmi 
> Signed-off-by: Xuelin Shi 
> ---
>  changes for v3:
>   - fix memory allocation flag GFP_xxx usage.
>   - add re_jr_issue_pending call in cleanup.
>   - remove unnecessary dma_run_dependencies(...).
>   - use dma_cookie_complete(...) instead of direct updating cookie.
>
>  drivers/dma/Kconfig|  11 +
>  drivers/dma/Makefile   |   1 +
>  drivers/dma/fsl_raid.c | 878 
> +
>  drivers/dma/fsl_raid.h | 308 +
>  4 files changed, 1198 insertions(+)
>  create mode 100644 drivers/dma/fsl_raid.c
>  create mode 100644 drivers/dma/fsl_raid.h
>
> diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
> index 605b016..829f41c 100644
> --- a/drivers/dma/Kconfig
> +++ b/drivers/dma/Kconfig
> @@ -100,6 +100,17 @@ config FSL_DMA
>   EloPlus is on mpc85xx and mpc86xx and Pxxx parts, and the Elo3 is on
>   some Txxx and Bxxx parts.
>
> +config FSL_RAID
> +tristate "Freescale RAID engine Support"
> +depends on FSL_SOC && !FSL_DMA

This won't work in the case where FSL_DMA=m.

Instead, I think you want to use "depends on
!ASYNC_TX_ENABLE_CHANNEL_SWITCH" which is the actual dependency.

> +select DMA_ENGINE
> +select DMA_ENGINE_RAID
> +---help---
> +  Enable support for Freescale RAID Engine. RAID Engine is
> +  available on some QorIQ SoCs (like P5020). It has
> +  the capability to offload memcpy, xor and pq computation
> + for raid5/6.
> +
[..]
> diff --git a/drivers/dma/fsl_raid.c b/drivers/dma/fsl_raid.c
> new file mode 100644
> index 000..4b389b1
> --- /dev/null
> +++ b/drivers/dma/fsl_raid.c
> @@ -0,0 +1,878 @@
[..]
> +void fill_cfd_frame(struct cmpnd_frame *cf, u8 index,
> +   size_t length, dma_addr_t addr, bool final)
> +{
> +   u32 efrl = length & CF_LENGTH_MASK;
> +   efrl |= final << CF_FINAL_SHIFT;
> +   cf[index].efrl32 = efrl;
> +   cf[index].addr_high = (addr >> 32) & HWDESC_ADDR_HIGH_MASK;

Use "upper_32_bits()" here otherwise:

  drivers/dma/fsl_raid.c: In function 'fill_cfd_frame':
  drivers/dma/fsl_raid.c:258:2: warning: right shift count >= width of type

> +   cf[index].addr_low = (u32)addr;

Use lower_32_bits() here to be symmetrical.

> +}
> +
> +static struct fsl_re_dma_async_tx_desc *re_jr_init_desc(struct re_jr *jr,
> +   struct fsl_re_dma_async_tx_desc *desc, void *cf, dma_addr_t paddr)
> +{
> +   desc->jr = jr;
> +   desc->async_tx.tx_submit = re_jr_tx_submit;
> +   dma_async_tx_descriptor_init(&desc->async_tx, &jr->chan);
> +   INIT_LIST_HEAD(&desc->node);
> +
> +   desc->hwdesc.fmt32 = FRAME_FORMAT << HWDESC_FMT_SHIFT;
> +   desc->hwdesc.lbea32 = (paddr >> 32) & HWDESC_ADDR_HIGH_MASK;

Same comment/warning as above...

> +   desc->hwdesc.addr_low = (u32)paddr;

ditto.
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[PATCH v3] dmaengine: driver support for FSL RaidEngine device.

2014-04-11 Thread xuelin.shi

From: Xuelin Shi 

The RaidEngine is a new FSL hardware used for Raid5/6 acceration.

This patch enables the RaidEngine functionality and provides
hardware offloading capability for memcpy, xor and pq computation.
It works with async_tx.

Signed-off-by: Harninder Rai 
Signed-off-by: Naveen Burmi 
Signed-off-by: Xuelin Shi 
---
 changes for v3:
  - fix memory allocation flag GFP_xxx usage.  
  - add re_jr_issue_pending call in cleanup.
  - remove unnecessary dma_run_dependencies(...).
  - use dma_cookie_complete(...) instead of direct updating cookie.

 drivers/dma/Kconfig|  11 +
 drivers/dma/Makefile   |   1 +
 drivers/dma/fsl_raid.c | 878 +
 drivers/dma/fsl_raid.h | 308 +
 4 files changed, 1198 insertions(+)
 create mode 100644 drivers/dma/fsl_raid.c
 create mode 100644 drivers/dma/fsl_raid.h

diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index 605b016..829f41c 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -100,6 +100,17 @@ config FSL_DMA
  EloPlus is on mpc85xx and mpc86xx and Pxxx parts, and the Elo3 is on
  some Txxx and Bxxx parts.
 
+config FSL_RAID
+tristate "Freescale RAID engine Support"
+depends on FSL_SOC && !FSL_DMA
+select DMA_ENGINE 
+select DMA_ENGINE_RAID
+---help---
+  Enable support for Freescale RAID Engine. RAID Engine is
+  available on some QorIQ SoCs (like P5020). It has
+  the capability to offload memcpy, xor and pq computation
+ for raid5/6.
+ 
 config MPC512X_DMA
tristate "Freescale MPC512x built-in DMA engine support"
depends on PPC_MPC512x || PPC_MPC831x
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index a029d0f4..60b163b 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -44,3 +44,4 @@ obj-$(CONFIG_DMA_JZ4740) += dma-jz4740.o
 obj-$(CONFIG_TI_CPPI41) += cppi41.o
 obj-$(CONFIG_K3_DMA) += k3dma.o
 obj-$(CONFIG_MOXART_DMA) += moxart-dma.o
+obj-$(CONFIG_FSL_RAID) += fsl_raid.o
diff --git a/drivers/dma/fsl_raid.c b/drivers/dma/fsl_raid.c
new file mode 100644
index 000..4b389b1
--- /dev/null
+++ b/drivers/dma/fsl_raid.c
@@ -0,0 +1,878 @@
+/*
+ * drivers/dma/fsl_raid.c
+ *
+ * Freescale RAID Engine device driver
+ *
+ * Author:
+ * Harninder Rai 
+ * Naveen Burmi 
+ *
+ * Rewrite:
+ * Xuelin Shi 
+ *
+ * Copyright (c) 2010-2014 Freescale Semiconductor, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ *   names of its contributors may be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Theory of operation:
+ *
+ * General capabilities:
+ * RAID Engine (RE) block is capable of offloading XOR, memcpy and P/Q
+ * calculations required in RAID5 and RAID6 operations. RE driver
+ * registers with Linux's ASYNC layer as dma driver. RE hardware
+ * maintains strict ordering of the requests through chained
+ * command queueing.
+ *
+ * Data flow:
+ * Software RAID layer of Linux (MD layer) maintains RAID partitions,
+ * strips, stripes etc. It sends requests to the underlying AYSNC layer
+ * which further passes it to RE driver. ASYNC layer decides which request
+ * goes to which job ring of RE hardware. For every request processed by
+ * RAID Engine, driver gets an interrupt unless coalescing is set.

Re: [PATCH v3] dmaengine: driver support for FSL RaidEngine device.

RE: [PATCH v3] dmaengine: driver support for FSL RaidEngine device.

RE: [PATCH v3] dmaengine: driver support for FSL RaidEngine device.

Re: [PATCH v3] dmaengine: driver support for FSL RaidEngine device.

RE: [PATCH v3] dmaengine: driver support for FSL RaidEngine device.

Re: [PATCH v3] dmaengine: driver support for FSL RaidEngine device.

Re: [PATCH v3] dmaengine: driver support for FSL RaidEngine device.

[PATCH v3] dmaengine: driver support for FSL RaidEngine device.

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