This series fixes several similar but unrelated bugs with NMIs clobbering live registers without noticing it, because MSR[RI] is set. Pretty rare bugs, but serious silent corruption consequences.
For the most part these can be observed and tested quite easily with the mambo simulator, except that it does not seem to follow the architecture wrt leaving MSR[RI] unchanged for HV interrupts. Mambo clears MSR[RI], so you have to account for that manually. Since v1: - Fixed several build bugs. Since v2: - Improved changelog and comments. - Fixed the NIA test for virt mode interrupts. Since v3: - Fixed HPT crash due to use of PACA_EXGEN rather than EXSLB in the SLB interrupt handlers. Nicholas Piggin (4): powerpc/64s: Fix HV NMI vs HV interrupt recoverability test powerpc/64s: system reset interrupt preserve HSRRs powerpc/64s: Prepare to handle data interrupts vs d-side MCE reentrancy powerpc/64s: Fix data interrupts vs d-side MCE reentrancy arch/powerpc/include/asm/asm-prototypes.h | 8 ++ arch/powerpc/include/asm/nmi.h | 2 + arch/powerpc/kernel/exceptions-64s.S | 92 +++++++++++++++++++---- arch/powerpc/kernel/mce.c | 3 + arch/powerpc/kernel/traps.c | 91 +++++++++++++++++++++- 5 files changed, 179 insertions(+), 17 deletions(-) -- 2.18.0