This is listed as a requirement for Freescale CoreNet based devices (e.g
p4080ds with MPIC v4.x) after issuing a core reset to properly clear pending
interrupts.
Signed-off-by: Matthew McClintock m...@freescale.com
---
v2: Updated commit message
v3: Added detail in code comment as well
v4: Check for MPIC_FSL in mpic-flags to determine if we need 15 EOIs
arch/powerpc/sysdev/mpic.c | 10 ++
1 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index 9678081..0842c6f 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -1748,6 +1748,7 @@ void mpic_reset_core(int cpu)
struct mpic *mpic = mpic_primary;
u32 pir;
int cpuid = get_hard_smp_processor_id(cpu);
+ int i;
/* Set target bit for core reset */
pir = mpic_read(mpic-gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
@@ -1759,6 +1760,15 @@ void mpic_reset_core(int cpu)
pir = ~(1 cpuid);
mpic_write(mpic-gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir);
mpic_read(mpic-gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
+
+ /* Perform 15 EOI on each reset core to clear pending interrupts.
+* This is required for FSL CoreNet based devices */
+ if (mpic-flags MPIC_FSL) {
+ for (i = 0; i 15; i++) {
+ _mpic_write(mpic-reg_type, mpic-cpuregs[cpuid],
+ MPIC_CPU_EOI, 0);
+ }
+ }
}
#endif /* CONFIG_SMP */
--
1.7.6.1
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