Re: [PATCH v6 02/10] soc: fsl: cpm1: Add support for TSA
Le 17/02/2023 à 15:56, Herve Codina a écrit : > The TSA (Time Slot Assigner) purpose is to route some > TDM time-slots to other internal serial controllers. > > It is available in some PowerQUICC SoC such as the > MPC885 or MPC866. > > It is also available on some Quicc Engine SoCs. > This current version support CPM1 SoCs only and some > enhancement are needed to support Quicc Engine SoCs. > > Signed-off-by: Herve Codina > Acked-by: Li Yang Reviewed-by: Christophe Leroy > --- > drivers/soc/fsl/qe/Kconfig | 11 + > drivers/soc/fsl/qe/Makefile | 1 + > drivers/soc/fsl/qe/tsa.c| 846 > drivers/soc/fsl/qe/tsa.h| 42 ++ > 4 files changed, 900 insertions(+) > create mode 100644 drivers/soc/fsl/qe/tsa.c > create mode 100644 drivers/soc/fsl/qe/tsa.h > > diff --git a/drivers/soc/fsl/qe/Kconfig b/drivers/soc/fsl/qe/Kconfig > index 357c5800b112..b0088495c323 100644 > --- a/drivers/soc/fsl/qe/Kconfig > +++ b/drivers/soc/fsl/qe/Kconfig > @@ -33,6 +33,17 @@ config UCC > bool > default y if UCC_FAST || UCC_SLOW > > +config CPM_TSA > + tristate "CPM TSA support" > + depends on OF && HAS_IOMEM > + depends on CPM1 || COMPILE_TEST > + help > + Freescale CPM Time Slot Assigner (TSA) > + controller. > + > + This option enables support for this > + controller > + > config QE_TDM > bool > default y if FSL_UCC_HDLC > diff --git a/drivers/soc/fsl/qe/Makefile b/drivers/soc/fsl/qe/Makefile > index 55a555304f3a..45c961acc81b 100644 > --- a/drivers/soc/fsl/qe/Makefile > +++ b/drivers/soc/fsl/qe/Makefile > @@ -4,6 +4,7 @@ > # > obj-$(CONFIG_QUICC_ENGINE)+= qe.o qe_common.o qe_ic.o qe_io.o > obj-$(CONFIG_CPM) += qe_common.o > +obj-$(CONFIG_CPM_TSA)+= tsa.o > obj-$(CONFIG_UCC) += ucc.o > obj-$(CONFIG_UCC_SLOW) += ucc_slow.o > obj-$(CONFIG_UCC_FAST) += ucc_fast.o > diff --git a/drivers/soc/fsl/qe/tsa.c b/drivers/soc/fsl/qe/tsa.c > new file mode 100644 > index ..3646153117b3 > --- /dev/null > +++ b/drivers/soc/fsl/qe/tsa.c > @@ -0,0 +1,846 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * TSA driver > + * > + * Copyright 2022 CS GROUP France > + * > + * Author: Herve Codina > + */ > + > +#include "tsa.h" > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > + > +/* TSA SI RAM routing tables entry */ > +#define TSA_SIRAM_ENTRY_LAST (1 << 16) > +#define TSA_SIRAM_ENTRY_BYTE (1 << 17) > +#define TSA_SIRAM_ENTRY_CNT(x) (((x) & 0x0f) << 18) > +#define TSA_SIRAM_ENTRY_CSEL_MASK(0x7 << 22) > +#define TSA_SIRAM_ENTRY_CSEL_NU (0x0 << 22) > +#define TSA_SIRAM_ENTRY_CSEL_SCC2(0x2 << 22) > +#define TSA_SIRAM_ENTRY_CSEL_SCC3(0x3 << 22) > +#define TSA_SIRAM_ENTRY_CSEL_SCC4(0x4 << 22) > +#define TSA_SIRAM_ENTRY_CSEL_SMC1(0x5 << 22) > +#define TSA_SIRAM_ENTRY_CSEL_SMC2(0x6 << 22) > + > +/* SI mode register (32 bits) */ > +#define TSA_SIMODE 0x00 > +#define TSA_SIMODE_SMC20x8000 > +#define TSA_SIMODE_SMC10x8000 > +#define TSA_SIMODE_TDMA(x) ((x) << 0) > +#define TSA_SIMODE_TDMB(x) ((x) << 16) > +#define TSA_SIMODE_TDM_MASK 0x0fff > +#define TSA_SIMODE_TDM_SDM_MASK 0x0c00 > +#define TSA_SIMODE_TDM_SDM_NORM0x > +#define TSA_SIMODE_TDM_SDM_ECHO0x0400 > +#define TSA_SIMODE_TDM_SDM_INTL_LOOP 0x0800 > +#define TSA_SIMODE_TDM_SDM_LOOP_CTRL 0x0c00 > +#define TSA_SIMODE_TDM_RFSD(x) ((x) << 8) > +#define TSA_SIMODE_TDM_DSC 0x0080 > +#define TSA_SIMODE_TDM_CRT 0x0040 > +#define TSA_SIMODE_TDM_STZ 0x0020 > +#define TSA_SIMODE_TDM_CE0x0010 > +#define TSA_SIMODE_TDM_FE0x0008 > +#define TSA_SIMODE_TDM_GM0x0004 > +#define TSA_SIMODE_TDM_TFSD(x) ((x) << 0) > + > +/* SI global mode register (8 bits) */ > +#define TSA_SIGMR0x04 > +#define TSA_SIGMR_ENB(1<<3) > +#define TSA_SIGMR_ENA(1<<2) > +#define TSA_SIGMR_RDM_MASK 0x03 > +#define TSA_SIGMR_RDM_STATIC_TDMA 0x00 > +#define TSA_SIGMR_RDM_DYN_TDMA 0x01 > +#define TSA_SIGMR_RDM_STATIC_TDMAB 0x02 > +#define TSA_SIGMR_RDM_DYN_TDMAB0x03 > + > +/* SI status register (8 bits) */ > +#define TSA_SISTR0x06 > + > +/* SI command register (8 bits) */ > +#define TSA_SICMR0x07 > + > +/* SI clock route register (32 bits) */ > +#define TSA_SICR 0x0C > +#define TSA_SICR_SCC2(x) ((x) << 8) > +#define TSA_SICR_SCC3(x) ((x) << 16) > +#define TSA_SICR_SCC4(x) ((x) << 24) > +#define TSA_SICR_SCC_MASK0x0ff > +#define
[PATCH v6 02/10] soc: fsl: cpm1: Add support for TSA
The TSA (Time Slot Assigner) purpose is to route some TDM time-slots to other internal serial controllers. It is available in some PowerQUICC SoC such as the MPC885 or MPC866. It is also available on some Quicc Engine SoCs. This current version support CPM1 SoCs only and some enhancement are needed to support Quicc Engine SoCs. Signed-off-by: Herve Codina Acked-by: Li Yang --- drivers/soc/fsl/qe/Kconfig | 11 + drivers/soc/fsl/qe/Makefile | 1 + drivers/soc/fsl/qe/tsa.c| 846 drivers/soc/fsl/qe/tsa.h| 42 ++ 4 files changed, 900 insertions(+) create mode 100644 drivers/soc/fsl/qe/tsa.c create mode 100644 drivers/soc/fsl/qe/tsa.h diff --git a/drivers/soc/fsl/qe/Kconfig b/drivers/soc/fsl/qe/Kconfig index 357c5800b112..b0088495c323 100644 --- a/drivers/soc/fsl/qe/Kconfig +++ b/drivers/soc/fsl/qe/Kconfig @@ -33,6 +33,17 @@ config UCC bool default y if UCC_FAST || UCC_SLOW +config CPM_TSA + tristate "CPM TSA support" + depends on OF && HAS_IOMEM + depends on CPM1 || COMPILE_TEST + help + Freescale CPM Time Slot Assigner (TSA) + controller. + + This option enables support for this + controller + config QE_TDM bool default y if FSL_UCC_HDLC diff --git a/drivers/soc/fsl/qe/Makefile b/drivers/soc/fsl/qe/Makefile index 55a555304f3a..45c961acc81b 100644 --- a/drivers/soc/fsl/qe/Makefile +++ b/drivers/soc/fsl/qe/Makefile @@ -4,6 +4,7 @@ # obj-$(CONFIG_QUICC_ENGINE)+= qe.o qe_common.o qe_ic.o qe_io.o obj-$(CONFIG_CPM) += qe_common.o +obj-$(CONFIG_CPM_TSA) += tsa.o obj-$(CONFIG_UCC) += ucc.o obj-$(CONFIG_UCC_SLOW) += ucc_slow.o obj-$(CONFIG_UCC_FAST) += ucc_fast.o diff --git a/drivers/soc/fsl/qe/tsa.c b/drivers/soc/fsl/qe/tsa.c new file mode 100644 index ..3646153117b3 --- /dev/null +++ b/drivers/soc/fsl/qe/tsa.c @@ -0,0 +1,846 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * TSA driver + * + * Copyright 2022 CS GROUP France + * + * Author: Herve Codina + */ + +#include "tsa.h" +#include +#include +#include +#include +#include +#include +#include +#include + + +/* TSA SI RAM routing tables entry */ +#define TSA_SIRAM_ENTRY_LAST (1 << 16) +#define TSA_SIRAM_ENTRY_BYTE (1 << 17) +#define TSA_SIRAM_ENTRY_CNT(x) (((x) & 0x0f) << 18) +#define TSA_SIRAM_ENTRY_CSEL_MASK (0x7 << 22) +#define TSA_SIRAM_ENTRY_CSEL_NU(0x0 << 22) +#define TSA_SIRAM_ENTRY_CSEL_SCC2 (0x2 << 22) +#define TSA_SIRAM_ENTRY_CSEL_SCC3 (0x3 << 22) +#define TSA_SIRAM_ENTRY_CSEL_SCC4 (0x4 << 22) +#define TSA_SIRAM_ENTRY_CSEL_SMC1 (0x5 << 22) +#define TSA_SIRAM_ENTRY_CSEL_SMC2 (0x6 << 22) + +/* SI mode register (32 bits) */ +#define TSA_SIMODE 0x00 +#define TSA_SIMODE_SMC2 0x8000 +#define TSA_SIMODE_SMC1 0x8000 +#define TSA_SIMODE_TDMA(x) ((x) << 0) +#define TSA_SIMODE_TDMB(x) ((x) << 16) +#define TSA_SIMODE_TDM_MASK0x0fff +#define TSA_SIMODE_TDM_SDM_MASK0x0c00 +#define TSA_SIMODE_TDM_SDM_NORM 0x +#define TSA_SIMODE_TDM_SDM_ECHO 0x0400 +#define TSA_SIMODE_TDM_SDM_INTL_LOOP 0x0800 +#define TSA_SIMODE_TDM_SDM_LOOP_CTRL 0x0c00 +#define TSA_SIMODE_TDM_RFSD(x) ((x) << 8) +#define TSA_SIMODE_TDM_DSC 0x0080 +#define TSA_SIMODE_TDM_CRT 0x0040 +#define TSA_SIMODE_TDM_STZ 0x0020 +#define TSA_SIMODE_TDM_CE 0x0010 +#define TSA_SIMODE_TDM_FE 0x0008 +#define TSA_SIMODE_TDM_GM 0x0004 +#define TSA_SIMODE_TDM_TFSD(x) ((x) << 0) + +/* SI global mode register (8 bits) */ +#define TSA_SIGMR 0x04 +#define TSA_SIGMR_ENB (1<<3) +#define TSA_SIGMR_ENA (1<<2) +#define TSA_SIGMR_RDM_MASK 0x03 +#define TSA_SIGMR_RDM_STATIC_TDMA0x00 +#define TSA_SIGMR_RDM_DYN_TDMA 0x01 +#define TSA_SIGMR_RDM_STATIC_TDMAB 0x02 +#define TSA_SIGMR_RDM_DYN_TDMAB 0x03 + +/* SI status register (8 bits) */ +#define TSA_SISTR 0x06 + +/* SI command register (8 bits) */ +#define TSA_SICMR 0x07 + +/* SI clock route register (32 bits) */ +#define TSA_SICR 0x0C +#define TSA_SICR_SCC2(x) ((x) << 8) +#define TSA_SICR_SCC3(x) ((x) << 16) +#define TSA_SICR_SCC4(x) ((x) << 24) +#define TSA_SICR_SCC_MASK 0x0ff +#define TSA_SICR_SCC_GRX (1 << 7) +#define TSA_SICR_SCC_SCX_TSA (1 << 6) +#define TSA_SICR_SCC_RXCS_MASK (0x7 << 3) +#define TSA_SICR_SCC_RXCS_BRG1 (0x0 << 3) +#define TSA_SICR_SCC_RXCS_BRG2 (0x1 << 3) +#define TSA_SICR_SCC_RXCS_BRG3 (0x2 << 3) +#define TSA_SICR_SCC_RXCS_BRG4 (0x3 << 3) +#define
