Hi Scott,
Could you apply these patches?
[v6,1/4] powerpc/fsl: add E6500 PVR and SPRN_PWRMGTCR0 define,
http://patchwork.ozlabs.org/patch/302045/
[v6,2/4] powerpc/85xx: add hardware automatically enter altivec idle state,
http://patchwork.ozlabs.org/patch/302046/
[v6,3/4] powerpc/85xx: add hardware automatically enter pw20 state,
http://patchwork.ozlabs.org/patch/302047/
[v6,4/4] powerpc/85xx: add sysfs for pw20 state and altivec idle,
http://patchwork.ozlabs.org/patch/302048/
-Dongsheng
> -Original Message-
> From: Dongsheng Wang [mailto:dongsheng.w...@freescale.com]
> Sent: Tuesday, December 17, 2013 4:17 PM
> To: Wood Scott-B07421; Bhushan Bharat-R65777
> Cc: linuxppc-dev@lists.ozlabs.org; Wang Dongsheng-B40534
> Subject: [PATCH v6 1/4] powerpc/fsl: add E6500 PVR and SPRN_PWRMGTCR0 define
>
> From: Wang Dongsheng
>
> E6500 PVR and SPRN_PWRMGTCR0 will be used in subsequent pw20/altivec
> idle patches.
>
> Signed-off-by: Wang Dongsheng
> ---
> *v3:
> Add bit definitions for PWRMGTCR0.
>
> arch/powerpc/include/asm/reg.h | 2 ++
> arch/powerpc/include/asm/reg_booke.h | 9 +
> 2 files changed, 11 insertions(+)
>
> diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
> index 64264bf..d4160ca 100644
> --- a/arch/powerpc/include/asm/reg.h
> +++ b/arch/powerpc/include/asm/reg.h
> @@ -1053,6 +1053,8 @@
> #define PVR_8560 0x8020
> #define PVR_VER_E500V1 0x8020
> #define PVR_VER_E500V2 0x8021
> +#define PVR_VER_E65000x8040
> +
> /*
> * For the 8xx processors, all of them report the same PVR family for
> * the PowerPC core. The various versions of these processors must be
> diff --git a/arch/powerpc/include/asm/reg_booke.h
> b/arch/powerpc/include/asm/reg_booke.h
> index ed8f836..4a6457e 100644
> --- a/arch/powerpc/include/asm/reg_booke.h
> +++ b/arch/powerpc/include/asm/reg_booke.h
> @@ -170,6 +170,7 @@
> #define SPRN_L2CSR1 0x3FA /* L2 Data Cache Control and Status Register 1
> */
> #define SPRN_DCCR0x3FA /* Data Cache Cacheability Register */
> #define SPRN_ICCR0x3FB /* Instruction Cache Cacheability Register */
> +#define SPRN_PWRMGTCR0 0x3FB /* Power management control register 0
> */
> #define SPRN_SVR 0x3FF /* System Version Register */
>
> /*
> @@ -216,6 +217,14 @@
> #define CCR1_DPC0x0100 /* Disable L1 I-Cache/D-Cache parity
> checking */
> #define CCR1_TCS0x0080 /* Timer Clock Select */
>
> +/* Bit definitions for PWRMGTCR0. */
> +#define PWRMGTCR0_PW20_WAIT (1 << 14) /* PW20 state enable bit */
> +#define PWRMGTCR0_PW20_ENT_SHIFT 8
> +#define PWRMGTCR0_PW20_ENT 0x3F00
> +#define PWRMGTCR0_AV_IDLE_PD_EN (1 << 22) /* Altivec idle
> enable */
> +#define PWRMGTCR0_AV_IDLE_CNT_SHIFT 16
> +#define PWRMGTCR0_AV_IDLE_CNT0x3F
> +
> /* Bit definitions for the MCSR. */
> #define MCSR_MCS 0x8000 /* Machine Check Summary */
> #define MCSR_IB 0x4000 /* Instruction PLB Error */
> --
> 1.8.0
>
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