Re: [RFC PATCH 05/19] powerpc: wii: bootwrapper bits
Segher Boessenkool wrote:
+ * We enter with an unknown cache, high BATs and MMU status.
What does this mean? You know the low four BATs on entry and
nothing else?
That means that we do not make assumptions regarding:
- the state of the cache (enabled vs disabled)
- if the high BATs are enabled or not
- if the MMU is enabled or not
Is this clearer? I'm not a native english speaker as you may have noticed
already :-P
+asm (\n\
Global asm() is evil.
Yes, you said. Still, I'd like a proper argument :)
+mfmsr9\n\
+andi.0, 9, (14)|(15) /* MSR_DR|MSR_IR */\n\
+andc9, 9, 0\n\
mfmsr 9 ; rlwinm 9,9,0,~0x30 ?
Yes. Maybe
mfmsr 9 ; rlwinm 9,9,0,~((14)|(15)) /* MSR_DR|MSR_IR */
+mtspr0x01a, 8/* SRR0 */\n\
+mtspr0x01b, 9/* SRR1 */\n\
mtsrr0 and mtsrr1
Easier :)
+sync\n\
+rfi\n\
No need for sync before rfi
Ok.
+mtspr0x210, 8/* IBAT0U */\n\
+mtspr0x211, 8/* IBAT0L */\n\
You only need to set the upper BAT to zero, saves some code.
Great. Is this documented somewhere?
+isync\n\
isync here is cargo cult
I'll offer a dead chicken to compensate for this.
+li8, 0x01ff/* first 16MiB */\n\
+li9, 0x0002/* rw */\n\
+mtspr0x210, 8/* IBAT0U */\n\
+mtspr0x211, 9/* IBAT0L */\n\
+mtspr0x218, 8/* DBAT0U */\n\
+mtspr0x219, 9/* DBAT0L */\n\
M=0 for RAM?
See analog question for gamecube bootwrapper bits.
Also, you should normally write the lower BAT first. Doesn't matter
here because IR=DR=0 of course.
I can change that too if it's the general way to go.
+lis8, 0xcc00/* I/O mem */\n\
+ori8, 8, 0x3ff/* 32MiB */\n\
+lis9, 0x0c00\n\
+ori9, 9, 0x002a/* uncached, guarded, rw */\n\
+mtspr0x21a, 8/* DBAT1U */\n\
+mtspr0x21b, 9/* DBAT1L */\n\
Is there any real reason you don't identity map this?
No. There's a bit of nostalgia there.
(On the other hand there's no real reason to identity map it).
+sync\n\
+isync\n\
+\n\
Don't need these
I'll get rid of them, then.
+/* enable high BATs */\n\
+lis8, 0x8200\n\
+mtspr0x3f3, 8/* HID4 */\n\
You need to use read-modify-write here. Also, shouldn't you
enable the extra BATs before setting them?
No. You should first set them up and then enable them.
The content of the HIGH BATs is undefined on boot, AFAIK.
And you _do_ need isync here as far as I can see.
+/* enable caches */\n\
+mfspr8, 0x3f0\n\
+ori8, 8, 0xc000\n\
+mtspr0x3f0, 8/* HID0 */\n\
+isync\n\
You need to invalidate the L1 caches at the same time as you enable
them.
Ok. I'll check if the caches are enabled. If they aren't I'll invalidate and
enable them.
+void platform_init(unsigned long r3, unsigned long r4, unsigned long r5)
+{
+u32 heapsize = 24*1024*1024 - (u32)_end;
+
+simple_alloc_init(_end, heapsize, 32, 64);
+fdt_init(_dtb_start);
+
+if (!ug_grab_io_base() ug_is_adapter_present())
The ! reads weird. Can you not make ug_is_adapter_present()
call ug_grab_io_base(), anyway?
Calling ug_grab_io_base() from ug_is_adapter_present() can be misleading too
(you are supposed to just check if the adapter is present in that function,
according to the name).
If the ! is ugly I can use the following idiom, introducing an error variable.
error = ug_grab_io_base();
if (!error ug_is_adapter_present())
/* blah */
Thanks,
Albert
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Re: [RFC PATCH 05/19] powerpc: wii: bootwrapper bits
+ * We enter with an unknown cache, high BATs and MMU status. What does this mean? You know the low four BATs on entry and nothing else? That means that we do not make assumptions regarding: - the state of the cache (enabled vs disabled) - if the high BATs are enabled or not - if the MMU is enabled or not Is this clearer? Yeah it is. +mfmsr9\n\ +andi.0, 9, (14)|(15) /* MSR_DR|MSR_IR */\n\ +andc9, 9, 0\n\ mfmsr 9 ; rlwinm 9,9,0,~0x30 ? Yes. Maybe mfmsr 9 ; rlwinm 9,9,0,~((14)|(15)) /* MSR_DR|MSR_IR */ Sure, or ~0x30 with that comment. You can save an insn and make the code clearer at the same time, how exactly you write it, I don't care :-) +mtspr0x210, 8/* IBAT0U */\n\ +mtspr0x211, 8/* IBAT0L */\n\ You only need to set the upper BAT to zero, saves some code. Great. Is this documented somewhere? Sure, it's all in the PEM. +isync\n\ isync here is cargo cult I'll offer a dead chicken to compensate for this. Thanks, I needed some more of those :-) Also, you should normally write the lower BAT first. Doesn't matter here because IR=DR=0 of course. I can change that too if it's the general way to go. Please do. +lis8, 0xcc00/* I/O mem */\n\ +ori8, 8, 0x3ff/* 32MiB */\n\ +lis9, 0x0c00\n\ +ori9, 9, 0x002a/* uncached, guarded, rw */\n\ +mtspr0x21a, 8/* DBAT1U */\n\ +mtspr0x21b, 9/* DBAT1L */\n\ Is there any real reason you don't identity map this? No. There's a bit of nostalgia there. (On the other hand there's no real reason to identity map it). It's a tiny bit cleaner and stops people from wondering why :-) +/* enable high BATs */\n\ +lis8, 0x8200\n\ +mtspr0x3f3, 8/* HID4 */\n\ You need to use read-modify-write here. Also, shouldn't you enable the extra BATs before setting them? No. You should first set them up and then enable them. The content of the HIGH BATs is undefined on boot, AFAIK. All BATs are undefined at boot; you need to clear them / set them before enabling them (DR=1 or IR=1), so there is nothing special about the high BATs. What I am getting at is if the mfspr/mtspr to the high BATs does work when the HID bit for them is off. Please address the RMW thing (don't clear bits in HID4). +/* enable caches */\n\ +mfspr8, 0x3f0\n\ +ori8, 8, 0xc000\n\ +mtspr0x3f0, 8/* HID0 */\n\ +isync\n\ You need to invalidate the L1 caches at the same time as you enable them. Ok. I'll check if the caches are enabled. If they aren't I'll invalidate and enable them. Yeah, good point. If the ! is ugly I can use the following idiom, introducing an error variable. error = ug_grab_io_base(); if (!error ug_is_adapter_present()) /* blah */ Much clearer, thanks. Segher ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [RFC PATCH 05/19] powerpc: wii: bootwrapper bits
+ * We enter with an unknown cache, high BATs and MMU status.
What does this mean? You know the low four BATs on entry and
nothing else?
+asm (\n\
Global asm() is evil.
+ mfmsr 9\n\
+ andi. 0, 9, (14)|(15) /* MSR_DR|MSR_IR */\n\
+ andc9, 9, 0\n\
mfmsr 9 ; rlwinm 9,9,0,~0x30 ?
+ mtspr 0x01a, 8/* SRR0 */\n\
+ mtspr 0x01b, 9/* SRR1 */\n\
mtsrr0 and mtsrr1
+ sync\n\
+ rfi\n\
No need for sync before rfi
+ mtspr 0x210, 8/* IBAT0U */\n\
+ mtspr 0x211, 8/* IBAT0L */\n\
You only need to set the upper BAT to zero, saves some code.
+ isync\n\
isync here is cargo cult
+ li 8, 0x01ff /* first 16MiB */\n\
+ li 9, 0x0002 /* rw */\n\
+ mtspr 0x210, 8/* IBAT0U */\n\
+ mtspr 0x211, 9/* IBAT0L */\n\
+ mtspr 0x218, 8/* DBAT0U */\n\
+ mtspr 0x219, 9/* DBAT0L */\n\
M=0 for RAM?
Also, you should normally write the lower BAT first. Doesn't matter
here because IR=DR=0 of course.
+ lis 8, 0xcc00 /* I/O mem */\n\
+ ori 8, 8, 0x3ff /* 32MiB */\n\
+ lis 9, 0x0c00\n\
+ ori 9, 9, 0x002a/* uncached, guarded, rw */\n\
+ mtspr 0x21a, 8/* DBAT1U */\n\
+ mtspr 0x21b, 9/* DBAT1L */\n\
Is there any real reason you don't identity map this?
+ sync\n\
+ isync\n\
+\n\
Don't need these
+ /* enable high BATs */\n\
+ lis 8, 0x8200\n\
+ mtspr 0x3f3, 8/* HID4 */\n\
You need to use read-modify-write here. Also, shouldn't you
enable the extra BATs before setting them?
And you _do_ need isync here as far as I can see.
+ /* enable caches */\n\
+ mfspr 8, 0x3f0\n\
+ ori 8, 8, 0xc000\n\
+ mtspr 0x3f0, 8/* HID0 */\n\
+ isync\n\
You need to invalidate the L1 caches at the same time as you enable
them.
+void platform_init(unsigned long r3, unsigned long r4, unsigned
long r5)
+{
+ u32 heapsize = 24*1024*1024 - (u32)_end;
+
+ simple_alloc_init(_end, heapsize, 32, 64);
+ fdt_init(_dtb_start);
+
+ if (!ug_grab_io_base() ug_is_adapter_present())
The ! reads weird. Can you not make ug_is_adapter_present()
call ug_grab_io_base(), anyway?
Segher
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[RFC PATCH 05/19] powerpc: wii: bootwrapper bits
Add support for the Nintendo Wii video game console to the powerpc bootwrapper. dtbImage.wii is a wrapped image that contains a flat device tree, an entry point compatible with the Homebrew Channel and BootMii, and an optional initrd. Signed-off-by: Albert Herranz albert_herr...@yahoo.es --- arch/powerpc/boot/Makefile |3 +- arch/powerpc/boot/wii.c| 173 arch/powerpc/boot/wrapper |3 + 3 files changed, 178 insertions(+), 1 deletions(-) create mode 100644 arch/powerpc/boot/wii.c diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile index b2f06b0..fbaf101 100644 --- a/arch/powerpc/boot/Makefile +++ b/arch/powerpc/boot/Makefile @@ -77,7 +77,7 @@ src-plat := of.c cuboot-52xx.c cuboot-824x.c cuboot-83xx.c cuboot-85xx.c holly.c cuboot-warp.c cuboot-85xx-cpm2.c cuboot-yosemite.c simpleboot.c \ virtex405-head.S virtex.c redboot-83xx.c cuboot-sam440ep.c \ cuboot-acadia.c cuboot-amigaone.c cuboot-kilauea.c \ - gamecube.c + gamecube.c wii.c src-boot := $(src-wlib) $(src-plat) empty.c src-boot := $(addprefix $(obj)/, $(src-boot)) @@ -256,6 +256,7 @@ image-$(CONFIG_STORCENTER) += cuImage.storcenter image-$(CONFIG_MPC7448HPC2)+= cuImage.mpc7448hpc2 image-$(CONFIG_PPC_C2K)+= cuImage.c2k image-$(CONFIG_GAMECUBE) += dtbImage.gamecube +image-$(CONFIG_WII)+= dtbImage.wii # Board port in arch/powerpc/platform/amigaone/Kconfig image-$(CONFIG_AMIGAONE) += cuImage.amigaone diff --git a/arch/powerpc/boot/wii.c b/arch/powerpc/boot/wii.c new file mode 100644 index 000..65b73a1 --- /dev/null +++ b/arch/powerpc/boot/wii.c @@ -0,0 +1,173 @@ +/* + * arch/powerpc/boot/wii.c + * + * Nintendo Wii bootwrapper support + * Copyright (C) 2008-2009 The GameCube Linux Team + * Copyright (C) 2008,2009 Albert Herranz + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + */ + +#include stddef.h +#include stdio.h +#include types.h +#include io.h +#include ops.h + +#include ugecon.h + + +BSS_STACK(8192); + +/* + * We enter with an unknown cache, high BATs and MMU status. + * + * We enable the MMU with an identity mapped memory scheme as expected + * by the start code. + * + */ +asm (\n\ +.text\n\ +.globl _zimage_start\n\ +_zimage_start:\n\ +\n\ + mfmsr 9\n\ + andi. 0, 9, (14)|(15) /* MSR_DR|MSR_IR */\n\ + bcl 20, 31, 1f\n\ +1: \n\ + mflr8\n\ + clrlwi 8, 8, 3 /* convert to a real address */\n\ + addi8, 8, _mmu_off - 1b\n\ + andc9, 9, 0\n\ + mtspr 0x01a, 8/* SRR0 */\n\ + mtspr 0x01b, 9/* SRR1 */\n\ + sync\n\ + rfi\n\ +_mmu_off: \n\ + /* MMU disabled */\n\ +\n\ + /* Setup BATs */\n\ + isync\n\ + li 8, 0\n\ + mtspr 0x210, 8/* IBAT0U */\n\ + mtspr 0x211, 8/* IBAT0L */\n\ + mtspr 0x212, 8/* IBAT1U */\n\ + mtspr 0x213, 8/* IBAT1L */\n\ + mtspr 0x214, 8/* IBAT2U */\n\ + mtspr 0x215, 8/* IBAT2L */\n\ + mtspr 0x216, 8/* IBAT3U */\n\ + mtspr 0x217, 8/* IBAT3L */\n\ + mtspr 0x218, 8/* DBAT0U */\n\ + mtspr 0x219, 8/* DBAT0L */\n\ + mtspr 0x21a, 8/* DBAT1U */\n\ + mtspr 0x21b, 8/* DBAT1L */\n\ + mtspr 0x21c, 8/* DBAT2U */\n\ + mtspr 0x21d, 8/* DBAT2L */\n\ + mtspr 0x21e, 8/* DBAT3U */\n\ + mtspr 0x21f, 8/* DBAT3L */\n\ +\n\ + mtspr 0x230, 8/* IBAT4U */\n\ + mtspr 0x231, 8/* IBAT4L */\n\ + mtspr 0x232, 8/* IBAT5U */\n\ + mtspr 0x233, 8/* IBAT5L */\n\ + mtspr 0x234, 8/* IBAT6U */\n\ + mtspr 0x235, 8/* IBAT6L */\n\ + mtspr 0x236, 8/* IBAT7U */\n\ + mtspr 0x237, 8/* IBAT7L */\n\ + mtspr 0x238, 8/* DBAT4U */\n\ + mtspr 0x239, 8/* DBAT4L */\n\ + mtspr 0x23a, 8/* DBAT5U */\n\ + mtspr 0x23b, 8/* DBAT5L */\n\ + mtspr 0x23c, 8/* DBAT6U */\n\ + mtspr 0x23d, 8/* DBAT6L */\n\ + mtspr 0x23e, 8/* DBAT7U */\n\ + mtspr 0x23f, 8/* DBAT7L */\n\ +\n\ + isync\n\ + li 8, 0x01ff /* first 16MiB */\n\ + li 9, 0x0002 /* rw */\n\ + mtspr 0x210, 8/* IBAT0U */\n\ + mtspr 0x211, 9/* IBAT0L */\n\ + mtspr 0x218, 8/* DBAT0U */\n\ + mtspr 0x219, 9/* DBAT0L */\n\ +\n\ + lis
Re: [RFC PATCH 05/19] powerpc: wii: bootwrapper bits
On Sun, Nov 22, 2009 at 3:01 PM, Albert Herranz albert_herr...@yahoo.es wrote: Add support for the Nintendo Wii video game console to the powerpc bootwrapper. dtbImage.wii is a wrapped image that contains a flat device tree, an entry point compatible with the Homebrew Channel and BootMii, and an optional initrd. Signed-off-by: Albert Herranz albert_herr...@yahoo.es Acked-by: Grant Likely grant.lik...@secretlab.ca --- arch/powerpc/boot/Makefile | 3 +- arch/powerpc/boot/wii.c | 173 arch/powerpc/boot/wrapper | 3 + 3 files changed, 178 insertions(+), 1 deletions(-) create mode 100644 arch/powerpc/boot/wii.c diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile index b2f06b0..fbaf101 100644 --- a/arch/powerpc/boot/Makefile +++ b/arch/powerpc/boot/Makefile @@ -77,7 +77,7 @@ src-plat := of.c cuboot-52xx.c cuboot-824x.c cuboot-83xx.c cuboot-85xx.c holly.c cuboot-warp.c cuboot-85xx-cpm2.c cuboot-yosemite.c simpleboot.c \ virtex405-head.S virtex.c redboot-83xx.c cuboot-sam440ep.c \ cuboot-acadia.c cuboot-amigaone.c cuboot-kilauea.c \ - gamecube.c + gamecube.c wii.c src-boot := $(src-wlib) $(src-plat) empty.c src-boot := $(addprefix $(obj)/, $(src-boot)) @@ -256,6 +256,7 @@ image-$(CONFIG_STORCENTER) += cuImage.storcenter image-$(CONFIG_MPC7448HPC2) += cuImage.mpc7448hpc2 image-$(CONFIG_PPC_C2K) += cuImage.c2k image-$(CONFIG_GAMECUBE) += dtbImage.gamecube +image-$(CONFIG_WII) += dtbImage.wii # Board port in arch/powerpc/platform/amigaone/Kconfig image-$(CONFIG_AMIGAONE) += cuImage.amigaone diff --git a/arch/powerpc/boot/wii.c b/arch/powerpc/boot/wii.c new file mode 100644 index 000..65b73a1 --- /dev/null +++ b/arch/powerpc/boot/wii.c @@ -0,0 +1,173 @@ +/* + * arch/powerpc/boot/wii.c + * + * Nintendo Wii bootwrapper support + * Copyright (C) 2008-2009 The GameCube Linux Team + * Copyright (C) 2008,2009 Albert Herranz + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + */ + +#include stddef.h +#include stdio.h +#include types.h +#include io.h +#include ops.h + +#include ugecon.h + + +BSS_STACK(8192); + +/* + * We enter with an unknown cache, high BATs and MMU status. + * + * We enable the MMU with an identity mapped memory scheme as expected + * by the start code. + * + */ +asm (\n\ +.text\n\ +.globl _zimage_start\n\ +_zimage_start:\n\ +\n\ + mfmsr 9\n\ + andi. 0, 9, (14)|(15) /* MSR_DR|MSR_IR */\n\ + bcl 20, 31, 1f\n\ +1: \n\ + mflr 8\n\ + clrlwi 8, 8, 3 /* convert to a real address */\n\ + addi 8, 8, _mmu_off - 1b\n\ + andc 9, 9, 0\n\ + mtspr 0x01a, 8 /* SRR0 */\n\ + mtspr 0x01b, 9 /* SRR1 */\n\ + sync\n\ + rfi\n\ +_mmu_off: \n\ + /* MMU disabled */\n\ +\n\ + /* Setup BATs */\n\ + isync\n\ + li 8, 0\n\ + mtspr 0x210, 8 /* IBAT0U */\n\ + mtspr 0x211, 8 /* IBAT0L */\n\ + mtspr 0x212, 8 /* IBAT1U */\n\ + mtspr 0x213, 8 /* IBAT1L */\n\ + mtspr 0x214, 8 /* IBAT2U */\n\ + mtspr 0x215, 8 /* IBAT2L */\n\ + mtspr 0x216, 8 /* IBAT3U */\n\ + mtspr 0x217, 8 /* IBAT3L */\n\ + mtspr 0x218, 8 /* DBAT0U */\n\ + mtspr 0x219, 8 /* DBAT0L */\n\ + mtspr 0x21a, 8 /* DBAT1U */\n\ + mtspr 0x21b, 8 /* DBAT1L */\n\ + mtspr 0x21c, 8 /* DBAT2U */\n\ + mtspr 0x21d, 8 /* DBAT2L */\n\ + mtspr 0x21e, 8 /* DBAT3U */\n\ + mtspr 0x21f, 8 /* DBAT3L */\n\ +\n\ + mtspr 0x230, 8 /* IBAT4U */\n\ + mtspr 0x231, 8 /* IBAT4L */\n\ + mtspr 0x232, 8 /* IBAT5U */\n\ + mtspr 0x233, 8 /* IBAT5L */\n\ + mtspr 0x234, 8 /* IBAT6U */\n\ + mtspr 0x235, 8 /* IBAT6L */\n\ + mtspr 0x236, 8 /* IBAT7U */\n\ + mtspr 0x237, 8 /* IBAT7L */\n\ + mtspr 0x238, 8 /* DBAT4U */\n\ + mtspr 0x239, 8 /* DBAT4L */\n\ + mtspr 0x23a, 8 /* DBAT5U */\n\ + mtspr 0x23b, 8 /* DBAT5L */\n\ + mtspr 0x23c, 8 /* DBAT6U */\n\ + mtspr 0x23d, 8 /* DBAT6L */\n\ + mtspr 0x23e, 8 /* DBAT7U */\n\ + mtspr 0x23f, 8 /* DBAT7L */\n\ +\n\ + isync\n\ + li 8, 0x01ff /* first 16MiB */\n\
