Updates: Placed everything in one conditional. Updated commit message.
This takes values from the PowerPC ISA BookIII-E specifications that are for
DBCR0. Many of these values are different from those currently specified, which
are for the ppc405. Also added some bookE definitions for DBCR1 & DBCR2.
Signed-off-by: Jerone Young <[EMAIL PROTECTED]>
diff --git a/include/asm-powerpc/reg_booke.h b/include/asm-powerpc/reg_booke.h
--- a/include/asm-powerpc/reg_booke.h
+++ b/include/asm-powerpc/reg_booke.h
@@ -253,6 +253,7 @@
#define ESR_BO 0x0002 /* Byte Ordering */
/* Bit definitions related to the DBCR0. */
+#if defined(CONFIG_40x)
#define DBCR0_EDM 0x8000 /* External Debug Mode */
#define DBCR0_IDM 0x4000 /* Internal Debug Mode */
#define DBCR0_RST 0x3000 /* all the bits in the RST field */
@@ -275,6 +276,50 @@
#define DBCR0_IA12T0x8000 /* Instr Addr 1-2 range Toggle */
#define DBCR0_IA34T0x4000 /* Instr Addr 3-4 range Toggle */
#define DBCR0_FT 0x0001 /* Freeze Timers on debug event */
+#elif defined(CONFIG_BOOKE)
+#define DBCR0_EDM 0x8000 /* External Debug Mode */
+#define DBCR0_IDM 0x4000 /* Internal Debug Mode */
+/* DBCR0_RST* is 44x specific and not followed in fsl booke */
+#define DBCR0_RST 0x3000 /* all the bits in the RST field */
+#define DBCR0_RST_SYSTEM 0x3000/* System Reset */
+#define DBCR0_RST_CHIP 0x2000 /* Chip Reset */
+#define DBCR0_RST_CORE 0x1000 /* Core Reset */
+#define DBCR0_RST_NONE 0x /* No Reset */
+#define DBCR0_ICMP 0x0800 /* Instruction Completion */
+#define DBCR0_IC DBCR0_ICMP
+#define DBCR0_BRT 0x0400 /* Branch Taken */
+#define DBCR0_BR DBCR0_BRT
+#define DBCR0_IRPT 0x0200 /* Exception Debug Event */
+#define DBCR0_EDE DBCR0_IRPT
+#define DBCR0_TDE 0x0100 /* TRAP Debug Event */
+#define DBCR0_IAC1 0x0080 /* Instr Addr compare 1 enable */
+#define DBCR0_IA1 DBCR0_IAC1
+#define DBCR0_IAC2 0x0040 /* Instr Addr compare 2 enable */
+#define DBCR0_IA2 DBCR0_IAC2
+#define DBCR0_IAC3 0x0020 /* Instr Addr compare 3 enable */
+#define DBCR0_IA3 DBCR0_IAC3
+#define DBCR0_IAC4 0x0010 /* Instr Addr compare 4 enable */
+#define DBCR0_IA4 DBCR0_IAC4
+#define DBCR0_DAC1R0x0008 /* DAC 1 Read enable */
+#define DBCR0_DAC1W0x0004 /* DAC 1 Write enable */
+#define DBCR0_DAC2R0x0002 /* DAC 2 Read enable */
+#define DBCR0_DAC2W0x0001 /* DAC 2 Write enable */
+#define DBCR0_RET 0x8000 /* Return Debug Event */
+#define DBCR0_FT 0x0001 /* Freeze Timers on debug event */
+
+/* Bit definitions related to the DBCR1. */
+#define DBCR1_IAC12M 0x0080 /* Instr Addr 1-2 range enable */
+#define DBCR1_IAC12MX 0x00C0 /* Instr Addr 1-2 range eXclusive */
+#define DBCR1_IAC12AT 0x0001 /* Instr Addr 1-2 range Toggle */
+#define DBCR1_IAC34M 0x0080 /* Instr Addr 3-4 range enable */
+#define DBCR1_IAC34MX 0x00C0 /* Instr Addr 3-4 range eXclusive */
+#define DBCR1_IAC34AT 0x0001 /* Instr Addr 3-4 range Toggle */
+
+/* Bit definitions related to the DBCR2. */
+#define DBCR2_DAC12M 0x0080 /* DAC 1-2 range enable */
+#define DBCR2_DAC12MX 0x00C0 /* DAC 1-2 range eXclusive */
+#define DBCR2_DAC12A 0x0020 /* DAC 1-2 Asynchronous */
+#endif
/* Bit definitions related to the TCR. */
#define TCR_WP(x) (((x)&0x3)<<30) /* WDT Period */
___
Linuxppc-dev mailing list
Linuxppc-dev@ozlabs.org
https://ozlabs.org/mailman/listinfo/linuxppc-dev
